core.c 42 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include "core.h"
  21. #include "mac.h"
  22. #include "htc.h"
  23. #include "hif.h"
  24. #include "wmi.h"
  25. #include "bmi.h"
  26. #include "debug.h"
  27. #include "htt.h"
  28. #include "testmode.h"
  29. #include "wmi-ops.h"
  30. unsigned int ath10k_debug_mask;
  31. static unsigned int ath10k_cryptmode_param;
  32. static bool uart_print;
  33. static bool skip_otp;
  34. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  35. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  36. module_param(uart_print, bool, 0644);
  37. module_param(skip_otp, bool, 0644);
  38. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  39. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  40. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  41. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  42. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  43. {
  44. .id = QCA988X_HW_2_0_VERSION,
  45. .name = "qca988x hw2.0",
  46. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  47. .uart_pin = 7,
  48. .has_shifted_cc_wraparound = true,
  49. .otp_exe_param = 0,
  50. .channel_counters_freq_hz = 88000,
  51. .fw = {
  52. .dir = QCA988X_HW_2_0_FW_DIR,
  53. .fw = QCA988X_HW_2_0_FW_FILE,
  54. .otp = QCA988X_HW_2_0_OTP_FILE,
  55. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  56. .board_size = QCA988X_BOARD_DATA_SZ,
  57. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  58. },
  59. },
  60. {
  61. .id = QCA6174_HW_2_1_VERSION,
  62. .name = "qca6174 hw2.1",
  63. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  64. .uart_pin = 6,
  65. .otp_exe_param = 0,
  66. .channel_counters_freq_hz = 88000,
  67. .fw = {
  68. .dir = QCA6174_HW_2_1_FW_DIR,
  69. .fw = QCA6174_HW_2_1_FW_FILE,
  70. .otp = QCA6174_HW_2_1_OTP_FILE,
  71. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  72. .board_size = QCA6174_BOARD_DATA_SZ,
  73. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  74. },
  75. },
  76. {
  77. .id = QCA6174_HW_3_0_VERSION,
  78. .name = "qca6174 hw3.0",
  79. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  80. .uart_pin = 6,
  81. .otp_exe_param = 0,
  82. .channel_counters_freq_hz = 88000,
  83. .fw = {
  84. .dir = QCA6174_HW_3_0_FW_DIR,
  85. .fw = QCA6174_HW_3_0_FW_FILE,
  86. .otp = QCA6174_HW_3_0_OTP_FILE,
  87. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  88. .board_size = QCA6174_BOARD_DATA_SZ,
  89. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  90. },
  91. },
  92. {
  93. .id = QCA6174_HW_3_2_VERSION,
  94. .name = "qca6174 hw3.2",
  95. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  96. .uart_pin = 6,
  97. .otp_exe_param = 0,
  98. .channel_counters_freq_hz = 88000,
  99. .fw = {
  100. /* uses same binaries as hw3.0 */
  101. .dir = QCA6174_HW_3_0_FW_DIR,
  102. .fw = QCA6174_HW_3_0_FW_FILE,
  103. .otp = QCA6174_HW_3_0_OTP_FILE,
  104. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  105. .board_size = QCA6174_BOARD_DATA_SZ,
  106. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  107. },
  108. },
  109. {
  110. .id = QCA99X0_HW_2_0_DEV_VERSION,
  111. .name = "qca99x0 hw2.0",
  112. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  113. .uart_pin = 7,
  114. .otp_exe_param = 0x00000700,
  115. .continuous_frag_desc = true,
  116. .channel_counters_freq_hz = 150000,
  117. .fw = {
  118. .dir = QCA99X0_HW_2_0_FW_DIR,
  119. .fw = QCA99X0_HW_2_0_FW_FILE,
  120. .otp = QCA99X0_HW_2_0_OTP_FILE,
  121. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  122. .board_size = QCA99X0_BOARD_DATA_SZ,
  123. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  124. },
  125. },
  126. };
  127. static const char *const ath10k_core_fw_feature_str[] = {
  128. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  129. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  130. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  131. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  132. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  133. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  134. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  135. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  136. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  137. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  138. };
  139. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  140. size_t buf_len,
  141. enum ath10k_fw_features feat)
  142. {
  143. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  144. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  145. return scnprintf(buf, buf_len, "bit%d", feat);
  146. }
  147. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  148. }
  149. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  150. char *buf,
  151. size_t buf_len)
  152. {
  153. unsigned int len = 0;
  154. int i;
  155. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  156. if (test_bit(i, ar->fw_features)) {
  157. if (len > 0)
  158. len += scnprintf(buf + len, buf_len - len, ",");
  159. len += ath10k_core_get_fw_feature_str(buf + len,
  160. buf_len - len,
  161. i);
  162. }
  163. }
  164. }
  165. static void ath10k_send_suspend_complete(struct ath10k *ar)
  166. {
  167. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  168. complete(&ar->target_suspend);
  169. }
  170. static int ath10k_init_configure_target(struct ath10k *ar)
  171. {
  172. u32 param_host;
  173. int ret;
  174. /* tell target which HTC version it is used*/
  175. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  176. HTC_PROTOCOL_VERSION);
  177. if (ret) {
  178. ath10k_err(ar, "settings HTC version failed\n");
  179. return ret;
  180. }
  181. /* set the firmware mode to STA/IBSS/AP */
  182. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  183. if (ret) {
  184. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  185. return ret;
  186. }
  187. /* TODO following parameters need to be re-visited. */
  188. /* num_device */
  189. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  190. /* Firmware mode */
  191. /* FIXME: Why FW_MODE_AP ??.*/
  192. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  193. /* mac_addr_method */
  194. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  195. /* firmware_bridge */
  196. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  197. /* fwsubmode */
  198. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  199. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  200. if (ret) {
  201. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  202. return ret;
  203. }
  204. /* We do all byte-swapping on the host */
  205. ret = ath10k_bmi_write32(ar, hi_be, 0);
  206. if (ret) {
  207. ath10k_err(ar, "setting host CPU BE mode failed\n");
  208. return ret;
  209. }
  210. /* FW descriptor/Data swap flags */
  211. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  212. if (ret) {
  213. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  214. return ret;
  215. }
  216. /* Some devices have a special sanity check that verifies the PCI
  217. * Device ID is written to this host interest var. It is known to be
  218. * required to boot QCA6164.
  219. */
  220. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  221. ar->dev_id);
  222. if (ret) {
  223. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  224. return ret;
  225. }
  226. return 0;
  227. }
  228. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  229. const char *dir,
  230. const char *file)
  231. {
  232. char filename[100];
  233. const struct firmware *fw;
  234. int ret;
  235. if (file == NULL)
  236. return ERR_PTR(-ENOENT);
  237. if (dir == NULL)
  238. dir = ".";
  239. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  240. ret = request_firmware(&fw, filename, ar->dev);
  241. if (ret)
  242. return ERR_PTR(ret);
  243. return fw;
  244. }
  245. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  246. size_t data_len)
  247. {
  248. u32 board_data_size = ar->hw_params.fw.board_size;
  249. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  250. u32 board_ext_data_addr;
  251. int ret;
  252. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  253. if (ret) {
  254. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  255. ret);
  256. return ret;
  257. }
  258. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  259. "boot push board extended data addr 0x%x\n",
  260. board_ext_data_addr);
  261. if (board_ext_data_addr == 0)
  262. return 0;
  263. if (data_len != (board_data_size + board_ext_data_size)) {
  264. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  265. data_len, board_data_size, board_ext_data_size);
  266. return -EINVAL;
  267. }
  268. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  269. data + board_data_size,
  270. board_ext_data_size);
  271. if (ret) {
  272. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  273. return ret;
  274. }
  275. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  276. (board_ext_data_size << 16) | 1);
  277. if (ret) {
  278. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  279. ret);
  280. return ret;
  281. }
  282. return 0;
  283. }
  284. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  285. size_t data_len)
  286. {
  287. u32 board_data_size = ar->hw_params.fw.board_size;
  288. u32 address;
  289. int ret;
  290. ret = ath10k_push_board_ext_data(ar, data, data_len);
  291. if (ret) {
  292. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  293. goto exit;
  294. }
  295. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  296. if (ret) {
  297. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  298. goto exit;
  299. }
  300. ret = ath10k_bmi_write_memory(ar, address, data,
  301. min_t(u32, board_data_size,
  302. data_len));
  303. if (ret) {
  304. ath10k_err(ar, "could not write board data (%d)\n", ret);
  305. goto exit;
  306. }
  307. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  308. if (ret) {
  309. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  310. goto exit;
  311. }
  312. exit:
  313. return ret;
  314. }
  315. static int ath10k_download_cal_file(struct ath10k *ar)
  316. {
  317. int ret;
  318. if (!ar->cal_file)
  319. return -ENOENT;
  320. if (IS_ERR(ar->cal_file))
  321. return PTR_ERR(ar->cal_file);
  322. ret = ath10k_download_board_data(ar, ar->cal_file->data,
  323. ar->cal_file->size);
  324. if (ret) {
  325. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  326. return ret;
  327. }
  328. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  329. return 0;
  330. }
  331. static int ath10k_download_cal_dt(struct ath10k *ar)
  332. {
  333. struct device_node *node;
  334. int data_len;
  335. void *data;
  336. int ret;
  337. node = ar->dev->of_node;
  338. if (!node)
  339. /* Device Tree is optional, don't print any warnings if
  340. * there's no node for ath10k.
  341. */
  342. return -ENOENT;
  343. if (!of_get_property(node, "qcom,ath10k-calibration-data",
  344. &data_len)) {
  345. /* The calibration data node is optional */
  346. return -ENOENT;
  347. }
  348. if (data_len != QCA988X_CAL_DATA_LEN) {
  349. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  350. data_len);
  351. ret = -EMSGSIZE;
  352. goto out;
  353. }
  354. data = kmalloc(data_len, GFP_KERNEL);
  355. if (!data) {
  356. ret = -ENOMEM;
  357. goto out;
  358. }
  359. ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data",
  360. data, data_len);
  361. if (ret) {
  362. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  363. ret);
  364. goto out_free;
  365. }
  366. ret = ath10k_download_board_data(ar, data, data_len);
  367. if (ret) {
  368. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  369. ret);
  370. goto out_free;
  371. }
  372. ret = 0;
  373. out_free:
  374. kfree(data);
  375. out:
  376. return ret;
  377. }
  378. static int ath10k_download_and_run_otp(struct ath10k *ar)
  379. {
  380. u32 result, address = ar->hw_params.patch_load_addr;
  381. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  382. int ret;
  383. ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len);
  384. if (ret) {
  385. ath10k_err(ar, "failed to download board data: %d\n", ret);
  386. return ret;
  387. }
  388. /* OTP is optional */
  389. if (!ar->otp_data || !ar->otp_len) {
  390. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
  391. ar->otp_data, ar->otp_len);
  392. return 0;
  393. }
  394. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  395. address, ar->otp_len);
  396. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  397. if (ret) {
  398. ath10k_err(ar, "could not write otp (%d)\n", ret);
  399. return ret;
  400. }
  401. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  402. if (ret) {
  403. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  404. return ret;
  405. }
  406. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  407. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  408. ar->fw_features))
  409. && result != 0) {
  410. ath10k_err(ar, "otp calibration failed: %d", result);
  411. return -EINVAL;
  412. }
  413. return 0;
  414. }
  415. static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode)
  416. {
  417. u32 address, data_len;
  418. const char *mode_name;
  419. const void *data;
  420. int ret;
  421. address = ar->hw_params.patch_load_addr;
  422. switch (mode) {
  423. case ATH10K_FIRMWARE_MODE_NORMAL:
  424. data = ar->firmware_data;
  425. data_len = ar->firmware_len;
  426. mode_name = "normal";
  427. ret = ath10k_swap_code_seg_configure(ar,
  428. ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
  429. if (ret) {
  430. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  431. ret);
  432. return ret;
  433. }
  434. break;
  435. case ATH10K_FIRMWARE_MODE_UTF:
  436. data = ar->testmode.utf->data;
  437. data_len = ar->testmode.utf->size;
  438. mode_name = "utf";
  439. break;
  440. default:
  441. ath10k_err(ar, "unknown firmware mode: %d\n", mode);
  442. return -EINVAL;
  443. }
  444. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  445. "boot uploading firmware image %p len %d mode %s\n",
  446. data, data_len, mode_name);
  447. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  448. if (ret) {
  449. ath10k_err(ar, "failed to download %s firmware: %d\n",
  450. mode_name, ret);
  451. return ret;
  452. }
  453. return ret;
  454. }
  455. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  456. {
  457. if (!IS_ERR(ar->board))
  458. release_firmware(ar->board);
  459. if (!IS_ERR(ar->otp))
  460. release_firmware(ar->otp);
  461. if (!IS_ERR(ar->firmware))
  462. release_firmware(ar->firmware);
  463. if (!IS_ERR(ar->cal_file))
  464. release_firmware(ar->cal_file);
  465. ath10k_swap_code_seg_release(ar);
  466. ar->board = NULL;
  467. ar->board_data = NULL;
  468. ar->board_len = 0;
  469. ar->otp = NULL;
  470. ar->otp_data = NULL;
  471. ar->otp_len = 0;
  472. ar->firmware = NULL;
  473. ar->firmware_data = NULL;
  474. ar->firmware_len = 0;
  475. ar->cal_file = NULL;
  476. }
  477. static int ath10k_fetch_cal_file(struct ath10k *ar)
  478. {
  479. char filename[100];
  480. /* cal-<bus>-<id>.bin */
  481. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  482. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  483. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  484. if (IS_ERR(ar->cal_file))
  485. /* calibration file is optional, don't print any warnings */
  486. return PTR_ERR(ar->cal_file);
  487. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  488. ATH10K_FW_DIR, filename);
  489. return 0;
  490. }
  491. static int ath10k_core_fetch_spec_board_file(struct ath10k *ar)
  492. {
  493. char filename[100];
  494. scnprintf(filename, sizeof(filename), "board-%s-%s.bin",
  495. ath10k_bus_str(ar->hif.bus), ar->spec_board_id);
  496. ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename);
  497. if (IS_ERR(ar->board))
  498. return PTR_ERR(ar->board);
  499. ar->board_data = ar->board->data;
  500. ar->board_len = ar->board->size;
  501. ar->spec_board_loaded = true;
  502. return 0;
  503. }
  504. static int ath10k_core_fetch_generic_board_file(struct ath10k *ar)
  505. {
  506. if (!ar->hw_params.fw.board) {
  507. ath10k_err(ar, "failed to find board file fw entry\n");
  508. return -EINVAL;
  509. }
  510. ar->board = ath10k_fetch_fw_file(ar,
  511. ar->hw_params.fw.dir,
  512. ar->hw_params.fw.board);
  513. if (IS_ERR(ar->board))
  514. return PTR_ERR(ar->board);
  515. ar->board_data = ar->board->data;
  516. ar->board_len = ar->board->size;
  517. ar->spec_board_loaded = false;
  518. return 0;
  519. }
  520. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  521. {
  522. int ret;
  523. if (strlen(ar->spec_board_id) > 0) {
  524. ret = ath10k_core_fetch_spec_board_file(ar);
  525. if (ret) {
  526. ath10k_info(ar, "failed to load spec board file, falling back to generic: %d\n",
  527. ret);
  528. goto generic;
  529. }
  530. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found specific board file for %s\n",
  531. ar->spec_board_id);
  532. return 0;
  533. }
  534. generic:
  535. ret = ath10k_core_fetch_generic_board_file(ar);
  536. if (ret) {
  537. ath10k_err(ar, "failed to fetch generic board data: %d\n", ret);
  538. return ret;
  539. }
  540. return 0;
  541. }
  542. static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
  543. {
  544. int ret = 0;
  545. if (ar->hw_params.fw.fw == NULL) {
  546. ath10k_err(ar, "firmware file not defined\n");
  547. return -EINVAL;
  548. }
  549. ar->firmware = ath10k_fetch_fw_file(ar,
  550. ar->hw_params.fw.dir,
  551. ar->hw_params.fw.fw);
  552. if (IS_ERR(ar->firmware)) {
  553. ret = PTR_ERR(ar->firmware);
  554. ath10k_err(ar, "could not fetch firmware (%d)\n", ret);
  555. goto err;
  556. }
  557. ar->firmware_data = ar->firmware->data;
  558. ar->firmware_len = ar->firmware->size;
  559. /* OTP may be undefined. If so, don't fetch it at all */
  560. if (ar->hw_params.fw.otp == NULL)
  561. return 0;
  562. ar->otp = ath10k_fetch_fw_file(ar,
  563. ar->hw_params.fw.dir,
  564. ar->hw_params.fw.otp);
  565. if (IS_ERR(ar->otp)) {
  566. ret = PTR_ERR(ar->otp);
  567. ath10k_err(ar, "could not fetch otp (%d)\n", ret);
  568. goto err;
  569. }
  570. ar->otp_data = ar->otp->data;
  571. ar->otp_len = ar->otp->size;
  572. return 0;
  573. err:
  574. ath10k_core_free_firmware_files(ar);
  575. return ret;
  576. }
  577. static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
  578. {
  579. size_t magic_len, len, ie_len;
  580. int ie_id, i, index, bit, ret;
  581. struct ath10k_fw_ie *hdr;
  582. const u8 *data;
  583. __le32 *timestamp, *version;
  584. /* first fetch the firmware file (firmware-*.bin) */
  585. ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name);
  586. if (IS_ERR(ar->firmware)) {
  587. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  588. ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware));
  589. return PTR_ERR(ar->firmware);
  590. }
  591. data = ar->firmware->data;
  592. len = ar->firmware->size;
  593. /* magic also includes the null byte, check that as well */
  594. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  595. if (len < magic_len) {
  596. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  597. ar->hw_params.fw.dir, name, len);
  598. ret = -EINVAL;
  599. goto err;
  600. }
  601. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  602. ath10k_err(ar, "invalid firmware magic\n");
  603. ret = -EINVAL;
  604. goto err;
  605. }
  606. /* jump over the padding */
  607. magic_len = ALIGN(magic_len, 4);
  608. len -= magic_len;
  609. data += magic_len;
  610. /* loop elements */
  611. while (len > sizeof(struct ath10k_fw_ie)) {
  612. hdr = (struct ath10k_fw_ie *)data;
  613. ie_id = le32_to_cpu(hdr->id);
  614. ie_len = le32_to_cpu(hdr->len);
  615. len -= sizeof(*hdr);
  616. data += sizeof(*hdr);
  617. if (len < ie_len) {
  618. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  619. ie_id, len, ie_len);
  620. ret = -EINVAL;
  621. goto err;
  622. }
  623. switch (ie_id) {
  624. case ATH10K_FW_IE_FW_VERSION:
  625. if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1)
  626. break;
  627. memcpy(ar->hw->wiphy->fw_version, data, ie_len);
  628. ar->hw->wiphy->fw_version[ie_len] = '\0';
  629. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  630. "found fw version %s\n",
  631. ar->hw->wiphy->fw_version);
  632. break;
  633. case ATH10K_FW_IE_TIMESTAMP:
  634. if (ie_len != sizeof(u32))
  635. break;
  636. timestamp = (__le32 *)data;
  637. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  638. le32_to_cpup(timestamp));
  639. break;
  640. case ATH10K_FW_IE_FEATURES:
  641. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  642. "found firmware features ie (%zd B)\n",
  643. ie_len);
  644. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  645. index = i / 8;
  646. bit = i % 8;
  647. if (index == ie_len)
  648. break;
  649. if (data[index] & (1 << bit)) {
  650. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  651. "Enabling feature bit: %i\n",
  652. i);
  653. __set_bit(i, ar->fw_features);
  654. }
  655. }
  656. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  657. ar->fw_features,
  658. sizeof(ar->fw_features));
  659. break;
  660. case ATH10K_FW_IE_FW_IMAGE:
  661. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  662. "found fw image ie (%zd B)\n",
  663. ie_len);
  664. ar->firmware_data = data;
  665. ar->firmware_len = ie_len;
  666. break;
  667. case ATH10K_FW_IE_OTP_IMAGE:
  668. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  669. "found otp image ie (%zd B)\n",
  670. ie_len);
  671. ar->otp_data = data;
  672. ar->otp_len = ie_len;
  673. break;
  674. case ATH10K_FW_IE_WMI_OP_VERSION:
  675. if (ie_len != sizeof(u32))
  676. break;
  677. version = (__le32 *)data;
  678. ar->wmi.op_version = le32_to_cpup(version);
  679. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  680. ar->wmi.op_version);
  681. break;
  682. case ATH10K_FW_IE_HTT_OP_VERSION:
  683. if (ie_len != sizeof(u32))
  684. break;
  685. version = (__le32 *)data;
  686. ar->htt.op_version = le32_to_cpup(version);
  687. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  688. ar->htt.op_version);
  689. break;
  690. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  691. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  692. "found fw code swap image ie (%zd B)\n",
  693. ie_len);
  694. ar->swap.firmware_codeswap_data = data;
  695. ar->swap.firmware_codeswap_len = ie_len;
  696. break;
  697. default:
  698. ath10k_warn(ar, "Unknown FW IE: %u\n",
  699. le32_to_cpu(hdr->id));
  700. break;
  701. }
  702. /* jump over the padding */
  703. ie_len = ALIGN(ie_len, 4);
  704. len -= ie_len;
  705. data += ie_len;
  706. }
  707. if (!ar->firmware_data || !ar->firmware_len) {
  708. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  709. ar->hw_params.fw.dir, name);
  710. ret = -ENOMEDIUM;
  711. goto err;
  712. }
  713. return 0;
  714. err:
  715. ath10k_core_free_firmware_files(ar);
  716. return ret;
  717. }
  718. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  719. {
  720. int ret;
  721. /* calibration file is optional, don't check for any errors */
  722. ath10k_fetch_cal_file(ar);
  723. ret = ath10k_core_fetch_board_file(ar);
  724. if (ret) {
  725. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  726. return ret;
  727. }
  728. ar->fw_api = 5;
  729. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  730. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE);
  731. if (ret == 0)
  732. goto success;
  733. ar->fw_api = 4;
  734. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  735. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE);
  736. if (ret == 0)
  737. goto success;
  738. ar->fw_api = 3;
  739. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  740. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE);
  741. if (ret == 0)
  742. goto success;
  743. ar->fw_api = 2;
  744. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  745. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE);
  746. if (ret == 0)
  747. goto success;
  748. ar->fw_api = 1;
  749. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  750. ret = ath10k_core_fetch_firmware_api_1(ar);
  751. if (ret)
  752. return ret;
  753. success:
  754. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  755. return 0;
  756. }
  757. static int ath10k_download_cal_data(struct ath10k *ar)
  758. {
  759. int ret;
  760. ret = ath10k_download_cal_file(ar);
  761. if (ret == 0) {
  762. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  763. goto done;
  764. }
  765. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  766. "boot did not find a calibration file, try DT next: %d\n",
  767. ret);
  768. ret = ath10k_download_cal_dt(ar);
  769. if (ret == 0) {
  770. ar->cal_mode = ATH10K_CAL_MODE_DT;
  771. goto done;
  772. }
  773. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  774. "boot did not find DT entry, try OTP next: %d\n",
  775. ret);
  776. ret = ath10k_download_and_run_otp(ar);
  777. if (ret) {
  778. ath10k_err(ar, "failed to run otp: %d\n", ret);
  779. return ret;
  780. }
  781. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  782. done:
  783. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  784. ath10k_cal_mode_str(ar->cal_mode));
  785. return 0;
  786. }
  787. static int ath10k_init_uart(struct ath10k *ar)
  788. {
  789. int ret;
  790. /*
  791. * Explicitly setting UART prints to zero as target turns it on
  792. * based on scratch registers.
  793. */
  794. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  795. if (ret) {
  796. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  797. return ret;
  798. }
  799. if (!uart_print)
  800. return 0;
  801. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  802. if (ret) {
  803. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  804. return ret;
  805. }
  806. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  807. if (ret) {
  808. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  809. return ret;
  810. }
  811. /* Set the UART baud rate to 19200. */
  812. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  813. if (ret) {
  814. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  815. return ret;
  816. }
  817. ath10k_info(ar, "UART prints enabled\n");
  818. return 0;
  819. }
  820. static int ath10k_init_hw_params(struct ath10k *ar)
  821. {
  822. const struct ath10k_hw_params *uninitialized_var(hw_params);
  823. int i;
  824. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  825. hw_params = &ath10k_hw_params_list[i];
  826. if (hw_params->id == ar->target_version)
  827. break;
  828. }
  829. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  830. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  831. ar->target_version);
  832. return -EINVAL;
  833. }
  834. ar->hw_params = *hw_params;
  835. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  836. ar->hw_params.name, ar->target_version);
  837. return 0;
  838. }
  839. static void ath10k_core_restart(struct work_struct *work)
  840. {
  841. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  842. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  843. /* Place a barrier to make sure the compiler doesn't reorder
  844. * CRASH_FLUSH and calling other functions.
  845. */
  846. barrier();
  847. ieee80211_stop_queues(ar->hw);
  848. ath10k_drain_tx(ar);
  849. complete_all(&ar->scan.started);
  850. complete_all(&ar->scan.completed);
  851. complete_all(&ar->scan.on_channel);
  852. complete_all(&ar->offchan_tx_completed);
  853. complete_all(&ar->install_key_done);
  854. complete_all(&ar->vdev_setup_done);
  855. complete_all(&ar->thermal.wmi_sync);
  856. wake_up(&ar->htt.empty_tx_wq);
  857. wake_up(&ar->wmi.tx_credits_wq);
  858. wake_up(&ar->peer_mapping_wq);
  859. mutex_lock(&ar->conf_mutex);
  860. switch (ar->state) {
  861. case ATH10K_STATE_ON:
  862. ar->state = ATH10K_STATE_RESTARTING;
  863. ath10k_hif_stop(ar);
  864. ath10k_scan_finish(ar);
  865. ieee80211_restart_hw(ar->hw);
  866. break;
  867. case ATH10K_STATE_OFF:
  868. /* this can happen if driver is being unloaded
  869. * or if the crash happens during FW probing */
  870. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  871. break;
  872. case ATH10K_STATE_RESTARTING:
  873. /* hw restart might be requested from multiple places */
  874. break;
  875. case ATH10K_STATE_RESTARTED:
  876. ar->state = ATH10K_STATE_WEDGED;
  877. /* fall through */
  878. case ATH10K_STATE_WEDGED:
  879. ath10k_warn(ar, "device is wedged, will not restart\n");
  880. break;
  881. case ATH10K_STATE_UTF:
  882. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  883. break;
  884. }
  885. mutex_unlock(&ar->conf_mutex);
  886. }
  887. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  888. {
  889. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) &&
  890. !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  891. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  892. return -EINVAL;
  893. }
  894. if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  895. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  896. ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version);
  897. return -EINVAL;
  898. }
  899. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  900. switch (ath10k_cryptmode_param) {
  901. case ATH10K_CRYPT_MODE_HW:
  902. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  903. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  904. break;
  905. case ATH10K_CRYPT_MODE_SW:
  906. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  907. ar->fw_features)) {
  908. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  909. return -EINVAL;
  910. }
  911. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  912. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  913. break;
  914. default:
  915. ath10k_info(ar, "invalid cryptmode: %d\n",
  916. ath10k_cryptmode_param);
  917. return -EINVAL;
  918. }
  919. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  920. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  921. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  922. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  923. /* Workaround:
  924. *
  925. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  926. * and causes enormous performance issues (malformed frames,
  927. * etc).
  928. *
  929. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  930. * albeit a bit slower compared to regular operation.
  931. */
  932. ar->htt.max_num_amsdu = 1;
  933. }
  934. /* Backwards compatibility for firmwares without
  935. * ATH10K_FW_IE_WMI_OP_VERSION.
  936. */
  937. if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  938. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  939. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  940. ar->fw_features))
  941. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  942. else
  943. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  944. } else {
  945. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  946. }
  947. }
  948. switch (ar->wmi.op_version) {
  949. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  950. ar->max_num_peers = TARGET_NUM_PEERS;
  951. ar->max_num_stations = TARGET_NUM_STATIONS;
  952. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  953. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  954. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  955. WMI_STAT_PEER;
  956. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  957. break;
  958. case ATH10K_FW_WMI_OP_VERSION_10_1:
  959. case ATH10K_FW_WMI_OP_VERSION_10_2:
  960. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  961. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  962. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  963. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  964. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  965. ar->fw_stats_req_mask = WMI_STAT_PEER;
  966. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  967. break;
  968. case ATH10K_FW_WMI_OP_VERSION_TLV:
  969. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  970. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  971. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  972. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  973. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  974. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  975. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  976. WMI_STAT_PEER;
  977. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  978. break;
  979. case ATH10K_FW_WMI_OP_VERSION_10_4:
  980. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  981. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  982. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  983. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  984. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  985. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  986. ar->fw_stats_req_mask = WMI_STAT_PEER;
  987. ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM;
  988. break;
  989. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  990. case ATH10K_FW_WMI_OP_VERSION_MAX:
  991. WARN_ON(1);
  992. return -EINVAL;
  993. }
  994. /* Backwards compatibility for firmwares without
  995. * ATH10K_FW_IE_HTT_OP_VERSION.
  996. */
  997. if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  998. switch (ar->wmi.op_version) {
  999. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1000. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1001. break;
  1002. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1003. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1004. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1005. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1006. break;
  1007. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1008. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1009. break;
  1010. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1011. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1012. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1013. WARN_ON(1);
  1014. return -EINVAL;
  1015. }
  1016. }
  1017. return 0;
  1018. }
  1019. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
  1020. {
  1021. int status;
  1022. lockdep_assert_held(&ar->conf_mutex);
  1023. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1024. ath10k_bmi_start(ar);
  1025. if (ath10k_init_configure_target(ar)) {
  1026. status = -EINVAL;
  1027. goto err;
  1028. }
  1029. status = ath10k_download_cal_data(ar);
  1030. if (status)
  1031. goto err;
  1032. /* Some of of qca988x solutions are having global reset issue
  1033. * during target initialization. Bypassing PLL setting before
  1034. * downloading firmware and letting the SoC run on REF_CLK is
  1035. * fixing the problem. Corresponding firmware change is also needed
  1036. * to set the clock source once the target is initialized.
  1037. */
  1038. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1039. ar->fw_features)) {
  1040. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1041. if (status) {
  1042. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1043. status);
  1044. goto err;
  1045. }
  1046. }
  1047. status = ath10k_download_fw(ar, mode);
  1048. if (status)
  1049. goto err;
  1050. status = ath10k_init_uart(ar);
  1051. if (status)
  1052. goto err;
  1053. ar->htc.htc_ops.target_send_suspend_complete =
  1054. ath10k_send_suspend_complete;
  1055. status = ath10k_htc_init(ar);
  1056. if (status) {
  1057. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1058. goto err;
  1059. }
  1060. status = ath10k_bmi_done(ar);
  1061. if (status)
  1062. goto err;
  1063. status = ath10k_wmi_attach(ar);
  1064. if (status) {
  1065. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1066. goto err;
  1067. }
  1068. status = ath10k_htt_init(ar);
  1069. if (status) {
  1070. ath10k_err(ar, "failed to init htt: %d\n", status);
  1071. goto err_wmi_detach;
  1072. }
  1073. status = ath10k_htt_tx_alloc(&ar->htt);
  1074. if (status) {
  1075. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1076. goto err_wmi_detach;
  1077. }
  1078. status = ath10k_htt_rx_alloc(&ar->htt);
  1079. if (status) {
  1080. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1081. goto err_htt_tx_detach;
  1082. }
  1083. status = ath10k_hif_start(ar);
  1084. if (status) {
  1085. ath10k_err(ar, "could not start HIF: %d\n", status);
  1086. goto err_htt_rx_detach;
  1087. }
  1088. status = ath10k_htc_wait_target(&ar->htc);
  1089. if (status) {
  1090. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1091. goto err_hif_stop;
  1092. }
  1093. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1094. status = ath10k_htt_connect(&ar->htt);
  1095. if (status) {
  1096. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1097. goto err_hif_stop;
  1098. }
  1099. }
  1100. status = ath10k_wmi_connect(ar);
  1101. if (status) {
  1102. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1103. goto err_hif_stop;
  1104. }
  1105. status = ath10k_htc_start(&ar->htc);
  1106. if (status) {
  1107. ath10k_err(ar, "failed to start htc: %d\n", status);
  1108. goto err_hif_stop;
  1109. }
  1110. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1111. status = ath10k_wmi_wait_for_service_ready(ar);
  1112. if (status) {
  1113. ath10k_warn(ar, "wmi service ready event not received");
  1114. goto err_hif_stop;
  1115. }
  1116. }
  1117. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1118. ar->hw->wiphy->fw_version);
  1119. status = ath10k_wmi_cmd_init(ar);
  1120. if (status) {
  1121. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1122. status);
  1123. goto err_hif_stop;
  1124. }
  1125. status = ath10k_wmi_wait_for_unified_ready(ar);
  1126. if (status) {
  1127. ath10k_err(ar, "wmi unified ready event not received\n");
  1128. goto err_hif_stop;
  1129. }
  1130. /* If firmware indicates Full Rx Reorder support it must be used in a
  1131. * slightly different manner. Let HTT code know.
  1132. */
  1133. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1134. ar->wmi.svc_map));
  1135. status = ath10k_htt_rx_ring_refill(ar);
  1136. if (status) {
  1137. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1138. goto err_hif_stop;
  1139. }
  1140. /* we don't care about HTT in UTF mode */
  1141. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1142. status = ath10k_htt_setup(&ar->htt);
  1143. if (status) {
  1144. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1145. goto err_hif_stop;
  1146. }
  1147. }
  1148. status = ath10k_debug_start(ar);
  1149. if (status)
  1150. goto err_hif_stop;
  1151. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1152. INIT_LIST_HEAD(&ar->arvifs);
  1153. return 0;
  1154. err_hif_stop:
  1155. ath10k_hif_stop(ar);
  1156. err_htt_rx_detach:
  1157. ath10k_htt_rx_free(&ar->htt);
  1158. err_htt_tx_detach:
  1159. ath10k_htt_tx_free(&ar->htt);
  1160. err_wmi_detach:
  1161. ath10k_wmi_detach(ar);
  1162. err:
  1163. return status;
  1164. }
  1165. EXPORT_SYMBOL(ath10k_core_start);
  1166. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1167. {
  1168. int ret;
  1169. unsigned long time_left;
  1170. reinit_completion(&ar->target_suspend);
  1171. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1172. if (ret) {
  1173. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1174. return ret;
  1175. }
  1176. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1177. if (!time_left) {
  1178. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1179. return -ETIMEDOUT;
  1180. }
  1181. return 0;
  1182. }
  1183. void ath10k_core_stop(struct ath10k *ar)
  1184. {
  1185. lockdep_assert_held(&ar->conf_mutex);
  1186. ath10k_debug_stop(ar);
  1187. /* try to suspend target */
  1188. if (ar->state != ATH10K_STATE_RESTARTING &&
  1189. ar->state != ATH10K_STATE_UTF)
  1190. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1191. ath10k_hif_stop(ar);
  1192. ath10k_htt_tx_free(&ar->htt);
  1193. ath10k_htt_rx_free(&ar->htt);
  1194. ath10k_wmi_detach(ar);
  1195. }
  1196. EXPORT_SYMBOL(ath10k_core_stop);
  1197. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1198. * order to know what hw capabilities should be advertised to mac80211 it is
  1199. * necessary to load the firmware (and tear it down immediately since start
  1200. * hook will try to init it again) before registering */
  1201. static int ath10k_core_probe_fw(struct ath10k *ar)
  1202. {
  1203. struct bmi_target_info target_info;
  1204. int ret = 0;
  1205. ret = ath10k_hif_power_up(ar);
  1206. if (ret) {
  1207. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1208. return ret;
  1209. }
  1210. memset(&target_info, 0, sizeof(target_info));
  1211. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1212. if (ret) {
  1213. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1214. goto err_power_down;
  1215. }
  1216. ar->target_version = target_info.version;
  1217. ar->hw->wiphy->hw_version = target_info.version;
  1218. ret = ath10k_init_hw_params(ar);
  1219. if (ret) {
  1220. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1221. goto err_power_down;
  1222. }
  1223. ret = ath10k_core_fetch_firmware_files(ar);
  1224. if (ret) {
  1225. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1226. goto err_power_down;
  1227. }
  1228. ret = ath10k_core_init_firmware_features(ar);
  1229. if (ret) {
  1230. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1231. ret);
  1232. goto err_free_firmware_files;
  1233. }
  1234. ret = ath10k_swap_code_seg_init(ar);
  1235. if (ret) {
  1236. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1237. ret);
  1238. goto err_free_firmware_files;
  1239. }
  1240. mutex_lock(&ar->conf_mutex);
  1241. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL);
  1242. if (ret) {
  1243. ath10k_err(ar, "could not init core (%d)\n", ret);
  1244. goto err_unlock;
  1245. }
  1246. ath10k_print_driver_info(ar);
  1247. ath10k_core_stop(ar);
  1248. mutex_unlock(&ar->conf_mutex);
  1249. ath10k_hif_power_down(ar);
  1250. return 0;
  1251. err_unlock:
  1252. mutex_unlock(&ar->conf_mutex);
  1253. err_free_firmware_files:
  1254. ath10k_core_free_firmware_files(ar);
  1255. err_power_down:
  1256. ath10k_hif_power_down(ar);
  1257. return ret;
  1258. }
  1259. static void ath10k_core_register_work(struct work_struct *work)
  1260. {
  1261. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1262. int status;
  1263. status = ath10k_core_probe_fw(ar);
  1264. if (status) {
  1265. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1266. goto err;
  1267. }
  1268. status = ath10k_mac_register(ar);
  1269. if (status) {
  1270. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1271. goto err_release_fw;
  1272. }
  1273. status = ath10k_debug_register(ar);
  1274. if (status) {
  1275. ath10k_err(ar, "unable to initialize debugfs\n");
  1276. goto err_unregister_mac;
  1277. }
  1278. status = ath10k_spectral_create(ar);
  1279. if (status) {
  1280. ath10k_err(ar, "failed to initialize spectral\n");
  1281. goto err_debug_destroy;
  1282. }
  1283. status = ath10k_thermal_register(ar);
  1284. if (status) {
  1285. ath10k_err(ar, "could not register thermal device: %d\n",
  1286. status);
  1287. goto err_spectral_destroy;
  1288. }
  1289. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1290. return;
  1291. err_spectral_destroy:
  1292. ath10k_spectral_destroy(ar);
  1293. err_debug_destroy:
  1294. ath10k_debug_destroy(ar);
  1295. err_unregister_mac:
  1296. ath10k_mac_unregister(ar);
  1297. err_release_fw:
  1298. ath10k_core_free_firmware_files(ar);
  1299. err:
  1300. /* TODO: It's probably a good idea to release device from the driver
  1301. * but calling device_release_driver() here will cause a deadlock.
  1302. */
  1303. return;
  1304. }
  1305. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1306. {
  1307. ar->chip_id = chip_id;
  1308. queue_work(ar->workqueue, &ar->register_work);
  1309. return 0;
  1310. }
  1311. EXPORT_SYMBOL(ath10k_core_register);
  1312. void ath10k_core_unregister(struct ath10k *ar)
  1313. {
  1314. cancel_work_sync(&ar->register_work);
  1315. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1316. return;
  1317. ath10k_thermal_unregister(ar);
  1318. /* Stop spectral before unregistering from mac80211 to remove the
  1319. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1320. * would be already be free'd recursively, leading to a double free.
  1321. */
  1322. ath10k_spectral_destroy(ar);
  1323. /* We must unregister from mac80211 before we stop HTC and HIF.
  1324. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1325. * unhappy about callback failures. */
  1326. ath10k_mac_unregister(ar);
  1327. ath10k_testmode_destroy(ar);
  1328. ath10k_core_free_firmware_files(ar);
  1329. ath10k_debug_unregister(ar);
  1330. }
  1331. EXPORT_SYMBOL(ath10k_core_unregister);
  1332. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1333. enum ath10k_bus bus,
  1334. enum ath10k_hw_rev hw_rev,
  1335. const struct ath10k_hif_ops *hif_ops)
  1336. {
  1337. struct ath10k *ar;
  1338. int ret;
  1339. ar = ath10k_mac_create(priv_size);
  1340. if (!ar)
  1341. return NULL;
  1342. ar->ath_common.priv = ar;
  1343. ar->ath_common.hw = ar->hw;
  1344. ar->dev = dev;
  1345. ar->hw_rev = hw_rev;
  1346. ar->hif.ops = hif_ops;
  1347. ar->hif.bus = bus;
  1348. switch (hw_rev) {
  1349. case ATH10K_HW_QCA988X:
  1350. ar->regs = &qca988x_regs;
  1351. ar->hw_values = &qca988x_values;
  1352. break;
  1353. case ATH10K_HW_QCA6174:
  1354. ar->regs = &qca6174_regs;
  1355. ar->hw_values = &qca6174_values;
  1356. break;
  1357. case ATH10K_HW_QCA99X0:
  1358. ar->regs = &qca99x0_regs;
  1359. ar->hw_values = &qca99x0_values;
  1360. break;
  1361. default:
  1362. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1363. hw_rev);
  1364. ret = -ENOTSUPP;
  1365. goto err_free_mac;
  1366. }
  1367. init_completion(&ar->scan.started);
  1368. init_completion(&ar->scan.completed);
  1369. init_completion(&ar->scan.on_channel);
  1370. init_completion(&ar->target_suspend);
  1371. init_completion(&ar->wow.wakeup_completed);
  1372. init_completion(&ar->install_key_done);
  1373. init_completion(&ar->vdev_setup_done);
  1374. init_completion(&ar->thermal.wmi_sync);
  1375. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1376. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1377. if (!ar->workqueue)
  1378. goto err_free_mac;
  1379. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1380. if (!ar->workqueue_aux)
  1381. goto err_free_wq;
  1382. mutex_init(&ar->conf_mutex);
  1383. spin_lock_init(&ar->data_lock);
  1384. INIT_LIST_HEAD(&ar->peers);
  1385. init_waitqueue_head(&ar->peer_mapping_wq);
  1386. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1387. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1388. init_completion(&ar->offchan_tx_completed);
  1389. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1390. skb_queue_head_init(&ar->offchan_tx_queue);
  1391. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1392. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1393. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1394. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1395. ret = ath10k_debug_create(ar);
  1396. if (ret)
  1397. goto err_free_aux_wq;
  1398. return ar;
  1399. err_free_aux_wq:
  1400. destroy_workqueue(ar->workqueue_aux);
  1401. err_free_wq:
  1402. destroy_workqueue(ar->workqueue);
  1403. err_free_mac:
  1404. ath10k_mac_destroy(ar);
  1405. return NULL;
  1406. }
  1407. EXPORT_SYMBOL(ath10k_core_create);
  1408. void ath10k_core_destroy(struct ath10k *ar)
  1409. {
  1410. flush_workqueue(ar->workqueue);
  1411. destroy_workqueue(ar->workqueue);
  1412. flush_workqueue(ar->workqueue_aux);
  1413. destroy_workqueue(ar->workqueue_aux);
  1414. ath10k_debug_destroy(ar);
  1415. ath10k_mac_destroy(ar);
  1416. }
  1417. EXPORT_SYMBOL(ath10k_core_destroy);
  1418. MODULE_AUTHOR("Qualcomm Atheros");
  1419. MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
  1420. MODULE_LICENSE("Dual BSD/GPL");