smsc75xx.c 56 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc75xx.h"
  32. #define SMSC_CHIPNAME "smsc75xx"
  33. #define SMSC_DRIVER_VERSION "1.0.0"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (9000)
  40. #define LAN75XX_EEPROM_MAGIC (0x7500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC75XX_INTERNAL_PHY_ID (1)
  45. #define SMSC75XX_TX_OVERHEAD (8)
  46. #define MAX_RX_FIFO_SIZE (20 * 1024)
  47. #define MAX_TX_FIFO_SIZE (12 * 1024)
  48. #define USB_VENDOR_ID_SMSC (0x0424)
  49. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  50. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  51. #define RXW_PADDING 2
  52. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  53. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  54. #define SUSPEND_SUSPEND0 (0x01)
  55. #define SUSPEND_SUSPEND1 (0x02)
  56. #define SUSPEND_SUSPEND2 (0x04)
  57. #define SUSPEND_SUSPEND3 (0x08)
  58. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  59. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  60. struct smsc75xx_priv {
  61. struct usbnet *dev;
  62. u32 rfe_ctl;
  63. u32 wolopts;
  64. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  65. struct mutex dataport_mutex;
  66. spinlock_t rfe_ctl_lock;
  67. struct work_struct set_multicast;
  68. u8 suspend_flags;
  69. };
  70. struct usb_context {
  71. struct usb_ctrlrequest req;
  72. struct usbnet *dev;
  73. };
  74. static bool turbo_mode = true;
  75. module_param(turbo_mode, bool, 0644);
  76. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  77. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  78. u32 *data, int in_pm)
  79. {
  80. u32 buf;
  81. int ret;
  82. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  83. BUG_ON(!dev);
  84. if (!in_pm)
  85. fn = usbnet_read_cmd;
  86. else
  87. fn = usbnet_read_cmd_nopm;
  88. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  89. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  90. 0, index, &buf, 4);
  91. if (unlikely(ret < 0))
  92. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  93. index, ret);
  94. le32_to_cpus(&buf);
  95. *data = buf;
  96. return ret;
  97. }
  98. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  99. u32 data, int in_pm)
  100. {
  101. u32 buf;
  102. int ret;
  103. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  104. BUG_ON(!dev);
  105. if (!in_pm)
  106. fn = usbnet_write_cmd;
  107. else
  108. fn = usbnet_write_cmd_nopm;
  109. buf = data;
  110. cpu_to_le32s(&buf);
  111. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  112. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  113. 0, index, &buf, 4);
  114. if (unlikely(ret < 0))
  115. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  116. index, ret);
  117. return ret;
  118. }
  119. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  120. u32 *data)
  121. {
  122. return __smsc75xx_read_reg(dev, index, data, 1);
  123. }
  124. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  125. u32 data)
  126. {
  127. return __smsc75xx_write_reg(dev, index, data, 1);
  128. }
  129. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  130. u32 *data)
  131. {
  132. return __smsc75xx_read_reg(dev, index, data, 0);
  133. }
  134. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  135. u32 data)
  136. {
  137. return __smsc75xx_write_reg(dev, index, data, 0);
  138. }
  139. /* Loop until the read is completed with timeout
  140. * called with phy_mutex held */
  141. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  142. int in_pm)
  143. {
  144. unsigned long start_time = jiffies;
  145. u32 val;
  146. int ret;
  147. do {
  148. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  149. if (ret < 0) {
  150. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  151. return ret;
  152. }
  153. if (!(val & MII_ACCESS_BUSY))
  154. return 0;
  155. } while (!time_after(jiffies, start_time + HZ));
  156. return -EIO;
  157. }
  158. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  159. int in_pm)
  160. {
  161. struct usbnet *dev = netdev_priv(netdev);
  162. u32 val, addr;
  163. int ret;
  164. mutex_lock(&dev->phy_mutex);
  165. /* confirm MII not busy */
  166. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  167. if (ret < 0) {
  168. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  169. goto done;
  170. }
  171. /* set the address, index & direction (read from PHY) */
  172. phy_id &= dev->mii.phy_id_mask;
  173. idx &= dev->mii.reg_num_mask;
  174. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  175. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  176. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  177. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  178. if (ret < 0) {
  179. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  180. goto done;
  181. }
  182. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  183. if (ret < 0) {
  184. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  185. goto done;
  186. }
  187. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  188. if (ret < 0) {
  189. netdev_warn(dev->net, "Error reading MII_DATA\n");
  190. goto done;
  191. }
  192. ret = (u16)(val & 0xFFFF);
  193. done:
  194. mutex_unlock(&dev->phy_mutex);
  195. return ret;
  196. }
  197. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  198. int idx, int regval, int in_pm)
  199. {
  200. struct usbnet *dev = netdev_priv(netdev);
  201. u32 val, addr;
  202. int ret;
  203. mutex_lock(&dev->phy_mutex);
  204. /* confirm MII not busy */
  205. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  206. if (ret < 0) {
  207. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  208. goto done;
  209. }
  210. val = regval;
  211. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  212. if (ret < 0) {
  213. netdev_warn(dev->net, "Error writing MII_DATA\n");
  214. goto done;
  215. }
  216. /* set the address, index & direction (write to PHY) */
  217. phy_id &= dev->mii.phy_id_mask;
  218. idx &= dev->mii.reg_num_mask;
  219. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  220. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  221. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  222. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  223. if (ret < 0) {
  224. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  225. goto done;
  226. }
  227. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  228. if (ret < 0) {
  229. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  230. goto done;
  231. }
  232. done:
  233. mutex_unlock(&dev->phy_mutex);
  234. }
  235. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  236. int idx)
  237. {
  238. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  239. }
  240. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  241. int idx, int regval)
  242. {
  243. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  244. }
  245. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  246. {
  247. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  248. }
  249. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  250. int regval)
  251. {
  252. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  253. }
  254. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  255. {
  256. unsigned long start_time = jiffies;
  257. u32 val;
  258. int ret;
  259. do {
  260. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  261. if (ret < 0) {
  262. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  263. return ret;
  264. }
  265. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  266. break;
  267. udelay(40);
  268. } while (!time_after(jiffies, start_time + HZ));
  269. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  270. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  271. return -EIO;
  272. }
  273. return 0;
  274. }
  275. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  276. {
  277. unsigned long start_time = jiffies;
  278. u32 val;
  279. int ret;
  280. do {
  281. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  282. if (ret < 0) {
  283. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  284. return ret;
  285. }
  286. if (!(val & E2P_CMD_BUSY))
  287. return 0;
  288. udelay(40);
  289. } while (!time_after(jiffies, start_time + HZ));
  290. netdev_warn(dev->net, "EEPROM is busy\n");
  291. return -EIO;
  292. }
  293. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  294. u8 *data)
  295. {
  296. u32 val;
  297. int i, ret;
  298. BUG_ON(!dev);
  299. BUG_ON(!data);
  300. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  301. if (ret)
  302. return ret;
  303. for (i = 0; i < length; i++) {
  304. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  305. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  306. if (ret < 0) {
  307. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  308. return ret;
  309. }
  310. ret = smsc75xx_wait_eeprom(dev);
  311. if (ret < 0)
  312. return ret;
  313. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  314. if (ret < 0) {
  315. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  316. return ret;
  317. }
  318. data[i] = val & 0xFF;
  319. offset++;
  320. }
  321. return 0;
  322. }
  323. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  324. u8 *data)
  325. {
  326. u32 val;
  327. int i, ret;
  328. BUG_ON(!dev);
  329. BUG_ON(!data);
  330. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  331. if (ret)
  332. return ret;
  333. /* Issue write/erase enable command */
  334. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  335. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  336. if (ret < 0) {
  337. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  338. return ret;
  339. }
  340. ret = smsc75xx_wait_eeprom(dev);
  341. if (ret < 0)
  342. return ret;
  343. for (i = 0; i < length; i++) {
  344. /* Fill data register */
  345. val = data[i];
  346. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  347. if (ret < 0) {
  348. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  349. return ret;
  350. }
  351. /* Send "write" command */
  352. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  353. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  354. if (ret < 0) {
  355. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  356. return ret;
  357. }
  358. ret = smsc75xx_wait_eeprom(dev);
  359. if (ret < 0)
  360. return ret;
  361. offset++;
  362. }
  363. return 0;
  364. }
  365. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  366. {
  367. int i, ret;
  368. for (i = 0; i < 100; i++) {
  369. u32 dp_sel;
  370. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  371. if (ret < 0) {
  372. netdev_warn(dev->net, "Error reading DP_SEL\n");
  373. return ret;
  374. }
  375. if (dp_sel & DP_SEL_DPRDY)
  376. return 0;
  377. udelay(40);
  378. }
  379. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  380. return -EIO;
  381. }
  382. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  383. u32 length, u32 *buf)
  384. {
  385. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  386. u32 dp_sel;
  387. int i, ret;
  388. mutex_lock(&pdata->dataport_mutex);
  389. ret = smsc75xx_dataport_wait_not_busy(dev);
  390. if (ret < 0) {
  391. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  392. goto done;
  393. }
  394. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  395. if (ret < 0) {
  396. netdev_warn(dev->net, "Error reading DP_SEL\n");
  397. goto done;
  398. }
  399. dp_sel &= ~DP_SEL_RSEL;
  400. dp_sel |= ram_select;
  401. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  402. if (ret < 0) {
  403. netdev_warn(dev->net, "Error writing DP_SEL\n");
  404. goto done;
  405. }
  406. for (i = 0; i < length; i++) {
  407. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  408. if (ret < 0) {
  409. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  410. goto done;
  411. }
  412. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  413. if (ret < 0) {
  414. netdev_warn(dev->net, "Error writing DP_DATA\n");
  415. goto done;
  416. }
  417. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  418. if (ret < 0) {
  419. netdev_warn(dev->net, "Error writing DP_CMD\n");
  420. goto done;
  421. }
  422. ret = smsc75xx_dataport_wait_not_busy(dev);
  423. if (ret < 0) {
  424. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  425. goto done;
  426. }
  427. }
  428. done:
  429. mutex_unlock(&pdata->dataport_mutex);
  430. return ret;
  431. }
  432. /* returns hash bit number for given MAC address */
  433. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  434. {
  435. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  436. }
  437. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  438. {
  439. struct smsc75xx_priv *pdata =
  440. container_of(param, struct smsc75xx_priv, set_multicast);
  441. struct usbnet *dev = pdata->dev;
  442. int ret;
  443. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  444. pdata->rfe_ctl);
  445. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  446. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  447. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  448. if (ret < 0)
  449. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  450. }
  451. static void smsc75xx_set_multicast(struct net_device *netdev)
  452. {
  453. struct usbnet *dev = netdev_priv(netdev);
  454. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  455. unsigned long flags;
  456. int i;
  457. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  458. pdata->rfe_ctl &=
  459. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  460. pdata->rfe_ctl |= RFE_CTL_AB;
  461. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  462. pdata->multicast_hash_table[i] = 0;
  463. if (dev->net->flags & IFF_PROMISC) {
  464. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  465. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  466. } else if (dev->net->flags & IFF_ALLMULTI) {
  467. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  468. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  469. } else if (!netdev_mc_empty(dev->net)) {
  470. struct netdev_hw_addr *ha;
  471. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  472. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  473. netdev_for_each_mc_addr(ha, netdev) {
  474. u32 bitnum = smsc75xx_hash(ha->addr);
  475. pdata->multicast_hash_table[bitnum / 32] |=
  476. (1 << (bitnum % 32));
  477. }
  478. } else {
  479. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  480. pdata->rfe_ctl |= RFE_CTL_DPF;
  481. }
  482. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  483. /* defer register writes to a sleepable context */
  484. schedule_work(&pdata->set_multicast);
  485. }
  486. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  487. u16 lcladv, u16 rmtadv)
  488. {
  489. u32 flow = 0, fct_flow = 0;
  490. int ret;
  491. if (duplex == DUPLEX_FULL) {
  492. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  493. if (cap & FLOW_CTRL_TX) {
  494. flow = (FLOW_TX_FCEN | 0xFFFF);
  495. /* set fct_flow thresholds to 20% and 80% */
  496. fct_flow = (8 << 8) | 32;
  497. }
  498. if (cap & FLOW_CTRL_RX)
  499. flow |= FLOW_RX_FCEN;
  500. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  501. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  502. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  503. } else {
  504. netif_dbg(dev, link, dev->net, "half duplex\n");
  505. }
  506. ret = smsc75xx_write_reg(dev, FLOW, flow);
  507. if (ret < 0) {
  508. netdev_warn(dev->net, "Error writing FLOW\n");
  509. return ret;
  510. }
  511. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  512. if (ret < 0) {
  513. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  514. return ret;
  515. }
  516. return 0;
  517. }
  518. static int smsc75xx_link_reset(struct usbnet *dev)
  519. {
  520. struct mii_if_info *mii = &dev->mii;
  521. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  522. u16 lcladv, rmtadv;
  523. int ret;
  524. /* write to clear phy interrupt status */
  525. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  526. PHY_INT_SRC_CLEAR_ALL);
  527. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  528. if (ret < 0) {
  529. netdev_warn(dev->net, "Error writing INT_STS\n");
  530. return ret;
  531. }
  532. mii_check_media(mii, 1, 1);
  533. mii_ethtool_gset(&dev->mii, &ecmd);
  534. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  535. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  536. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  537. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  538. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  539. }
  540. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  541. {
  542. u32 intdata;
  543. if (urb->actual_length != 4) {
  544. netdev_warn(dev->net, "unexpected urb length %d\n",
  545. urb->actual_length);
  546. return;
  547. }
  548. memcpy(&intdata, urb->transfer_buffer, 4);
  549. le32_to_cpus(&intdata);
  550. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  551. if (intdata & INT_ENP_PHY_INT)
  552. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  553. else
  554. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  555. intdata);
  556. }
  557. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  558. {
  559. return MAX_EEPROM_SIZE;
  560. }
  561. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  562. struct ethtool_eeprom *ee, u8 *data)
  563. {
  564. struct usbnet *dev = netdev_priv(netdev);
  565. ee->magic = LAN75XX_EEPROM_MAGIC;
  566. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  567. }
  568. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  569. struct ethtool_eeprom *ee, u8 *data)
  570. {
  571. struct usbnet *dev = netdev_priv(netdev);
  572. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  573. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  574. ee->magic);
  575. return -EINVAL;
  576. }
  577. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  578. }
  579. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  580. struct ethtool_wolinfo *wolinfo)
  581. {
  582. struct usbnet *dev = netdev_priv(net);
  583. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  584. wolinfo->supported = SUPPORTED_WAKE;
  585. wolinfo->wolopts = pdata->wolopts;
  586. }
  587. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  588. struct ethtool_wolinfo *wolinfo)
  589. {
  590. struct usbnet *dev = netdev_priv(net);
  591. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  592. int ret;
  593. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  594. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  595. if (ret < 0)
  596. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  597. return ret;
  598. }
  599. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  600. .get_link = usbnet_get_link,
  601. .nway_reset = usbnet_nway_reset,
  602. .get_drvinfo = usbnet_get_drvinfo,
  603. .get_msglevel = usbnet_get_msglevel,
  604. .set_msglevel = usbnet_set_msglevel,
  605. .get_settings = usbnet_get_settings,
  606. .set_settings = usbnet_set_settings,
  607. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  608. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  609. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  610. .get_wol = smsc75xx_ethtool_get_wol,
  611. .set_wol = smsc75xx_ethtool_set_wol,
  612. };
  613. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  614. {
  615. struct usbnet *dev = netdev_priv(netdev);
  616. if (!netif_running(netdev))
  617. return -EINVAL;
  618. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  619. }
  620. static void smsc75xx_init_mac_address(struct usbnet *dev)
  621. {
  622. /* try reading mac address from EEPROM */
  623. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  624. dev->net->dev_addr) == 0) {
  625. if (is_valid_ether_addr(dev->net->dev_addr)) {
  626. /* eeprom values are valid so use them */
  627. netif_dbg(dev, ifup, dev->net,
  628. "MAC address read from EEPROM\n");
  629. return;
  630. }
  631. }
  632. /* no eeprom, or eeprom values are invalid. generate random MAC */
  633. eth_hw_addr_random(dev->net);
  634. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  635. }
  636. static int smsc75xx_set_mac_address(struct usbnet *dev)
  637. {
  638. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  639. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  640. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  641. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  642. if (ret < 0) {
  643. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  644. return ret;
  645. }
  646. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  647. if (ret < 0) {
  648. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  649. return ret;
  650. }
  651. addr_hi |= ADDR_FILTX_FB_VALID;
  652. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  653. if (ret < 0) {
  654. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  655. return ret;
  656. }
  657. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  658. if (ret < 0)
  659. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  660. return ret;
  661. }
  662. static int smsc75xx_phy_initialize(struct usbnet *dev)
  663. {
  664. int bmcr, ret, timeout = 0;
  665. /* Initialize MII structure */
  666. dev->mii.dev = dev->net;
  667. dev->mii.mdio_read = smsc75xx_mdio_read;
  668. dev->mii.mdio_write = smsc75xx_mdio_write;
  669. dev->mii.phy_id_mask = 0x1f;
  670. dev->mii.reg_num_mask = 0x1f;
  671. dev->mii.supports_gmii = 1;
  672. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  673. /* reset phy and wait for reset to complete */
  674. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  675. do {
  676. msleep(10);
  677. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  678. if (bmcr < 0) {
  679. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  680. return bmcr;
  681. }
  682. timeout++;
  683. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  684. if (timeout >= 100) {
  685. netdev_warn(dev->net, "timeout on PHY Reset\n");
  686. return -EIO;
  687. }
  688. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  689. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  690. ADVERTISE_PAUSE_ASYM);
  691. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  692. ADVERTISE_1000FULL);
  693. /* read and write to clear phy interrupt status */
  694. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  695. if (ret < 0) {
  696. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  697. return ret;
  698. }
  699. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  700. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  701. PHY_INT_MASK_DEFAULT);
  702. mii_nway_restart(&dev->mii);
  703. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  704. return 0;
  705. }
  706. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  707. {
  708. int ret = 0;
  709. u32 buf;
  710. bool rxenabled;
  711. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  712. if (ret < 0) {
  713. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  714. return ret;
  715. }
  716. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  717. if (rxenabled) {
  718. buf &= ~MAC_RX_RXEN;
  719. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  720. if (ret < 0) {
  721. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  722. return ret;
  723. }
  724. }
  725. /* add 4 to size for FCS */
  726. buf &= ~MAC_RX_MAX_SIZE;
  727. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  728. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  729. if (ret < 0) {
  730. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  731. return ret;
  732. }
  733. if (rxenabled) {
  734. buf |= MAC_RX_RXEN;
  735. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  736. if (ret < 0) {
  737. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  738. return ret;
  739. }
  740. }
  741. return 0;
  742. }
  743. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  744. {
  745. struct usbnet *dev = netdev_priv(netdev);
  746. int ret;
  747. if (new_mtu > MAX_SINGLE_PACKET_SIZE)
  748. return -EINVAL;
  749. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  750. if (ret < 0) {
  751. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  752. return ret;
  753. }
  754. return usbnet_change_mtu(netdev, new_mtu);
  755. }
  756. /* Enable or disable Rx checksum offload engine */
  757. static int smsc75xx_set_features(struct net_device *netdev,
  758. netdev_features_t features)
  759. {
  760. struct usbnet *dev = netdev_priv(netdev);
  761. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  762. unsigned long flags;
  763. int ret;
  764. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  765. if (features & NETIF_F_RXCSUM)
  766. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  767. else
  768. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  769. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  770. /* it's racing here! */
  771. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  772. if (ret < 0)
  773. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  774. return ret;
  775. }
  776. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  777. {
  778. int timeout = 0;
  779. do {
  780. u32 buf;
  781. int ret;
  782. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  783. if (ret < 0) {
  784. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  785. return ret;
  786. }
  787. if (buf & PMT_CTL_DEV_RDY)
  788. return 0;
  789. msleep(10);
  790. timeout++;
  791. } while (timeout < 100);
  792. netdev_warn(dev->net, "timeout waiting for device ready\n");
  793. return -EIO;
  794. }
  795. static int smsc75xx_reset(struct usbnet *dev)
  796. {
  797. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  798. u32 buf;
  799. int ret = 0, timeout;
  800. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  801. ret = smsc75xx_wait_ready(dev, 0);
  802. if (ret < 0) {
  803. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  804. return ret;
  805. }
  806. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  807. if (ret < 0) {
  808. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  809. return ret;
  810. }
  811. buf |= HW_CFG_LRST;
  812. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  813. if (ret < 0) {
  814. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  815. return ret;
  816. }
  817. timeout = 0;
  818. do {
  819. msleep(10);
  820. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  821. if (ret < 0) {
  822. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  823. return ret;
  824. }
  825. timeout++;
  826. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  827. if (timeout >= 100) {
  828. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  829. return -EIO;
  830. }
  831. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  832. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  833. if (ret < 0) {
  834. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  835. return ret;
  836. }
  837. buf |= PMT_CTL_PHY_RST;
  838. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  839. if (ret < 0) {
  840. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  841. return ret;
  842. }
  843. timeout = 0;
  844. do {
  845. msleep(10);
  846. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  847. if (ret < 0) {
  848. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  849. return ret;
  850. }
  851. timeout++;
  852. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  853. if (timeout >= 100) {
  854. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  855. return -EIO;
  856. }
  857. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  858. ret = smsc75xx_set_mac_address(dev);
  859. if (ret < 0) {
  860. netdev_warn(dev->net, "Failed to set mac address\n");
  861. return ret;
  862. }
  863. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  864. dev->net->dev_addr);
  865. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  866. if (ret < 0) {
  867. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  868. return ret;
  869. }
  870. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  871. buf);
  872. buf |= HW_CFG_BIR;
  873. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  874. if (ret < 0) {
  875. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  876. return ret;
  877. }
  878. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  879. if (ret < 0) {
  880. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  881. return ret;
  882. }
  883. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  884. buf);
  885. if (!turbo_mode) {
  886. buf = 0;
  887. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  888. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  889. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  890. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  891. } else {
  892. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  893. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  894. }
  895. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  896. (ulong)dev->rx_urb_size);
  897. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  898. if (ret < 0) {
  899. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  900. return ret;
  901. }
  902. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  903. if (ret < 0) {
  904. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  905. return ret;
  906. }
  907. netif_dbg(dev, ifup, dev->net,
  908. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  909. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  910. if (ret < 0) {
  911. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  912. return ret;
  913. }
  914. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  915. if (ret < 0) {
  916. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  917. return ret;
  918. }
  919. netif_dbg(dev, ifup, dev->net,
  920. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  921. if (turbo_mode) {
  922. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  923. if (ret < 0) {
  924. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  925. return ret;
  926. }
  927. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  928. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  929. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  930. if (ret < 0) {
  931. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  932. return ret;
  933. }
  934. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  935. if (ret < 0) {
  936. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  937. return ret;
  938. }
  939. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  940. }
  941. /* set FIFO sizes */
  942. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  943. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  944. if (ret < 0) {
  945. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  946. return ret;
  947. }
  948. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  949. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  950. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  951. if (ret < 0) {
  952. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  953. return ret;
  954. }
  955. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  956. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  957. if (ret < 0) {
  958. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  959. return ret;
  960. }
  961. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  962. if (ret < 0) {
  963. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  964. return ret;
  965. }
  966. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  967. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  968. if (ret < 0) {
  969. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  970. return ret;
  971. }
  972. /* only set default GPIO/LED settings if no EEPROM is detected */
  973. if (!(buf & E2P_CMD_LOADED)) {
  974. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  975. if (ret < 0) {
  976. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  977. return ret;
  978. }
  979. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  980. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  981. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  982. if (ret < 0) {
  983. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  984. return ret;
  985. }
  986. }
  987. ret = smsc75xx_write_reg(dev, FLOW, 0);
  988. if (ret < 0) {
  989. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  990. return ret;
  991. }
  992. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  993. if (ret < 0) {
  994. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  995. return ret;
  996. }
  997. /* Don't need rfe_ctl_lock during initialisation */
  998. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  999. if (ret < 0) {
  1000. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1001. return ret;
  1002. }
  1003. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1004. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1005. if (ret < 0) {
  1006. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1007. return ret;
  1008. }
  1009. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1010. if (ret < 0) {
  1011. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1012. return ret;
  1013. }
  1014. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1015. pdata->rfe_ctl);
  1016. /* Enable or disable checksum offload engines */
  1017. smsc75xx_set_features(dev->net, dev->net->features);
  1018. smsc75xx_set_multicast(dev->net);
  1019. ret = smsc75xx_phy_initialize(dev);
  1020. if (ret < 0) {
  1021. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1022. return ret;
  1023. }
  1024. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1025. if (ret < 0) {
  1026. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1027. return ret;
  1028. }
  1029. /* enable PHY interrupts */
  1030. buf |= INT_ENP_PHY_INT;
  1031. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1032. if (ret < 0) {
  1033. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1034. return ret;
  1035. }
  1036. /* allow mac to detect speed and duplex from phy */
  1037. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1038. if (ret < 0) {
  1039. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1040. return ret;
  1041. }
  1042. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1043. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1044. if (ret < 0) {
  1045. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1046. return ret;
  1047. }
  1048. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1049. if (ret < 0) {
  1050. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1051. return ret;
  1052. }
  1053. buf |= MAC_TX_TXEN;
  1054. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1055. if (ret < 0) {
  1056. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1057. return ret;
  1058. }
  1059. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1060. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1061. if (ret < 0) {
  1062. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1063. return ret;
  1064. }
  1065. buf |= FCT_TX_CTL_EN;
  1066. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1067. if (ret < 0) {
  1068. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1069. return ret;
  1070. }
  1071. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1072. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1073. if (ret < 0) {
  1074. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1075. return ret;
  1076. }
  1077. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1078. if (ret < 0) {
  1079. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1080. return ret;
  1081. }
  1082. buf |= MAC_RX_RXEN;
  1083. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1084. if (ret < 0) {
  1085. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1086. return ret;
  1087. }
  1088. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1089. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1090. if (ret < 0) {
  1091. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1092. return ret;
  1093. }
  1094. buf |= FCT_RX_CTL_EN;
  1095. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1096. if (ret < 0) {
  1097. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1098. return ret;
  1099. }
  1100. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1101. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1102. return 0;
  1103. }
  1104. static const struct net_device_ops smsc75xx_netdev_ops = {
  1105. .ndo_open = usbnet_open,
  1106. .ndo_stop = usbnet_stop,
  1107. .ndo_start_xmit = usbnet_start_xmit,
  1108. .ndo_tx_timeout = usbnet_tx_timeout,
  1109. .ndo_change_mtu = smsc75xx_change_mtu,
  1110. .ndo_set_mac_address = eth_mac_addr,
  1111. .ndo_validate_addr = eth_validate_addr,
  1112. .ndo_do_ioctl = smsc75xx_ioctl,
  1113. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1114. .ndo_set_features = smsc75xx_set_features,
  1115. };
  1116. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1117. {
  1118. struct smsc75xx_priv *pdata = NULL;
  1119. int ret;
  1120. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1121. ret = usbnet_get_endpoints(dev, intf);
  1122. if (ret < 0) {
  1123. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1124. return ret;
  1125. }
  1126. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1127. GFP_KERNEL);
  1128. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1129. if (!pdata)
  1130. return -ENOMEM;
  1131. pdata->dev = dev;
  1132. spin_lock_init(&pdata->rfe_ctl_lock);
  1133. mutex_init(&pdata->dataport_mutex);
  1134. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1135. if (DEFAULT_TX_CSUM_ENABLE)
  1136. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1137. if (DEFAULT_RX_CSUM_ENABLE)
  1138. dev->net->features |= NETIF_F_RXCSUM;
  1139. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1140. NETIF_F_RXCSUM;
  1141. ret = smsc75xx_wait_ready(dev, 0);
  1142. if (ret < 0) {
  1143. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1144. return ret;
  1145. }
  1146. smsc75xx_init_mac_address(dev);
  1147. /* Init all registers */
  1148. ret = smsc75xx_reset(dev);
  1149. if (ret < 0) {
  1150. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1151. return ret;
  1152. }
  1153. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1154. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1155. dev->net->flags |= IFF_MULTICAST;
  1156. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1157. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1158. return 0;
  1159. }
  1160. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1161. {
  1162. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1163. if (pdata) {
  1164. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1165. kfree(pdata);
  1166. pdata = NULL;
  1167. dev->data[0] = 0;
  1168. }
  1169. }
  1170. static u16 smsc_crc(const u8 *buffer, size_t len)
  1171. {
  1172. return bitrev16(crc16(0xFFFF, buffer, len));
  1173. }
  1174. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1175. u32 wuf_mask1)
  1176. {
  1177. int cfg_base = WUF_CFGX + filter * 4;
  1178. int mask_base = WUF_MASKX + filter * 16;
  1179. int ret;
  1180. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1181. if (ret < 0) {
  1182. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1183. return ret;
  1184. }
  1185. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1186. if (ret < 0) {
  1187. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1188. return ret;
  1189. }
  1190. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1191. if (ret < 0) {
  1192. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1193. return ret;
  1194. }
  1195. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1196. if (ret < 0) {
  1197. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1198. return ret;
  1199. }
  1200. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1201. if (ret < 0) {
  1202. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1203. return ret;
  1204. }
  1205. return 0;
  1206. }
  1207. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1208. {
  1209. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1210. u32 val;
  1211. int ret;
  1212. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1213. if (ret < 0) {
  1214. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1215. return ret;
  1216. }
  1217. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1218. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1219. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1220. if (ret < 0) {
  1221. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1222. return ret;
  1223. }
  1224. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1225. return 0;
  1226. }
  1227. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1228. {
  1229. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1230. u32 val;
  1231. int ret;
  1232. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1233. if (ret < 0) {
  1234. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1235. return ret;
  1236. }
  1237. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1238. val |= PMT_CTL_SUS_MODE_1;
  1239. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1240. if (ret < 0) {
  1241. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1242. return ret;
  1243. }
  1244. /* clear wol status, enable energy detection */
  1245. val &= ~PMT_CTL_WUPS;
  1246. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1247. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1248. if (ret < 0) {
  1249. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1250. return ret;
  1251. }
  1252. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1253. return 0;
  1254. }
  1255. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1256. {
  1257. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1258. u32 val;
  1259. int ret;
  1260. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1261. if (ret < 0) {
  1262. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1263. return ret;
  1264. }
  1265. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1266. val |= PMT_CTL_SUS_MODE_2;
  1267. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1268. if (ret < 0) {
  1269. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1270. return ret;
  1271. }
  1272. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1273. return 0;
  1274. }
  1275. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1276. {
  1277. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1278. u32 val;
  1279. int ret;
  1280. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1281. if (ret < 0) {
  1282. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1283. return ret;
  1284. }
  1285. if (val & FCT_RX_CTL_RXUSED) {
  1286. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1287. return -EBUSY;
  1288. }
  1289. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1290. if (ret < 0) {
  1291. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1292. return ret;
  1293. }
  1294. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1295. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1296. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1297. if (ret < 0) {
  1298. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1299. return ret;
  1300. }
  1301. /* clear wol status */
  1302. val &= ~PMT_CTL_WUPS;
  1303. val |= PMT_CTL_WUPS_WOL;
  1304. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1305. if (ret < 0) {
  1306. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1307. return ret;
  1308. }
  1309. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1310. return 0;
  1311. }
  1312. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1313. {
  1314. struct mii_if_info *mii = &dev->mii;
  1315. int ret;
  1316. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1317. /* read to clear */
  1318. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1319. if (ret < 0) {
  1320. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1321. return ret;
  1322. }
  1323. /* enable interrupt source */
  1324. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1325. if (ret < 0) {
  1326. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1327. return ret;
  1328. }
  1329. ret |= mask;
  1330. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1331. return 0;
  1332. }
  1333. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1334. {
  1335. struct mii_if_info *mii = &dev->mii;
  1336. int ret;
  1337. /* first, a dummy read, needed to latch some MII phys */
  1338. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1339. if (ret < 0) {
  1340. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1341. return ret;
  1342. }
  1343. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1344. if (ret < 0) {
  1345. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1346. return ret;
  1347. }
  1348. return !!(ret & BMSR_LSTATUS);
  1349. }
  1350. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1351. {
  1352. int ret;
  1353. if (!netif_running(dev->net)) {
  1354. /* interface is ifconfig down so fully power down hw */
  1355. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1356. return smsc75xx_enter_suspend2(dev);
  1357. }
  1358. if (!link_up) {
  1359. /* link is down so enter EDPD mode */
  1360. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1361. /* enable PHY wakeup events for if cable is attached */
  1362. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1363. PHY_INT_MASK_ANEG_COMP);
  1364. if (ret < 0) {
  1365. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1366. return ret;
  1367. }
  1368. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1369. return smsc75xx_enter_suspend1(dev);
  1370. }
  1371. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1372. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1373. PHY_INT_MASK_LINK_DOWN);
  1374. if (ret < 0) {
  1375. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1376. return ret;
  1377. }
  1378. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1379. return smsc75xx_enter_suspend3(dev);
  1380. }
  1381. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1382. {
  1383. struct usbnet *dev = usb_get_intfdata(intf);
  1384. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1385. u32 val, link_up;
  1386. int ret;
  1387. ret = usbnet_suspend(intf, message);
  1388. if (ret < 0) {
  1389. netdev_warn(dev->net, "usbnet_suspend error\n");
  1390. return ret;
  1391. }
  1392. if (pdata->suspend_flags) {
  1393. netdev_warn(dev->net, "error during last resume\n");
  1394. pdata->suspend_flags = 0;
  1395. }
  1396. /* determine if link is up using only _nopm functions */
  1397. link_up = smsc75xx_link_ok_nopm(dev);
  1398. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1399. ret = smsc75xx_autosuspend(dev, link_up);
  1400. goto done;
  1401. }
  1402. /* if we get this far we're not autosuspending */
  1403. /* if no wol options set, or if link is down and we're not waking on
  1404. * PHY activity, enter lowest power SUSPEND2 mode
  1405. */
  1406. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1407. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1408. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1409. /* disable energy detect (link up) & wake up events */
  1410. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1411. if (ret < 0) {
  1412. netdev_warn(dev->net, "Error reading WUCSR\n");
  1413. goto done;
  1414. }
  1415. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1416. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1417. if (ret < 0) {
  1418. netdev_warn(dev->net, "Error writing WUCSR\n");
  1419. goto done;
  1420. }
  1421. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1422. if (ret < 0) {
  1423. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1424. goto done;
  1425. }
  1426. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1427. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1428. if (ret < 0) {
  1429. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1430. goto done;
  1431. }
  1432. ret = smsc75xx_enter_suspend2(dev);
  1433. goto done;
  1434. }
  1435. if (pdata->wolopts & WAKE_PHY) {
  1436. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1437. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1438. if (ret < 0) {
  1439. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1440. goto done;
  1441. }
  1442. /* if link is down then configure EDPD and enter SUSPEND1,
  1443. * otherwise enter SUSPEND0 below
  1444. */
  1445. if (!link_up) {
  1446. struct mii_if_info *mii = &dev->mii;
  1447. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1448. /* enable energy detect power-down mode */
  1449. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1450. PHY_MODE_CTRL_STS);
  1451. if (ret < 0) {
  1452. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1453. goto done;
  1454. }
  1455. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1456. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1457. PHY_MODE_CTRL_STS, ret);
  1458. /* enter SUSPEND1 mode */
  1459. ret = smsc75xx_enter_suspend1(dev);
  1460. goto done;
  1461. }
  1462. }
  1463. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1464. int i, filter = 0;
  1465. /* disable all filters */
  1466. for (i = 0; i < WUF_NUM; i++) {
  1467. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1468. if (ret < 0) {
  1469. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1470. goto done;
  1471. }
  1472. }
  1473. if (pdata->wolopts & WAKE_MCAST) {
  1474. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1475. netdev_info(dev->net, "enabling multicast detection\n");
  1476. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1477. | smsc_crc(mcast, 3);
  1478. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1479. if (ret < 0) {
  1480. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1481. goto done;
  1482. }
  1483. }
  1484. if (pdata->wolopts & WAKE_ARP) {
  1485. const u8 arp[] = {0x08, 0x06};
  1486. netdev_info(dev->net, "enabling ARP detection\n");
  1487. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1488. | smsc_crc(arp, 2);
  1489. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1490. if (ret < 0) {
  1491. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1492. goto done;
  1493. }
  1494. }
  1495. /* clear any pending pattern match packet status */
  1496. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1497. if (ret < 0) {
  1498. netdev_warn(dev->net, "Error reading WUCSR\n");
  1499. goto done;
  1500. }
  1501. val |= WUCSR_WUFR;
  1502. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1503. if (ret < 0) {
  1504. netdev_warn(dev->net, "Error writing WUCSR\n");
  1505. goto done;
  1506. }
  1507. netdev_info(dev->net, "enabling packet match detection\n");
  1508. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1509. if (ret < 0) {
  1510. netdev_warn(dev->net, "Error reading WUCSR\n");
  1511. goto done;
  1512. }
  1513. val |= WUCSR_WUEN;
  1514. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1515. if (ret < 0) {
  1516. netdev_warn(dev->net, "Error writing WUCSR\n");
  1517. goto done;
  1518. }
  1519. } else {
  1520. netdev_info(dev->net, "disabling packet match detection\n");
  1521. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1522. if (ret < 0) {
  1523. netdev_warn(dev->net, "Error reading WUCSR\n");
  1524. goto done;
  1525. }
  1526. val &= ~WUCSR_WUEN;
  1527. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1528. if (ret < 0) {
  1529. netdev_warn(dev->net, "Error writing WUCSR\n");
  1530. goto done;
  1531. }
  1532. }
  1533. /* disable magic, bcast & unicast wakeup sources */
  1534. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1535. if (ret < 0) {
  1536. netdev_warn(dev->net, "Error reading WUCSR\n");
  1537. goto done;
  1538. }
  1539. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1540. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1541. if (ret < 0) {
  1542. netdev_warn(dev->net, "Error writing WUCSR\n");
  1543. goto done;
  1544. }
  1545. if (pdata->wolopts & WAKE_PHY) {
  1546. netdev_info(dev->net, "enabling PHY wakeup\n");
  1547. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1548. if (ret < 0) {
  1549. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1550. goto done;
  1551. }
  1552. /* clear wol status, enable energy detection */
  1553. val &= ~PMT_CTL_WUPS;
  1554. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1555. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1556. if (ret < 0) {
  1557. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1558. goto done;
  1559. }
  1560. }
  1561. if (pdata->wolopts & WAKE_MAGIC) {
  1562. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1563. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1564. if (ret < 0) {
  1565. netdev_warn(dev->net, "Error reading WUCSR\n");
  1566. goto done;
  1567. }
  1568. /* clear any pending magic packet status */
  1569. val |= WUCSR_MPR | WUCSR_MPEN;
  1570. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1571. if (ret < 0) {
  1572. netdev_warn(dev->net, "Error writing WUCSR\n");
  1573. goto done;
  1574. }
  1575. }
  1576. if (pdata->wolopts & WAKE_BCAST) {
  1577. netdev_info(dev->net, "enabling broadcast detection\n");
  1578. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1579. if (ret < 0) {
  1580. netdev_warn(dev->net, "Error reading WUCSR\n");
  1581. goto done;
  1582. }
  1583. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1584. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1585. if (ret < 0) {
  1586. netdev_warn(dev->net, "Error writing WUCSR\n");
  1587. goto done;
  1588. }
  1589. }
  1590. if (pdata->wolopts & WAKE_UCAST) {
  1591. netdev_info(dev->net, "enabling unicast detection\n");
  1592. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1593. if (ret < 0) {
  1594. netdev_warn(dev->net, "Error reading WUCSR\n");
  1595. goto done;
  1596. }
  1597. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1598. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1599. if (ret < 0) {
  1600. netdev_warn(dev->net, "Error writing WUCSR\n");
  1601. goto done;
  1602. }
  1603. }
  1604. /* enable receiver to enable frame reception */
  1605. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1606. if (ret < 0) {
  1607. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1608. goto done;
  1609. }
  1610. val |= MAC_RX_RXEN;
  1611. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1612. if (ret < 0) {
  1613. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1614. goto done;
  1615. }
  1616. /* some wol options are enabled, so enter SUSPEND0 */
  1617. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1618. ret = smsc75xx_enter_suspend0(dev);
  1619. done:
  1620. /*
  1621. * TODO: resume() might need to handle the suspend failure
  1622. * in system sleep
  1623. */
  1624. if (ret && PMSG_IS_AUTO(message))
  1625. usbnet_resume(intf);
  1626. return ret;
  1627. }
  1628. static int smsc75xx_resume(struct usb_interface *intf)
  1629. {
  1630. struct usbnet *dev = usb_get_intfdata(intf);
  1631. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1632. u8 suspend_flags = pdata->suspend_flags;
  1633. int ret;
  1634. u32 val;
  1635. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1636. /* do this first to ensure it's cleared even in error case */
  1637. pdata->suspend_flags = 0;
  1638. if (suspend_flags & SUSPEND_ALLMODES) {
  1639. /* Disable wakeup sources */
  1640. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1641. if (ret < 0) {
  1642. netdev_warn(dev->net, "Error reading WUCSR\n");
  1643. return ret;
  1644. }
  1645. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1646. | WUCSR_BCST_EN);
  1647. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1648. if (ret < 0) {
  1649. netdev_warn(dev->net, "Error writing WUCSR\n");
  1650. return ret;
  1651. }
  1652. /* clear wake-up status */
  1653. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1654. if (ret < 0) {
  1655. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1656. return ret;
  1657. }
  1658. val &= ~PMT_CTL_WOL_EN;
  1659. val |= PMT_CTL_WUPS;
  1660. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1661. if (ret < 0) {
  1662. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1663. return ret;
  1664. }
  1665. }
  1666. if (suspend_flags & SUSPEND_SUSPEND2) {
  1667. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1668. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1669. if (ret < 0) {
  1670. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1671. return ret;
  1672. }
  1673. val |= PMT_CTL_PHY_PWRUP;
  1674. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1675. if (ret < 0) {
  1676. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1677. return ret;
  1678. }
  1679. }
  1680. ret = smsc75xx_wait_ready(dev, 1);
  1681. if (ret < 0) {
  1682. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1683. return ret;
  1684. }
  1685. return usbnet_resume(intf);
  1686. }
  1687. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1688. u32 rx_cmd_a, u32 rx_cmd_b)
  1689. {
  1690. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1691. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1692. skb->ip_summed = CHECKSUM_NONE;
  1693. } else {
  1694. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1695. skb->ip_summed = CHECKSUM_COMPLETE;
  1696. }
  1697. }
  1698. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1699. {
  1700. /* This check is no longer done by usbnet */
  1701. if (skb->len < dev->net->hard_header_len)
  1702. return 0;
  1703. while (skb->len > 0) {
  1704. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1705. struct sk_buff *ax_skb;
  1706. unsigned char *packet;
  1707. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1708. le32_to_cpus(&rx_cmd_a);
  1709. skb_pull(skb, 4);
  1710. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1711. le32_to_cpus(&rx_cmd_b);
  1712. skb_pull(skb, 4 + RXW_PADDING);
  1713. packet = skb->data;
  1714. /* get the packet length */
  1715. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1716. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1717. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1718. netif_dbg(dev, rx_err, dev->net,
  1719. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1720. dev->net->stats.rx_errors++;
  1721. dev->net->stats.rx_dropped++;
  1722. if (rx_cmd_a & RX_CMD_A_FCS)
  1723. dev->net->stats.rx_crc_errors++;
  1724. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1725. dev->net->stats.rx_frame_errors++;
  1726. } else {
  1727. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1728. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1729. netif_dbg(dev, rx_err, dev->net,
  1730. "size err rx_cmd_a=0x%08x\n",
  1731. rx_cmd_a);
  1732. return 0;
  1733. }
  1734. /* last frame in this batch */
  1735. if (skb->len == size) {
  1736. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1737. rx_cmd_b);
  1738. skb_trim(skb, skb->len - 4); /* remove fcs */
  1739. skb->truesize = size + sizeof(struct sk_buff);
  1740. return 1;
  1741. }
  1742. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1743. if (unlikely(!ax_skb)) {
  1744. netdev_warn(dev->net, "Error allocating skb\n");
  1745. return 0;
  1746. }
  1747. ax_skb->len = size;
  1748. ax_skb->data = packet;
  1749. skb_set_tail_pointer(ax_skb, size);
  1750. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1751. rx_cmd_b);
  1752. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1753. ax_skb->truesize = size + sizeof(struct sk_buff);
  1754. usbnet_skb_return(dev, ax_skb);
  1755. }
  1756. skb_pull(skb, size);
  1757. /* padding bytes before the next frame starts */
  1758. if (skb->len)
  1759. skb_pull(skb, align_count);
  1760. }
  1761. if (unlikely(skb->len < 0)) {
  1762. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1763. return 0;
  1764. }
  1765. return 1;
  1766. }
  1767. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1768. struct sk_buff *skb, gfp_t flags)
  1769. {
  1770. u32 tx_cmd_a, tx_cmd_b;
  1771. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1772. struct sk_buff *skb2 =
  1773. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1774. dev_kfree_skb_any(skb);
  1775. skb = skb2;
  1776. if (!skb)
  1777. return NULL;
  1778. }
  1779. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1780. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1781. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1782. if (skb_is_gso(skb)) {
  1783. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1784. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1785. tx_cmd_a |= TX_CMD_A_LSO;
  1786. } else {
  1787. tx_cmd_b = 0;
  1788. }
  1789. skb_push(skb, 4);
  1790. cpu_to_le32s(&tx_cmd_b);
  1791. memcpy(skb->data, &tx_cmd_b, 4);
  1792. skb_push(skb, 4);
  1793. cpu_to_le32s(&tx_cmd_a);
  1794. memcpy(skb->data, &tx_cmd_a, 4);
  1795. return skb;
  1796. }
  1797. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1798. {
  1799. dev->intf->needs_remote_wakeup = on;
  1800. return 0;
  1801. }
  1802. static const struct driver_info smsc75xx_info = {
  1803. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1804. .bind = smsc75xx_bind,
  1805. .unbind = smsc75xx_unbind,
  1806. .link_reset = smsc75xx_link_reset,
  1807. .reset = smsc75xx_reset,
  1808. .rx_fixup = smsc75xx_rx_fixup,
  1809. .tx_fixup = smsc75xx_tx_fixup,
  1810. .status = smsc75xx_status,
  1811. .manage_power = smsc75xx_manage_power,
  1812. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1813. };
  1814. static const struct usb_device_id products[] = {
  1815. {
  1816. /* SMSC7500 USB Gigabit Ethernet Device */
  1817. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1818. .driver_info = (unsigned long) &smsc75xx_info,
  1819. },
  1820. {
  1821. /* SMSC7500 USB Gigabit Ethernet Device */
  1822. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1823. .driver_info = (unsigned long) &smsc75xx_info,
  1824. },
  1825. { }, /* END */
  1826. };
  1827. MODULE_DEVICE_TABLE(usb, products);
  1828. static struct usb_driver smsc75xx_driver = {
  1829. .name = SMSC_CHIPNAME,
  1830. .id_table = products,
  1831. .probe = usbnet_probe,
  1832. .suspend = smsc75xx_suspend,
  1833. .resume = smsc75xx_resume,
  1834. .reset_resume = smsc75xx_resume,
  1835. .disconnect = usbnet_disconnect,
  1836. .disable_hub_initiated_lpm = 1,
  1837. .supports_autosuspend = 1,
  1838. };
  1839. module_usb_driver(smsc75xx_driver);
  1840. MODULE_AUTHOR("Nancy Lin");
  1841. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1842. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1843. MODULE_LICENSE("GPL");