qlcnic_ctx.c 39 KB

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  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 3, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 4, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
  40. {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  41. {QLCNIC_CMD_DCB_QUERY_PARAM, 4, 1},
  42. };
  43. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  44. {
  45. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  46. (0xcafe << 16);
  47. }
  48. /* Allocate mailbox registers */
  49. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  50. struct qlcnic_adapter *adapter, u32 type)
  51. {
  52. int i, size;
  53. const struct qlcnic_mailbox_metadata *mbx_tbl;
  54. mbx_tbl = qlcnic_mbx_tbl;
  55. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  56. for (i = 0; i < size; i++) {
  57. if (type == mbx_tbl[i].cmd) {
  58. mbx->req.num = mbx_tbl[i].in_args;
  59. mbx->rsp.num = mbx_tbl[i].out_args;
  60. mbx->req.arg = kcalloc(mbx->req.num,
  61. sizeof(u32), GFP_ATOMIC);
  62. if (!mbx->req.arg)
  63. return -ENOMEM;
  64. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  65. sizeof(u32), GFP_ATOMIC);
  66. if (!mbx->rsp.arg) {
  67. kfree(mbx->req.arg);
  68. mbx->req.arg = NULL;
  69. return -ENOMEM;
  70. }
  71. mbx->req.arg[0] = type;
  72. break;
  73. }
  74. }
  75. return 0;
  76. }
  77. /* Free up mailbox registers */
  78. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  79. {
  80. kfree(cmd->req.arg);
  81. cmd->req.arg = NULL;
  82. kfree(cmd->rsp.arg);
  83. cmd->rsp.arg = NULL;
  84. }
  85. static u32
  86. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  87. {
  88. u32 rsp;
  89. int timeout = 0, err = 0;
  90. do {
  91. /* give atleast 1ms for firmware to respond */
  92. mdelay(1);
  93. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  94. return QLCNIC_CDRP_RSP_TIMEOUT;
  95. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  96. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  97. return rsp;
  98. }
  99. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  100. struct qlcnic_cmd_args *cmd)
  101. {
  102. int i, err = 0;
  103. u32 rsp;
  104. u32 signature;
  105. struct pci_dev *pdev = adapter->pdev;
  106. struct qlcnic_hardware_context *ahw = adapter->ahw;
  107. const char *fmt;
  108. signature = qlcnic_get_cmd_signature(ahw);
  109. /* Acquire semaphore before accessing CRB */
  110. if (qlcnic_api_lock(adapter)) {
  111. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  112. return cmd->rsp.arg[0];
  113. }
  114. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  115. for (i = 1; i < cmd->req.num; i++)
  116. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  117. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  118. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  119. rsp = qlcnic_poll_rsp(adapter);
  120. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  121. dev_err(&pdev->dev, "command timeout, response = 0x%x\n", rsp);
  122. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  123. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  124. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  125. switch (cmd->rsp.arg[0]) {
  126. case QLCNIC_RCODE_INVALID_ARGS:
  127. fmt = "CDRP invalid args: [%d]\n";
  128. break;
  129. case QLCNIC_RCODE_NOT_SUPPORTED:
  130. case QLCNIC_RCODE_NOT_IMPL:
  131. fmt = "CDRP command not supported: [%d]\n";
  132. break;
  133. case QLCNIC_RCODE_NOT_PERMITTED:
  134. fmt = "CDRP requested action not permitted: [%d]\n";
  135. break;
  136. case QLCNIC_RCODE_INVALID:
  137. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  138. break;
  139. case QLCNIC_RCODE_TIMEOUT:
  140. fmt = "CDRP command timeout: [%d]\n";
  141. break;
  142. default:
  143. fmt = "CDRP command failed: [%d]\n";
  144. break;
  145. }
  146. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  147. qlcnic_dump_mbx(adapter, cmd);
  148. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  149. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  150. for (i = 1; i < cmd->rsp.num; i++)
  151. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  152. /* Release semaphore */
  153. qlcnic_api_unlock(adapter);
  154. return cmd->rsp.arg[0];
  155. }
  156. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  157. {
  158. struct qlcnic_cmd_args cmd;
  159. u32 arg1, arg2, arg3;
  160. char drv_string[12];
  161. int err = 0;
  162. memset(drv_string, 0, sizeof(drv_string));
  163. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  164. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  165. _QLCNIC_LINUX_SUBVERSION);
  166. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  167. if (err)
  168. return err;
  169. memcpy(&arg1, drv_string, sizeof(u32));
  170. memcpy(&arg2, drv_string + 4, sizeof(u32));
  171. memcpy(&arg3, drv_string + 8, sizeof(u32));
  172. cmd.req.arg[1] = arg1;
  173. cmd.req.arg[2] = arg2;
  174. cmd.req.arg[3] = arg3;
  175. err = qlcnic_issue_cmd(adapter, &cmd);
  176. if (err) {
  177. dev_info(&adapter->pdev->dev,
  178. "Failed to set driver version in firmware\n");
  179. err = -EIO;
  180. }
  181. qlcnic_free_mbx_args(&cmd);
  182. return err;
  183. }
  184. int
  185. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  186. {
  187. int err = 0;
  188. struct qlcnic_cmd_args cmd;
  189. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  190. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  191. return err;
  192. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  193. if (err)
  194. return err;
  195. cmd.req.arg[1] = recv_ctx->context_id;
  196. cmd.req.arg[2] = mtu;
  197. err = qlcnic_issue_cmd(adapter, &cmd);
  198. if (err) {
  199. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  200. err = -EIO;
  201. }
  202. qlcnic_free_mbx_args(&cmd);
  203. return err;
  204. }
  205. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  206. {
  207. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  208. struct qlcnic_hardware_context *ahw = adapter->ahw;
  209. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  210. struct net_device *netdev = adapter->netdev;
  211. u32 temp_intr_crb_mode, temp_rds_crb_mode;
  212. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  213. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  214. struct qlcnic_hostrq_rds_ring *prq_rds;
  215. struct qlcnic_hostrq_sds_ring *prq_sds;
  216. struct qlcnic_host_rds_ring *rds_ring;
  217. struct qlcnic_host_sds_ring *sds_ring;
  218. struct qlcnic_cardrsp_rx_ctx *prsp;
  219. struct qlcnic_hostrq_rx_ctx *prq;
  220. u8 i, nrds_rings, nsds_rings;
  221. struct qlcnic_cmd_args cmd;
  222. size_t rq_size, rsp_size;
  223. u32 cap, reg, val, reg2;
  224. u64 phys_addr;
  225. u16 temp_u16;
  226. void *addr;
  227. int err;
  228. nrds_rings = adapter->max_rds_rings;
  229. nsds_rings = adapter->drv_sds_rings;
  230. rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  231. nsds_rings);
  232. rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  233. nsds_rings);
  234. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  235. &hostrq_phys_addr, GFP_KERNEL);
  236. if (addr == NULL)
  237. return -ENOMEM;
  238. prq = addr;
  239. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  240. &cardrsp_phys_addr, GFP_KERNEL);
  241. if (addr == NULL) {
  242. err = -ENOMEM;
  243. goto out_free_rq;
  244. }
  245. prsp = addr;
  246. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  247. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  248. | QLCNIC_CAP0_VALIDOFF);
  249. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  250. if (qlcnic_check_multi_tx(adapter) &&
  251. !adapter->ahw->diag_test) {
  252. cap |= QLCNIC_CAP0_TX_MULTI;
  253. } else {
  254. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  255. prq->valid_field_offset = cpu_to_le16(temp_u16);
  256. prq->txrx_sds_binding = nsds_rings - 1;
  257. temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  258. prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
  259. temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
  260. prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
  261. }
  262. prq->capabilities[0] = cpu_to_le32(cap);
  263. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  264. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  265. prq->rds_ring_offset = 0;
  266. val = le32_to_cpu(prq->rds_ring_offset) +
  267. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  268. prq->sds_ring_offset = cpu_to_le32(val);
  269. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  270. le32_to_cpu(prq->rds_ring_offset));
  271. for (i = 0; i < nrds_rings; i++) {
  272. rds_ring = &recv_ctx->rds_rings[i];
  273. rds_ring->producer = 0;
  274. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  275. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  276. prq_rds[i].ring_kind = cpu_to_le32(i);
  277. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  278. }
  279. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  280. le32_to_cpu(prq->sds_ring_offset));
  281. for (i = 0; i < nsds_rings; i++) {
  282. sds_ring = &recv_ctx->sds_rings[i];
  283. sds_ring->consumer = 0;
  284. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  285. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  286. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  287. if (qlcnic_check_multi_tx(adapter) &&
  288. !adapter->ahw->diag_test)
  289. prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
  290. else
  291. prq_sds[i].msi_index = cpu_to_le16(i);
  292. }
  293. phys_addr = hostrq_phys_addr;
  294. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  295. if (err)
  296. goto out_free_rsp;
  297. cmd.req.arg[1] = MSD(phys_addr);
  298. cmd.req.arg[2] = LSD(phys_addr);
  299. cmd.req.arg[3] = rq_size;
  300. err = qlcnic_issue_cmd(adapter, &cmd);
  301. if (err) {
  302. dev_err(&adapter->pdev->dev,
  303. "Failed to create rx ctx in firmware%d\n", err);
  304. goto out_free_rsp;
  305. }
  306. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  307. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  308. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  309. rds_ring = &recv_ctx->rds_rings[i];
  310. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  311. rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
  312. }
  313. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  314. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  315. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  316. sds_ring = &recv_ctx->sds_rings[i];
  317. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  318. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  319. reg2 = ahw->intr_tbl[i].src;
  320. else
  321. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  322. sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
  323. sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
  324. }
  325. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  326. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  327. recv_ctx->virt_port = prsp->virt_port;
  328. netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
  329. recv_ctx->context_id, recv_ctx->state);
  330. qlcnic_free_mbx_args(&cmd);
  331. out_free_rsp:
  332. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  333. cardrsp_phys_addr);
  334. out_free_rq:
  335. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  336. return err;
  337. }
  338. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  339. {
  340. int err;
  341. struct qlcnic_cmd_args cmd;
  342. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  343. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  344. if (err)
  345. return;
  346. cmd.req.arg[1] = recv_ctx->context_id;
  347. err = qlcnic_issue_cmd(adapter, &cmd);
  348. if (err)
  349. dev_err(&adapter->pdev->dev,
  350. "Failed to destroy rx ctx in firmware\n");
  351. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  352. qlcnic_free_mbx_args(&cmd);
  353. }
  354. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  355. struct qlcnic_host_tx_ring *tx_ring,
  356. int ring)
  357. {
  358. struct qlcnic_hardware_context *ahw = adapter->ahw;
  359. struct net_device *netdev = adapter->netdev;
  360. struct qlcnic_hostrq_tx_ctx *prq;
  361. struct qlcnic_hostrq_cds_ring *prq_cds;
  362. struct qlcnic_cardrsp_tx_ctx *prsp;
  363. struct qlcnic_cmd_args cmd;
  364. u32 temp, intr_mask, temp_int_crb_mode;
  365. dma_addr_t rq_phys_addr, rsp_phys_addr;
  366. int temp_nsds_rings, index, err;
  367. void *rq_addr, *rsp_addr;
  368. size_t rq_size, rsp_size;
  369. u64 phys_addr;
  370. u16 msix_id;
  371. /* reset host resources */
  372. tx_ring->producer = 0;
  373. tx_ring->sw_consumer = 0;
  374. *(tx_ring->hw_consumer) = 0;
  375. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  376. rq_addr = dma_zalloc_coherent(&adapter->pdev->dev, rq_size,
  377. &rq_phys_addr, GFP_KERNEL);
  378. if (!rq_addr)
  379. return -ENOMEM;
  380. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  381. rsp_addr = dma_zalloc_coherent(&adapter->pdev->dev, rsp_size,
  382. &rsp_phys_addr, GFP_KERNEL);
  383. if (!rsp_addr) {
  384. err = -ENOMEM;
  385. goto out_free_rq;
  386. }
  387. prq = rq_addr;
  388. prsp = rsp_addr;
  389. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  390. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  391. QLCNIC_CAP0_LSO);
  392. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  393. temp |= QLCNIC_CAP0_TX_MULTI;
  394. prq->capabilities[0] = cpu_to_le32(temp);
  395. if (qlcnic_check_multi_tx(adapter) &&
  396. !adapter->ahw->diag_test) {
  397. temp_nsds_rings = adapter->drv_sds_rings;
  398. index = temp_nsds_rings + ring;
  399. msix_id = ahw->intr_tbl[index].id;
  400. prq->msi_index = cpu_to_le16(msix_id);
  401. } else {
  402. temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  403. prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
  404. prq->msi_index = 0;
  405. }
  406. prq->interrupt_ctl = 0;
  407. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  408. prq_cds = &prq->cds_ring;
  409. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  410. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  411. phys_addr = rq_phys_addr;
  412. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  413. if (err)
  414. goto out_free_rsp;
  415. cmd.req.arg[1] = MSD(phys_addr);
  416. cmd.req.arg[2] = LSD(phys_addr);
  417. cmd.req.arg[3] = rq_size;
  418. err = qlcnic_issue_cmd(adapter, &cmd);
  419. if (err == QLCNIC_RCODE_SUCCESS) {
  420. tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
  421. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  422. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  423. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  424. if (qlcnic_check_multi_tx(adapter) &&
  425. !adapter->ahw->diag_test &&
  426. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  427. index = adapter->drv_sds_rings + ring;
  428. intr_mask = ahw->intr_tbl[index].src;
  429. tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
  430. }
  431. netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
  432. tx_ring->ctx_id, tx_ring->state);
  433. } else {
  434. netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
  435. err);
  436. err = -EIO;
  437. }
  438. qlcnic_free_mbx_args(&cmd);
  439. out_free_rsp:
  440. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  441. rsp_phys_addr);
  442. out_free_rq:
  443. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  444. return err;
  445. }
  446. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  447. struct qlcnic_host_tx_ring *tx_ring)
  448. {
  449. struct qlcnic_cmd_args cmd;
  450. int ret;
  451. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  452. if (ret)
  453. return;
  454. cmd.req.arg[1] = tx_ring->ctx_id;
  455. if (qlcnic_issue_cmd(adapter, &cmd))
  456. dev_err(&adapter->pdev->dev,
  457. "Failed to destroy tx ctx in firmware\n");
  458. qlcnic_free_mbx_args(&cmd);
  459. }
  460. int
  461. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  462. {
  463. int err;
  464. struct qlcnic_cmd_args cmd;
  465. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  466. if (err)
  467. return err;
  468. cmd.req.arg[1] = config;
  469. err = qlcnic_issue_cmd(adapter, &cmd);
  470. qlcnic_free_mbx_args(&cmd);
  471. return err;
  472. }
  473. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  474. {
  475. void *addr;
  476. int err, ring;
  477. struct qlcnic_recv_context *recv_ctx;
  478. struct qlcnic_host_rds_ring *rds_ring;
  479. struct qlcnic_host_sds_ring *sds_ring;
  480. struct qlcnic_host_tx_ring *tx_ring;
  481. __le32 *ptr;
  482. struct pci_dev *pdev = adapter->pdev;
  483. recv_ctx = adapter->recv_ctx;
  484. for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
  485. tx_ring = &adapter->tx_ring[ring];
  486. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  487. &tx_ring->hw_cons_phys_addr,
  488. GFP_KERNEL);
  489. if (ptr == NULL)
  490. return -ENOMEM;
  491. tx_ring->hw_consumer = ptr;
  492. /* cmd desc ring */
  493. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  494. &tx_ring->phys_addr,
  495. GFP_KERNEL);
  496. if (addr == NULL) {
  497. err = -ENOMEM;
  498. goto err_out_free;
  499. }
  500. tx_ring->desc_head = addr;
  501. }
  502. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  503. rds_ring = &recv_ctx->rds_rings[ring];
  504. addr = dma_alloc_coherent(&adapter->pdev->dev,
  505. RCV_DESC_RINGSIZE(rds_ring),
  506. &rds_ring->phys_addr, GFP_KERNEL);
  507. if (addr == NULL) {
  508. err = -ENOMEM;
  509. goto err_out_free;
  510. }
  511. rds_ring->desc_head = addr;
  512. }
  513. for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
  514. sds_ring = &recv_ctx->sds_rings[ring];
  515. addr = dma_alloc_coherent(&adapter->pdev->dev,
  516. STATUS_DESC_RINGSIZE(sds_ring),
  517. &sds_ring->phys_addr, GFP_KERNEL);
  518. if (addr == NULL) {
  519. err = -ENOMEM;
  520. goto err_out_free;
  521. }
  522. sds_ring->desc_head = addr;
  523. }
  524. return 0;
  525. err_out_free:
  526. qlcnic_free_hw_resources(adapter);
  527. return err;
  528. }
  529. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  530. {
  531. int i, err, ring;
  532. if (dev->flags & QLCNIC_NEED_FLR) {
  533. pci_reset_function(dev->pdev);
  534. dev->flags &= ~QLCNIC_NEED_FLR;
  535. }
  536. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  537. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  538. err = qlcnic_83xx_config_intrpt(dev, 1);
  539. if (err)
  540. return err;
  541. }
  542. }
  543. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  544. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
  545. err = qlcnic_82xx_mq_intrpt(dev, 1);
  546. if (err)
  547. return err;
  548. }
  549. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  550. if (err)
  551. goto err_out;
  552. for (ring = 0; ring < dev->drv_tx_rings; ring++) {
  553. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  554. &dev->tx_ring[ring],
  555. ring);
  556. if (err) {
  557. qlcnic_fw_cmd_del_rx_ctx(dev);
  558. if (ring == 0)
  559. goto err_out;
  560. for (i = 0; i < ring; i++)
  561. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  562. goto err_out;
  563. }
  564. }
  565. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  566. return 0;
  567. err_out:
  568. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  569. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
  570. qlcnic_82xx_config_intrpt(dev, 0);
  571. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  572. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  573. qlcnic_83xx_config_intrpt(dev, 0);
  574. }
  575. return err;
  576. }
  577. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  578. {
  579. int ring;
  580. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  581. qlcnic_fw_cmd_del_rx_ctx(adapter);
  582. for (ring = 0; ring < adapter->drv_tx_rings; ring++)
  583. qlcnic_fw_cmd_del_tx_ctx(adapter,
  584. &adapter->tx_ring[ring]);
  585. if (qlcnic_82xx_check(adapter) &&
  586. (adapter->flags & QLCNIC_MSIX_ENABLED) &&
  587. qlcnic_check_multi_tx(adapter) &&
  588. !adapter->ahw->diag_test)
  589. qlcnic_82xx_config_intrpt(adapter, 0);
  590. if (qlcnic_83xx_check(adapter) &&
  591. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  592. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  593. qlcnic_83xx_config_intrpt(adapter, 0);
  594. }
  595. /* Allow dma queues to drain after context reset */
  596. mdelay(20);
  597. }
  598. }
  599. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  600. {
  601. struct qlcnic_recv_context *recv_ctx;
  602. struct qlcnic_host_rds_ring *rds_ring;
  603. struct qlcnic_host_sds_ring *sds_ring;
  604. struct qlcnic_host_tx_ring *tx_ring;
  605. int ring;
  606. recv_ctx = adapter->recv_ctx;
  607. for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
  608. tx_ring = &adapter->tx_ring[ring];
  609. if (tx_ring->hw_consumer != NULL) {
  610. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  611. tx_ring->hw_consumer,
  612. tx_ring->hw_cons_phys_addr);
  613. tx_ring->hw_consumer = NULL;
  614. }
  615. if (tx_ring->desc_head != NULL) {
  616. dma_free_coherent(&adapter->pdev->dev,
  617. TX_DESC_RINGSIZE(tx_ring),
  618. tx_ring->desc_head,
  619. tx_ring->phys_addr);
  620. tx_ring->desc_head = NULL;
  621. }
  622. }
  623. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  624. rds_ring = &recv_ctx->rds_rings[ring];
  625. if (rds_ring->desc_head != NULL) {
  626. dma_free_coherent(&adapter->pdev->dev,
  627. RCV_DESC_RINGSIZE(rds_ring),
  628. rds_ring->desc_head,
  629. rds_ring->phys_addr);
  630. rds_ring->desc_head = NULL;
  631. }
  632. }
  633. for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
  634. sds_ring = &recv_ctx->sds_rings[ring];
  635. if (sds_ring->desc_head != NULL) {
  636. dma_free_coherent(&adapter->pdev->dev,
  637. STATUS_DESC_RINGSIZE(sds_ring),
  638. sds_ring->desc_head,
  639. sds_ring->phys_addr);
  640. sds_ring->desc_head = NULL;
  641. }
  642. }
  643. }
  644. int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
  645. {
  646. struct qlcnic_hardware_context *ahw = adapter->ahw;
  647. struct net_device *netdev = adapter->netdev;
  648. struct qlcnic_cmd_args cmd;
  649. u32 type, val;
  650. int i, err = 0;
  651. for (i = 0; i < ahw->num_msix; i++) {
  652. qlcnic_alloc_mbx_args(&cmd, adapter,
  653. QLCNIC_CMD_MQ_TX_CONFIG_INTR);
  654. type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
  655. val = type | (ahw->intr_tbl[i].type << 4);
  656. if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
  657. val |= (ahw->intr_tbl[i].id << 16);
  658. cmd.req.arg[1] = val;
  659. err = qlcnic_issue_cmd(adapter, &cmd);
  660. if (err) {
  661. netdev_err(netdev, "Failed to %s interrupts %d\n",
  662. op_type == QLCNIC_INTRPT_ADD ? "Add" :
  663. "Delete", err);
  664. qlcnic_free_mbx_args(&cmd);
  665. return err;
  666. }
  667. val = cmd.rsp.arg[1];
  668. if (LSB(val)) {
  669. netdev_info(netdev,
  670. "failed to configure interrupt for %d\n",
  671. ahw->intr_tbl[i].id);
  672. continue;
  673. }
  674. if (op_type) {
  675. ahw->intr_tbl[i].id = MSW(val);
  676. ahw->intr_tbl[i].enabled = 1;
  677. ahw->intr_tbl[i].src = cmd.rsp.arg[2];
  678. } else {
  679. ahw->intr_tbl[i].id = i;
  680. ahw->intr_tbl[i].enabled = 0;
  681. ahw->intr_tbl[i].src = 0;
  682. }
  683. qlcnic_free_mbx_args(&cmd);
  684. }
  685. return err;
  686. }
  687. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
  688. u8 function)
  689. {
  690. int err, i;
  691. struct qlcnic_cmd_args cmd;
  692. u32 mac_low, mac_high;
  693. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  694. if (err)
  695. return err;
  696. cmd.req.arg[1] = function | BIT_8;
  697. err = qlcnic_issue_cmd(adapter, &cmd);
  698. if (err == QLCNIC_RCODE_SUCCESS) {
  699. mac_low = cmd.rsp.arg[1];
  700. mac_high = cmd.rsp.arg[2];
  701. for (i = 0; i < 2; i++)
  702. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  703. for (i = 2; i < 6; i++)
  704. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  705. } else {
  706. dev_err(&adapter->pdev->dev,
  707. "Failed to get mac address%d\n", err);
  708. err = -EIO;
  709. }
  710. qlcnic_free_mbx_args(&cmd);
  711. return err;
  712. }
  713. /* Get info of a NIC partition */
  714. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  715. struct qlcnic_info *npar_info, u8 func_id)
  716. {
  717. int err;
  718. dma_addr_t nic_dma_t;
  719. const struct qlcnic_info_le *nic_info;
  720. void *nic_info_addr;
  721. struct qlcnic_cmd_args cmd;
  722. size_t nic_size = sizeof(struct qlcnic_info_le);
  723. nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
  724. &nic_dma_t, GFP_KERNEL);
  725. if (!nic_info_addr)
  726. return -ENOMEM;
  727. nic_info = nic_info_addr;
  728. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  729. if (err)
  730. goto out_free_dma;
  731. cmd.req.arg[1] = MSD(nic_dma_t);
  732. cmd.req.arg[2] = LSD(nic_dma_t);
  733. cmd.req.arg[3] = (func_id << 16 | nic_size);
  734. err = qlcnic_issue_cmd(adapter, &cmd);
  735. if (err != QLCNIC_RCODE_SUCCESS) {
  736. dev_err(&adapter->pdev->dev,
  737. "Failed to get nic info%d\n", err);
  738. err = -EIO;
  739. } else {
  740. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  741. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  742. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  743. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  744. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  745. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  746. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  747. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  748. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  749. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  750. }
  751. qlcnic_free_mbx_args(&cmd);
  752. out_free_dma:
  753. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  754. nic_dma_t);
  755. return err;
  756. }
  757. /* Configure a NIC partition */
  758. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  759. struct qlcnic_info *nic)
  760. {
  761. int err = -EIO;
  762. dma_addr_t nic_dma_t;
  763. void *nic_info_addr;
  764. struct qlcnic_cmd_args cmd;
  765. struct qlcnic_info_le *nic_info;
  766. size_t nic_size = sizeof(struct qlcnic_info_le);
  767. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  768. return err;
  769. nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
  770. &nic_dma_t, GFP_KERNEL);
  771. if (!nic_info_addr)
  772. return -ENOMEM;
  773. nic_info = nic_info_addr;
  774. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  775. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  776. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  777. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  778. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  779. nic_info->max_mac_filters = nic->max_mac_filters;
  780. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  781. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  782. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  783. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  784. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  785. if (err)
  786. goto out_free_dma;
  787. cmd.req.arg[1] = MSD(nic_dma_t);
  788. cmd.req.arg[2] = LSD(nic_dma_t);
  789. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  790. err = qlcnic_issue_cmd(adapter, &cmd);
  791. if (err != QLCNIC_RCODE_SUCCESS) {
  792. dev_err(&adapter->pdev->dev,
  793. "Failed to set nic info%d\n", err);
  794. err = -EIO;
  795. }
  796. qlcnic_free_mbx_args(&cmd);
  797. out_free_dma:
  798. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  799. nic_dma_t);
  800. return err;
  801. }
  802. /* Get PCI Info of a partition */
  803. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  804. struct qlcnic_pci_info *pci_info)
  805. {
  806. struct qlcnic_hardware_context *ahw = adapter->ahw;
  807. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  808. size_t pci_size = npar_size * ahw->max_vnic_func;
  809. u16 nic = 0, fcoe = 0, iscsi = 0;
  810. struct qlcnic_pci_info_le *npar;
  811. struct qlcnic_cmd_args cmd;
  812. dma_addr_t pci_info_dma_t;
  813. void *pci_info_addr;
  814. int err = 0, i;
  815. pci_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, pci_size,
  816. &pci_info_dma_t, GFP_KERNEL);
  817. if (!pci_info_addr)
  818. return -ENOMEM;
  819. npar = pci_info_addr;
  820. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  821. if (err)
  822. goto out_free_dma;
  823. cmd.req.arg[1] = MSD(pci_info_dma_t);
  824. cmd.req.arg[2] = LSD(pci_info_dma_t);
  825. cmd.req.arg[3] = pci_size;
  826. err = qlcnic_issue_cmd(adapter, &cmd);
  827. ahw->total_nic_func = 0;
  828. if (err == QLCNIC_RCODE_SUCCESS) {
  829. for (i = 0; i < ahw->max_vnic_func; i++, npar++, pci_info++) {
  830. pci_info->id = le16_to_cpu(npar->id);
  831. pci_info->active = le16_to_cpu(npar->active);
  832. if (!pci_info->active)
  833. continue;
  834. pci_info->type = le16_to_cpu(npar->type);
  835. err = qlcnic_get_pci_func_type(adapter, pci_info->type,
  836. &nic, &fcoe, &iscsi);
  837. pci_info->default_port =
  838. le16_to_cpu(npar->default_port);
  839. pci_info->tx_min_bw =
  840. le16_to_cpu(npar->tx_min_bw);
  841. pci_info->tx_max_bw =
  842. le16_to_cpu(npar->tx_max_bw);
  843. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  844. }
  845. } else {
  846. dev_err(&adapter->pdev->dev,
  847. "Failed to get PCI Info%d\n", err);
  848. err = -EIO;
  849. }
  850. ahw->total_nic_func = nic;
  851. ahw->total_pci_func = nic + fcoe + iscsi;
  852. if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
  853. dev_err(&adapter->pdev->dev,
  854. "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
  855. __func__, ahw->total_nic_func, ahw->total_pci_func);
  856. err = -EIO;
  857. }
  858. qlcnic_free_mbx_args(&cmd);
  859. out_free_dma:
  860. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  861. pci_info_dma_t);
  862. return err;
  863. }
  864. /* Configure eSwitch for port mirroring */
  865. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  866. u8 enable_mirroring, u8 pci_func)
  867. {
  868. struct device *dev = &adapter->pdev->dev;
  869. struct qlcnic_cmd_args cmd;
  870. int err = -EIO;
  871. u32 arg1;
  872. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  873. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) {
  874. dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
  875. __func__);
  876. return err;
  877. }
  878. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  879. arg1 |= pci_func << 8;
  880. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  881. QLCNIC_CMD_SET_PORTMIRRORING);
  882. if (err)
  883. return err;
  884. cmd.req.arg[1] = arg1;
  885. err = qlcnic_issue_cmd(adapter, &cmd);
  886. if (err != QLCNIC_RCODE_SUCCESS)
  887. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  888. pci_func, id);
  889. else
  890. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  891. pci_func, id);
  892. qlcnic_free_mbx_args(&cmd);
  893. return err;
  894. }
  895. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  896. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  897. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  898. struct qlcnic_esw_stats_le *stats;
  899. dma_addr_t stats_dma_t;
  900. void *stats_addr;
  901. u32 arg1;
  902. struct qlcnic_cmd_args cmd;
  903. int err;
  904. if (esw_stats == NULL)
  905. return -ENOMEM;
  906. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  907. (func != adapter->ahw->pci_func)) {
  908. dev_err(&adapter->pdev->dev,
  909. "Not privilege to query stats for func=%d", func);
  910. return -EIO;
  911. }
  912. stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
  913. &stats_dma_t, GFP_KERNEL);
  914. if (!stats_addr)
  915. return -ENOMEM;
  916. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  917. arg1 |= rx_tx << 15 | stats_size << 16;
  918. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  919. QLCNIC_CMD_GET_ESWITCH_STATS);
  920. if (err)
  921. goto out_free_dma;
  922. cmd.req.arg[1] = arg1;
  923. cmd.req.arg[2] = MSD(stats_dma_t);
  924. cmd.req.arg[3] = LSD(stats_dma_t);
  925. err = qlcnic_issue_cmd(adapter, &cmd);
  926. if (!err) {
  927. stats = stats_addr;
  928. esw_stats->context_id = le16_to_cpu(stats->context_id);
  929. esw_stats->version = le16_to_cpu(stats->version);
  930. esw_stats->size = le16_to_cpu(stats->size);
  931. esw_stats->multicast_frames =
  932. le64_to_cpu(stats->multicast_frames);
  933. esw_stats->broadcast_frames =
  934. le64_to_cpu(stats->broadcast_frames);
  935. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  936. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  937. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  938. esw_stats->errors = le64_to_cpu(stats->errors);
  939. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  940. }
  941. qlcnic_free_mbx_args(&cmd);
  942. out_free_dma:
  943. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  944. stats_dma_t);
  945. return err;
  946. }
  947. /* This routine will retrieve the MAC statistics from firmware */
  948. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  949. struct qlcnic_mac_statistics *mac_stats)
  950. {
  951. struct qlcnic_mac_statistics_le *stats;
  952. struct qlcnic_cmd_args cmd;
  953. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  954. dma_addr_t stats_dma_t;
  955. void *stats_addr;
  956. int err;
  957. if (mac_stats == NULL)
  958. return -ENOMEM;
  959. stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
  960. &stats_dma_t, GFP_KERNEL);
  961. if (!stats_addr)
  962. return -ENOMEM;
  963. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  964. if (err)
  965. goto out_free_dma;
  966. cmd.req.arg[1] = stats_size << 16;
  967. cmd.req.arg[2] = MSD(stats_dma_t);
  968. cmd.req.arg[3] = LSD(stats_dma_t);
  969. err = qlcnic_issue_cmd(adapter, &cmd);
  970. if (!err) {
  971. stats = stats_addr;
  972. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  973. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  974. mac_stats->mac_tx_mcast_pkts =
  975. le64_to_cpu(stats->mac_tx_mcast_pkts);
  976. mac_stats->mac_tx_bcast_pkts =
  977. le64_to_cpu(stats->mac_tx_bcast_pkts);
  978. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  979. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  980. mac_stats->mac_rx_mcast_pkts =
  981. le64_to_cpu(stats->mac_rx_mcast_pkts);
  982. mac_stats->mac_rx_length_error =
  983. le64_to_cpu(stats->mac_rx_length_error);
  984. mac_stats->mac_rx_length_small =
  985. le64_to_cpu(stats->mac_rx_length_small);
  986. mac_stats->mac_rx_length_large =
  987. le64_to_cpu(stats->mac_rx_length_large);
  988. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  989. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  990. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  991. } else {
  992. dev_err(&adapter->pdev->dev,
  993. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  994. }
  995. qlcnic_free_mbx_args(&cmd);
  996. out_free_dma:
  997. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  998. stats_dma_t);
  999. return err;
  1000. }
  1001. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  1002. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  1003. struct __qlcnic_esw_statistics port_stats;
  1004. u8 i;
  1005. int ret = -EIO;
  1006. if (esw_stats == NULL)
  1007. return -ENOMEM;
  1008. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1009. return -EIO;
  1010. if (adapter->npars == NULL)
  1011. return -EIO;
  1012. memset(esw_stats, 0, sizeof(u64));
  1013. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1014. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1015. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  1016. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  1017. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  1018. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  1019. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  1020. esw_stats->context_id = eswitch;
  1021. for (i = 0; i < adapter->ahw->total_nic_func; i++) {
  1022. if (adapter->npars[i].phy_port != eswitch)
  1023. continue;
  1024. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  1025. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  1026. rx_tx, &port_stats))
  1027. continue;
  1028. esw_stats->size = port_stats.size;
  1029. esw_stats->version = port_stats.version;
  1030. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  1031. port_stats.unicast_frames);
  1032. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  1033. port_stats.multicast_frames);
  1034. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  1035. port_stats.broadcast_frames);
  1036. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  1037. port_stats.dropped_frames);
  1038. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  1039. port_stats.errors);
  1040. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  1041. port_stats.local_frames);
  1042. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  1043. port_stats.numbytes);
  1044. ret = 0;
  1045. }
  1046. return ret;
  1047. }
  1048. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  1049. const u8 port, const u8 rx_tx)
  1050. {
  1051. struct qlcnic_hardware_context *ahw = adapter->ahw;
  1052. struct qlcnic_cmd_args cmd;
  1053. int err;
  1054. u32 arg1;
  1055. if (ahw->op_mode != QLCNIC_MGMT_FUNC)
  1056. return -EIO;
  1057. if (func_esw == QLCNIC_STATS_PORT) {
  1058. if (port >= ahw->max_vnic_func)
  1059. goto err_ret;
  1060. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  1061. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  1062. goto err_ret;
  1063. } else {
  1064. goto err_ret;
  1065. }
  1066. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  1067. goto err_ret;
  1068. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  1069. arg1 |= BIT_14 | rx_tx << 15;
  1070. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1071. QLCNIC_CMD_GET_ESWITCH_STATS);
  1072. if (err)
  1073. return err;
  1074. cmd.req.arg[1] = arg1;
  1075. err = qlcnic_issue_cmd(adapter, &cmd);
  1076. qlcnic_free_mbx_args(&cmd);
  1077. return err;
  1078. err_ret:
  1079. dev_err(&adapter->pdev->dev,
  1080. "Invalid args func_esw %d port %d rx_ctx %d\n",
  1081. func_esw, port, rx_tx);
  1082. return -EIO;
  1083. }
  1084. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1085. u32 *arg1, u32 *arg2)
  1086. {
  1087. struct device *dev = &adapter->pdev->dev;
  1088. struct qlcnic_cmd_args cmd;
  1089. u8 pci_func = *arg1 >> 8;
  1090. int err;
  1091. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1092. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  1093. if (err)
  1094. return err;
  1095. cmd.req.arg[1] = *arg1;
  1096. err = qlcnic_issue_cmd(adapter, &cmd);
  1097. *arg1 = cmd.rsp.arg[1];
  1098. *arg2 = cmd.rsp.arg[2];
  1099. qlcnic_free_mbx_args(&cmd);
  1100. if (err == QLCNIC_RCODE_SUCCESS)
  1101. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  1102. pci_func);
  1103. else
  1104. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1105. pci_func);
  1106. return err;
  1107. }
  1108. /* Configure eSwitch port
  1109. op_mode = 0 for setting default port behavior
  1110. op_mode = 1 for setting vlan id
  1111. op_mode = 2 for deleting vlan id
  1112. op_type = 0 for vlan_id
  1113. op_type = 1 for port vlan_id
  1114. */
  1115. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1116. struct qlcnic_esw_func_cfg *esw_cfg)
  1117. {
  1118. struct device *dev = &adapter->pdev->dev;
  1119. struct qlcnic_cmd_args cmd;
  1120. int err = -EIO, index;
  1121. u32 arg1, arg2 = 0;
  1122. u8 pci_func;
  1123. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
  1124. dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
  1125. __func__);
  1126. return err;
  1127. }
  1128. pci_func = esw_cfg->pci_func;
  1129. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1130. if (index < 0)
  1131. return err;
  1132. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1133. arg1 |= (pci_func << 8);
  1134. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1135. return err;
  1136. arg1 &= ~(0x0ff << 8);
  1137. arg1 |= (pci_func << 8);
  1138. arg1 &= ~(BIT_2 | BIT_3);
  1139. switch (esw_cfg->op_mode) {
  1140. case QLCNIC_PORT_DEFAULTS:
  1141. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1142. arg2 |= (BIT_0 | BIT_1);
  1143. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1144. arg2 |= (BIT_2 | BIT_3);
  1145. if (!(esw_cfg->discard_tagged))
  1146. arg1 &= ~BIT_4;
  1147. if (!(esw_cfg->promisc_mode))
  1148. arg1 &= ~BIT_6;
  1149. if (!(esw_cfg->mac_override))
  1150. arg1 &= ~BIT_7;
  1151. if (!(esw_cfg->mac_anti_spoof))
  1152. arg2 &= ~BIT_0;
  1153. if (!(esw_cfg->offload_flags & BIT_0))
  1154. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1155. if (!(esw_cfg->offload_flags & BIT_1))
  1156. arg2 &= ~BIT_2;
  1157. if (!(esw_cfg->offload_flags & BIT_2))
  1158. arg2 &= ~BIT_3;
  1159. break;
  1160. case QLCNIC_ADD_VLAN:
  1161. arg1 &= ~(0x0ffff << 16);
  1162. arg1 |= (BIT_2 | BIT_5);
  1163. arg1 |= (esw_cfg->vlan_id << 16);
  1164. break;
  1165. case QLCNIC_DEL_VLAN:
  1166. arg1 |= (BIT_3 | BIT_5);
  1167. arg1 &= ~(0x0ffff << 16);
  1168. break;
  1169. default:
  1170. dev_err(&adapter->pdev->dev, "%s: Invalid opmode 0x%x\n",
  1171. __func__, esw_cfg->op_mode);
  1172. return err;
  1173. }
  1174. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1175. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1176. if (err)
  1177. return err;
  1178. cmd.req.arg[1] = arg1;
  1179. cmd.req.arg[2] = arg2;
  1180. err = qlcnic_issue_cmd(adapter, &cmd);
  1181. qlcnic_free_mbx_args(&cmd);
  1182. if (err != QLCNIC_RCODE_SUCCESS)
  1183. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1184. pci_func);
  1185. else
  1186. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1187. pci_func);
  1188. return err;
  1189. }
  1190. int
  1191. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1192. struct qlcnic_esw_func_cfg *esw_cfg)
  1193. {
  1194. u32 arg1, arg2;
  1195. int index;
  1196. u8 phy_port;
  1197. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1198. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1199. if (index < 0)
  1200. return -EIO;
  1201. phy_port = adapter->npars[index].phy_port;
  1202. } else {
  1203. phy_port = adapter->ahw->physical_port;
  1204. }
  1205. arg1 = phy_port;
  1206. arg1 |= (esw_cfg->pci_func << 8);
  1207. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1208. return -EIO;
  1209. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1210. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1211. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1212. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1213. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1214. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1215. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1216. return 0;
  1217. }