ethoc.c 32 KB

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  1. /*
  2. * linux/drivers/net/ethernet/ethoc.c
  3. *
  4. * Copyright (C) 2007-2008 Avionic Design Development GmbH
  5. * Copyright (C) 2008-2009 Avionic Design GmbH
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Written by Thierry Reding <thierry.reding@avionic-design.de>
  12. */
  13. #include <linux/dma-mapping.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/clk.h>
  16. #include <linux/crc32.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/mii.h>
  20. #include <linux/phy.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/sched.h>
  23. #include <linux/slab.h>
  24. #include <linux/of.h>
  25. #include <linux/module.h>
  26. #include <net/ethoc.h>
  27. static int buffer_size = 0x8000; /* 32 KBytes */
  28. module_param(buffer_size, int, 0);
  29. MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  30. /* register offsets */
  31. #define MODER 0x00
  32. #define INT_SOURCE 0x04
  33. #define INT_MASK 0x08
  34. #define IPGT 0x0c
  35. #define IPGR1 0x10
  36. #define IPGR2 0x14
  37. #define PACKETLEN 0x18
  38. #define COLLCONF 0x1c
  39. #define TX_BD_NUM 0x20
  40. #define CTRLMODER 0x24
  41. #define MIIMODER 0x28
  42. #define MIICOMMAND 0x2c
  43. #define MIIADDRESS 0x30
  44. #define MIITX_DATA 0x34
  45. #define MIIRX_DATA 0x38
  46. #define MIISTATUS 0x3c
  47. #define MAC_ADDR0 0x40
  48. #define MAC_ADDR1 0x44
  49. #define ETH_HASH0 0x48
  50. #define ETH_HASH1 0x4c
  51. #define ETH_TXCTRL 0x50
  52. #define ETH_END 0x54
  53. /* mode register */
  54. #define MODER_RXEN (1 << 0) /* receive enable */
  55. #define MODER_TXEN (1 << 1) /* transmit enable */
  56. #define MODER_NOPRE (1 << 2) /* no preamble */
  57. #define MODER_BRO (1 << 3) /* broadcast address */
  58. #define MODER_IAM (1 << 4) /* individual address mode */
  59. #define MODER_PRO (1 << 5) /* promiscuous mode */
  60. #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
  61. #define MODER_LOOP (1 << 7) /* loopback */
  62. #define MODER_NBO (1 << 8) /* no back-off */
  63. #define MODER_EDE (1 << 9) /* excess defer enable */
  64. #define MODER_FULLD (1 << 10) /* full duplex */
  65. #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
  66. #define MODER_DCRC (1 << 12) /* delayed CRC enable */
  67. #define MODER_CRC (1 << 13) /* CRC enable */
  68. #define MODER_HUGE (1 << 14) /* huge packets enable */
  69. #define MODER_PAD (1 << 15) /* padding enabled */
  70. #define MODER_RSM (1 << 16) /* receive small packets */
  71. /* interrupt source and mask registers */
  72. #define INT_MASK_TXF (1 << 0) /* transmit frame */
  73. #define INT_MASK_TXE (1 << 1) /* transmit error */
  74. #define INT_MASK_RXF (1 << 2) /* receive frame */
  75. #define INT_MASK_RXE (1 << 3) /* receive error */
  76. #define INT_MASK_BUSY (1 << 4)
  77. #define INT_MASK_TXC (1 << 5) /* transmit control frame */
  78. #define INT_MASK_RXC (1 << 6) /* receive control frame */
  79. #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
  80. #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
  81. #define INT_MASK_ALL ( \
  82. INT_MASK_TXF | INT_MASK_TXE | \
  83. INT_MASK_RXF | INT_MASK_RXE | \
  84. INT_MASK_TXC | INT_MASK_RXC | \
  85. INT_MASK_BUSY \
  86. )
  87. /* packet length register */
  88. #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
  89. #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
  90. #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
  91. PACKETLEN_MAX(max))
  92. /* transmit buffer number register */
  93. #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
  94. /* control module mode register */
  95. #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
  96. #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
  97. #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
  98. /* MII mode register */
  99. #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
  100. #define MIIMODER_NOPRE (1 << 8) /* no preamble */
  101. /* MII command register */
  102. #define MIICOMMAND_SCAN (1 << 0) /* scan status */
  103. #define MIICOMMAND_READ (1 << 1) /* read status */
  104. #define MIICOMMAND_WRITE (1 << 2) /* write control data */
  105. /* MII address register */
  106. #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
  107. #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
  108. #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
  109. MIIADDRESS_RGAD(reg))
  110. /* MII transmit data register */
  111. #define MIITX_DATA_VAL(x) ((x) & 0xffff)
  112. /* MII receive data register */
  113. #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
  114. /* MII status register */
  115. #define MIISTATUS_LINKFAIL (1 << 0)
  116. #define MIISTATUS_BUSY (1 << 1)
  117. #define MIISTATUS_INVALID (1 << 2)
  118. /* TX buffer descriptor */
  119. #define TX_BD_CS (1 << 0) /* carrier sense lost */
  120. #define TX_BD_DF (1 << 1) /* defer indication */
  121. #define TX_BD_LC (1 << 2) /* late collision */
  122. #define TX_BD_RL (1 << 3) /* retransmission limit */
  123. #define TX_BD_RETRY_MASK (0x00f0)
  124. #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
  125. #define TX_BD_UR (1 << 8) /* transmitter underrun */
  126. #define TX_BD_CRC (1 << 11) /* TX CRC enable */
  127. #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
  128. #define TX_BD_WRAP (1 << 13)
  129. #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
  130. #define TX_BD_READY (1 << 15) /* TX buffer ready */
  131. #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
  132. #define TX_BD_LEN_MASK (0xffff << 16)
  133. #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
  134. TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
  135. /* RX buffer descriptor */
  136. #define RX_BD_LC (1 << 0) /* late collision */
  137. #define RX_BD_CRC (1 << 1) /* RX CRC error */
  138. #define RX_BD_SF (1 << 2) /* short frame */
  139. #define RX_BD_TL (1 << 3) /* too long */
  140. #define RX_BD_DN (1 << 4) /* dribble nibble */
  141. #define RX_BD_IS (1 << 5) /* invalid symbol */
  142. #define RX_BD_OR (1 << 6) /* receiver overrun */
  143. #define RX_BD_MISS (1 << 7)
  144. #define RX_BD_CF (1 << 8) /* control frame */
  145. #define RX_BD_WRAP (1 << 13)
  146. #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
  147. #define RX_BD_EMPTY (1 << 15)
  148. #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
  149. #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
  150. RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
  151. #define ETHOC_BUFSIZ 1536
  152. #define ETHOC_ZLEN 64
  153. #define ETHOC_BD_BASE 0x400
  154. #define ETHOC_TIMEOUT (HZ / 2)
  155. #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
  156. /**
  157. * struct ethoc - driver-private device structure
  158. * @iobase: pointer to I/O memory region
  159. * @membase: pointer to buffer memory region
  160. * @dma_alloc: dma allocated buffer size
  161. * @io_region_size: I/O memory region size
  162. * @num_bd: number of buffer descriptors
  163. * @num_tx: number of send buffers
  164. * @cur_tx: last send buffer written
  165. * @dty_tx: last buffer actually sent
  166. * @num_rx: number of receive buffers
  167. * @cur_rx: current receive buffer
  168. * @vma: pointer to array of virtual memory addresses for buffers
  169. * @netdev: pointer to network device structure
  170. * @napi: NAPI structure
  171. * @msg_enable: device state flags
  172. * @lock: device lock
  173. * @phy: attached PHY
  174. * @mdio: MDIO bus for PHY access
  175. * @phy_id: address of attached PHY
  176. */
  177. struct ethoc {
  178. void __iomem *iobase;
  179. void __iomem *membase;
  180. int dma_alloc;
  181. resource_size_t io_region_size;
  182. unsigned int num_bd;
  183. unsigned int num_tx;
  184. unsigned int cur_tx;
  185. unsigned int dty_tx;
  186. unsigned int num_rx;
  187. unsigned int cur_rx;
  188. void **vma;
  189. struct net_device *netdev;
  190. struct napi_struct napi;
  191. u32 msg_enable;
  192. spinlock_t lock;
  193. struct phy_device *phy;
  194. struct mii_bus *mdio;
  195. struct clk *clk;
  196. s8 phy_id;
  197. };
  198. /**
  199. * struct ethoc_bd - buffer descriptor
  200. * @stat: buffer statistics
  201. * @addr: physical memory address
  202. */
  203. struct ethoc_bd {
  204. u32 stat;
  205. u32 addr;
  206. };
  207. static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
  208. {
  209. return ioread32(dev->iobase + offset);
  210. }
  211. static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
  212. {
  213. iowrite32(data, dev->iobase + offset);
  214. }
  215. static inline void ethoc_read_bd(struct ethoc *dev, int index,
  216. struct ethoc_bd *bd)
  217. {
  218. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  219. bd->stat = ethoc_read(dev, offset + 0);
  220. bd->addr = ethoc_read(dev, offset + 4);
  221. }
  222. static inline void ethoc_write_bd(struct ethoc *dev, int index,
  223. const struct ethoc_bd *bd)
  224. {
  225. loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  226. ethoc_write(dev, offset + 0, bd->stat);
  227. ethoc_write(dev, offset + 4, bd->addr);
  228. }
  229. static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
  230. {
  231. u32 imask = ethoc_read(dev, INT_MASK);
  232. imask |= mask;
  233. ethoc_write(dev, INT_MASK, imask);
  234. }
  235. static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
  236. {
  237. u32 imask = ethoc_read(dev, INT_MASK);
  238. imask &= ~mask;
  239. ethoc_write(dev, INT_MASK, imask);
  240. }
  241. static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
  242. {
  243. ethoc_write(dev, INT_SOURCE, mask);
  244. }
  245. static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
  246. {
  247. u32 mode = ethoc_read(dev, MODER);
  248. mode |= MODER_RXEN | MODER_TXEN;
  249. ethoc_write(dev, MODER, mode);
  250. }
  251. static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
  252. {
  253. u32 mode = ethoc_read(dev, MODER);
  254. mode &= ~(MODER_RXEN | MODER_TXEN);
  255. ethoc_write(dev, MODER, mode);
  256. }
  257. static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
  258. {
  259. struct ethoc_bd bd;
  260. int i;
  261. void *vma;
  262. dev->cur_tx = 0;
  263. dev->dty_tx = 0;
  264. dev->cur_rx = 0;
  265. ethoc_write(dev, TX_BD_NUM, dev->num_tx);
  266. /* setup transmission buffers */
  267. bd.addr = mem_start;
  268. bd.stat = TX_BD_IRQ | TX_BD_CRC;
  269. vma = dev->membase;
  270. for (i = 0; i < dev->num_tx; i++) {
  271. if (i == dev->num_tx - 1)
  272. bd.stat |= TX_BD_WRAP;
  273. ethoc_write_bd(dev, i, &bd);
  274. bd.addr += ETHOC_BUFSIZ;
  275. dev->vma[i] = vma;
  276. vma += ETHOC_BUFSIZ;
  277. }
  278. bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
  279. for (i = 0; i < dev->num_rx; i++) {
  280. if (i == dev->num_rx - 1)
  281. bd.stat |= RX_BD_WRAP;
  282. ethoc_write_bd(dev, dev->num_tx + i, &bd);
  283. bd.addr += ETHOC_BUFSIZ;
  284. dev->vma[dev->num_tx + i] = vma;
  285. vma += ETHOC_BUFSIZ;
  286. }
  287. return 0;
  288. }
  289. static int ethoc_reset(struct ethoc *dev)
  290. {
  291. u32 mode;
  292. /* TODO: reset controller? */
  293. ethoc_disable_rx_and_tx(dev);
  294. /* TODO: setup registers */
  295. /* enable FCS generation and automatic padding */
  296. mode = ethoc_read(dev, MODER);
  297. mode |= MODER_CRC | MODER_PAD;
  298. ethoc_write(dev, MODER, mode);
  299. /* set full-duplex mode */
  300. mode = ethoc_read(dev, MODER);
  301. mode |= MODER_FULLD;
  302. ethoc_write(dev, MODER, mode);
  303. ethoc_write(dev, IPGT, 0x15);
  304. ethoc_ack_irq(dev, INT_MASK_ALL);
  305. ethoc_enable_irq(dev, INT_MASK_ALL);
  306. ethoc_enable_rx_and_tx(dev);
  307. return 0;
  308. }
  309. static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
  310. struct ethoc_bd *bd)
  311. {
  312. struct net_device *netdev = dev->netdev;
  313. unsigned int ret = 0;
  314. if (bd->stat & RX_BD_TL) {
  315. dev_err(&netdev->dev, "RX: frame too long\n");
  316. netdev->stats.rx_length_errors++;
  317. ret++;
  318. }
  319. if (bd->stat & RX_BD_SF) {
  320. dev_err(&netdev->dev, "RX: frame too short\n");
  321. netdev->stats.rx_length_errors++;
  322. ret++;
  323. }
  324. if (bd->stat & RX_BD_DN) {
  325. dev_err(&netdev->dev, "RX: dribble nibble\n");
  326. netdev->stats.rx_frame_errors++;
  327. }
  328. if (bd->stat & RX_BD_CRC) {
  329. dev_err(&netdev->dev, "RX: wrong CRC\n");
  330. netdev->stats.rx_crc_errors++;
  331. ret++;
  332. }
  333. if (bd->stat & RX_BD_OR) {
  334. dev_err(&netdev->dev, "RX: overrun\n");
  335. netdev->stats.rx_over_errors++;
  336. ret++;
  337. }
  338. if (bd->stat & RX_BD_MISS)
  339. netdev->stats.rx_missed_errors++;
  340. if (bd->stat & RX_BD_LC) {
  341. dev_err(&netdev->dev, "RX: late collision\n");
  342. netdev->stats.collisions++;
  343. ret++;
  344. }
  345. return ret;
  346. }
  347. static int ethoc_rx(struct net_device *dev, int limit)
  348. {
  349. struct ethoc *priv = netdev_priv(dev);
  350. int count;
  351. for (count = 0; count < limit; ++count) {
  352. unsigned int entry;
  353. struct ethoc_bd bd;
  354. entry = priv->num_tx + priv->cur_rx;
  355. ethoc_read_bd(priv, entry, &bd);
  356. if (bd.stat & RX_BD_EMPTY) {
  357. ethoc_ack_irq(priv, INT_MASK_RX);
  358. /* If packet (interrupt) came in between checking
  359. * BD_EMTPY and clearing the interrupt source, then we
  360. * risk missing the packet as the RX interrupt won't
  361. * trigger right away when we reenable it; hence, check
  362. * BD_EMTPY here again to make sure there isn't such a
  363. * packet waiting for us...
  364. */
  365. ethoc_read_bd(priv, entry, &bd);
  366. if (bd.stat & RX_BD_EMPTY)
  367. break;
  368. }
  369. if (ethoc_update_rx_stats(priv, &bd) == 0) {
  370. int size = bd.stat >> 16;
  371. struct sk_buff *skb;
  372. size -= 4; /* strip the CRC */
  373. skb = netdev_alloc_skb_ip_align(dev, size);
  374. if (likely(skb)) {
  375. void *src = priv->vma[entry];
  376. memcpy_fromio(skb_put(skb, size), src, size);
  377. skb->protocol = eth_type_trans(skb, dev);
  378. dev->stats.rx_packets++;
  379. dev->stats.rx_bytes += size;
  380. netif_receive_skb(skb);
  381. } else {
  382. if (net_ratelimit())
  383. dev_warn(&dev->dev,
  384. "low on memory - packet dropped\n");
  385. dev->stats.rx_dropped++;
  386. break;
  387. }
  388. }
  389. /* clear the buffer descriptor so it can be reused */
  390. bd.stat &= ~RX_BD_STATS;
  391. bd.stat |= RX_BD_EMPTY;
  392. ethoc_write_bd(priv, entry, &bd);
  393. if (++priv->cur_rx == priv->num_rx)
  394. priv->cur_rx = 0;
  395. }
  396. return count;
  397. }
  398. static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
  399. {
  400. struct net_device *netdev = dev->netdev;
  401. if (bd->stat & TX_BD_LC) {
  402. dev_err(&netdev->dev, "TX: late collision\n");
  403. netdev->stats.tx_window_errors++;
  404. }
  405. if (bd->stat & TX_BD_RL) {
  406. dev_err(&netdev->dev, "TX: retransmit limit\n");
  407. netdev->stats.tx_aborted_errors++;
  408. }
  409. if (bd->stat & TX_BD_UR) {
  410. dev_err(&netdev->dev, "TX: underrun\n");
  411. netdev->stats.tx_fifo_errors++;
  412. }
  413. if (bd->stat & TX_BD_CS) {
  414. dev_err(&netdev->dev, "TX: carrier sense lost\n");
  415. netdev->stats.tx_carrier_errors++;
  416. }
  417. if (bd->stat & TX_BD_STATS)
  418. netdev->stats.tx_errors++;
  419. netdev->stats.collisions += (bd->stat >> 4) & 0xf;
  420. netdev->stats.tx_bytes += bd->stat >> 16;
  421. netdev->stats.tx_packets++;
  422. }
  423. static int ethoc_tx(struct net_device *dev, int limit)
  424. {
  425. struct ethoc *priv = netdev_priv(dev);
  426. int count;
  427. struct ethoc_bd bd;
  428. for (count = 0; count < limit; ++count) {
  429. unsigned int entry;
  430. entry = priv->dty_tx & (priv->num_tx-1);
  431. ethoc_read_bd(priv, entry, &bd);
  432. if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
  433. ethoc_ack_irq(priv, INT_MASK_TX);
  434. /* If interrupt came in between reading in the BD
  435. * and clearing the interrupt source, then we risk
  436. * missing the event as the TX interrupt won't trigger
  437. * right away when we reenable it; hence, check
  438. * BD_EMPTY here again to make sure there isn't such an
  439. * event pending...
  440. */
  441. ethoc_read_bd(priv, entry, &bd);
  442. if (bd.stat & TX_BD_READY ||
  443. (priv->dty_tx == priv->cur_tx))
  444. break;
  445. }
  446. ethoc_update_tx_stats(priv, &bd);
  447. priv->dty_tx++;
  448. }
  449. if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
  450. netif_wake_queue(dev);
  451. return count;
  452. }
  453. static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
  454. {
  455. struct net_device *dev = dev_id;
  456. struct ethoc *priv = netdev_priv(dev);
  457. u32 pending;
  458. u32 mask;
  459. /* Figure out what triggered the interrupt...
  460. * The tricky bit here is that the interrupt source bits get
  461. * set in INT_SOURCE for an event regardless of whether that
  462. * event is masked or not. Thus, in order to figure out what
  463. * triggered the interrupt, we need to remove the sources
  464. * for all events that are currently masked. This behaviour
  465. * is not particularly well documented but reasonable...
  466. */
  467. mask = ethoc_read(priv, INT_MASK);
  468. pending = ethoc_read(priv, INT_SOURCE);
  469. pending &= mask;
  470. if (unlikely(pending == 0))
  471. return IRQ_NONE;
  472. ethoc_ack_irq(priv, pending);
  473. /* We always handle the dropped packet interrupt */
  474. if (pending & INT_MASK_BUSY) {
  475. dev_err(&dev->dev, "packet dropped\n");
  476. dev->stats.rx_dropped++;
  477. }
  478. /* Handle receive/transmit event by switching to polling */
  479. if (pending & (INT_MASK_TX | INT_MASK_RX)) {
  480. ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  481. napi_schedule(&priv->napi);
  482. }
  483. return IRQ_HANDLED;
  484. }
  485. static int ethoc_get_mac_address(struct net_device *dev, void *addr)
  486. {
  487. struct ethoc *priv = netdev_priv(dev);
  488. u8 *mac = (u8 *)addr;
  489. u32 reg;
  490. reg = ethoc_read(priv, MAC_ADDR0);
  491. mac[2] = (reg >> 24) & 0xff;
  492. mac[3] = (reg >> 16) & 0xff;
  493. mac[4] = (reg >> 8) & 0xff;
  494. mac[5] = (reg >> 0) & 0xff;
  495. reg = ethoc_read(priv, MAC_ADDR1);
  496. mac[0] = (reg >> 8) & 0xff;
  497. mac[1] = (reg >> 0) & 0xff;
  498. return 0;
  499. }
  500. static int ethoc_poll(struct napi_struct *napi, int budget)
  501. {
  502. struct ethoc *priv = container_of(napi, struct ethoc, napi);
  503. int rx_work_done = 0;
  504. int tx_work_done = 0;
  505. rx_work_done = ethoc_rx(priv->netdev, budget);
  506. tx_work_done = ethoc_tx(priv->netdev, budget);
  507. if (rx_work_done < budget && tx_work_done < budget) {
  508. napi_complete(napi);
  509. ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  510. }
  511. return rx_work_done;
  512. }
  513. static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
  514. {
  515. struct ethoc *priv = bus->priv;
  516. int i;
  517. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
  518. ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
  519. for (i = 0; i < 5; i++) {
  520. u32 status = ethoc_read(priv, MIISTATUS);
  521. if (!(status & MIISTATUS_BUSY)) {
  522. u32 data = ethoc_read(priv, MIIRX_DATA);
  523. /* reset MII command register */
  524. ethoc_write(priv, MIICOMMAND, 0);
  525. return data;
  526. }
  527. usleep_range(100, 200);
  528. }
  529. return -EBUSY;
  530. }
  531. static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
  532. {
  533. struct ethoc *priv = bus->priv;
  534. int i;
  535. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
  536. ethoc_write(priv, MIITX_DATA, val);
  537. ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
  538. for (i = 0; i < 5; i++) {
  539. u32 stat = ethoc_read(priv, MIISTATUS);
  540. if (!(stat & MIISTATUS_BUSY)) {
  541. /* reset MII command register */
  542. ethoc_write(priv, MIICOMMAND, 0);
  543. return 0;
  544. }
  545. usleep_range(100, 200);
  546. }
  547. return -EBUSY;
  548. }
  549. static void ethoc_mdio_poll(struct net_device *dev)
  550. {
  551. }
  552. static int ethoc_mdio_probe(struct net_device *dev)
  553. {
  554. struct ethoc *priv = netdev_priv(dev);
  555. struct phy_device *phy;
  556. int err;
  557. if (priv->phy_id != -1)
  558. phy = priv->mdio->phy_map[priv->phy_id];
  559. else
  560. phy = phy_find_first(priv->mdio);
  561. if (!phy) {
  562. dev_err(&dev->dev, "no PHY found\n");
  563. return -ENXIO;
  564. }
  565. err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
  566. PHY_INTERFACE_MODE_GMII);
  567. if (err) {
  568. dev_err(&dev->dev, "could not attach to PHY\n");
  569. return err;
  570. }
  571. priv->phy = phy;
  572. phy->advertising &= ~(ADVERTISED_1000baseT_Full |
  573. ADVERTISED_1000baseT_Half);
  574. phy->supported &= ~(SUPPORTED_1000baseT_Full |
  575. SUPPORTED_1000baseT_Half);
  576. return 0;
  577. }
  578. static int ethoc_open(struct net_device *dev)
  579. {
  580. struct ethoc *priv = netdev_priv(dev);
  581. int ret;
  582. ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
  583. dev->name, dev);
  584. if (ret)
  585. return ret;
  586. ethoc_init_ring(priv, dev->mem_start);
  587. ethoc_reset(priv);
  588. if (netif_queue_stopped(dev)) {
  589. dev_dbg(&dev->dev, " resuming queue\n");
  590. netif_wake_queue(dev);
  591. } else {
  592. dev_dbg(&dev->dev, " starting queue\n");
  593. netif_start_queue(dev);
  594. }
  595. phy_start(priv->phy);
  596. napi_enable(&priv->napi);
  597. if (netif_msg_ifup(priv)) {
  598. dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
  599. dev->base_addr, dev->mem_start, dev->mem_end);
  600. }
  601. return 0;
  602. }
  603. static int ethoc_stop(struct net_device *dev)
  604. {
  605. struct ethoc *priv = netdev_priv(dev);
  606. napi_disable(&priv->napi);
  607. if (priv->phy)
  608. phy_stop(priv->phy);
  609. ethoc_disable_rx_and_tx(priv);
  610. free_irq(dev->irq, dev);
  611. if (!netif_queue_stopped(dev))
  612. netif_stop_queue(dev);
  613. return 0;
  614. }
  615. static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  616. {
  617. struct ethoc *priv = netdev_priv(dev);
  618. struct mii_ioctl_data *mdio = if_mii(ifr);
  619. struct phy_device *phy = NULL;
  620. if (!netif_running(dev))
  621. return -EINVAL;
  622. if (cmd != SIOCGMIIPHY) {
  623. if (mdio->phy_id >= PHY_MAX_ADDR)
  624. return -ERANGE;
  625. phy = priv->mdio->phy_map[mdio->phy_id];
  626. if (!phy)
  627. return -ENODEV;
  628. } else {
  629. phy = priv->phy;
  630. }
  631. return phy_mii_ioctl(phy, ifr, cmd);
  632. }
  633. static void ethoc_do_set_mac_address(struct net_device *dev)
  634. {
  635. struct ethoc *priv = netdev_priv(dev);
  636. unsigned char *mac = dev->dev_addr;
  637. ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
  638. (mac[4] << 8) | (mac[5] << 0));
  639. ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
  640. }
  641. static int ethoc_set_mac_address(struct net_device *dev, void *p)
  642. {
  643. const struct sockaddr *addr = p;
  644. if (!is_valid_ether_addr(addr->sa_data))
  645. return -EADDRNOTAVAIL;
  646. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  647. ethoc_do_set_mac_address(dev);
  648. return 0;
  649. }
  650. static void ethoc_set_multicast_list(struct net_device *dev)
  651. {
  652. struct ethoc *priv = netdev_priv(dev);
  653. u32 mode = ethoc_read(priv, MODER);
  654. struct netdev_hw_addr *ha;
  655. u32 hash[2] = { 0, 0 };
  656. /* set loopback mode if requested */
  657. if (dev->flags & IFF_LOOPBACK)
  658. mode |= MODER_LOOP;
  659. else
  660. mode &= ~MODER_LOOP;
  661. /* receive broadcast frames if requested */
  662. if (dev->flags & IFF_BROADCAST)
  663. mode &= ~MODER_BRO;
  664. else
  665. mode |= MODER_BRO;
  666. /* enable promiscuous mode if requested */
  667. if (dev->flags & IFF_PROMISC)
  668. mode |= MODER_PRO;
  669. else
  670. mode &= ~MODER_PRO;
  671. ethoc_write(priv, MODER, mode);
  672. /* receive multicast frames */
  673. if (dev->flags & IFF_ALLMULTI) {
  674. hash[0] = 0xffffffff;
  675. hash[1] = 0xffffffff;
  676. } else {
  677. netdev_for_each_mc_addr(ha, dev) {
  678. u32 crc = ether_crc(ETH_ALEN, ha->addr);
  679. int bit = (crc >> 26) & 0x3f;
  680. hash[bit >> 5] |= 1 << (bit & 0x1f);
  681. }
  682. }
  683. ethoc_write(priv, ETH_HASH0, hash[0]);
  684. ethoc_write(priv, ETH_HASH1, hash[1]);
  685. }
  686. static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
  687. {
  688. return -ENOSYS;
  689. }
  690. static void ethoc_tx_timeout(struct net_device *dev)
  691. {
  692. struct ethoc *priv = netdev_priv(dev);
  693. u32 pending = ethoc_read(priv, INT_SOURCE);
  694. if (likely(pending))
  695. ethoc_interrupt(dev->irq, dev);
  696. }
  697. static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
  698. {
  699. struct ethoc *priv = netdev_priv(dev);
  700. struct ethoc_bd bd;
  701. unsigned int entry;
  702. void *dest;
  703. if (unlikely(skb->len > ETHOC_BUFSIZ)) {
  704. dev->stats.tx_errors++;
  705. goto out;
  706. }
  707. entry = priv->cur_tx % priv->num_tx;
  708. spin_lock_irq(&priv->lock);
  709. priv->cur_tx++;
  710. ethoc_read_bd(priv, entry, &bd);
  711. if (unlikely(skb->len < ETHOC_ZLEN))
  712. bd.stat |= TX_BD_PAD;
  713. else
  714. bd.stat &= ~TX_BD_PAD;
  715. dest = priv->vma[entry];
  716. memcpy_toio(dest, skb->data, skb->len);
  717. bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
  718. bd.stat |= TX_BD_LEN(skb->len);
  719. ethoc_write_bd(priv, entry, &bd);
  720. bd.stat |= TX_BD_READY;
  721. ethoc_write_bd(priv, entry, &bd);
  722. if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
  723. dev_dbg(&dev->dev, "stopping queue\n");
  724. netif_stop_queue(dev);
  725. }
  726. spin_unlock_irq(&priv->lock);
  727. skb_tx_timestamp(skb);
  728. out:
  729. dev_kfree_skb(skb);
  730. return NETDEV_TX_OK;
  731. }
  732. static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  733. {
  734. struct ethoc *priv = netdev_priv(dev);
  735. struct phy_device *phydev = priv->phy;
  736. if (!phydev)
  737. return -EOPNOTSUPP;
  738. return phy_ethtool_gset(phydev, cmd);
  739. }
  740. static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  741. {
  742. struct ethoc *priv = netdev_priv(dev);
  743. struct phy_device *phydev = priv->phy;
  744. if (!phydev)
  745. return -EOPNOTSUPP;
  746. return phy_ethtool_sset(phydev, cmd);
  747. }
  748. static int ethoc_get_regs_len(struct net_device *netdev)
  749. {
  750. return ETH_END;
  751. }
  752. static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  753. void *p)
  754. {
  755. struct ethoc *priv = netdev_priv(dev);
  756. u32 *regs_buff = p;
  757. unsigned i;
  758. regs->version = 0;
  759. for (i = 0; i < ETH_END / sizeof(u32); ++i)
  760. regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
  761. }
  762. static void ethoc_get_ringparam(struct net_device *dev,
  763. struct ethtool_ringparam *ring)
  764. {
  765. struct ethoc *priv = netdev_priv(dev);
  766. ring->rx_max_pending = priv->num_bd - 1;
  767. ring->rx_mini_max_pending = 0;
  768. ring->rx_jumbo_max_pending = 0;
  769. ring->tx_max_pending = priv->num_bd - 1;
  770. ring->rx_pending = priv->num_rx;
  771. ring->rx_mini_pending = 0;
  772. ring->rx_jumbo_pending = 0;
  773. ring->tx_pending = priv->num_tx;
  774. }
  775. static int ethoc_set_ringparam(struct net_device *dev,
  776. struct ethtool_ringparam *ring)
  777. {
  778. struct ethoc *priv = netdev_priv(dev);
  779. if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
  780. ring->tx_pending + ring->rx_pending > priv->num_bd)
  781. return -EINVAL;
  782. if (ring->rx_mini_pending || ring->rx_jumbo_pending)
  783. return -EINVAL;
  784. if (netif_running(dev)) {
  785. netif_tx_disable(dev);
  786. ethoc_disable_rx_and_tx(priv);
  787. ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  788. synchronize_irq(dev->irq);
  789. }
  790. priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
  791. priv->num_rx = ring->rx_pending;
  792. ethoc_init_ring(priv, dev->mem_start);
  793. if (netif_running(dev)) {
  794. ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
  795. ethoc_enable_rx_and_tx(priv);
  796. netif_wake_queue(dev);
  797. }
  798. return 0;
  799. }
  800. const struct ethtool_ops ethoc_ethtool_ops = {
  801. .get_settings = ethoc_get_settings,
  802. .set_settings = ethoc_set_settings,
  803. .get_regs_len = ethoc_get_regs_len,
  804. .get_regs = ethoc_get_regs,
  805. .get_link = ethtool_op_get_link,
  806. .get_ringparam = ethoc_get_ringparam,
  807. .set_ringparam = ethoc_set_ringparam,
  808. .get_ts_info = ethtool_op_get_ts_info,
  809. };
  810. static const struct net_device_ops ethoc_netdev_ops = {
  811. .ndo_open = ethoc_open,
  812. .ndo_stop = ethoc_stop,
  813. .ndo_do_ioctl = ethoc_ioctl,
  814. .ndo_set_mac_address = ethoc_set_mac_address,
  815. .ndo_set_rx_mode = ethoc_set_multicast_list,
  816. .ndo_change_mtu = ethoc_change_mtu,
  817. .ndo_tx_timeout = ethoc_tx_timeout,
  818. .ndo_start_xmit = ethoc_start_xmit,
  819. };
  820. /**
  821. * ethoc_probe - initialize OpenCores ethernet MAC
  822. * pdev: platform device
  823. */
  824. static int ethoc_probe(struct platform_device *pdev)
  825. {
  826. struct net_device *netdev = NULL;
  827. struct resource *res = NULL;
  828. struct resource *mmio = NULL;
  829. struct resource *mem = NULL;
  830. struct ethoc *priv = NULL;
  831. unsigned int phy;
  832. int num_bd;
  833. int ret = 0;
  834. bool random_mac = false;
  835. struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  836. u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
  837. /* allocate networking device */
  838. netdev = alloc_etherdev(sizeof(struct ethoc));
  839. if (!netdev) {
  840. ret = -ENOMEM;
  841. goto out;
  842. }
  843. SET_NETDEV_DEV(netdev, &pdev->dev);
  844. platform_set_drvdata(pdev, netdev);
  845. /* obtain I/O memory space */
  846. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  847. if (!res) {
  848. dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
  849. ret = -ENXIO;
  850. goto free;
  851. }
  852. mmio = devm_request_mem_region(&pdev->dev, res->start,
  853. resource_size(res), res->name);
  854. if (!mmio) {
  855. dev_err(&pdev->dev, "cannot request I/O memory space\n");
  856. ret = -ENXIO;
  857. goto free;
  858. }
  859. netdev->base_addr = mmio->start;
  860. /* obtain buffer memory space */
  861. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  862. if (res) {
  863. mem = devm_request_mem_region(&pdev->dev, res->start,
  864. resource_size(res), res->name);
  865. if (!mem) {
  866. dev_err(&pdev->dev, "cannot request memory space\n");
  867. ret = -ENXIO;
  868. goto free;
  869. }
  870. netdev->mem_start = mem->start;
  871. netdev->mem_end = mem->end;
  872. }
  873. /* obtain device IRQ number */
  874. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  875. if (!res) {
  876. dev_err(&pdev->dev, "cannot obtain IRQ\n");
  877. ret = -ENXIO;
  878. goto free;
  879. }
  880. netdev->irq = res->start;
  881. /* setup driver-private data */
  882. priv = netdev_priv(netdev);
  883. priv->netdev = netdev;
  884. priv->dma_alloc = 0;
  885. priv->io_region_size = resource_size(mmio);
  886. priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
  887. resource_size(mmio));
  888. if (!priv->iobase) {
  889. dev_err(&pdev->dev, "cannot remap I/O memory space\n");
  890. ret = -ENXIO;
  891. goto error;
  892. }
  893. if (netdev->mem_end) {
  894. priv->membase = devm_ioremap_nocache(&pdev->dev,
  895. netdev->mem_start, resource_size(mem));
  896. if (!priv->membase) {
  897. dev_err(&pdev->dev, "cannot remap memory space\n");
  898. ret = -ENXIO;
  899. goto error;
  900. }
  901. } else {
  902. /* Allocate buffer memory */
  903. priv->membase = dmam_alloc_coherent(&pdev->dev,
  904. buffer_size, (void *)&netdev->mem_start,
  905. GFP_KERNEL);
  906. if (!priv->membase) {
  907. dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
  908. buffer_size);
  909. ret = -ENOMEM;
  910. goto error;
  911. }
  912. netdev->mem_end = netdev->mem_start + buffer_size;
  913. priv->dma_alloc = buffer_size;
  914. }
  915. /* calculate the number of TX/RX buffers, maximum 128 supported */
  916. num_bd = min_t(unsigned int,
  917. 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
  918. if (num_bd < 4) {
  919. ret = -ENODEV;
  920. goto error;
  921. }
  922. priv->num_bd = num_bd;
  923. /* num_tx must be a power of two */
  924. priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
  925. priv->num_rx = num_bd - priv->num_tx;
  926. dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
  927. priv->num_tx, priv->num_rx);
  928. priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
  929. if (!priv->vma) {
  930. ret = -ENOMEM;
  931. goto error;
  932. }
  933. /* Allow the platform setup code to pass in a MAC address. */
  934. if (pdata) {
  935. memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
  936. priv->phy_id = pdata->phy_id;
  937. } else {
  938. const uint8_t *mac;
  939. mac = of_get_property(pdev->dev.of_node,
  940. "local-mac-address",
  941. NULL);
  942. if (mac)
  943. memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
  944. priv->phy_id = -1;
  945. }
  946. /* Check that the given MAC address is valid. If it isn't, read the
  947. * current MAC from the controller.
  948. */
  949. if (!is_valid_ether_addr(netdev->dev_addr))
  950. ethoc_get_mac_address(netdev, netdev->dev_addr);
  951. /* Check the MAC again for validity, if it still isn't choose and
  952. * program a random one.
  953. */
  954. if (!is_valid_ether_addr(netdev->dev_addr)) {
  955. eth_random_addr(netdev->dev_addr);
  956. random_mac = true;
  957. }
  958. ethoc_do_set_mac_address(netdev);
  959. if (random_mac)
  960. netdev->addr_assign_type = NET_ADDR_RANDOM;
  961. /* Allow the platform setup code to adjust MII management bus clock. */
  962. if (!eth_clkfreq) {
  963. struct clk *clk = devm_clk_get(&pdev->dev, NULL);
  964. if (!IS_ERR(clk)) {
  965. priv->clk = clk;
  966. clk_prepare_enable(clk);
  967. eth_clkfreq = clk_get_rate(clk);
  968. }
  969. }
  970. if (eth_clkfreq) {
  971. u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
  972. if (!clkdiv)
  973. clkdiv = 2;
  974. dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
  975. ethoc_write(priv, MIIMODER,
  976. (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
  977. clkdiv);
  978. }
  979. /* register MII bus */
  980. priv->mdio = mdiobus_alloc();
  981. if (!priv->mdio) {
  982. ret = -ENOMEM;
  983. goto free;
  984. }
  985. priv->mdio->name = "ethoc-mdio";
  986. snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
  987. priv->mdio->name, pdev->id);
  988. priv->mdio->read = ethoc_mdio_read;
  989. priv->mdio->write = ethoc_mdio_write;
  990. priv->mdio->priv = priv;
  991. priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  992. if (!priv->mdio->irq) {
  993. ret = -ENOMEM;
  994. goto free_mdio;
  995. }
  996. for (phy = 0; phy < PHY_MAX_ADDR; phy++)
  997. priv->mdio->irq[phy] = PHY_POLL;
  998. ret = mdiobus_register(priv->mdio);
  999. if (ret) {
  1000. dev_err(&netdev->dev, "failed to register MDIO bus\n");
  1001. goto free_mdio;
  1002. }
  1003. ret = ethoc_mdio_probe(netdev);
  1004. if (ret) {
  1005. dev_err(&netdev->dev, "failed to probe MDIO bus\n");
  1006. goto error;
  1007. }
  1008. /* setup the net_device structure */
  1009. netdev->netdev_ops = &ethoc_netdev_ops;
  1010. netdev->watchdog_timeo = ETHOC_TIMEOUT;
  1011. netdev->features |= 0;
  1012. netdev->ethtool_ops = &ethoc_ethtool_ops;
  1013. /* setup NAPI */
  1014. netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
  1015. spin_lock_init(&priv->lock);
  1016. ret = register_netdev(netdev);
  1017. if (ret < 0) {
  1018. dev_err(&netdev->dev, "failed to register interface\n");
  1019. goto error2;
  1020. }
  1021. goto out;
  1022. error2:
  1023. netif_napi_del(&priv->napi);
  1024. error:
  1025. mdiobus_unregister(priv->mdio);
  1026. free_mdio:
  1027. kfree(priv->mdio->irq);
  1028. mdiobus_free(priv->mdio);
  1029. free:
  1030. if (priv->clk)
  1031. clk_disable_unprepare(priv->clk);
  1032. free_netdev(netdev);
  1033. out:
  1034. return ret;
  1035. }
  1036. /**
  1037. * ethoc_remove - shutdown OpenCores ethernet MAC
  1038. * @pdev: platform device
  1039. */
  1040. static int ethoc_remove(struct platform_device *pdev)
  1041. {
  1042. struct net_device *netdev = platform_get_drvdata(pdev);
  1043. struct ethoc *priv = netdev_priv(netdev);
  1044. if (netdev) {
  1045. netif_napi_del(&priv->napi);
  1046. phy_disconnect(priv->phy);
  1047. priv->phy = NULL;
  1048. if (priv->mdio) {
  1049. mdiobus_unregister(priv->mdio);
  1050. kfree(priv->mdio->irq);
  1051. mdiobus_free(priv->mdio);
  1052. }
  1053. if (priv->clk)
  1054. clk_disable_unprepare(priv->clk);
  1055. unregister_netdev(netdev);
  1056. free_netdev(netdev);
  1057. }
  1058. return 0;
  1059. }
  1060. #ifdef CONFIG_PM
  1061. static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
  1062. {
  1063. return -ENOSYS;
  1064. }
  1065. static int ethoc_resume(struct platform_device *pdev)
  1066. {
  1067. return -ENOSYS;
  1068. }
  1069. #else
  1070. # define ethoc_suspend NULL
  1071. # define ethoc_resume NULL
  1072. #endif
  1073. static const struct of_device_id ethoc_match[] = {
  1074. { .compatible = "opencores,ethoc", },
  1075. {},
  1076. };
  1077. MODULE_DEVICE_TABLE(of, ethoc_match);
  1078. static struct platform_driver ethoc_driver = {
  1079. .probe = ethoc_probe,
  1080. .remove = ethoc_remove,
  1081. .suspend = ethoc_suspend,
  1082. .resume = ethoc_resume,
  1083. .driver = {
  1084. .name = "ethoc",
  1085. .of_match_table = ethoc_match,
  1086. },
  1087. };
  1088. module_platform_driver(ethoc_driver);
  1089. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  1090. MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
  1091. MODULE_LICENSE("GPL v2");