xgene_enet_main.h 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226
  1. /* Applied Micro X-Gene SoC Ethernet Driver
  2. *
  3. * Copyright (c) 2014, Applied Micro Circuits Corporation
  4. * Authors: Iyappan Subramanian <isubramanian@apm.com>
  5. * Ravi Patel <rapatel@apm.com>
  6. * Keyur Chudgar <kchudgar@apm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #ifndef __XGENE_ENET_MAIN_H__
  22. #define __XGENE_ENET_MAIN_H__
  23. #include <linux/acpi.h>
  24. #include <linux/clk.h>
  25. #include <linux/efi.h>
  26. #include <linux/io.h>
  27. #include <linux/of_platform.h>
  28. #include <linux/of_net.h>
  29. #include <linux/of_mdio.h>
  30. #include <linux/module.h>
  31. #include <net/ip.h>
  32. #include <linux/prefetch.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/phy.h>
  35. #include "xgene_enet_hw.h"
  36. #include "xgene_enet_ring2.h"
  37. #define XGENE_DRV_VERSION "v1.0"
  38. #define XGENE_ENET_MAX_MTU 1536
  39. #define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
  40. #define BUFLEN_16K (16 * 1024)
  41. #define NUM_PKT_BUF 64
  42. #define NUM_BUFPOOL 32
  43. #define MAX_EXP_BUFFS 256
  44. #define XGENE_ENET_MSS 1448
  45. #define XGENE_MIN_ENET_FRAME_SIZE 60
  46. #define START_CPU_BUFNUM_0 0
  47. #define START_ETH_BUFNUM_0 2
  48. #define START_BP_BUFNUM_0 0x22
  49. #define START_RING_NUM_0 8
  50. #define START_CPU_BUFNUM_1 12
  51. #define START_ETH_BUFNUM_1 10
  52. #define START_BP_BUFNUM_1 0x2A
  53. #define START_RING_NUM_1 264
  54. #define X2_START_CPU_BUFNUM_0 0
  55. #define X2_START_ETH_BUFNUM_0 0
  56. #define X2_START_BP_BUFNUM_0 0x20
  57. #define X2_START_RING_NUM_0 0
  58. #define X2_START_CPU_BUFNUM_1 0xc
  59. #define X2_START_ETH_BUFNUM_1 0
  60. #define X2_START_BP_BUFNUM_1 0x20
  61. #define X2_START_RING_NUM_1 256
  62. #define IRQ_ID_SIZE 16
  63. #define XGENE_MAX_TXC_RINGS 1
  64. #define PHY_POLL_LINK_ON (10 * HZ)
  65. #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
  66. enum xgene_enet_id {
  67. XGENE_ENET1 = 1,
  68. XGENE_ENET2
  69. };
  70. /* software context of a descriptor ring */
  71. struct xgene_enet_desc_ring {
  72. struct net_device *ndev;
  73. u16 id;
  74. u16 num;
  75. u16 head;
  76. u16 tail;
  77. u16 exp_buf_tail;
  78. u16 slots;
  79. u16 irq;
  80. char irq_name[IRQ_ID_SIZE];
  81. u32 size;
  82. u32 state[X2_NUM_RING_CONFIG];
  83. void __iomem *cmd_base;
  84. void __iomem *cmd;
  85. dma_addr_t dma;
  86. dma_addr_t irq_mbox_dma;
  87. void *irq_mbox_addr;
  88. u16 dst_ring_num;
  89. u8 nbufpool;
  90. struct sk_buff *(*rx_skb);
  91. struct sk_buff *(*cp_skb);
  92. dma_addr_t *frag_dma_addr;
  93. enum xgene_enet_ring_cfgsize cfgsize;
  94. struct xgene_enet_desc_ring *cp_ring;
  95. struct xgene_enet_desc_ring *buf_pool;
  96. struct napi_struct napi;
  97. union {
  98. void *desc_addr;
  99. struct xgene_enet_raw_desc *raw_desc;
  100. struct xgene_enet_raw_desc16 *raw_desc16;
  101. };
  102. __le64 *exp_bufs;
  103. };
  104. struct xgene_mac_ops {
  105. void (*init)(struct xgene_enet_pdata *pdata);
  106. void (*reset)(struct xgene_enet_pdata *pdata);
  107. void (*tx_enable)(struct xgene_enet_pdata *pdata);
  108. void (*rx_enable)(struct xgene_enet_pdata *pdata);
  109. void (*tx_disable)(struct xgene_enet_pdata *pdata);
  110. void (*rx_disable)(struct xgene_enet_pdata *pdata);
  111. void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
  112. void (*set_mss)(struct xgene_enet_pdata *pdata);
  113. void (*link_state)(struct work_struct *work);
  114. };
  115. struct xgene_port_ops {
  116. int (*reset)(struct xgene_enet_pdata *pdata);
  117. void (*cle_bypass)(struct xgene_enet_pdata *pdata,
  118. u32 dst_ring_num, u16 bufpool_id);
  119. void (*shutdown)(struct xgene_enet_pdata *pdata);
  120. };
  121. struct xgene_ring_ops {
  122. u8 num_ring_config;
  123. u8 num_ring_id_shift;
  124. struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
  125. void (*clear)(struct xgene_enet_desc_ring *);
  126. void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
  127. u32 (*len)(struct xgene_enet_desc_ring *);
  128. };
  129. /* ethernet private data */
  130. struct xgene_enet_pdata {
  131. struct net_device *ndev;
  132. struct mii_bus *mdio_bus;
  133. struct phy_device *phy_dev;
  134. int phy_speed;
  135. struct clk *clk;
  136. struct platform_device *pdev;
  137. enum xgene_enet_id enet_id;
  138. struct xgene_enet_desc_ring *tx_ring;
  139. struct xgene_enet_desc_ring *rx_ring;
  140. char *dev_name;
  141. u32 rx_buff_cnt;
  142. u32 tx_qcnt_hi;
  143. u32 cp_qcnt_hi;
  144. u32 cp_qcnt_low;
  145. u32 rx_irq;
  146. u32 txc_irq;
  147. u8 cq_cnt;
  148. void __iomem *eth_csr_addr;
  149. void __iomem *eth_ring_if_addr;
  150. void __iomem *eth_diag_csr_addr;
  151. void __iomem *mcx_mac_addr;
  152. void __iomem *mcx_mac_csr_addr;
  153. void __iomem *base_addr;
  154. void __iomem *ring_csr_addr;
  155. void __iomem *ring_cmd_addr;
  156. int phy_mode;
  157. enum xgene_enet_rm rm;
  158. struct rtnl_link_stats64 stats;
  159. struct xgene_mac_ops *mac_ops;
  160. struct xgene_port_ops *port_ops;
  161. struct xgene_ring_ops *ring_ops;
  162. struct delayed_work link_work;
  163. u32 port_id;
  164. u8 cpu_bufnum;
  165. u8 eth_bufnum;
  166. u8 bp_bufnum;
  167. u16 ring_num;
  168. u32 mss;
  169. };
  170. struct xgene_indirect_ctl {
  171. void __iomem *addr;
  172. void __iomem *ctl;
  173. void __iomem *cmd;
  174. void __iomem *cmd_done;
  175. };
  176. /* Set the specified value into a bit-field defined by its starting position
  177. * and length within a single u64.
  178. */
  179. static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
  180. {
  181. return (val & ((1ULL << len) - 1)) << pos;
  182. }
  183. #define SET_VAL(field, val) \
  184. xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
  185. #define SET_BIT(field) \
  186. xgene_enet_set_field_value(field ## _POS, 1, 1)
  187. /* Get the value from a bit-field defined by its starting position
  188. * and length within the specified u64.
  189. */
  190. static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
  191. {
  192. return (src >> pos) & ((1ULL << len) - 1);
  193. }
  194. #define GET_VAL(field, src) \
  195. xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
  196. #define GET_BIT(field, src) \
  197. xgene_enet_get_field_value(field ## _POS, 1, src)
  198. static inline struct device *ndev_to_dev(struct net_device *ndev)
  199. {
  200. return ndev->dev.parent;
  201. }
  202. void xgene_enet_set_ethtool_ops(struct net_device *netdev);
  203. #endif /* __XGENE_ENET_MAIN_H__ */