mv88e6060.c 6.7 KB

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  1. /*
  2. * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
  3. * Copyright (c) 2008-2009 Marvell Semiconductor
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/jiffies.h>
  12. #include <linux/list.h>
  13. #include <linux/module.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/phy.h>
  16. #include <net/dsa.h>
  17. #define REG_PORT(p) (8 + (p))
  18. #define REG_GLOBAL 0x0f
  19. static int reg_read(struct dsa_switch *ds, int addr, int reg)
  20. {
  21. struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  22. if (bus == NULL)
  23. return -EINVAL;
  24. return mdiobus_read(bus, ds->pd->sw_addr + addr, reg);
  25. }
  26. #define REG_READ(addr, reg) \
  27. ({ \
  28. int __ret; \
  29. \
  30. __ret = reg_read(ds, addr, reg); \
  31. if (__ret < 0) \
  32. return __ret; \
  33. __ret; \
  34. })
  35. static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  36. {
  37. struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  38. if (bus == NULL)
  39. return -EINVAL;
  40. return mdiobus_write(bus, ds->pd->sw_addr + addr, reg, val);
  41. }
  42. #define REG_WRITE(addr, reg, val) \
  43. ({ \
  44. int __ret; \
  45. \
  46. __ret = reg_write(ds, addr, reg, val); \
  47. if (__ret < 0) \
  48. return __ret; \
  49. })
  50. static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
  51. {
  52. struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  53. int ret;
  54. if (bus == NULL)
  55. return NULL;
  56. ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
  57. if (ret >= 0) {
  58. if (ret == 0x0600)
  59. return "Marvell 88E6060 (A0)";
  60. if (ret == 0x0601 || ret == 0x0602)
  61. return "Marvell 88E6060 (B0)";
  62. if ((ret & 0xfff0) == 0x0600)
  63. return "Marvell 88E6060";
  64. }
  65. return NULL;
  66. }
  67. static int mv88e6060_switch_reset(struct dsa_switch *ds)
  68. {
  69. int i;
  70. int ret;
  71. unsigned long timeout;
  72. /* Set all ports to the disabled state. */
  73. for (i = 0; i < 6; i++) {
  74. ret = REG_READ(REG_PORT(i), 0x04);
  75. REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  76. }
  77. /* Wait for transmit queues to drain. */
  78. usleep_range(2000, 4000);
  79. /* Reset the switch. */
  80. REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
  81. /* Wait up to one second for reset to complete. */
  82. timeout = jiffies + 1 * HZ;
  83. while (time_before(jiffies, timeout)) {
  84. ret = REG_READ(REG_GLOBAL, 0x00);
  85. if ((ret & 0x8000) == 0x0000)
  86. break;
  87. usleep_range(1000, 2000);
  88. }
  89. if (time_after(jiffies, timeout))
  90. return -ETIMEDOUT;
  91. return 0;
  92. }
  93. static int mv88e6060_setup_global(struct dsa_switch *ds)
  94. {
  95. /* Disable discarding of frames with excessive collisions,
  96. * set the maximum frame size to 1536 bytes, and mask all
  97. * interrupt sources.
  98. */
  99. REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
  100. /* Enable automatic address learning, set the address
  101. * database size to 1024 entries, and set the default aging
  102. * time to 5 minutes.
  103. */
  104. REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
  105. return 0;
  106. }
  107. static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
  108. {
  109. int addr = REG_PORT(p);
  110. /* Do not force flow control, disable Ingress and Egress
  111. * Header tagging, disable VLAN tunneling, and set the port
  112. * state to Forwarding. Additionally, if this is the CPU
  113. * port, enable Ingress and Egress Trailer tagging mode.
  114. */
  115. REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
  116. /* Port based VLAN map: give each port its own address
  117. * database, allow the CPU port to talk to each of the 'real'
  118. * ports, and allow each of the 'real' ports to only talk to
  119. * the CPU port.
  120. */
  121. REG_WRITE(addr, 0x06,
  122. ((p & 0xf) << 12) |
  123. (dsa_is_cpu_port(ds, p) ?
  124. ds->phys_port_mask :
  125. (1 << ds->dst->cpu_port)));
  126. /* Port Association Vector: when learning source addresses
  127. * of packets, add the address to the address database using
  128. * a port bitmap that has only the bit for this port set and
  129. * the other bits clear.
  130. */
  131. REG_WRITE(addr, 0x0b, 1 << p);
  132. return 0;
  133. }
  134. static int mv88e6060_setup(struct dsa_switch *ds)
  135. {
  136. int i;
  137. int ret;
  138. ret = mv88e6060_switch_reset(ds);
  139. if (ret < 0)
  140. return ret;
  141. /* @@@ initialise atu */
  142. ret = mv88e6060_setup_global(ds);
  143. if (ret < 0)
  144. return ret;
  145. for (i = 0; i < 6; i++) {
  146. ret = mv88e6060_setup_port(ds, i);
  147. if (ret < 0)
  148. return ret;
  149. }
  150. return 0;
  151. }
  152. static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
  153. {
  154. REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
  155. REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
  156. REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
  157. return 0;
  158. }
  159. static int mv88e6060_port_to_phy_addr(int port)
  160. {
  161. if (port >= 0 && port <= 5)
  162. return port;
  163. return -1;
  164. }
  165. static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
  166. {
  167. int addr;
  168. addr = mv88e6060_port_to_phy_addr(port);
  169. if (addr == -1)
  170. return 0xffff;
  171. return reg_read(ds, addr, regnum);
  172. }
  173. static int
  174. mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  175. {
  176. int addr;
  177. addr = mv88e6060_port_to_phy_addr(port);
  178. if (addr == -1)
  179. return 0xffff;
  180. return reg_write(ds, addr, regnum, val);
  181. }
  182. static void mv88e6060_poll_link(struct dsa_switch *ds)
  183. {
  184. int i;
  185. for (i = 0; i < DSA_MAX_PORTS; i++) {
  186. struct net_device *dev;
  187. int uninitialized_var(port_status);
  188. int link;
  189. int speed;
  190. int duplex;
  191. int fc;
  192. dev = ds->ports[i];
  193. if (dev == NULL)
  194. continue;
  195. link = 0;
  196. if (dev->flags & IFF_UP) {
  197. port_status = reg_read(ds, REG_PORT(i), 0x00);
  198. if (port_status < 0)
  199. continue;
  200. link = !!(port_status & 0x1000);
  201. }
  202. if (!link) {
  203. if (netif_carrier_ok(dev)) {
  204. netdev_info(dev, "link down\n");
  205. netif_carrier_off(dev);
  206. }
  207. continue;
  208. }
  209. speed = (port_status & 0x0100) ? 100 : 10;
  210. duplex = (port_status & 0x0200) ? 1 : 0;
  211. fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
  212. if (!netif_carrier_ok(dev)) {
  213. netdev_info(dev,
  214. "link up, %d Mb/s, %s duplex, flow control %sabled\n",
  215. speed,
  216. duplex ? "full" : "half",
  217. fc ? "en" : "dis");
  218. netif_carrier_on(dev);
  219. }
  220. }
  221. }
  222. static struct dsa_switch_driver mv88e6060_switch_driver = {
  223. .tag_protocol = DSA_TAG_PROTO_TRAILER,
  224. .probe = mv88e6060_probe,
  225. .setup = mv88e6060_setup,
  226. .set_addr = mv88e6060_set_addr,
  227. .phy_read = mv88e6060_phy_read,
  228. .phy_write = mv88e6060_phy_write,
  229. .poll_link = mv88e6060_poll_link,
  230. };
  231. static int __init mv88e6060_init(void)
  232. {
  233. register_switch_driver(&mv88e6060_switch_driver);
  234. return 0;
  235. }
  236. module_init(mv88e6060_init);
  237. static void __exit mv88e6060_cleanup(void)
  238. {
  239. unregister_switch_driver(&mv88e6060_switch_driver);
  240. }
  241. module_exit(mv88e6060_cleanup);
  242. MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
  243. MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
  244. MODULE_LICENSE("GPL");
  245. MODULE_ALIAS("platform:mv88e6060");