sdhci-of-arasan.c 6.2 KB

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  1. /*
  2. * Arasan Secure Digital Host Controller Interface.
  3. * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (c) 2012 Wind River Systems, Inc.
  5. * Copyright (C) 2013 Pengutronix e.K.
  6. * Copyright (C) 2013 Xilinx Inc.
  7. *
  8. * Based on sdhci-of-esdhc.c
  9. *
  10. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  11. * Copyright (c) 2009 MontaVista Software, Inc.
  12. *
  13. * Authors: Xiaobo Xie <X.Xie@freescale.com>
  14. * Anton Vorontsov <avorontsov@ru.mvista.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or (at
  19. * your option) any later version.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/of_device.h>
  23. #include "sdhci-pltfm.h"
  24. #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
  25. #define CLK_CTRL_TIMEOUT_SHIFT 16
  26. #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
  27. #define CLK_CTRL_TIMEOUT_MIN_EXP 13
  28. /**
  29. * struct sdhci_arasan_data
  30. * @clk_ahb: Pointer to the AHB clock
  31. */
  32. struct sdhci_arasan_data {
  33. struct clk *clk_ahb;
  34. };
  35. static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
  36. {
  37. u32 div;
  38. unsigned long freq;
  39. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  40. div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
  41. div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
  42. freq = clk_get_rate(pltfm_host->clk);
  43. freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
  44. return freq;
  45. }
  46. static struct sdhci_ops sdhci_arasan_ops = {
  47. .set_clock = sdhci_set_clock,
  48. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  49. .get_timeout_clock = sdhci_arasan_get_timeout_clock,
  50. .set_bus_width = sdhci_set_bus_width,
  51. .reset = sdhci_reset,
  52. .set_uhs_signaling = sdhci_set_uhs_signaling,
  53. };
  54. static struct sdhci_pltfm_data sdhci_arasan_pdata = {
  55. .ops = &sdhci_arasan_ops,
  56. .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  57. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  58. SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
  59. };
  60. #ifdef CONFIG_PM_SLEEP
  61. /**
  62. * sdhci_arasan_suspend - Suspend method for the driver
  63. * @dev: Address of the device structure
  64. * Returns 0 on success and error value on error
  65. *
  66. * Put the device in a low power state.
  67. */
  68. static int sdhci_arasan_suspend(struct device *dev)
  69. {
  70. struct platform_device *pdev = to_platform_device(dev);
  71. struct sdhci_host *host = platform_get_drvdata(pdev);
  72. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  73. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  74. int ret;
  75. ret = sdhci_suspend_host(host);
  76. if (ret)
  77. return ret;
  78. clk_disable(pltfm_host->clk);
  79. clk_disable(sdhci_arasan->clk_ahb);
  80. return 0;
  81. }
  82. /**
  83. * sdhci_arasan_resume - Resume method for the driver
  84. * @dev: Address of the device structure
  85. * Returns 0 on success and error value on error
  86. *
  87. * Resume operation after suspend
  88. */
  89. static int sdhci_arasan_resume(struct device *dev)
  90. {
  91. struct platform_device *pdev = to_platform_device(dev);
  92. struct sdhci_host *host = platform_get_drvdata(pdev);
  93. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  94. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  95. int ret;
  96. ret = clk_enable(sdhci_arasan->clk_ahb);
  97. if (ret) {
  98. dev_err(dev, "Cannot enable AHB clock.\n");
  99. return ret;
  100. }
  101. ret = clk_enable(pltfm_host->clk);
  102. if (ret) {
  103. dev_err(dev, "Cannot enable SD clock.\n");
  104. clk_disable(sdhci_arasan->clk_ahb);
  105. return ret;
  106. }
  107. return sdhci_resume_host(host);
  108. }
  109. #endif /* ! CONFIG_PM_SLEEP */
  110. static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
  111. sdhci_arasan_resume);
  112. static int sdhci_arasan_probe(struct platform_device *pdev)
  113. {
  114. int ret;
  115. struct clk *clk_xin;
  116. struct sdhci_host *host;
  117. struct sdhci_pltfm_host *pltfm_host;
  118. struct sdhci_arasan_data *sdhci_arasan;
  119. sdhci_arasan = devm_kzalloc(&pdev->dev, sizeof(*sdhci_arasan),
  120. GFP_KERNEL);
  121. if (!sdhci_arasan)
  122. return -ENOMEM;
  123. sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
  124. if (IS_ERR(sdhci_arasan->clk_ahb)) {
  125. dev_err(&pdev->dev, "clk_ahb clock not found.\n");
  126. return PTR_ERR(sdhci_arasan->clk_ahb);
  127. }
  128. clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
  129. if (IS_ERR(clk_xin)) {
  130. dev_err(&pdev->dev, "clk_xin clock not found.\n");
  131. return PTR_ERR(clk_xin);
  132. }
  133. ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
  134. if (ret) {
  135. dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
  136. return ret;
  137. }
  138. ret = clk_prepare_enable(clk_xin);
  139. if (ret) {
  140. dev_err(&pdev->dev, "Unable to enable SD clock.\n");
  141. goto clk_dis_ahb;
  142. }
  143. host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, 0);
  144. if (IS_ERR(host)) {
  145. ret = PTR_ERR(host);
  146. goto clk_disable_all;
  147. }
  148. if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
  149. host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
  150. host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
  151. }
  152. sdhci_get_of_property(pdev);
  153. pltfm_host = sdhci_priv(host);
  154. pltfm_host->priv = sdhci_arasan;
  155. pltfm_host->clk = clk_xin;
  156. ret = mmc_of_parse(host->mmc);
  157. if (ret) {
  158. dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
  159. goto clk_disable_all;
  160. }
  161. ret = sdhci_add_host(host);
  162. if (ret)
  163. goto err_pltfm_free;
  164. return 0;
  165. err_pltfm_free:
  166. sdhci_pltfm_free(pdev);
  167. clk_disable_all:
  168. clk_disable_unprepare(clk_xin);
  169. clk_dis_ahb:
  170. clk_disable_unprepare(sdhci_arasan->clk_ahb);
  171. return ret;
  172. }
  173. static int sdhci_arasan_remove(struct platform_device *pdev)
  174. {
  175. struct sdhci_host *host = platform_get_drvdata(pdev);
  176. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  177. struct sdhci_arasan_data *sdhci_arasan = pltfm_host->priv;
  178. clk_disable_unprepare(sdhci_arasan->clk_ahb);
  179. return sdhci_pltfm_unregister(pdev);
  180. }
  181. static const struct of_device_id sdhci_arasan_of_match[] = {
  182. { .compatible = "arasan,sdhci-8.9a" },
  183. { .compatible = "arasan,sdhci-5.1" },
  184. { .compatible = "arasan,sdhci-4.9a" },
  185. { }
  186. };
  187. MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
  188. static struct platform_driver sdhci_arasan_driver = {
  189. .driver = {
  190. .name = "sdhci-arasan",
  191. .of_match_table = sdhci_arasan_of_match,
  192. .pm = &sdhci_arasan_dev_pm_ops,
  193. },
  194. .probe = sdhci_arasan_probe,
  195. .remove = sdhci_arasan_remove,
  196. };
  197. module_platform_driver(sdhci_arasan_driver);
  198. MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
  199. MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
  200. MODULE_LICENSE("GPL");