gsc-core.c 30 KB

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  1. /*
  2. * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Samsung EXYNOS5 SoC series G-Scaler driver
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published
  9. * by the Free Software Foundation, either version 2 of the License,
  10. * or (at your option) any later version.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/errno.h>
  16. #include <linux/bug.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/list.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/clk.h>
  25. #include <linux/of.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include "gsc-core.h"
  28. #define GSC_CLOCK_GATE_NAME "gscl"
  29. static const struct gsc_fmt gsc_formats[] = {
  30. {
  31. .name = "RGB565",
  32. .pixelformat = V4L2_PIX_FMT_RGB565X,
  33. .depth = { 16 },
  34. .color = GSC_RGB,
  35. .num_planes = 1,
  36. .num_comp = 1,
  37. }, {
  38. .name = "XRGB-8-8-8-8, 32 bpp",
  39. .pixelformat = V4L2_PIX_FMT_RGB32,
  40. .depth = { 32 },
  41. .color = GSC_RGB,
  42. .num_planes = 1,
  43. .num_comp = 1,
  44. }, {
  45. .name = "YUV 4:2:2 packed, YCbYCr",
  46. .pixelformat = V4L2_PIX_FMT_YUYV,
  47. .depth = { 16 },
  48. .color = GSC_YUV422,
  49. .yorder = GSC_LSB_Y,
  50. .corder = GSC_CBCR,
  51. .num_planes = 1,
  52. .num_comp = 1,
  53. .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
  54. }, {
  55. .name = "YUV 4:2:2 packed, CbYCrY",
  56. .pixelformat = V4L2_PIX_FMT_UYVY,
  57. .depth = { 16 },
  58. .color = GSC_YUV422,
  59. .yorder = GSC_LSB_C,
  60. .corder = GSC_CBCR,
  61. .num_planes = 1,
  62. .num_comp = 1,
  63. .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
  64. }, {
  65. .name = "YUV 4:2:2 packed, CrYCbY",
  66. .pixelformat = V4L2_PIX_FMT_VYUY,
  67. .depth = { 16 },
  68. .color = GSC_YUV422,
  69. .yorder = GSC_LSB_C,
  70. .corder = GSC_CRCB,
  71. .num_planes = 1,
  72. .num_comp = 1,
  73. .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
  74. }, {
  75. .name = "YUV 4:2:2 packed, YCrYCb",
  76. .pixelformat = V4L2_PIX_FMT_YVYU,
  77. .depth = { 16 },
  78. .color = GSC_YUV422,
  79. .yorder = GSC_LSB_Y,
  80. .corder = GSC_CRCB,
  81. .num_planes = 1,
  82. .num_comp = 1,
  83. .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
  84. }, {
  85. .name = "YUV 4:4:4 planar, YCbYCr",
  86. .pixelformat = V4L2_PIX_FMT_YUV32,
  87. .depth = { 32 },
  88. .color = GSC_YUV444,
  89. .yorder = GSC_LSB_Y,
  90. .corder = GSC_CBCR,
  91. .num_planes = 1,
  92. .num_comp = 1,
  93. }, {
  94. .name = "YUV 4:2:2 planar, Y/Cb/Cr",
  95. .pixelformat = V4L2_PIX_FMT_YUV422P,
  96. .depth = { 16 },
  97. .color = GSC_YUV422,
  98. .yorder = GSC_LSB_Y,
  99. .corder = GSC_CBCR,
  100. .num_planes = 1,
  101. .num_comp = 3,
  102. }, {
  103. .name = "YUV 4:2:2 planar, Y/CbCr",
  104. .pixelformat = V4L2_PIX_FMT_NV16,
  105. .depth = { 16 },
  106. .color = GSC_YUV422,
  107. .yorder = GSC_LSB_Y,
  108. .corder = GSC_CBCR,
  109. .num_planes = 1,
  110. .num_comp = 2,
  111. }, {
  112. .name = "YUV 4:2:2 planar, Y/CrCb",
  113. .pixelformat = V4L2_PIX_FMT_NV61,
  114. .depth = { 16 },
  115. .color = GSC_YUV422,
  116. .yorder = GSC_LSB_Y,
  117. .corder = GSC_CRCB,
  118. .num_planes = 1,
  119. .num_comp = 2,
  120. }, {
  121. .name = "YUV 4:2:0 planar, YCbCr",
  122. .pixelformat = V4L2_PIX_FMT_YUV420,
  123. .depth = { 12 },
  124. .color = GSC_YUV420,
  125. .yorder = GSC_LSB_Y,
  126. .corder = GSC_CBCR,
  127. .num_planes = 1,
  128. .num_comp = 3,
  129. }, {
  130. .name = "YUV 4:2:0 planar, YCrCb",
  131. .pixelformat = V4L2_PIX_FMT_YVU420,
  132. .depth = { 12 },
  133. .color = GSC_YUV420,
  134. .yorder = GSC_LSB_Y,
  135. .corder = GSC_CRCB,
  136. .num_planes = 1,
  137. .num_comp = 3,
  138. }, {
  139. .name = "YUV 4:2:0 planar, Y/CbCr",
  140. .pixelformat = V4L2_PIX_FMT_NV12,
  141. .depth = { 12 },
  142. .color = GSC_YUV420,
  143. .yorder = GSC_LSB_Y,
  144. .corder = GSC_CBCR,
  145. .num_planes = 1,
  146. .num_comp = 2,
  147. }, {
  148. .name = "YUV 4:2:0 planar, Y/CrCb",
  149. .pixelformat = V4L2_PIX_FMT_NV21,
  150. .depth = { 12 },
  151. .color = GSC_YUV420,
  152. .yorder = GSC_LSB_Y,
  153. .corder = GSC_CRCB,
  154. .num_planes = 1,
  155. .num_comp = 2,
  156. }, {
  157. .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
  158. .pixelformat = V4L2_PIX_FMT_NV12M,
  159. .depth = { 8, 4 },
  160. .color = GSC_YUV420,
  161. .yorder = GSC_LSB_Y,
  162. .corder = GSC_CBCR,
  163. .num_planes = 2,
  164. .num_comp = 2,
  165. }, {
  166. .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
  167. .pixelformat = V4L2_PIX_FMT_YUV420M,
  168. .depth = { 8, 2, 2 },
  169. .color = GSC_YUV420,
  170. .yorder = GSC_LSB_Y,
  171. .corder = GSC_CBCR,
  172. .num_planes = 3,
  173. .num_comp = 3,
  174. }, {
  175. .name = "YUV 4:2:0 non-contig. 3p, Y/Cr/Cb",
  176. .pixelformat = V4L2_PIX_FMT_YVU420M,
  177. .depth = { 8, 2, 2 },
  178. .color = GSC_YUV420,
  179. .yorder = GSC_LSB_Y,
  180. .corder = GSC_CRCB,
  181. .num_planes = 3,
  182. .num_comp = 3,
  183. }, {
  184. .name = "YUV 4:2:0 n.c. 2p, Y/CbCr tiled",
  185. .pixelformat = V4L2_PIX_FMT_NV12MT_16X16,
  186. .depth = { 8, 4 },
  187. .color = GSC_YUV420,
  188. .yorder = GSC_LSB_Y,
  189. .corder = GSC_CBCR,
  190. .num_planes = 2,
  191. .num_comp = 2,
  192. }
  193. };
  194. const struct gsc_fmt *get_format(int index)
  195. {
  196. if (index >= ARRAY_SIZE(gsc_formats))
  197. return NULL;
  198. return (struct gsc_fmt *)&gsc_formats[index];
  199. }
  200. const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index)
  201. {
  202. const struct gsc_fmt *fmt, *def_fmt = NULL;
  203. unsigned int i;
  204. if (index >= ARRAY_SIZE(gsc_formats))
  205. return NULL;
  206. for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) {
  207. fmt = get_format(i);
  208. if (pixelformat && fmt->pixelformat == *pixelformat)
  209. return fmt;
  210. if (mbus_code && fmt->mbus_code == *mbus_code)
  211. return fmt;
  212. if (index == i)
  213. def_fmt = fmt;
  214. }
  215. return def_fmt;
  216. }
  217. void gsc_set_frame_size(struct gsc_frame *frame, int width, int height)
  218. {
  219. frame->f_width = width;
  220. frame->f_height = height;
  221. frame->crop.width = width;
  222. frame->crop.height = height;
  223. frame->crop.left = 0;
  224. frame->crop.top = 0;
  225. }
  226. int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
  227. u32 *ratio)
  228. {
  229. if ((dst > src) || (dst >= src / var->poly_sc_down_max)) {
  230. *ratio = 1;
  231. return 0;
  232. }
  233. if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) {
  234. pr_err("Exceeded maximum downscaling ratio (1/16))");
  235. return -EINVAL;
  236. }
  237. *ratio = (dst > (src / 8)) ? 2 : 4;
  238. return 0;
  239. }
  240. void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh)
  241. {
  242. if (hratio == 4 && vratio == 4)
  243. *sh = 4;
  244. else if ((hratio == 4 && vratio == 2) ||
  245. (hratio == 2 && vratio == 4))
  246. *sh = 3;
  247. else if ((hratio == 4 && vratio == 1) ||
  248. (hratio == 1 && vratio == 4) ||
  249. (hratio == 2 && vratio == 2))
  250. *sh = 2;
  251. else if (hratio == 1 && vratio == 1)
  252. *sh = 0;
  253. else
  254. *sh = 1;
  255. }
  256. void gsc_check_src_scale_info(struct gsc_variant *var,
  257. struct gsc_frame *s_frame, u32 *wratio,
  258. u32 tx, u32 ty, u32 *hratio)
  259. {
  260. int remainder = 0, walign, halign;
  261. if (is_yuv420(s_frame->fmt->color)) {
  262. walign = GSC_SC_ALIGN_4;
  263. halign = GSC_SC_ALIGN_4;
  264. } else if (is_yuv422(s_frame->fmt->color)) {
  265. walign = GSC_SC_ALIGN_4;
  266. halign = GSC_SC_ALIGN_2;
  267. } else {
  268. walign = GSC_SC_ALIGN_2;
  269. halign = GSC_SC_ALIGN_2;
  270. }
  271. remainder = s_frame->crop.width % (*wratio * walign);
  272. if (remainder) {
  273. s_frame->crop.width -= remainder;
  274. gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio);
  275. pr_info("cropped src width size is recalculated from %d to %d",
  276. s_frame->crop.width + remainder, s_frame->crop.width);
  277. }
  278. remainder = s_frame->crop.height % (*hratio * halign);
  279. if (remainder) {
  280. s_frame->crop.height -= remainder;
  281. gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio);
  282. pr_info("cropped src height size is recalculated from %d to %d",
  283. s_frame->crop.height + remainder, s_frame->crop.height);
  284. }
  285. }
  286. int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f)
  287. {
  288. const struct gsc_fmt *fmt;
  289. fmt = find_fmt(NULL, NULL, f->index);
  290. if (!fmt)
  291. return -EINVAL;
  292. strlcpy(f->description, fmt->name, sizeof(f->description));
  293. f->pixelformat = fmt->pixelformat;
  294. return 0;
  295. }
  296. static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32 *ret_addr)
  297. {
  298. if (frm->addr.y == addr) {
  299. *index = 0;
  300. *ret_addr = frm->addr.y;
  301. } else if (frm->addr.cb == addr) {
  302. *index = 1;
  303. *ret_addr = frm->addr.cb;
  304. } else if (frm->addr.cr == addr) {
  305. *index = 2;
  306. *ret_addr = frm->addr.cr;
  307. } else {
  308. pr_err("Plane address is wrong");
  309. return -EINVAL;
  310. }
  311. return 0;
  312. }
  313. void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
  314. {
  315. u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len;
  316. f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0;
  317. f_chk_addr = frm->addr.y;
  318. f_chk_len = frm->payload[0];
  319. if (frm->fmt->num_planes == 2) {
  320. s_chk_addr = frm->addr.cb;
  321. s_chk_len = frm->payload[1];
  322. } else if (frm->fmt->num_planes == 3) {
  323. u32 low_addr, low_plane, mid_addr, mid_plane;
  324. u32 high_addr, high_plane;
  325. u32 t_min, t_max;
  326. t_min = min3(frm->addr.y, frm->addr.cb, frm->addr.cr);
  327. if (get_plane_info(frm, t_min, &low_plane, &low_addr))
  328. return;
  329. t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr);
  330. if (get_plane_info(frm, t_max, &high_plane, &high_addr))
  331. return;
  332. mid_plane = 3 - (low_plane + high_plane);
  333. if (mid_plane == 0)
  334. mid_addr = frm->addr.y;
  335. else if (mid_plane == 1)
  336. mid_addr = frm->addr.cb;
  337. else if (mid_plane == 2)
  338. mid_addr = frm->addr.cr;
  339. else
  340. return;
  341. f_chk_addr = low_addr;
  342. if (mid_addr + frm->payload[mid_plane] - low_addr >
  343. high_addr + frm->payload[high_plane] - mid_addr) {
  344. f_chk_len = frm->payload[low_plane];
  345. s_chk_addr = mid_addr;
  346. s_chk_len = high_addr +
  347. frm->payload[high_plane] - mid_addr;
  348. } else {
  349. f_chk_len = mid_addr +
  350. frm->payload[mid_plane] - low_addr;
  351. s_chk_addr = high_addr;
  352. s_chk_len = frm->payload[high_plane];
  353. }
  354. }
  355. pr_debug("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n",
  356. f_chk_addr, f_chk_len, s_chk_addr, s_chk_len);
  357. }
  358. int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
  359. {
  360. struct gsc_dev *gsc = ctx->gsc_dev;
  361. struct gsc_variant *variant = gsc->variant;
  362. struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
  363. const struct gsc_fmt *fmt;
  364. u32 max_w, max_h, mod_x, mod_y;
  365. u32 min_w, min_h, tmp_w, tmp_h;
  366. int i;
  367. pr_debug("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
  368. fmt = find_fmt(&pix_mp->pixelformat, NULL, 0);
  369. if (!fmt) {
  370. pr_err("pixelformat format (0x%X) invalid\n",
  371. pix_mp->pixelformat);
  372. return -EINVAL;
  373. }
  374. if (pix_mp->field == V4L2_FIELD_ANY)
  375. pix_mp->field = V4L2_FIELD_NONE;
  376. else if (pix_mp->field != V4L2_FIELD_NONE) {
  377. pr_err("Not supported field order(%d)\n", pix_mp->field);
  378. return -EINVAL;
  379. }
  380. max_w = variant->pix_max->target_rot_dis_w;
  381. max_h = variant->pix_max->target_rot_dis_h;
  382. mod_x = ffs(variant->pix_align->org_w) - 1;
  383. if (is_yuv420(fmt->color))
  384. mod_y = ffs(variant->pix_align->org_h) - 1;
  385. else
  386. mod_y = ffs(variant->pix_align->org_h) - 2;
  387. if (V4L2_TYPE_IS_OUTPUT(f->type)) {
  388. min_w = variant->pix_min->org_w;
  389. min_h = variant->pix_min->org_h;
  390. } else {
  391. min_w = variant->pix_min->target_rot_dis_w;
  392. min_h = variant->pix_min->target_rot_dis_h;
  393. }
  394. pr_debug("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
  395. mod_x, mod_y, max_w, max_h);
  396. /* To check if image size is modified to adjust parameter against
  397. hardware abilities */
  398. tmp_w = pix_mp->width;
  399. tmp_h = pix_mp->height;
  400. v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
  401. &pix_mp->height, min_h, max_h, mod_y, 0);
  402. if (tmp_w != pix_mp->width || tmp_h != pix_mp->height)
  403. pr_info("Image size has been modified from %dx%d to %dx%d",
  404. tmp_w, tmp_h, pix_mp->width, pix_mp->height);
  405. pix_mp->num_planes = fmt->num_planes;
  406. if (pix_mp->width >= 1280) /* HD */
  407. pix_mp->colorspace = V4L2_COLORSPACE_REC709;
  408. else /* SD */
  409. pix_mp->colorspace = V4L2_COLORSPACE_SMPTE170M;
  410. for (i = 0; i < pix_mp->num_planes; ++i) {
  411. int bpl = (pix_mp->width * fmt->depth[i]) >> 3;
  412. pix_mp->plane_fmt[i].bytesperline = bpl;
  413. pix_mp->plane_fmt[i].sizeimage = bpl * pix_mp->height;
  414. pr_debug("[%d]: bpl: %d, sizeimage: %d",
  415. i, bpl, pix_mp->plane_fmt[i].sizeimage);
  416. }
  417. return 0;
  418. }
  419. int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
  420. {
  421. struct gsc_frame *frame;
  422. struct v4l2_pix_format_mplane *pix_mp;
  423. int i;
  424. frame = ctx_get_frame(ctx, f->type);
  425. if (IS_ERR(frame))
  426. return PTR_ERR(frame);
  427. pix_mp = &f->fmt.pix_mp;
  428. pix_mp->width = frame->f_width;
  429. pix_mp->height = frame->f_height;
  430. pix_mp->field = V4L2_FIELD_NONE;
  431. pix_mp->pixelformat = frame->fmt->pixelformat;
  432. pix_mp->colorspace = V4L2_COLORSPACE_REC709;
  433. pix_mp->num_planes = frame->fmt->num_planes;
  434. for (i = 0; i < pix_mp->num_planes; ++i) {
  435. pix_mp->plane_fmt[i].bytesperline = (frame->f_width *
  436. frame->fmt->depth[i]) / 8;
  437. pix_mp->plane_fmt[i].sizeimage =
  438. pix_mp->plane_fmt[i].bytesperline * frame->f_height;
  439. }
  440. return 0;
  441. }
  442. void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h)
  443. {
  444. if (tmp_w != *w || tmp_h != *h) {
  445. pr_info("Cropped size has been modified from %dx%d to %dx%d",
  446. *w, *h, tmp_w, tmp_h);
  447. *w = tmp_w;
  448. *h = tmp_h;
  449. }
  450. }
  451. int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
  452. {
  453. struct gsc_frame *frame;
  454. frame = ctx_get_frame(ctx, cr->type);
  455. if (IS_ERR(frame))
  456. return PTR_ERR(frame);
  457. cr->c = frame->crop;
  458. return 0;
  459. }
  460. int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
  461. {
  462. struct gsc_frame *f;
  463. struct gsc_dev *gsc = ctx->gsc_dev;
  464. struct gsc_variant *variant = gsc->variant;
  465. u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h;
  466. u32 min_w, min_h, max_w, max_h;
  467. if (cr->c.top < 0 || cr->c.left < 0) {
  468. pr_err("doesn't support negative values for top & left\n");
  469. return -EINVAL;
  470. }
  471. pr_debug("user put w: %d, h: %d", cr->c.width, cr->c.height);
  472. if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  473. f = &ctx->d_frame;
  474. else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
  475. f = &ctx->s_frame;
  476. else
  477. return -EINVAL;
  478. max_w = f->f_width;
  479. max_h = f->f_height;
  480. tmp_w = cr->c.width;
  481. tmp_h = cr->c.height;
  482. if (V4L2_TYPE_IS_OUTPUT(cr->type)) {
  483. if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) ||
  484. is_rgb(f->fmt->color))
  485. min_w = 32;
  486. else
  487. min_w = 64;
  488. if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 3) ||
  489. is_yuv420(f->fmt->color))
  490. min_h = 32;
  491. else
  492. min_h = 16;
  493. } else {
  494. if (is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color))
  495. mod_x = ffs(variant->pix_align->target_w) - 1;
  496. if (is_yuv420(f->fmt->color))
  497. mod_y = ffs(variant->pix_align->target_h) - 1;
  498. if (ctx->gsc_ctrls.rotate->val == 90 ||
  499. ctx->gsc_ctrls.rotate->val == 270) {
  500. max_w = f->f_height;
  501. max_h = f->f_width;
  502. min_w = variant->pix_min->target_rot_en_w;
  503. min_h = variant->pix_min->target_rot_en_h;
  504. tmp_w = cr->c.height;
  505. tmp_h = cr->c.width;
  506. } else {
  507. min_w = variant->pix_min->target_rot_dis_w;
  508. min_h = variant->pix_min->target_rot_dis_h;
  509. }
  510. }
  511. pr_debug("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d",
  512. mod_x, mod_y, min_w, min_h);
  513. pr_debug("tmp_w : %d, tmp_h : %d", tmp_w, tmp_h);
  514. v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x,
  515. &tmp_h, min_h, max_h, mod_y, 0);
  516. if (!V4L2_TYPE_IS_OUTPUT(cr->type) &&
  517. (ctx->gsc_ctrls.rotate->val == 90 ||
  518. ctx->gsc_ctrls.rotate->val == 270))
  519. gsc_check_crop_change(tmp_h, tmp_w,
  520. &cr->c.width, &cr->c.height);
  521. else
  522. gsc_check_crop_change(tmp_w, tmp_h,
  523. &cr->c.width, &cr->c.height);
  524. /* adjust left/top if cropping rectangle is out of bounds */
  525. /* Need to add code to algin left value with 2's multiple */
  526. if (cr->c.left + tmp_w > max_w)
  527. cr->c.left = max_w - tmp_w;
  528. if (cr->c.top + tmp_h > max_h)
  529. cr->c.top = max_h - tmp_h;
  530. if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) &&
  531. cr->c.left & 1)
  532. cr->c.left -= 1;
  533. pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
  534. cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h);
  535. return 0;
  536. }
  537. int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
  538. int dh, int rot, int out_path)
  539. {
  540. int tmp_w, tmp_h, sc_down_max;
  541. if (out_path == GSC_DMA)
  542. sc_down_max = var->sc_down_max;
  543. else
  544. sc_down_max = var->local_sc_down;
  545. if (rot == 90 || rot == 270) {
  546. tmp_w = dh;
  547. tmp_h = dw;
  548. } else {
  549. tmp_w = dw;
  550. tmp_h = dh;
  551. }
  552. if ((sw / tmp_w) > sc_down_max ||
  553. (sh / tmp_h) > sc_down_max ||
  554. (tmp_w / sw) > var->sc_up_max ||
  555. (tmp_h / sh) > var->sc_up_max)
  556. return -EINVAL;
  557. return 0;
  558. }
  559. int gsc_set_scaler_info(struct gsc_ctx *ctx)
  560. {
  561. struct gsc_scaler *sc = &ctx->scaler;
  562. struct gsc_frame *s_frame = &ctx->s_frame;
  563. struct gsc_frame *d_frame = &ctx->d_frame;
  564. struct gsc_variant *variant = ctx->gsc_dev->variant;
  565. struct device *dev = &ctx->gsc_dev->pdev->dev;
  566. int tx, ty;
  567. int ret;
  568. ret = gsc_check_scaler_ratio(variant, s_frame->crop.width,
  569. s_frame->crop.height, d_frame->crop.width, d_frame->crop.height,
  570. ctx->gsc_ctrls.rotate->val, ctx->out_path);
  571. if (ret) {
  572. pr_err("out of scaler range");
  573. return ret;
  574. }
  575. if (ctx->gsc_ctrls.rotate->val == 90 ||
  576. ctx->gsc_ctrls.rotate->val == 270) {
  577. ty = d_frame->crop.width;
  578. tx = d_frame->crop.height;
  579. } else {
  580. tx = d_frame->crop.width;
  581. ty = d_frame->crop.height;
  582. }
  583. if (tx <= 0 || ty <= 0) {
  584. dev_err(dev, "Invalid target size: %dx%d", tx, ty);
  585. return -EINVAL;
  586. }
  587. ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width,
  588. tx, &sc->pre_hratio);
  589. if (ret) {
  590. pr_err("Horizontal scale ratio is out of range");
  591. return ret;
  592. }
  593. ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height,
  594. ty, &sc->pre_vratio);
  595. if (ret) {
  596. pr_err("Vertical scale ratio is out of range");
  597. return ret;
  598. }
  599. gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio,
  600. tx, ty, &sc->pre_vratio);
  601. gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
  602. &sc->pre_shfactor);
  603. sc->main_hratio = (s_frame->crop.width << 16) / tx;
  604. sc->main_vratio = (s_frame->crop.height << 16) / ty;
  605. pr_debug("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d",
  606. s_frame->crop.width, s_frame->crop.height, tx, ty);
  607. pr_debug("scaler ratio info : pre_shfactor : %d, pre_h : %d",
  608. sc->pre_shfactor, sc->pre_hratio);
  609. pr_debug("pre_v :%d, main_h : %d, main_v : %d",
  610. sc->pre_vratio, sc->main_hratio, sc->main_vratio);
  611. return 0;
  612. }
  613. static int __gsc_s_ctrl(struct gsc_ctx *ctx, struct v4l2_ctrl *ctrl)
  614. {
  615. struct gsc_dev *gsc = ctx->gsc_dev;
  616. struct gsc_variant *variant = gsc->variant;
  617. unsigned int flags = GSC_DST_FMT | GSC_SRC_FMT;
  618. int ret = 0;
  619. if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
  620. return 0;
  621. switch (ctrl->id) {
  622. case V4L2_CID_HFLIP:
  623. ctx->hflip = ctrl->val;
  624. break;
  625. case V4L2_CID_VFLIP:
  626. ctx->vflip = ctrl->val;
  627. break;
  628. case V4L2_CID_ROTATE:
  629. if ((ctx->state & flags) == flags) {
  630. ret = gsc_check_scaler_ratio(variant,
  631. ctx->s_frame.crop.width,
  632. ctx->s_frame.crop.height,
  633. ctx->d_frame.crop.width,
  634. ctx->d_frame.crop.height,
  635. ctx->gsc_ctrls.rotate->val,
  636. ctx->out_path);
  637. if (ret)
  638. return -EINVAL;
  639. }
  640. ctx->rotation = ctrl->val;
  641. break;
  642. case V4L2_CID_ALPHA_COMPONENT:
  643. ctx->d_frame.alpha = ctrl->val;
  644. break;
  645. }
  646. ctx->state |= GSC_PARAMS;
  647. return 0;
  648. }
  649. static int gsc_s_ctrl(struct v4l2_ctrl *ctrl)
  650. {
  651. struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
  652. unsigned long flags;
  653. int ret;
  654. spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
  655. ret = __gsc_s_ctrl(ctx, ctrl);
  656. spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
  657. return ret;
  658. }
  659. static const struct v4l2_ctrl_ops gsc_ctrl_ops = {
  660. .s_ctrl = gsc_s_ctrl,
  661. };
  662. int gsc_ctrls_create(struct gsc_ctx *ctx)
  663. {
  664. if (ctx->ctrls_rdy) {
  665. pr_err("Control handler of this context was created already");
  666. return 0;
  667. }
  668. v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM);
  669. ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  670. &gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
  671. ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  672. &gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
  673. ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  674. &gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
  675. ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  676. &gsc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
  677. ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
  678. if (ctx->ctrl_handler.error) {
  679. int err = ctx->ctrl_handler.error;
  680. v4l2_ctrl_handler_free(&ctx->ctrl_handler);
  681. pr_err("Failed to create G-Scaler control handlers");
  682. return err;
  683. }
  684. return 0;
  685. }
  686. void gsc_ctrls_delete(struct gsc_ctx *ctx)
  687. {
  688. if (ctx->ctrls_rdy) {
  689. v4l2_ctrl_handler_free(&ctx->ctrl_handler);
  690. ctx->ctrls_rdy = false;
  691. }
  692. }
  693. /* The color format (num_comp, num_planes) must be already configured. */
  694. int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
  695. struct gsc_frame *frame, struct gsc_addr *addr)
  696. {
  697. int ret = 0;
  698. u32 pix_size;
  699. if ((vb == NULL) || (frame == NULL))
  700. return -EINVAL;
  701. pix_size = frame->f_width * frame->f_height;
  702. pr_debug("num_planes= %d, num_comp= %d, pix_size= %d",
  703. frame->fmt->num_planes, frame->fmt->num_comp, pix_size);
  704. addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
  705. if (frame->fmt->num_planes == 1) {
  706. switch (frame->fmt->num_comp) {
  707. case 1:
  708. addr->cb = 0;
  709. addr->cr = 0;
  710. break;
  711. case 2:
  712. /* decompose Y into Y/Cb */
  713. addr->cb = (dma_addr_t)(addr->y + pix_size);
  714. addr->cr = 0;
  715. break;
  716. case 3:
  717. /* decompose Y into Y/Cb/Cr */
  718. addr->cb = (dma_addr_t)(addr->y + pix_size);
  719. if (GSC_YUV420 == frame->fmt->color)
  720. addr->cr = (dma_addr_t)(addr->cb
  721. + (pix_size >> 2));
  722. else /* 422 */
  723. addr->cr = (dma_addr_t)(addr->cb
  724. + (pix_size >> 1));
  725. break;
  726. default:
  727. pr_err("Invalid the number of color planes");
  728. return -EINVAL;
  729. }
  730. } else {
  731. if (frame->fmt->num_planes >= 2)
  732. addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
  733. if (frame->fmt->num_planes == 3)
  734. addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
  735. }
  736. if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) ||
  737. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) ||
  738. (frame->fmt->pixelformat == V4L2_PIX_FMT_NV61) ||
  739. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) ||
  740. (frame->fmt->pixelformat == V4L2_PIX_FMT_NV21) ||
  741. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))
  742. swap(addr->cb, addr->cr);
  743. pr_debug("ADDR: y= %pad cb= %pad cr= %pad ret= %d",
  744. &addr->y, &addr->cb, &addr->cr, ret);
  745. return ret;
  746. }
  747. static irqreturn_t gsc_irq_handler(int irq, void *priv)
  748. {
  749. struct gsc_dev *gsc = priv;
  750. struct gsc_ctx *ctx;
  751. int gsc_irq;
  752. gsc_irq = gsc_hw_get_irq_status(gsc);
  753. gsc_hw_clear_irq(gsc, gsc_irq);
  754. if (gsc_irq == GSC_IRQ_OVERRUN) {
  755. pr_err("Local path input over-run interrupt has occurred!\n");
  756. return IRQ_HANDLED;
  757. }
  758. spin_lock(&gsc->slock);
  759. if (test_and_clear_bit(ST_M2M_PEND, &gsc->state)) {
  760. gsc_hw_enable_control(gsc, false);
  761. if (test_and_clear_bit(ST_M2M_SUSPENDING, &gsc->state)) {
  762. set_bit(ST_M2M_SUSPENDED, &gsc->state);
  763. wake_up(&gsc->irq_queue);
  764. goto isr_unlock;
  765. }
  766. ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
  767. if (!ctx || !ctx->m2m_ctx)
  768. goto isr_unlock;
  769. spin_unlock(&gsc->slock);
  770. gsc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
  771. /* wake_up job_abort, stop_streaming */
  772. if (ctx->state & GSC_CTX_STOP_REQ) {
  773. ctx->state &= ~GSC_CTX_STOP_REQ;
  774. wake_up(&gsc->irq_queue);
  775. }
  776. return IRQ_HANDLED;
  777. }
  778. isr_unlock:
  779. spin_unlock(&gsc->slock);
  780. return IRQ_HANDLED;
  781. }
  782. static struct gsc_pix_max gsc_v_100_max = {
  783. .org_scaler_bypass_w = 8192,
  784. .org_scaler_bypass_h = 8192,
  785. .org_scaler_input_w = 4800,
  786. .org_scaler_input_h = 3344,
  787. .real_rot_dis_w = 4800,
  788. .real_rot_dis_h = 3344,
  789. .real_rot_en_w = 2047,
  790. .real_rot_en_h = 2047,
  791. .target_rot_dis_w = 4800,
  792. .target_rot_dis_h = 3344,
  793. .target_rot_en_w = 2016,
  794. .target_rot_en_h = 2016,
  795. };
  796. static struct gsc_pix_min gsc_v_100_min = {
  797. .org_w = 64,
  798. .org_h = 32,
  799. .real_w = 64,
  800. .real_h = 32,
  801. .target_rot_dis_w = 64,
  802. .target_rot_dis_h = 32,
  803. .target_rot_en_w = 32,
  804. .target_rot_en_h = 16,
  805. };
  806. static struct gsc_pix_align gsc_v_100_align = {
  807. .org_h = 16,
  808. .org_w = 16, /* yuv420 : 16, others : 8 */
  809. .offset_h = 2, /* yuv420/422 : 2, others : 1 */
  810. .real_w = 16, /* yuv420/422 : 4~16, others : 2~8 */
  811. .real_h = 16, /* yuv420 : 4~16, others : 1 */
  812. .target_w = 2, /* yuv420/422 : 2, others : 1 */
  813. .target_h = 2, /* yuv420 : 2, others : 1 */
  814. };
  815. static struct gsc_variant gsc_v_100_variant = {
  816. .pix_max = &gsc_v_100_max,
  817. .pix_min = &gsc_v_100_min,
  818. .pix_align = &gsc_v_100_align,
  819. .in_buf_cnt = 32,
  820. .out_buf_cnt = 32,
  821. .sc_up_max = 8,
  822. .sc_down_max = 16,
  823. .poly_sc_down_max = 4,
  824. .pre_sc_down_max = 4,
  825. .local_sc_down = 2,
  826. };
  827. static struct gsc_driverdata gsc_v_100_drvdata = {
  828. .variant = {
  829. [0] = &gsc_v_100_variant,
  830. [1] = &gsc_v_100_variant,
  831. [2] = &gsc_v_100_variant,
  832. [3] = &gsc_v_100_variant,
  833. },
  834. .num_entities = 4,
  835. .lclk_frequency = 266000000UL,
  836. };
  837. static const struct platform_device_id gsc_driver_ids[] = {
  838. {
  839. .name = "exynos-gsc",
  840. .driver_data = (unsigned long)&gsc_v_100_drvdata,
  841. },
  842. {},
  843. };
  844. MODULE_DEVICE_TABLE(platform, gsc_driver_ids);
  845. static const struct of_device_id exynos_gsc_match[] = {
  846. {
  847. .compatible = "samsung,exynos5-gsc",
  848. .data = &gsc_v_100_drvdata,
  849. },
  850. {},
  851. };
  852. MODULE_DEVICE_TABLE(of, exynos_gsc_match);
  853. static void *gsc_get_drv_data(struct platform_device *pdev)
  854. {
  855. struct gsc_driverdata *driver_data = NULL;
  856. if (pdev->dev.of_node) {
  857. const struct of_device_id *match;
  858. match = of_match_node(exynos_gsc_match,
  859. pdev->dev.of_node);
  860. if (match)
  861. driver_data = (struct gsc_driverdata *)match->data;
  862. } else {
  863. driver_data = (struct gsc_driverdata *)
  864. platform_get_device_id(pdev)->driver_data;
  865. }
  866. return driver_data;
  867. }
  868. static void gsc_clk_put(struct gsc_dev *gsc)
  869. {
  870. if (!IS_ERR(gsc->clock))
  871. clk_unprepare(gsc->clock);
  872. }
  873. static int gsc_clk_get(struct gsc_dev *gsc)
  874. {
  875. int ret;
  876. dev_dbg(&gsc->pdev->dev, "gsc_clk_get Called\n");
  877. gsc->clock = devm_clk_get(&gsc->pdev->dev, GSC_CLOCK_GATE_NAME);
  878. if (IS_ERR(gsc->clock)) {
  879. dev_err(&gsc->pdev->dev, "failed to get clock~~~: %s\n",
  880. GSC_CLOCK_GATE_NAME);
  881. return PTR_ERR(gsc->clock);
  882. }
  883. ret = clk_prepare(gsc->clock);
  884. if (ret < 0) {
  885. dev_err(&gsc->pdev->dev, "clock prepare failed for clock: %s\n",
  886. GSC_CLOCK_GATE_NAME);
  887. gsc->clock = ERR_PTR(-EINVAL);
  888. return ret;
  889. }
  890. return 0;
  891. }
  892. static int gsc_m2m_suspend(struct gsc_dev *gsc)
  893. {
  894. unsigned long flags;
  895. int timeout;
  896. spin_lock_irqsave(&gsc->slock, flags);
  897. if (!gsc_m2m_pending(gsc)) {
  898. spin_unlock_irqrestore(&gsc->slock, flags);
  899. return 0;
  900. }
  901. clear_bit(ST_M2M_SUSPENDED, &gsc->state);
  902. set_bit(ST_M2M_SUSPENDING, &gsc->state);
  903. spin_unlock_irqrestore(&gsc->slock, flags);
  904. timeout = wait_event_timeout(gsc->irq_queue,
  905. test_bit(ST_M2M_SUSPENDED, &gsc->state),
  906. GSC_SHUTDOWN_TIMEOUT);
  907. clear_bit(ST_M2M_SUSPENDING, &gsc->state);
  908. return timeout == 0 ? -EAGAIN : 0;
  909. }
  910. static int gsc_m2m_resume(struct gsc_dev *gsc)
  911. {
  912. struct gsc_ctx *ctx;
  913. unsigned long flags;
  914. spin_lock_irqsave(&gsc->slock, flags);
  915. /* Clear for full H/W setup in first run after resume */
  916. ctx = gsc->m2m.ctx;
  917. gsc->m2m.ctx = NULL;
  918. spin_unlock_irqrestore(&gsc->slock, flags);
  919. if (test_and_clear_bit(ST_M2M_SUSPENDED, &gsc->state))
  920. gsc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
  921. return 0;
  922. }
  923. static int gsc_probe(struct platform_device *pdev)
  924. {
  925. struct gsc_dev *gsc;
  926. struct resource *res;
  927. struct gsc_driverdata *drv_data = gsc_get_drv_data(pdev);
  928. struct device *dev = &pdev->dev;
  929. int ret = 0;
  930. gsc = devm_kzalloc(dev, sizeof(struct gsc_dev), GFP_KERNEL);
  931. if (!gsc)
  932. return -ENOMEM;
  933. if (dev->of_node)
  934. gsc->id = of_alias_get_id(pdev->dev.of_node, "gsc");
  935. else
  936. gsc->id = pdev->id;
  937. if (gsc->id >= drv_data->num_entities) {
  938. dev_err(dev, "Invalid platform device id: %d\n", gsc->id);
  939. return -EINVAL;
  940. }
  941. gsc->variant = drv_data->variant[gsc->id];
  942. gsc->pdev = pdev;
  943. gsc->pdata = dev->platform_data;
  944. init_waitqueue_head(&gsc->irq_queue);
  945. spin_lock_init(&gsc->slock);
  946. mutex_init(&gsc->lock);
  947. gsc->clock = ERR_PTR(-EINVAL);
  948. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  949. gsc->regs = devm_ioremap_resource(dev, res);
  950. if (IS_ERR(gsc->regs))
  951. return PTR_ERR(gsc->regs);
  952. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  953. if (!res) {
  954. dev_err(dev, "failed to get IRQ resource\n");
  955. return -ENXIO;
  956. }
  957. ret = gsc_clk_get(gsc);
  958. if (ret)
  959. return ret;
  960. ret = devm_request_irq(dev, res->start, gsc_irq_handler,
  961. 0, pdev->name, gsc);
  962. if (ret) {
  963. dev_err(dev, "failed to install irq (%d)\n", ret);
  964. goto err_clk;
  965. }
  966. ret = v4l2_device_register(dev, &gsc->v4l2_dev);
  967. if (ret)
  968. goto err_clk;
  969. ret = gsc_register_m2m_device(gsc);
  970. if (ret)
  971. goto err_v4l2;
  972. platform_set_drvdata(pdev, gsc);
  973. pm_runtime_enable(dev);
  974. ret = pm_runtime_get_sync(&pdev->dev);
  975. if (ret < 0)
  976. goto err_m2m;
  977. /* Initialize continious memory allocator */
  978. gsc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  979. if (IS_ERR(gsc->alloc_ctx)) {
  980. ret = PTR_ERR(gsc->alloc_ctx);
  981. goto err_pm;
  982. }
  983. dev_dbg(dev, "gsc-%d registered successfully\n", gsc->id);
  984. pm_runtime_put(dev);
  985. return 0;
  986. err_pm:
  987. pm_runtime_put(dev);
  988. err_m2m:
  989. gsc_unregister_m2m_device(gsc);
  990. err_v4l2:
  991. v4l2_device_unregister(&gsc->v4l2_dev);
  992. err_clk:
  993. gsc_clk_put(gsc);
  994. return ret;
  995. }
  996. static int gsc_remove(struct platform_device *pdev)
  997. {
  998. struct gsc_dev *gsc = platform_get_drvdata(pdev);
  999. gsc_unregister_m2m_device(gsc);
  1000. v4l2_device_unregister(&gsc->v4l2_dev);
  1001. vb2_dma_contig_cleanup_ctx(gsc->alloc_ctx);
  1002. pm_runtime_disable(&pdev->dev);
  1003. gsc_clk_put(gsc);
  1004. dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name);
  1005. return 0;
  1006. }
  1007. static int gsc_runtime_resume(struct device *dev)
  1008. {
  1009. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1010. int ret = 0;
  1011. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1012. ret = clk_enable(gsc->clock);
  1013. if (ret)
  1014. return ret;
  1015. gsc_hw_set_sw_reset(gsc);
  1016. gsc_wait_reset(gsc);
  1017. return gsc_m2m_resume(gsc);
  1018. }
  1019. static int gsc_runtime_suspend(struct device *dev)
  1020. {
  1021. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1022. int ret = 0;
  1023. ret = gsc_m2m_suspend(gsc);
  1024. if (!ret)
  1025. clk_disable(gsc->clock);
  1026. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1027. return ret;
  1028. }
  1029. static int gsc_resume(struct device *dev)
  1030. {
  1031. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1032. unsigned long flags;
  1033. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1034. /* Do not resume if the device was idle before system suspend */
  1035. spin_lock_irqsave(&gsc->slock, flags);
  1036. if (!test_and_clear_bit(ST_SUSPEND, &gsc->state) ||
  1037. !gsc_m2m_opened(gsc)) {
  1038. spin_unlock_irqrestore(&gsc->slock, flags);
  1039. return 0;
  1040. }
  1041. spin_unlock_irqrestore(&gsc->slock, flags);
  1042. if (!pm_runtime_suspended(dev))
  1043. return gsc_runtime_resume(dev);
  1044. return 0;
  1045. }
  1046. static int gsc_suspend(struct device *dev)
  1047. {
  1048. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1049. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1050. if (test_and_set_bit(ST_SUSPEND, &gsc->state))
  1051. return 0;
  1052. if (!pm_runtime_suspended(dev))
  1053. return gsc_runtime_suspend(dev);
  1054. return 0;
  1055. }
  1056. static const struct dev_pm_ops gsc_pm_ops = {
  1057. .suspend = gsc_suspend,
  1058. .resume = gsc_resume,
  1059. .runtime_suspend = gsc_runtime_suspend,
  1060. .runtime_resume = gsc_runtime_resume,
  1061. };
  1062. static struct platform_driver gsc_driver = {
  1063. .probe = gsc_probe,
  1064. .remove = gsc_remove,
  1065. .id_table = gsc_driver_ids,
  1066. .driver = {
  1067. .name = GSC_MODULE_NAME,
  1068. .pm = &gsc_pm_ops,
  1069. .of_match_table = exynos_gsc_match,
  1070. }
  1071. };
  1072. module_platform_driver(gsc_driver);
  1073. MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>");
  1074. MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver");
  1075. MODULE_LICENSE("GPL");