coda-bit.c 59 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/log2.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-fh.h>
  25. #include <media/v4l2-mem2mem.h>
  26. #include <media/videobuf2-core.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include <media/videobuf2-vmalloc.h>
  29. #include "coda.h"
  30. #define CREATE_TRACE_POINTS
  31. #include "trace.h"
  32. #define CODA_PARA_BUF_SIZE (10 * 1024)
  33. #define CODA7_PS_BUF_SIZE 0x28000
  34. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  35. #define CODA_DEFAULT_GAMMA 4096
  36. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  37. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  38. static inline int coda_is_initialized(struct coda_dev *dev)
  39. {
  40. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  41. }
  42. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  43. {
  44. return coda_read(dev, CODA_REG_BIT_BUSY);
  45. }
  46. static int coda_wait_timeout(struct coda_dev *dev)
  47. {
  48. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  49. while (coda_isbusy(dev)) {
  50. if (time_after(jiffies, timeout))
  51. return -ETIMEDOUT;
  52. }
  53. return 0;
  54. }
  55. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  56. {
  57. struct coda_dev *dev = ctx->dev;
  58. if (dev->devtype->product == CODA_960 ||
  59. dev->devtype->product == CODA_7541) {
  60. /* Restore context related registers to CODA */
  61. coda_write(dev, ctx->bit_stream_param,
  62. CODA_REG_BIT_BIT_STREAM_PARAM);
  63. coda_write(dev, ctx->frm_dis_flg,
  64. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  65. coda_write(dev, ctx->frame_mem_ctrl,
  66. CODA_REG_BIT_FRAME_MEM_CTRL);
  67. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  68. }
  69. if (dev->devtype->product == CODA_960) {
  70. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  71. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  72. }
  73. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  74. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  75. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  76. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  77. trace_coda_bit_run(ctx, cmd);
  78. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  79. }
  80. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  81. {
  82. struct coda_dev *dev = ctx->dev;
  83. int ret;
  84. coda_command_async(ctx, cmd);
  85. ret = coda_wait_timeout(dev);
  86. trace_coda_bit_done(ctx);
  87. return ret;
  88. }
  89. int coda_hw_reset(struct coda_ctx *ctx)
  90. {
  91. struct coda_dev *dev = ctx->dev;
  92. unsigned long timeout;
  93. unsigned int idx;
  94. int ret;
  95. if (!dev->rstc)
  96. return -ENOENT;
  97. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  98. if (dev->devtype->product == CODA_960) {
  99. timeout = jiffies + msecs_to_jiffies(100);
  100. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  101. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  102. if (time_after(jiffies, timeout))
  103. return -ETIME;
  104. cpu_relax();
  105. }
  106. }
  107. ret = reset_control_reset(dev->rstc);
  108. if (ret < 0)
  109. return ret;
  110. if (dev->devtype->product == CODA_960)
  111. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  112. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  113. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  114. ret = coda_wait_timeout(dev);
  115. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  116. return ret;
  117. }
  118. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  119. {
  120. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  121. struct coda_dev *dev = ctx->dev;
  122. u32 rd_ptr;
  123. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  124. kfifo->out = (kfifo->in & ~kfifo->mask) |
  125. (rd_ptr - ctx->bitstream.paddr);
  126. if (kfifo->out > kfifo->in)
  127. kfifo->out -= kfifo->mask + 1;
  128. }
  129. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  130. {
  131. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  132. struct coda_dev *dev = ctx->dev;
  133. u32 rd_ptr, wr_ptr;
  134. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  135. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  136. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  137. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  138. }
  139. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  140. {
  141. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  142. struct coda_dev *dev = ctx->dev;
  143. u32 wr_ptr;
  144. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  145. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  146. }
  147. static int coda_bitstream_queue(struct coda_ctx *ctx,
  148. struct vb2_buffer *src_buf)
  149. {
  150. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  151. u32 n;
  152. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
  153. src_size);
  154. if (n < src_size)
  155. return -ENOSPC;
  156. src_buf->v4l2_buf.sequence = ctx->qsequence++;
  157. return 0;
  158. }
  159. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  160. struct vb2_buffer *src_buf)
  161. {
  162. int ret;
  163. if (coda_get_bitstream_payload(ctx) +
  164. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  165. return false;
  166. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  167. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  168. return true;
  169. }
  170. ret = coda_bitstream_queue(ctx, src_buf);
  171. if (ret < 0) {
  172. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  173. return false;
  174. }
  175. /* Sync read pointer to device */
  176. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  177. coda_kfifo_sync_to_device_write(ctx);
  178. ctx->hold = false;
  179. return true;
  180. }
  181. void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
  182. {
  183. struct vb2_buffer *src_buf;
  184. struct coda_buffer_meta *meta;
  185. unsigned long flags;
  186. u32 start;
  187. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
  188. return;
  189. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  190. /*
  191. * Only queue a single JPEG into the bitstream buffer, except
  192. * to increase payload over 512 bytes or if in hold state.
  193. */
  194. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  195. (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
  196. break;
  197. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  198. /* Drop frames that do not start/end with a SOI/EOI markers */
  199. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  200. !coda_jpeg_check_buffer(ctx, src_buf)) {
  201. v4l2_err(&ctx->dev->v4l2_dev,
  202. "dropping invalid JPEG frame %d\n",
  203. ctx->qsequence);
  204. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  205. v4l2_m2m_buf_done(src_buf, streaming ?
  206. VB2_BUF_STATE_ERROR :
  207. VB2_BUF_STATE_QUEUED);
  208. continue;
  209. }
  210. /* Dump empty buffers */
  211. if (!vb2_get_plane_payload(src_buf, 0)) {
  212. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  213. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  214. continue;
  215. }
  216. /* Buffer start position */
  217. start = ctx->bitstream_fifo.kfifo.in &
  218. ctx->bitstream_fifo.kfifo.mask;
  219. if (coda_bitstream_try_queue(ctx, src_buf)) {
  220. /*
  221. * Source buffer is queued in the bitstream ringbuffer;
  222. * queue the timestamp and mark source buffer as done
  223. */
  224. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  225. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  226. if (meta) {
  227. meta->sequence = src_buf->v4l2_buf.sequence;
  228. meta->timecode = src_buf->v4l2_buf.timecode;
  229. meta->timestamp = src_buf->v4l2_buf.timestamp;
  230. meta->start = start;
  231. meta->end = ctx->bitstream_fifo.kfifo.in &
  232. ctx->bitstream_fifo.kfifo.mask;
  233. spin_lock_irqsave(&ctx->buffer_meta_lock,
  234. flags);
  235. list_add_tail(&meta->list,
  236. &ctx->buffer_meta_list);
  237. ctx->num_metas++;
  238. spin_unlock_irqrestore(&ctx->buffer_meta_lock,
  239. flags);
  240. trace_coda_bit_queue(ctx, src_buf, meta);
  241. }
  242. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  243. } else {
  244. break;
  245. }
  246. }
  247. }
  248. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  249. {
  250. struct coda_dev *dev = ctx->dev;
  251. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  252. /* If this context is currently running, update the hardware flag */
  253. if ((dev->devtype->product == CODA_960) &&
  254. coda_isbusy(dev) &&
  255. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  256. coda_write(dev, ctx->bit_stream_param,
  257. CODA_REG_BIT_BIT_STREAM_PARAM);
  258. }
  259. }
  260. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  261. {
  262. struct coda_dev *dev = ctx->dev;
  263. u32 *p = ctx->parabuf.vaddr;
  264. if (dev->devtype->product == CODA_DX6)
  265. p[index] = value;
  266. else
  267. p[index ^ 1] = value;
  268. }
  269. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  270. struct coda_aux_buf *buf, size_t size,
  271. const char *name)
  272. {
  273. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  274. }
  275. static void coda_free_framebuffers(struct coda_ctx *ctx)
  276. {
  277. int i;
  278. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  279. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  280. }
  281. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  282. struct coda_q_data *q_data, u32 fourcc)
  283. {
  284. struct coda_dev *dev = ctx->dev;
  285. int width, height;
  286. int ysize;
  287. int ret;
  288. int i;
  289. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  290. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  291. width = round_up(q_data->width, 16);
  292. height = round_up(q_data->height, 16);
  293. } else {
  294. width = round_up(q_data->width, 8);
  295. height = q_data->height;
  296. }
  297. ysize = width * height;
  298. /* Allocate frame buffers */
  299. for (i = 0; i < ctx->num_internal_frames; i++) {
  300. size_t size;
  301. char *name;
  302. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  303. size = round_up(ysize, 4096) + ysize / 2;
  304. else
  305. size = ysize + ysize / 2;
  306. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  307. dev->devtype->product != CODA_DX6)
  308. size += ysize / 4;
  309. name = kasprintf(GFP_KERNEL, "fb%d", i);
  310. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  311. size, name);
  312. kfree(name);
  313. if (ret < 0) {
  314. coda_free_framebuffers(ctx);
  315. return ret;
  316. }
  317. }
  318. /* Register frame buffers in the parameter buffer */
  319. for (i = 0; i < ctx->num_internal_frames; i++) {
  320. u32 y, cb, cr;
  321. /* Start addresses of Y, Cb, Cr planes */
  322. y = ctx->internal_frames[i].paddr;
  323. cb = y + ysize;
  324. cr = y + ysize + ysize/4;
  325. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
  326. cb = round_up(cb, 4096);
  327. cr = 0;
  328. /* Packed 20-bit MSB of base addresses */
  329. /* YYYYYCCC, CCyyyyyc, cccc.... */
  330. y = (y & 0xfffff000) | cb >> 20;
  331. cb = (cb & 0x000ff000) << 12;
  332. }
  333. coda_parabuf_write(ctx, i * 3 + 0, y);
  334. coda_parabuf_write(ctx, i * 3 + 1, cb);
  335. coda_parabuf_write(ctx, i * 3 + 2, cr);
  336. /* mvcol buffer for h.264 */
  337. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  338. dev->devtype->product != CODA_DX6)
  339. coda_parabuf_write(ctx, 96 + i,
  340. ctx->internal_frames[i].paddr +
  341. ysize + ysize/4 + ysize/4);
  342. }
  343. /* mvcol buffer for mpeg4 */
  344. if ((dev->devtype->product != CODA_DX6) &&
  345. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  346. coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
  347. ysize + ysize/4 + ysize/4);
  348. return 0;
  349. }
  350. static void coda_free_context_buffers(struct coda_ctx *ctx)
  351. {
  352. struct coda_dev *dev = ctx->dev;
  353. coda_free_aux_buf(dev, &ctx->slicebuf);
  354. coda_free_aux_buf(dev, &ctx->psbuf);
  355. if (dev->devtype->product != CODA_DX6)
  356. coda_free_aux_buf(dev, &ctx->workbuf);
  357. coda_free_aux_buf(dev, &ctx->parabuf);
  358. }
  359. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  360. struct coda_q_data *q_data)
  361. {
  362. struct coda_dev *dev = ctx->dev;
  363. size_t size;
  364. int ret;
  365. if (!ctx->parabuf.vaddr) {
  366. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  367. CODA_PARA_BUF_SIZE, "parabuf");
  368. if (ret < 0)
  369. return ret;
  370. }
  371. if (dev->devtype->product == CODA_DX6)
  372. return 0;
  373. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  374. /* worst case slice size */
  375. size = (DIV_ROUND_UP(q_data->width, 16) *
  376. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  377. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  378. "slicebuf");
  379. if (ret < 0)
  380. goto err;
  381. }
  382. if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
  383. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  384. CODA7_PS_BUF_SIZE, "psbuf");
  385. if (ret < 0)
  386. goto err;
  387. }
  388. if (!ctx->workbuf.vaddr) {
  389. size = dev->devtype->workbuf_size;
  390. if (dev->devtype->product == CODA_960 &&
  391. q_data->fourcc == V4L2_PIX_FMT_H264)
  392. size += CODA9_PS_SAVE_SIZE;
  393. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  394. "workbuf");
  395. if (ret < 0)
  396. goto err;
  397. }
  398. return 0;
  399. err:
  400. coda_free_context_buffers(ctx);
  401. return ret;
  402. }
  403. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  404. int header_code, u8 *header, int *size)
  405. {
  406. struct coda_dev *dev = ctx->dev;
  407. size_t bufsize;
  408. int ret;
  409. int i;
  410. if (dev->devtype->product == CODA_960)
  411. memset(vb2_plane_vaddr(buf, 0), 0, 64);
  412. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  413. CODA_CMD_ENC_HEADER_BB_START);
  414. bufsize = vb2_plane_size(buf, 0);
  415. if (dev->devtype->product == CODA_960)
  416. bufsize /= 1024;
  417. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  418. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  419. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  420. if (ret < 0) {
  421. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  422. return ret;
  423. }
  424. if (dev->devtype->product == CODA_960) {
  425. for (i = 63; i > 0; i--)
  426. if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
  427. break;
  428. *size = i + 1;
  429. } else {
  430. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  431. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  432. }
  433. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  434. return 0;
  435. }
  436. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  437. {
  438. phys_addr_t ret;
  439. size = round_up(size, 1024);
  440. if (size > iram->remaining)
  441. return 0;
  442. iram->remaining -= size;
  443. ret = iram->next_paddr;
  444. iram->next_paddr += size;
  445. return ret;
  446. }
  447. static void coda_setup_iram(struct coda_ctx *ctx)
  448. {
  449. struct coda_iram_info *iram_info = &ctx->iram_info;
  450. struct coda_dev *dev = ctx->dev;
  451. int w64, w128;
  452. int mb_width;
  453. int dbk_bits;
  454. int bit_bits;
  455. int ip_bits;
  456. memset(iram_info, 0, sizeof(*iram_info));
  457. iram_info->next_paddr = dev->iram.paddr;
  458. iram_info->remaining = dev->iram.size;
  459. if (!dev->iram.vaddr)
  460. return;
  461. switch (dev->devtype->product) {
  462. case CODA_7541:
  463. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  464. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  465. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  466. break;
  467. case CODA_960:
  468. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  469. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  470. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  471. break;
  472. default: /* CODA_DX6 */
  473. return;
  474. }
  475. if (ctx->inst_type == CODA_INST_ENCODER) {
  476. struct coda_q_data *q_data_src;
  477. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  478. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  479. w128 = mb_width * 128;
  480. w64 = mb_width * 64;
  481. /* Prioritize in case IRAM is too small for everything */
  482. if (dev->devtype->product == CODA_7541) {
  483. iram_info->search_ram_size = round_up(mb_width * 16 *
  484. 36 + 2048, 1024);
  485. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  486. iram_info->search_ram_size);
  487. if (!iram_info->search_ram_paddr) {
  488. pr_err("IRAM is smaller than the search ram size\n");
  489. goto out;
  490. }
  491. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  492. CODA7_USE_ME_ENABLE;
  493. }
  494. /* Only H.264BP and H.263P3 are considered */
  495. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  496. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  497. if (!iram_info->buf_dbk_c_use)
  498. goto out;
  499. iram_info->axi_sram_use |= dbk_bits;
  500. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  501. if (!iram_info->buf_bit_use)
  502. goto out;
  503. iram_info->axi_sram_use |= bit_bits;
  504. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  505. if (!iram_info->buf_ip_ac_dc_use)
  506. goto out;
  507. iram_info->axi_sram_use |= ip_bits;
  508. /* OVL and BTP disabled for encoder */
  509. } else if (ctx->inst_type == CODA_INST_DECODER) {
  510. struct coda_q_data *q_data_dst;
  511. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  512. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  513. w128 = mb_width * 128;
  514. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  515. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  516. if (!iram_info->buf_dbk_c_use)
  517. goto out;
  518. iram_info->axi_sram_use |= dbk_bits;
  519. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  520. if (!iram_info->buf_bit_use)
  521. goto out;
  522. iram_info->axi_sram_use |= bit_bits;
  523. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  524. if (!iram_info->buf_ip_ac_dc_use)
  525. goto out;
  526. iram_info->axi_sram_use |= ip_bits;
  527. /* OVL and BTP unused as there is no VC1 support yet */
  528. }
  529. out:
  530. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  531. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  532. "IRAM smaller than needed\n");
  533. if (dev->devtype->product == CODA_7541) {
  534. /* TODO - Enabling these causes picture errors on CODA7541 */
  535. if (ctx->inst_type == CODA_INST_DECODER) {
  536. /* fw 1.4.50 */
  537. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  538. CODA7_USE_IP_ENABLE);
  539. } else {
  540. /* fw 13.4.29 */
  541. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  542. CODA7_USE_HOST_DBK_ENABLE |
  543. CODA7_USE_IP_ENABLE |
  544. CODA7_USE_DBK_ENABLE);
  545. }
  546. }
  547. }
  548. static u32 coda_supported_firmwares[] = {
  549. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  550. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  551. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  552. };
  553. static bool coda_firmware_supported(u32 vernum)
  554. {
  555. int i;
  556. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  557. if (vernum == coda_supported_firmwares[i])
  558. return true;
  559. return false;
  560. }
  561. int coda_check_firmware(struct coda_dev *dev)
  562. {
  563. u16 product, major, minor, release;
  564. u32 data;
  565. int ret;
  566. ret = clk_prepare_enable(dev->clk_per);
  567. if (ret)
  568. goto err_clk_per;
  569. ret = clk_prepare_enable(dev->clk_ahb);
  570. if (ret)
  571. goto err_clk_ahb;
  572. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  573. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  574. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  575. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  576. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  577. if (coda_wait_timeout(dev)) {
  578. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  579. ret = -EIO;
  580. goto err_run_cmd;
  581. }
  582. if (dev->devtype->product == CODA_960) {
  583. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  584. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  585. data);
  586. }
  587. /* Check we are compatible with the loaded firmware */
  588. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  589. product = CODA_FIRMWARE_PRODUCT(data);
  590. major = CODA_FIRMWARE_MAJOR(data);
  591. minor = CODA_FIRMWARE_MINOR(data);
  592. release = CODA_FIRMWARE_RELEASE(data);
  593. clk_disable_unprepare(dev->clk_per);
  594. clk_disable_unprepare(dev->clk_ahb);
  595. if (product != dev->devtype->product) {
  596. v4l2_err(&dev->v4l2_dev,
  597. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  598. coda_product_name(dev->devtype->product),
  599. coda_product_name(product), major, minor, release);
  600. return -EINVAL;
  601. }
  602. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  603. coda_product_name(product));
  604. if (coda_firmware_supported(data)) {
  605. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  606. major, minor, release);
  607. } else {
  608. v4l2_warn(&dev->v4l2_dev,
  609. "Unsupported firmware version: %u.%u.%u\n",
  610. major, minor, release);
  611. }
  612. return 0;
  613. err_run_cmd:
  614. clk_disable_unprepare(dev->clk_ahb);
  615. err_clk_ahb:
  616. clk_disable_unprepare(dev->clk_per);
  617. err_clk_per:
  618. return ret;
  619. }
  620. static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
  621. {
  622. u32 cache_size, cache_config;
  623. if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
  624. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  625. cache_size = 0x20262024;
  626. cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
  627. } else {
  628. /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
  629. cache_size = 0x02440243;
  630. cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
  631. }
  632. coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  633. if (fourcc == V4L2_PIX_FMT_NV12) {
  634. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  635. 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  636. 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  637. } else {
  638. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  639. 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  640. 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  641. }
  642. coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  643. }
  644. /*
  645. * Encoder context operations
  646. */
  647. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  648. struct v4l2_requestbuffers *rb)
  649. {
  650. struct coda_q_data *q_data_src;
  651. int ret;
  652. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  653. return 0;
  654. if (rb->count) {
  655. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  656. ret = coda_alloc_context_buffers(ctx, q_data_src);
  657. if (ret < 0)
  658. return ret;
  659. } else {
  660. coda_free_context_buffers(ctx);
  661. }
  662. return 0;
  663. }
  664. static int coda_start_encoding(struct coda_ctx *ctx)
  665. {
  666. struct coda_dev *dev = ctx->dev;
  667. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  668. struct coda_q_data *q_data_src, *q_data_dst;
  669. u32 bitstream_buf, bitstream_size;
  670. struct vb2_buffer *buf;
  671. int gamma, ret, value;
  672. u32 dst_fourcc;
  673. int num_fb;
  674. u32 stride;
  675. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  676. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  677. dst_fourcc = q_data_dst->fourcc;
  678. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  679. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  680. bitstream_size = q_data_dst->sizeimage;
  681. if (!coda_is_initialized(dev)) {
  682. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  683. return -EFAULT;
  684. }
  685. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  686. if (!ctx->params.jpeg_qmat_tab[0])
  687. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  688. if (!ctx->params.jpeg_qmat_tab[1])
  689. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  690. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  691. }
  692. mutex_lock(&dev->coda_mutex);
  693. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  694. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  695. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  696. switch (dev->devtype->product) {
  697. case CODA_DX6:
  698. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  699. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  700. break;
  701. case CODA_960:
  702. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  703. /* fallthrough */
  704. case CODA_7541:
  705. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  706. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  707. break;
  708. }
  709. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  710. CODA9_FRAME_TILED2LINEAR);
  711. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  712. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  713. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  714. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  715. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  716. if (dev->devtype->product == CODA_DX6) {
  717. /* Configure the coda */
  718. coda_write(dev, dev->iram.paddr,
  719. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  720. }
  721. /* Could set rotation here if needed */
  722. value = 0;
  723. switch (dev->devtype->product) {
  724. case CODA_DX6:
  725. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  726. << CODADX6_PICWIDTH_OFFSET;
  727. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  728. << CODA_PICHEIGHT_OFFSET;
  729. break;
  730. case CODA_7541:
  731. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  732. value = (round_up(q_data_src->width, 16) &
  733. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  734. value |= (round_up(q_data_src->height, 16) &
  735. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  736. break;
  737. }
  738. /* fallthrough */
  739. case CODA_960:
  740. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  741. << CODA7_PICWIDTH_OFFSET;
  742. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  743. << CODA_PICHEIGHT_OFFSET;
  744. }
  745. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  746. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  747. ctx->params.framerate = 0;
  748. coda_write(dev, ctx->params.framerate,
  749. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  750. ctx->params.codec_mode = ctx->codec->mode;
  751. switch (dst_fourcc) {
  752. case V4L2_PIX_FMT_MPEG4:
  753. if (dev->devtype->product == CODA_960)
  754. coda_write(dev, CODA9_STD_MPEG4,
  755. CODA_CMD_ENC_SEQ_COD_STD);
  756. else
  757. coda_write(dev, CODA_STD_MPEG4,
  758. CODA_CMD_ENC_SEQ_COD_STD);
  759. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  760. break;
  761. case V4L2_PIX_FMT_H264:
  762. if (dev->devtype->product == CODA_960)
  763. coda_write(dev, CODA9_STD_H264,
  764. CODA_CMD_ENC_SEQ_COD_STD);
  765. else
  766. coda_write(dev, CODA_STD_H264,
  767. CODA_CMD_ENC_SEQ_COD_STD);
  768. if (ctx->params.h264_deblk_enabled) {
  769. value = ((ctx->params.h264_deblk_alpha &
  770. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  771. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  772. ((ctx->params.h264_deblk_beta &
  773. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  774. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  775. } else {
  776. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  777. }
  778. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  779. break;
  780. case V4L2_PIX_FMT_JPEG:
  781. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  782. coda_write(dev, ctx->params.jpeg_restart_interval,
  783. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  784. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  785. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  786. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  787. coda_jpeg_write_tables(ctx);
  788. break;
  789. default:
  790. v4l2_err(v4l2_dev,
  791. "dst format (0x%08x) invalid.\n", dst_fourcc);
  792. ret = -EINVAL;
  793. goto out;
  794. }
  795. /*
  796. * slice mode and GOP size registers are used for thumb size/offset
  797. * in JPEG mode
  798. */
  799. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  800. switch (ctx->params.slice_mode) {
  801. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  802. value = 0;
  803. break;
  804. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  805. value = (ctx->params.slice_max_mb &
  806. CODA_SLICING_SIZE_MASK)
  807. << CODA_SLICING_SIZE_OFFSET;
  808. value |= (1 & CODA_SLICING_UNIT_MASK)
  809. << CODA_SLICING_UNIT_OFFSET;
  810. value |= 1 & CODA_SLICING_MODE_MASK;
  811. break;
  812. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  813. value = (ctx->params.slice_max_bits &
  814. CODA_SLICING_SIZE_MASK)
  815. << CODA_SLICING_SIZE_OFFSET;
  816. value |= (0 & CODA_SLICING_UNIT_MASK)
  817. << CODA_SLICING_UNIT_OFFSET;
  818. value |= 1 & CODA_SLICING_MODE_MASK;
  819. break;
  820. }
  821. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  822. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  823. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  824. }
  825. if (ctx->params.bitrate) {
  826. /* Rate control enabled */
  827. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  828. << CODA_RATECONTROL_BITRATE_OFFSET;
  829. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  830. value |= (ctx->params.vbv_delay &
  831. CODA_RATECONTROL_INITIALDELAY_MASK)
  832. << CODA_RATECONTROL_INITIALDELAY_OFFSET;
  833. if (dev->devtype->product == CODA_960)
  834. value |= BIT(31); /* disable autoskip */
  835. } else {
  836. value = 0;
  837. }
  838. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  839. coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  840. coda_write(dev, ctx->params.intra_refresh,
  841. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  842. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  843. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  844. value = 0;
  845. if (dev->devtype->product == CODA_960)
  846. gamma = CODA9_DEFAULT_GAMMA;
  847. else
  848. gamma = CODA_DEFAULT_GAMMA;
  849. if (gamma > 0) {
  850. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  851. CODA_CMD_ENC_SEQ_RC_GAMMA);
  852. }
  853. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  854. coda_write(dev,
  855. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  856. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  857. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  858. }
  859. if (dev->devtype->product == CODA_960) {
  860. if (ctx->params.h264_max_qp)
  861. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  862. if (CODA_DEFAULT_GAMMA > 0)
  863. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  864. } else {
  865. if (CODA_DEFAULT_GAMMA > 0) {
  866. if (dev->devtype->product == CODA_DX6)
  867. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  868. else
  869. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  870. }
  871. if (ctx->params.h264_min_qp)
  872. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  873. if (ctx->params.h264_max_qp)
  874. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  875. }
  876. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  877. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  878. coda_setup_iram(ctx);
  879. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  880. switch (dev->devtype->product) {
  881. case CODA_DX6:
  882. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  883. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  884. break;
  885. case CODA_7541:
  886. coda_write(dev, ctx->iram_info.search_ram_paddr,
  887. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  888. coda_write(dev, ctx->iram_info.search_ram_size,
  889. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  890. break;
  891. case CODA_960:
  892. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  893. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  894. }
  895. }
  896. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  897. if (ret < 0) {
  898. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  899. goto out;
  900. }
  901. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  902. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  903. ret = -EFAULT;
  904. goto out;
  905. }
  906. ctx->initialized = 1;
  907. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  908. if (dev->devtype->product == CODA_960)
  909. ctx->num_internal_frames = 4;
  910. else
  911. ctx->num_internal_frames = 2;
  912. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  913. if (ret < 0) {
  914. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  915. goto out;
  916. }
  917. num_fb = 2;
  918. stride = q_data_src->bytesperline;
  919. } else {
  920. ctx->num_internal_frames = 0;
  921. num_fb = 0;
  922. stride = 0;
  923. }
  924. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  925. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  926. if (dev->devtype->product == CODA_7541) {
  927. coda_write(dev, q_data_src->bytesperline,
  928. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  929. }
  930. if (dev->devtype->product != CODA_DX6) {
  931. coda_write(dev, ctx->iram_info.buf_bit_use,
  932. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  933. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  934. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  935. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  936. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  937. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  938. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  939. coda_write(dev, ctx->iram_info.buf_ovl_use,
  940. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  941. if (dev->devtype->product == CODA_960) {
  942. coda_write(dev, ctx->iram_info.buf_btp_use,
  943. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  944. coda9_set_frame_cache(ctx, q_data_src->fourcc);
  945. /* FIXME */
  946. coda_write(dev, ctx->internal_frames[2].paddr,
  947. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  948. coda_write(dev, ctx->internal_frames[3].paddr,
  949. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  950. }
  951. }
  952. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  953. if (ret < 0) {
  954. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  955. goto out;
  956. }
  957. /* Save stream headers */
  958. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  959. switch (dst_fourcc) {
  960. case V4L2_PIX_FMT_H264:
  961. /*
  962. * Get SPS in the first frame and copy it to an
  963. * intermediate buffer.
  964. */
  965. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  966. &ctx->vpu_header[0][0],
  967. &ctx->vpu_header_size[0]);
  968. if (ret < 0)
  969. goto out;
  970. /*
  971. * Get PPS in the first frame and copy it to an
  972. * intermediate buffer.
  973. */
  974. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  975. &ctx->vpu_header[1][0],
  976. &ctx->vpu_header_size[1]);
  977. if (ret < 0)
  978. goto out;
  979. /*
  980. * Length of H.264 headers is variable and thus it might not be
  981. * aligned for the coda to append the encoded frame. In that is
  982. * the case a filler NAL must be added to header 2.
  983. */
  984. ctx->vpu_header_size[2] = coda_h264_padding(
  985. (ctx->vpu_header_size[0] +
  986. ctx->vpu_header_size[1]),
  987. ctx->vpu_header[2]);
  988. break;
  989. case V4L2_PIX_FMT_MPEG4:
  990. /*
  991. * Get VOS in the first frame and copy it to an
  992. * intermediate buffer
  993. */
  994. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  995. &ctx->vpu_header[0][0],
  996. &ctx->vpu_header_size[0]);
  997. if (ret < 0)
  998. goto out;
  999. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  1000. &ctx->vpu_header[1][0],
  1001. &ctx->vpu_header_size[1]);
  1002. if (ret < 0)
  1003. goto out;
  1004. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  1005. &ctx->vpu_header[2][0],
  1006. &ctx->vpu_header_size[2]);
  1007. if (ret < 0)
  1008. goto out;
  1009. break;
  1010. default:
  1011. /* No more formats need to save headers at the moment */
  1012. break;
  1013. }
  1014. out:
  1015. mutex_unlock(&dev->coda_mutex);
  1016. return ret;
  1017. }
  1018. static int coda_prepare_encode(struct coda_ctx *ctx)
  1019. {
  1020. struct coda_q_data *q_data_src, *q_data_dst;
  1021. struct vb2_buffer *src_buf, *dst_buf;
  1022. struct coda_dev *dev = ctx->dev;
  1023. int force_ipicture;
  1024. int quant_param = 0;
  1025. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  1026. u32 rot_mode = 0;
  1027. u32 dst_fourcc;
  1028. u32 reg;
  1029. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  1030. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1031. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1032. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1033. dst_fourcc = q_data_dst->fourcc;
  1034. src_buf->v4l2_buf.sequence = ctx->osequence;
  1035. dst_buf->v4l2_buf.sequence = ctx->osequence;
  1036. ctx->osequence++;
  1037. /*
  1038. * Workaround coda firmware BUG that only marks the first
  1039. * frame as IDR. This is a problem for some decoders that can't
  1040. * recover when a frame is lost.
  1041. */
  1042. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  1043. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1044. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1045. } else {
  1046. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1047. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1048. }
  1049. if (dev->devtype->product == CODA_960)
  1050. coda_set_gdi_regs(ctx);
  1051. /*
  1052. * Copy headers at the beginning of the first frame for H.264 only.
  1053. * In MPEG4 they are already copied by the coda.
  1054. */
  1055. if (src_buf->v4l2_buf.sequence == 0) {
  1056. pic_stream_buffer_addr =
  1057. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  1058. ctx->vpu_header_size[0] +
  1059. ctx->vpu_header_size[1] +
  1060. ctx->vpu_header_size[2];
  1061. pic_stream_buffer_size = q_data_dst->sizeimage -
  1062. ctx->vpu_header_size[0] -
  1063. ctx->vpu_header_size[1] -
  1064. ctx->vpu_header_size[2];
  1065. memcpy(vb2_plane_vaddr(dst_buf, 0),
  1066. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1067. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  1068. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  1069. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  1070. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  1071. ctx->vpu_header_size[2]);
  1072. } else {
  1073. pic_stream_buffer_addr =
  1074. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  1075. pic_stream_buffer_size = q_data_dst->sizeimage;
  1076. }
  1077. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1078. force_ipicture = 1;
  1079. switch (dst_fourcc) {
  1080. case V4L2_PIX_FMT_H264:
  1081. quant_param = ctx->params.h264_intra_qp;
  1082. break;
  1083. case V4L2_PIX_FMT_MPEG4:
  1084. quant_param = ctx->params.mpeg4_intra_qp;
  1085. break;
  1086. case V4L2_PIX_FMT_JPEG:
  1087. quant_param = 30;
  1088. break;
  1089. default:
  1090. v4l2_warn(&ctx->dev->v4l2_dev,
  1091. "cannot set intra qp, fmt not supported\n");
  1092. break;
  1093. }
  1094. } else {
  1095. force_ipicture = 0;
  1096. switch (dst_fourcc) {
  1097. case V4L2_PIX_FMT_H264:
  1098. quant_param = ctx->params.h264_inter_qp;
  1099. break;
  1100. case V4L2_PIX_FMT_MPEG4:
  1101. quant_param = ctx->params.mpeg4_inter_qp;
  1102. break;
  1103. default:
  1104. v4l2_warn(&ctx->dev->v4l2_dev,
  1105. "cannot set inter qp, fmt not supported\n");
  1106. break;
  1107. }
  1108. }
  1109. /* submit */
  1110. if (ctx->params.rot_mode)
  1111. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1112. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1113. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1114. if (dev->devtype->product == CODA_960) {
  1115. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1116. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1117. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1118. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1119. } else {
  1120. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1121. }
  1122. coda_write_base(ctx, q_data_src, src_buf, reg);
  1123. coda_write(dev, force_ipicture << 1 & 0x2,
  1124. CODA_CMD_ENC_PIC_OPTION);
  1125. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1126. coda_write(dev, pic_stream_buffer_size / 1024,
  1127. CODA_CMD_ENC_PIC_BB_SIZE);
  1128. if (!ctx->streamon_out) {
  1129. /* After streamoff on the output side, set stream end flag */
  1130. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1131. coda_write(dev, ctx->bit_stream_param,
  1132. CODA_REG_BIT_BIT_STREAM_PARAM);
  1133. }
  1134. if (dev->devtype->product != CODA_DX6)
  1135. coda_write(dev, ctx->iram_info.axi_sram_use,
  1136. CODA7_REG_BIT_AXI_SRAM_USE);
  1137. trace_coda_enc_pic_run(ctx, src_buf);
  1138. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1139. return 0;
  1140. }
  1141. static void coda_finish_encode(struct coda_ctx *ctx)
  1142. {
  1143. struct vb2_buffer *src_buf, *dst_buf;
  1144. struct coda_dev *dev = ctx->dev;
  1145. u32 wr_ptr, start_ptr;
  1146. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1147. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1148. trace_coda_enc_pic_done(ctx, dst_buf);
  1149. /* Get results from the coda */
  1150. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1151. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1152. /* Calculate bytesused field */
  1153. if (dst_buf->v4l2_buf.sequence == 0) {
  1154. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1155. ctx->vpu_header_size[0] +
  1156. ctx->vpu_header_size[1] +
  1157. ctx->vpu_header_size[2]);
  1158. } else {
  1159. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1160. }
  1161. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1162. wr_ptr - start_ptr);
  1163. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1164. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1165. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1166. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1167. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1168. } else {
  1169. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1170. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1171. }
  1172. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1173. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1174. dst_buf->v4l2_buf.flags |=
  1175. src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1176. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1177. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1178. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1179. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  1180. ctx->gopcounter--;
  1181. if (ctx->gopcounter < 0)
  1182. ctx->gopcounter = ctx->params.gop_size - 1;
  1183. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1184. "job finished: encoding frame (%d) (%s)\n",
  1185. dst_buf->v4l2_buf.sequence,
  1186. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1187. "KEYFRAME" : "PFRAME");
  1188. }
  1189. static void coda_seq_end_work(struct work_struct *work)
  1190. {
  1191. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1192. struct coda_dev *dev = ctx->dev;
  1193. mutex_lock(&ctx->buffer_mutex);
  1194. mutex_lock(&dev->coda_mutex);
  1195. if (ctx->initialized == 0)
  1196. goto out;
  1197. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1198. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1199. __func__);
  1200. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1201. v4l2_err(&dev->v4l2_dev,
  1202. "CODA_COMMAND_SEQ_END failed\n");
  1203. }
  1204. /*
  1205. * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
  1206. * from the output stream after the h.264 decoder has run. Resetting the
  1207. * hardware after the decoder has finished seems to help.
  1208. */
  1209. if (dev->devtype->product == CODA_960)
  1210. coda_hw_reset(ctx);
  1211. kfifo_init(&ctx->bitstream_fifo,
  1212. ctx->bitstream.vaddr, ctx->bitstream.size);
  1213. coda_free_framebuffers(ctx);
  1214. ctx->initialized = 0;
  1215. out:
  1216. mutex_unlock(&dev->coda_mutex);
  1217. mutex_unlock(&ctx->buffer_mutex);
  1218. }
  1219. static void coda_bit_release(struct coda_ctx *ctx)
  1220. {
  1221. mutex_lock(&ctx->buffer_mutex);
  1222. coda_free_framebuffers(ctx);
  1223. coda_free_context_buffers(ctx);
  1224. coda_free_bitstream_buffer(ctx);
  1225. mutex_unlock(&ctx->buffer_mutex);
  1226. }
  1227. const struct coda_context_ops coda_bit_encode_ops = {
  1228. .queue_init = coda_encoder_queue_init,
  1229. .reqbufs = coda_encoder_reqbufs,
  1230. .start_streaming = coda_start_encoding,
  1231. .prepare_run = coda_prepare_encode,
  1232. .finish_run = coda_finish_encode,
  1233. .seq_end_work = coda_seq_end_work,
  1234. .release = coda_bit_release,
  1235. };
  1236. /*
  1237. * Decoder context operations
  1238. */
  1239. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1240. struct coda_q_data *q_data)
  1241. {
  1242. if (ctx->bitstream.vaddr)
  1243. return 0;
  1244. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1245. ctx->bitstream.vaddr = dma_alloc_writecombine(
  1246. &ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1247. &ctx->bitstream.paddr, GFP_KERNEL);
  1248. if (!ctx->bitstream.vaddr) {
  1249. v4l2_err(&ctx->dev->v4l2_dev,
  1250. "failed to allocate bitstream ringbuffer");
  1251. return -ENOMEM;
  1252. }
  1253. kfifo_init(&ctx->bitstream_fifo,
  1254. ctx->bitstream.vaddr, ctx->bitstream.size);
  1255. return 0;
  1256. }
  1257. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1258. {
  1259. if (ctx->bitstream.vaddr == NULL)
  1260. return;
  1261. dma_free_writecombine(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1262. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1263. ctx->bitstream.vaddr = NULL;
  1264. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1265. }
  1266. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1267. struct v4l2_requestbuffers *rb)
  1268. {
  1269. struct coda_q_data *q_data_src;
  1270. int ret;
  1271. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1272. return 0;
  1273. if (rb->count) {
  1274. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1275. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1276. if (ret < 0)
  1277. return ret;
  1278. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1279. if (ret < 0) {
  1280. coda_free_context_buffers(ctx);
  1281. return ret;
  1282. }
  1283. } else {
  1284. coda_free_bitstream_buffer(ctx);
  1285. coda_free_context_buffers(ctx);
  1286. }
  1287. return 0;
  1288. }
  1289. static int __coda_start_decoding(struct coda_ctx *ctx)
  1290. {
  1291. struct coda_q_data *q_data_src, *q_data_dst;
  1292. u32 bitstream_buf, bitstream_size;
  1293. struct coda_dev *dev = ctx->dev;
  1294. int width, height;
  1295. u32 src_fourcc, dst_fourcc;
  1296. u32 val;
  1297. int ret;
  1298. /* Start decoding */
  1299. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1300. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1301. bitstream_buf = ctx->bitstream.paddr;
  1302. bitstream_size = ctx->bitstream.size;
  1303. src_fourcc = q_data_src->fourcc;
  1304. dst_fourcc = q_data_dst->fourcc;
  1305. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1306. /* Update coda bitstream read and write pointers from kfifo */
  1307. coda_kfifo_sync_to_device_full(ctx);
  1308. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  1309. CODA9_FRAME_TILED2LINEAR);
  1310. if (dst_fourcc == V4L2_PIX_FMT_NV12)
  1311. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1312. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  1313. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  1314. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1315. ctx->display_idx = -1;
  1316. ctx->frm_dis_flg = 0;
  1317. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1318. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1319. CODA_REG_BIT_BIT_STREAM_PARAM);
  1320. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1321. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1322. val = 0;
  1323. if ((dev->devtype->product == CODA_7541) ||
  1324. (dev->devtype->product == CODA_960))
  1325. val |= CODA_REORDER_ENABLE;
  1326. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1327. val |= CODA_NO_INT_ENABLE;
  1328. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1329. ctx->params.codec_mode = ctx->codec->mode;
  1330. if (dev->devtype->product == CODA_960 &&
  1331. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1332. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1333. else
  1334. ctx->params.codec_mode_aux = 0;
  1335. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1336. if (dev->devtype->product == CODA_7541) {
  1337. coda_write(dev, ctx->psbuf.paddr,
  1338. CODA_CMD_DEC_SEQ_PS_BB_START);
  1339. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1340. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1341. }
  1342. if (dev->devtype->product == CODA_960) {
  1343. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1344. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1345. }
  1346. }
  1347. if (dev->devtype->product != CODA_960)
  1348. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1349. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1350. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1351. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1352. return -ETIMEDOUT;
  1353. }
  1354. ctx->initialized = 1;
  1355. /* Update kfifo out pointer from coda bitstream read pointer */
  1356. coda_kfifo_sync_from_device(ctx);
  1357. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1358. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1359. v4l2_err(&dev->v4l2_dev,
  1360. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1361. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1362. return -EAGAIN;
  1363. }
  1364. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1365. if (dev->devtype->product == CODA_DX6) {
  1366. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1367. height = val & CODADX6_PICHEIGHT_MASK;
  1368. } else {
  1369. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1370. height = val & CODA7_PICHEIGHT_MASK;
  1371. }
  1372. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1373. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1374. width, height, q_data_dst->bytesperline,
  1375. q_data_dst->height);
  1376. return -EINVAL;
  1377. }
  1378. width = round_up(width, 16);
  1379. height = round_up(height, 16);
  1380. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1381. __func__, ctx->idx, width, height);
  1382. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1383. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1384. v4l2_err(&dev->v4l2_dev,
  1385. "not enough framebuffers to decode (%d < %d)\n",
  1386. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1387. return -EINVAL;
  1388. }
  1389. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1390. u32 left_right;
  1391. u32 top_bottom;
  1392. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1393. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1394. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1395. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1396. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1397. (left_right & 0x3ff);
  1398. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1399. (top_bottom & 0x3ff);
  1400. }
  1401. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1402. if (ret < 0) {
  1403. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1404. return ret;
  1405. }
  1406. /* Tell the decoder how many frame buffers we allocated. */
  1407. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1408. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1409. if (dev->devtype->product != CODA_DX6) {
  1410. /* Set secondary AXI IRAM */
  1411. coda_setup_iram(ctx);
  1412. coda_write(dev, ctx->iram_info.buf_bit_use,
  1413. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1414. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1415. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1416. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1417. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1418. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1419. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1420. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1421. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1422. if (dev->devtype->product == CODA_960) {
  1423. coda_write(dev, ctx->iram_info.buf_btp_use,
  1424. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1425. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1426. coda9_set_frame_cache(ctx, dst_fourcc);
  1427. }
  1428. }
  1429. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1430. coda_write(dev, ctx->slicebuf.paddr,
  1431. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1432. coda_write(dev, ctx->slicebuf.size / 1024,
  1433. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1434. }
  1435. if (dev->devtype->product == CODA_7541) {
  1436. int max_mb_x = 1920 / 16;
  1437. int max_mb_y = 1088 / 16;
  1438. int max_mb_num = max_mb_x * max_mb_y;
  1439. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1440. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1441. } else if (dev->devtype->product == CODA_960) {
  1442. int max_mb_x = 1920 / 16;
  1443. int max_mb_y = 1088 / 16;
  1444. int max_mb_num = max_mb_x * max_mb_y;
  1445. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1446. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1447. }
  1448. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1449. v4l2_err(&ctx->dev->v4l2_dev,
  1450. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1451. return -ETIMEDOUT;
  1452. }
  1453. return 0;
  1454. }
  1455. static int coda_start_decoding(struct coda_ctx *ctx)
  1456. {
  1457. struct coda_dev *dev = ctx->dev;
  1458. int ret;
  1459. mutex_lock(&dev->coda_mutex);
  1460. ret = __coda_start_decoding(ctx);
  1461. mutex_unlock(&dev->coda_mutex);
  1462. return ret;
  1463. }
  1464. static int coda_prepare_decode(struct coda_ctx *ctx)
  1465. {
  1466. struct vb2_buffer *dst_buf;
  1467. struct coda_dev *dev = ctx->dev;
  1468. struct coda_q_data *q_data_dst;
  1469. struct coda_buffer_meta *meta;
  1470. unsigned long flags;
  1471. u32 reg_addr, reg_stride;
  1472. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1473. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1474. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1475. mutex_lock(&ctx->bitstream_mutex);
  1476. coda_fill_bitstream(ctx, true);
  1477. mutex_unlock(&ctx->bitstream_mutex);
  1478. if (coda_get_bitstream_payload(ctx) < 512 &&
  1479. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1480. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1481. "bitstream payload: %d, skipping\n",
  1482. coda_get_bitstream_payload(ctx));
  1483. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1484. return -EAGAIN;
  1485. }
  1486. /* Run coda_start_decoding (again) if not yet initialized */
  1487. if (!ctx->initialized) {
  1488. int ret = __coda_start_decoding(ctx);
  1489. if (ret < 0) {
  1490. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1491. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1492. return -EAGAIN;
  1493. } else {
  1494. ctx->initialized = 1;
  1495. }
  1496. }
  1497. if (dev->devtype->product == CODA_960)
  1498. coda_set_gdi_regs(ctx);
  1499. if (dev->devtype->product == CODA_960) {
  1500. /*
  1501. * The CODA960 seems to have an internal list of buffers with
  1502. * 64 entries that includes the registered frame buffers as
  1503. * well as the rotator buffer output.
  1504. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1505. */
  1506. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
  1507. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1508. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1509. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1510. } else {
  1511. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1512. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1513. }
  1514. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1515. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1516. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1517. CODA_CMD_DEC_PIC_ROT_MODE);
  1518. switch (dev->devtype->product) {
  1519. case CODA_DX6:
  1520. /* TBD */
  1521. case CODA_7541:
  1522. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1523. break;
  1524. case CODA_960:
  1525. /* 'hardcode to use interrupt disable mode'? */
  1526. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1527. break;
  1528. }
  1529. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1530. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1531. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1532. if (dev->devtype->product != CODA_DX6)
  1533. coda_write(dev, ctx->iram_info.axi_sram_use,
  1534. CODA7_REG_BIT_AXI_SRAM_USE);
  1535. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1536. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1537. struct coda_buffer_meta, list);
  1538. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1539. /* If this is the last buffer in the bitstream, add padding */
  1540. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1541. ctx->bitstream_fifo.kfifo.mask)) {
  1542. static unsigned char buf[512];
  1543. unsigned int pad;
  1544. /* Pad to multiple of 256 and then add 256 more */
  1545. pad = ((0 - meta->end) & 0xff) + 256;
  1546. memset(buf, 0xff, sizeof(buf));
  1547. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1548. }
  1549. }
  1550. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1551. coda_kfifo_sync_to_device_full(ctx);
  1552. /* Clear decode success flag */
  1553. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1554. trace_coda_dec_pic_run(ctx, meta);
  1555. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1556. return 0;
  1557. }
  1558. static void coda_finish_decode(struct coda_ctx *ctx)
  1559. {
  1560. struct coda_dev *dev = ctx->dev;
  1561. struct coda_q_data *q_data_src;
  1562. struct coda_q_data *q_data_dst;
  1563. struct vb2_buffer *dst_buf;
  1564. struct coda_buffer_meta *meta;
  1565. unsigned long payload;
  1566. unsigned long flags;
  1567. int width, height;
  1568. int decoded_idx;
  1569. int display_idx;
  1570. u32 src_fourcc;
  1571. int success;
  1572. u32 err_mb;
  1573. u32 val;
  1574. /* Update kfifo out pointer from coda bitstream read pointer */
  1575. coda_kfifo_sync_from_device(ctx);
  1576. /*
  1577. * in stream-end mode, the read pointer can overshoot the write pointer
  1578. * by up to 512 bytes
  1579. */
  1580. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1581. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1582. kfifo_init(&ctx->bitstream_fifo,
  1583. ctx->bitstream.vaddr, ctx->bitstream.size);
  1584. }
  1585. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1586. src_fourcc = q_data_src->fourcc;
  1587. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1588. if (val != 1)
  1589. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1590. success = val & 0x1;
  1591. if (!success)
  1592. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1593. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1594. if (val & (1 << 3))
  1595. v4l2_err(&dev->v4l2_dev,
  1596. "insufficient PS buffer space (%d bytes)\n",
  1597. ctx->psbuf.size);
  1598. if (val & (1 << 2))
  1599. v4l2_err(&dev->v4l2_dev,
  1600. "insufficient slice buffer space (%d bytes)\n",
  1601. ctx->slicebuf.size);
  1602. }
  1603. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1604. width = (val >> 16) & 0xffff;
  1605. height = val & 0xffff;
  1606. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1607. /* frame crop information */
  1608. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1609. u32 left_right;
  1610. u32 top_bottom;
  1611. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1612. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1613. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1614. /* Keep current crop information */
  1615. } else {
  1616. struct v4l2_rect *rect = &q_data_dst->rect;
  1617. rect->left = left_right >> 16 & 0xffff;
  1618. rect->top = top_bottom >> 16 & 0xffff;
  1619. rect->width = width - rect->left -
  1620. (left_right & 0xffff);
  1621. rect->height = height - rect->top -
  1622. (top_bottom & 0xffff);
  1623. }
  1624. } else {
  1625. /* no cropping */
  1626. }
  1627. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1628. if (err_mb > 0)
  1629. v4l2_err(&dev->v4l2_dev,
  1630. "errors in %d macroblocks\n", err_mb);
  1631. if (dev->devtype->product == CODA_7541) {
  1632. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1633. if (val == 0) {
  1634. /* not enough bitstream data */
  1635. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1636. "prescan failed: %d\n", val);
  1637. ctx->hold = true;
  1638. return;
  1639. }
  1640. }
  1641. ctx->frm_dis_flg = coda_read(dev,
  1642. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1643. /*
  1644. * The previous display frame was copied out by the rotator,
  1645. * now it can be overwritten again
  1646. */
  1647. if (ctx->display_idx >= 0 &&
  1648. ctx->display_idx < ctx->num_internal_frames) {
  1649. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1650. coda_write(dev, ctx->frm_dis_flg,
  1651. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1652. }
  1653. /*
  1654. * The index of the last decoded frame, not necessarily in
  1655. * display order, and the index of the next display frame.
  1656. * The latter could have been decoded in a previous run.
  1657. */
  1658. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1659. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1660. if (decoded_idx == -1) {
  1661. /* no frame was decoded, but we might have a display frame */
  1662. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1663. ctx->sequence_offset++;
  1664. else if (ctx->display_idx < 0)
  1665. ctx->hold = true;
  1666. } else if (decoded_idx == -2) {
  1667. /* no frame was decoded, we still return remaining buffers */
  1668. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1669. v4l2_err(&dev->v4l2_dev,
  1670. "decoded frame index out of range: %d\n", decoded_idx);
  1671. } else {
  1672. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1673. val -= ctx->sequence_offset;
  1674. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1675. if (!list_empty(&ctx->buffer_meta_list)) {
  1676. meta = list_first_entry(&ctx->buffer_meta_list,
  1677. struct coda_buffer_meta, list);
  1678. list_del(&meta->list);
  1679. ctx->num_metas--;
  1680. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1681. /*
  1682. * Clamp counters to 16 bits for comparison, as the HW
  1683. * counter rolls over at this point for h.264. This
  1684. * may be different for other formats, but using 16 bits
  1685. * should be enough to detect most errors and saves us
  1686. * from doing different things based on the format.
  1687. */
  1688. if ((val & 0xffff) != (meta->sequence & 0xffff)) {
  1689. v4l2_err(&dev->v4l2_dev,
  1690. "sequence number mismatch (%d(%d) != %d)\n",
  1691. val, ctx->sequence_offset,
  1692. meta->sequence);
  1693. }
  1694. ctx->frame_metas[decoded_idx] = *meta;
  1695. kfree(meta);
  1696. } else {
  1697. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1698. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1699. memset(&ctx->frame_metas[decoded_idx], 0,
  1700. sizeof(struct coda_buffer_meta));
  1701. ctx->frame_metas[decoded_idx].sequence = val;
  1702. ctx->sequence_offset++;
  1703. }
  1704. trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
  1705. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1706. if (val == 0)
  1707. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1708. else if (val == 1)
  1709. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1710. else
  1711. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1712. ctx->frame_errors[decoded_idx] = err_mb;
  1713. }
  1714. if (display_idx == -1) {
  1715. /*
  1716. * no more frames to be decoded, but there could still
  1717. * be rotator output to dequeue
  1718. */
  1719. ctx->hold = true;
  1720. } else if (display_idx == -3) {
  1721. /* possibly prescan failure */
  1722. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1723. v4l2_err(&dev->v4l2_dev,
  1724. "presentation frame index out of range: %d\n",
  1725. display_idx);
  1726. }
  1727. /* If a frame was copied out, return it */
  1728. if (ctx->display_idx >= 0 &&
  1729. ctx->display_idx < ctx->num_internal_frames) {
  1730. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1731. dst_buf->v4l2_buf.sequence = ctx->osequence++;
  1732. dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1733. V4L2_BUF_FLAG_PFRAME |
  1734. V4L2_BUF_FLAG_BFRAME);
  1735. dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
  1736. meta = &ctx->frame_metas[ctx->display_idx];
  1737. dst_buf->v4l2_buf.timecode = meta->timecode;
  1738. dst_buf->v4l2_buf.timestamp = meta->timestamp;
  1739. trace_coda_dec_rot_done(ctx, dst_buf, meta);
  1740. switch (q_data_dst->fourcc) {
  1741. case V4L2_PIX_FMT_YUV420:
  1742. case V4L2_PIX_FMT_YVU420:
  1743. case V4L2_PIX_FMT_NV12:
  1744. default:
  1745. payload = width * height * 3 / 2;
  1746. break;
  1747. case V4L2_PIX_FMT_YUV422P:
  1748. payload = width * height * 2;
  1749. break;
  1750. }
  1751. vb2_set_plane_payload(dst_buf, 0, payload);
  1752. coda_m2m_buf_done(ctx, dst_buf, ctx->frame_errors[display_idx] ?
  1753. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1754. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1755. "job finished: decoding frame (%d) (%s)\n",
  1756. dst_buf->v4l2_buf.sequence,
  1757. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1758. "KEYFRAME" : "PFRAME");
  1759. } else {
  1760. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1761. "job finished: no frame decoded\n");
  1762. }
  1763. /* The rotator will copy the current display frame next time */
  1764. ctx->display_idx = display_idx;
  1765. }
  1766. const struct coda_context_ops coda_bit_decode_ops = {
  1767. .queue_init = coda_decoder_queue_init,
  1768. .reqbufs = coda_decoder_reqbufs,
  1769. .start_streaming = coda_start_decoding,
  1770. .prepare_run = coda_prepare_decode,
  1771. .finish_run = coda_finish_decode,
  1772. .seq_end_work = coda_seq_end_work,
  1773. .release = coda_bit_release,
  1774. };
  1775. irqreturn_t coda_irq_handler(int irq, void *data)
  1776. {
  1777. struct coda_dev *dev = data;
  1778. struct coda_ctx *ctx;
  1779. /* read status register to attend the IRQ */
  1780. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1781. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1782. CODA_REG_BIT_INT_CLEAR);
  1783. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1784. if (ctx == NULL) {
  1785. v4l2_err(&dev->v4l2_dev,
  1786. "Instance released before the end of transaction\n");
  1787. mutex_unlock(&dev->coda_mutex);
  1788. return IRQ_HANDLED;
  1789. }
  1790. trace_coda_bit_done(ctx);
  1791. if (ctx->aborting) {
  1792. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1793. "task has been aborted\n");
  1794. }
  1795. if (coda_isbusy(ctx->dev)) {
  1796. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1797. "coda is still busy!!!!\n");
  1798. return IRQ_NONE;
  1799. }
  1800. complete(&ctx->completion);
  1801. return IRQ_HANDLED;
  1802. }