ocrdma_verbs.c 85 KB

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  1. /* This file is part of the Emulex RoCE Device Driver for
  2. * RoCE (RDMA over Converged Ethernet) adapters.
  3. * Copyright (C) 2012-2015 Emulex. All rights reserved.
  4. * EMULEX and SLI are trademarks of Emulex.
  5. * www.emulex.com
  6. *
  7. * This software is available to you under a choice of one of two licenses.
  8. * You may choose to be licensed under the terms of the GNU General Public
  9. * License (GPL) Version 2, available from the file COPYING in the main
  10. * directory of this source tree, or the BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions
  14. * are met:
  15. *
  16. * - Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the distribution.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32. * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. * Contact Information:
  36. * linux-drivers@emulex.com
  37. *
  38. * Emulex
  39. * 3333 Susan Street
  40. * Costa Mesa, CA 92626
  41. */
  42. #include <linux/dma-mapping.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/iw_cm.h>
  46. #include <rdma/ib_umem.h>
  47. #include <rdma/ib_addr.h>
  48. #include <rdma/ib_cache.h>
  49. #include "ocrdma.h"
  50. #include "ocrdma_hw.h"
  51. #include "ocrdma_verbs.h"
  52. #include "ocrdma_abi.h"
  53. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  54. {
  55. if (index > 1)
  56. return -EINVAL;
  57. *pkey = 0xffff;
  58. return 0;
  59. }
  60. int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
  61. int index, union ib_gid *sgid)
  62. {
  63. int ret;
  64. struct ocrdma_dev *dev;
  65. dev = get_ocrdma_dev(ibdev);
  66. memset(sgid, 0, sizeof(*sgid));
  67. if (index >= OCRDMA_MAX_SGID)
  68. return -EINVAL;
  69. ret = ib_get_cached_gid(ibdev, port, index, sgid);
  70. if (ret == -EAGAIN) {
  71. memcpy(sgid, &zgid, sizeof(*sgid));
  72. return 0;
  73. }
  74. return ret;
  75. }
  76. int ocrdma_add_gid(struct ib_device *device,
  77. u8 port_num,
  78. unsigned int index,
  79. const union ib_gid *gid,
  80. const struct ib_gid_attr *attr,
  81. void **context) {
  82. return 0;
  83. }
  84. int ocrdma_del_gid(struct ib_device *device,
  85. u8 port_num,
  86. unsigned int index,
  87. void **context) {
  88. return 0;
  89. }
  90. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr,
  91. struct ib_udata *uhw)
  92. {
  93. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  94. if (uhw->inlen || uhw->outlen)
  95. return -EINVAL;
  96. memset(attr, 0, sizeof *attr);
  97. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  98. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  99. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  100. attr->max_mr_size = dev->attr.max_mr_size;
  101. attr->page_size_cap = 0xffff000;
  102. attr->vendor_id = dev->nic_info.pdev->vendor;
  103. attr->vendor_part_id = dev->nic_info.pdev->device;
  104. attr->hw_ver = dev->asic_id;
  105. attr->max_qp = dev->attr.max_qp;
  106. attr->max_ah = OCRDMA_MAX_AH;
  107. attr->max_qp_wr = dev->attr.max_wqe;
  108. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  109. IB_DEVICE_RC_RNR_NAK_GEN |
  110. IB_DEVICE_SHUTDOWN_PORT |
  111. IB_DEVICE_SYS_IMAGE_GUID |
  112. IB_DEVICE_LOCAL_DMA_LKEY |
  113. IB_DEVICE_MEM_MGT_EXTENSIONS;
  114. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge);
  115. attr->max_sge_rd = 0;
  116. attr->max_cq = dev->attr.max_cq;
  117. attr->max_cqe = dev->attr.max_cqe;
  118. attr->max_mr = dev->attr.max_mr;
  119. attr->max_mw = dev->attr.max_mw;
  120. attr->max_pd = dev->attr.max_pd;
  121. attr->atomic_cap = 0;
  122. attr->max_fmr = 0;
  123. attr->max_map_per_fmr = 0;
  124. attr->max_qp_rd_atom =
  125. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  126. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  127. attr->max_srq = dev->attr.max_srq;
  128. attr->max_srq_sge = dev->attr.max_srq_sge;
  129. attr->max_srq_wr = dev->attr.max_rqe;
  130. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  131. attr->max_fast_reg_page_list_len = dev->attr.max_pages_per_frmr;
  132. attr->max_pkeys = 1;
  133. return 0;
  134. }
  135. struct net_device *ocrdma_get_netdev(struct ib_device *ibdev, u8 port_num)
  136. {
  137. struct ocrdma_dev *dev;
  138. struct net_device *ndev = NULL;
  139. rcu_read_lock();
  140. dev = get_ocrdma_dev(ibdev);
  141. if (dev)
  142. ndev = dev->nic_info.netdev;
  143. if (ndev)
  144. dev_hold(ndev);
  145. rcu_read_unlock();
  146. return ndev;
  147. }
  148. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  149. u8 *ib_speed, u8 *ib_width)
  150. {
  151. int status;
  152. u8 speed;
  153. status = ocrdma_mbx_get_link_speed(dev, &speed);
  154. if (status)
  155. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  156. switch (speed) {
  157. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  158. *ib_speed = IB_SPEED_SDR;
  159. *ib_width = IB_WIDTH_1X;
  160. break;
  161. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  162. *ib_speed = IB_SPEED_QDR;
  163. *ib_width = IB_WIDTH_1X;
  164. break;
  165. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  166. *ib_speed = IB_SPEED_DDR;
  167. *ib_width = IB_WIDTH_4X;
  168. break;
  169. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  170. *ib_speed = IB_SPEED_QDR;
  171. *ib_width = IB_WIDTH_4X;
  172. break;
  173. default:
  174. /* Unsupported */
  175. *ib_speed = IB_SPEED_SDR;
  176. *ib_width = IB_WIDTH_1X;
  177. }
  178. }
  179. int ocrdma_query_port(struct ib_device *ibdev,
  180. u8 port, struct ib_port_attr *props)
  181. {
  182. enum ib_port_state port_state;
  183. struct ocrdma_dev *dev;
  184. struct net_device *netdev;
  185. dev = get_ocrdma_dev(ibdev);
  186. if (port > 1) {
  187. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  188. dev->id, port);
  189. return -EINVAL;
  190. }
  191. netdev = dev->nic_info.netdev;
  192. if (netif_running(netdev) && netif_oper_up(netdev)) {
  193. port_state = IB_PORT_ACTIVE;
  194. props->phys_state = 5;
  195. } else {
  196. port_state = IB_PORT_DOWN;
  197. props->phys_state = 3;
  198. }
  199. props->max_mtu = IB_MTU_4096;
  200. props->active_mtu = iboe_get_mtu(netdev->mtu);
  201. props->lid = 0;
  202. props->lmc = 0;
  203. props->sm_lid = 0;
  204. props->sm_sl = 0;
  205. props->state = port_state;
  206. props->port_cap_flags =
  207. IB_PORT_CM_SUP |
  208. IB_PORT_REINIT_SUP |
  209. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP |
  210. IB_PORT_IP_BASED_GIDS;
  211. props->gid_tbl_len = OCRDMA_MAX_SGID;
  212. props->pkey_tbl_len = 1;
  213. props->bad_pkey_cntr = 0;
  214. props->qkey_viol_cntr = 0;
  215. get_link_speed_and_width(dev, &props->active_speed,
  216. &props->active_width);
  217. props->max_msg_sz = 0x80000000;
  218. props->max_vl_num = 4;
  219. return 0;
  220. }
  221. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  222. struct ib_port_modify *props)
  223. {
  224. struct ocrdma_dev *dev;
  225. dev = get_ocrdma_dev(ibdev);
  226. if (port > 1) {
  227. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  228. return -EINVAL;
  229. }
  230. return 0;
  231. }
  232. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  233. unsigned long len)
  234. {
  235. struct ocrdma_mm *mm;
  236. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  237. if (mm == NULL)
  238. return -ENOMEM;
  239. mm->key.phy_addr = phy_addr;
  240. mm->key.len = len;
  241. INIT_LIST_HEAD(&mm->entry);
  242. mutex_lock(&uctx->mm_list_lock);
  243. list_add_tail(&mm->entry, &uctx->mm_head);
  244. mutex_unlock(&uctx->mm_list_lock);
  245. return 0;
  246. }
  247. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  248. unsigned long len)
  249. {
  250. struct ocrdma_mm *mm, *tmp;
  251. mutex_lock(&uctx->mm_list_lock);
  252. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  253. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  254. continue;
  255. list_del(&mm->entry);
  256. kfree(mm);
  257. break;
  258. }
  259. mutex_unlock(&uctx->mm_list_lock);
  260. }
  261. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  262. unsigned long len)
  263. {
  264. bool found = false;
  265. struct ocrdma_mm *mm;
  266. mutex_lock(&uctx->mm_list_lock);
  267. list_for_each_entry(mm, &uctx->mm_head, entry) {
  268. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  269. continue;
  270. found = true;
  271. break;
  272. }
  273. mutex_unlock(&uctx->mm_list_lock);
  274. return found;
  275. }
  276. static u16 _ocrdma_pd_mgr_get_bitmap(struct ocrdma_dev *dev, bool dpp_pool)
  277. {
  278. u16 pd_bitmap_idx = 0;
  279. const unsigned long *pd_bitmap;
  280. if (dpp_pool) {
  281. pd_bitmap = dev->pd_mgr->pd_dpp_bitmap;
  282. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  283. dev->pd_mgr->max_dpp_pd);
  284. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_dpp_bitmap);
  285. dev->pd_mgr->pd_dpp_count++;
  286. if (dev->pd_mgr->pd_dpp_count > dev->pd_mgr->pd_dpp_thrsh)
  287. dev->pd_mgr->pd_dpp_thrsh = dev->pd_mgr->pd_dpp_count;
  288. } else {
  289. pd_bitmap = dev->pd_mgr->pd_norm_bitmap;
  290. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  291. dev->pd_mgr->max_normal_pd);
  292. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_norm_bitmap);
  293. dev->pd_mgr->pd_norm_count++;
  294. if (dev->pd_mgr->pd_norm_count > dev->pd_mgr->pd_norm_thrsh)
  295. dev->pd_mgr->pd_norm_thrsh = dev->pd_mgr->pd_norm_count;
  296. }
  297. return pd_bitmap_idx;
  298. }
  299. static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id,
  300. bool dpp_pool)
  301. {
  302. u16 pd_count;
  303. u16 pd_bit_index;
  304. pd_count = dpp_pool ? dev->pd_mgr->pd_dpp_count :
  305. dev->pd_mgr->pd_norm_count;
  306. if (pd_count == 0)
  307. return -EINVAL;
  308. if (dpp_pool) {
  309. pd_bit_index = pd_id - dev->pd_mgr->pd_dpp_start;
  310. if (pd_bit_index >= dev->pd_mgr->max_dpp_pd) {
  311. return -EINVAL;
  312. } else {
  313. __clear_bit(pd_bit_index, dev->pd_mgr->pd_dpp_bitmap);
  314. dev->pd_mgr->pd_dpp_count--;
  315. }
  316. } else {
  317. pd_bit_index = pd_id - dev->pd_mgr->pd_norm_start;
  318. if (pd_bit_index >= dev->pd_mgr->max_normal_pd) {
  319. return -EINVAL;
  320. } else {
  321. __clear_bit(pd_bit_index, dev->pd_mgr->pd_norm_bitmap);
  322. dev->pd_mgr->pd_norm_count--;
  323. }
  324. }
  325. return 0;
  326. }
  327. static u8 ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
  328. bool dpp_pool)
  329. {
  330. int status;
  331. mutex_lock(&dev->dev_lock);
  332. status = _ocrdma_pd_mgr_put_bitmap(dev, pd_id, dpp_pool);
  333. mutex_unlock(&dev->dev_lock);
  334. return status;
  335. }
  336. static int ocrdma_get_pd_num(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
  337. {
  338. u16 pd_idx = 0;
  339. int status = 0;
  340. mutex_lock(&dev->dev_lock);
  341. if (pd->dpp_enabled) {
  342. /* try allocating DPP PD, if not available then normal PD */
  343. if (dev->pd_mgr->pd_dpp_count < dev->pd_mgr->max_dpp_pd) {
  344. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, true);
  345. pd->id = dev->pd_mgr->pd_dpp_start + pd_idx;
  346. pd->dpp_page = dev->pd_mgr->dpp_page_index + pd_idx;
  347. } else if (dev->pd_mgr->pd_norm_count <
  348. dev->pd_mgr->max_normal_pd) {
  349. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  350. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  351. pd->dpp_enabled = false;
  352. } else {
  353. status = -EINVAL;
  354. }
  355. } else {
  356. if (dev->pd_mgr->pd_norm_count < dev->pd_mgr->max_normal_pd) {
  357. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  358. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  359. } else {
  360. status = -EINVAL;
  361. }
  362. }
  363. mutex_unlock(&dev->dev_lock);
  364. return status;
  365. }
  366. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  367. struct ocrdma_ucontext *uctx,
  368. struct ib_udata *udata)
  369. {
  370. struct ocrdma_pd *pd = NULL;
  371. int status = 0;
  372. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  373. if (!pd)
  374. return ERR_PTR(-ENOMEM);
  375. if (udata && uctx && dev->attr.max_dpp_pds) {
  376. pd->dpp_enabled =
  377. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  378. pd->num_dpp_qp =
  379. pd->dpp_enabled ? (dev->nic_info.db_page_size /
  380. dev->attr.wqe_size) : 0;
  381. }
  382. if (dev->pd_mgr->pd_prealloc_valid) {
  383. status = ocrdma_get_pd_num(dev, pd);
  384. if (status == 0) {
  385. return pd;
  386. } else {
  387. kfree(pd);
  388. return ERR_PTR(status);
  389. }
  390. }
  391. retry:
  392. status = ocrdma_mbx_alloc_pd(dev, pd);
  393. if (status) {
  394. if (pd->dpp_enabled) {
  395. pd->dpp_enabled = false;
  396. pd->num_dpp_qp = 0;
  397. goto retry;
  398. } else {
  399. kfree(pd);
  400. return ERR_PTR(status);
  401. }
  402. }
  403. return pd;
  404. }
  405. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  406. struct ocrdma_pd *pd)
  407. {
  408. return (uctx->cntxt_pd == pd ? true : false);
  409. }
  410. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  411. struct ocrdma_pd *pd)
  412. {
  413. int status = 0;
  414. if (dev->pd_mgr->pd_prealloc_valid)
  415. status = ocrdma_put_pd_num(dev, pd->id, pd->dpp_enabled);
  416. else
  417. status = ocrdma_mbx_dealloc_pd(dev, pd);
  418. kfree(pd);
  419. return status;
  420. }
  421. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  422. struct ocrdma_ucontext *uctx,
  423. struct ib_udata *udata)
  424. {
  425. int status = 0;
  426. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  427. if (IS_ERR(uctx->cntxt_pd)) {
  428. status = PTR_ERR(uctx->cntxt_pd);
  429. uctx->cntxt_pd = NULL;
  430. goto err;
  431. }
  432. uctx->cntxt_pd->uctx = uctx;
  433. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  434. err:
  435. return status;
  436. }
  437. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  438. {
  439. struct ocrdma_pd *pd = uctx->cntxt_pd;
  440. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  441. if (uctx->pd_in_use) {
  442. pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
  443. __func__, dev->id, pd->id);
  444. }
  445. uctx->cntxt_pd = NULL;
  446. (void)_ocrdma_dealloc_pd(dev, pd);
  447. return 0;
  448. }
  449. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  450. {
  451. struct ocrdma_pd *pd = NULL;
  452. mutex_lock(&uctx->mm_list_lock);
  453. if (!uctx->pd_in_use) {
  454. uctx->pd_in_use = true;
  455. pd = uctx->cntxt_pd;
  456. }
  457. mutex_unlock(&uctx->mm_list_lock);
  458. return pd;
  459. }
  460. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  461. {
  462. mutex_lock(&uctx->mm_list_lock);
  463. uctx->pd_in_use = false;
  464. mutex_unlock(&uctx->mm_list_lock);
  465. }
  466. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  467. struct ib_udata *udata)
  468. {
  469. int status;
  470. struct ocrdma_ucontext *ctx;
  471. struct ocrdma_alloc_ucontext_resp resp;
  472. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  473. struct pci_dev *pdev = dev->nic_info.pdev;
  474. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  475. if (!udata)
  476. return ERR_PTR(-EFAULT);
  477. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  478. if (!ctx)
  479. return ERR_PTR(-ENOMEM);
  480. INIT_LIST_HEAD(&ctx->mm_head);
  481. mutex_init(&ctx->mm_list_lock);
  482. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  483. &ctx->ah_tbl.pa, GFP_KERNEL);
  484. if (!ctx->ah_tbl.va) {
  485. kfree(ctx);
  486. return ERR_PTR(-ENOMEM);
  487. }
  488. memset(ctx->ah_tbl.va, 0, map_len);
  489. ctx->ah_tbl.len = map_len;
  490. memset(&resp, 0, sizeof(resp));
  491. resp.ah_tbl_len = ctx->ah_tbl.len;
  492. resp.ah_tbl_page = virt_to_phys(ctx->ah_tbl.va);
  493. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  494. if (status)
  495. goto map_err;
  496. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  497. if (status)
  498. goto pd_err;
  499. resp.dev_id = dev->id;
  500. resp.max_inline_data = dev->attr.max_inline_data;
  501. resp.wqe_size = dev->attr.wqe_size;
  502. resp.rqe_size = dev->attr.rqe_size;
  503. resp.dpp_wqe_size = dev->attr.wqe_size;
  504. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  505. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  506. if (status)
  507. goto cpy_err;
  508. return &ctx->ibucontext;
  509. cpy_err:
  510. pd_err:
  511. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  512. map_err:
  513. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  514. ctx->ah_tbl.pa);
  515. kfree(ctx);
  516. return ERR_PTR(status);
  517. }
  518. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  519. {
  520. int status = 0;
  521. struct ocrdma_mm *mm, *tmp;
  522. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  523. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  524. struct pci_dev *pdev = dev->nic_info.pdev;
  525. status = ocrdma_dealloc_ucontext_pd(uctx);
  526. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  527. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  528. uctx->ah_tbl.pa);
  529. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  530. list_del(&mm->entry);
  531. kfree(mm);
  532. }
  533. kfree(uctx);
  534. return status;
  535. }
  536. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  537. {
  538. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  539. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  540. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  541. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  542. unsigned long len = (vma->vm_end - vma->vm_start);
  543. int status = 0;
  544. bool found;
  545. if (vma->vm_start & (PAGE_SIZE - 1))
  546. return -EINVAL;
  547. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  548. if (!found)
  549. return -EINVAL;
  550. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  551. dev->nic_info.db_total_size)) &&
  552. (len <= dev->nic_info.db_page_size)) {
  553. if (vma->vm_flags & VM_READ)
  554. return -EPERM;
  555. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  556. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  557. len, vma->vm_page_prot);
  558. } else if (dev->nic_info.dpp_unmapped_len &&
  559. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  560. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  561. dev->nic_info.dpp_unmapped_len)) &&
  562. (len <= dev->nic_info.dpp_unmapped_len)) {
  563. if (vma->vm_flags & VM_READ)
  564. return -EPERM;
  565. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  566. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  567. len, vma->vm_page_prot);
  568. } else {
  569. status = remap_pfn_range(vma, vma->vm_start,
  570. vma->vm_pgoff, len, vma->vm_page_prot);
  571. }
  572. return status;
  573. }
  574. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  575. struct ib_ucontext *ib_ctx,
  576. struct ib_udata *udata)
  577. {
  578. int status;
  579. u64 db_page_addr;
  580. u64 dpp_page_addr = 0;
  581. u32 db_page_size;
  582. struct ocrdma_alloc_pd_uresp rsp;
  583. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  584. memset(&rsp, 0, sizeof(rsp));
  585. rsp.id = pd->id;
  586. rsp.dpp_enabled = pd->dpp_enabled;
  587. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  588. db_page_size = dev->nic_info.db_page_size;
  589. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  590. if (status)
  591. return status;
  592. if (pd->dpp_enabled) {
  593. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  594. (pd->id * PAGE_SIZE);
  595. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  596. PAGE_SIZE);
  597. if (status)
  598. goto dpp_map_err;
  599. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  600. rsp.dpp_page_addr_lo = dpp_page_addr;
  601. }
  602. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  603. if (status)
  604. goto ucopy_err;
  605. pd->uctx = uctx;
  606. return 0;
  607. ucopy_err:
  608. if (pd->dpp_enabled)
  609. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  610. dpp_map_err:
  611. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  612. return status;
  613. }
  614. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  615. struct ib_ucontext *context,
  616. struct ib_udata *udata)
  617. {
  618. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  619. struct ocrdma_pd *pd;
  620. struct ocrdma_ucontext *uctx = NULL;
  621. int status;
  622. u8 is_uctx_pd = false;
  623. if (udata && context) {
  624. uctx = get_ocrdma_ucontext(context);
  625. pd = ocrdma_get_ucontext_pd(uctx);
  626. if (pd) {
  627. is_uctx_pd = true;
  628. goto pd_mapping;
  629. }
  630. }
  631. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  632. if (IS_ERR(pd)) {
  633. status = PTR_ERR(pd);
  634. goto exit;
  635. }
  636. pd_mapping:
  637. if (udata && context) {
  638. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  639. if (status)
  640. goto err;
  641. }
  642. return &pd->ibpd;
  643. err:
  644. if (is_uctx_pd) {
  645. ocrdma_release_ucontext_pd(uctx);
  646. } else {
  647. status = _ocrdma_dealloc_pd(dev, pd);
  648. }
  649. exit:
  650. return ERR_PTR(status);
  651. }
  652. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  653. {
  654. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  655. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  656. struct ocrdma_ucontext *uctx = NULL;
  657. int status = 0;
  658. u64 usr_db;
  659. uctx = pd->uctx;
  660. if (uctx) {
  661. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  662. (pd->id * PAGE_SIZE);
  663. if (pd->dpp_enabled)
  664. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  665. usr_db = ocrdma_get_db_addr(dev, pd->id);
  666. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  667. if (is_ucontext_pd(uctx, pd)) {
  668. ocrdma_release_ucontext_pd(uctx);
  669. return status;
  670. }
  671. }
  672. status = _ocrdma_dealloc_pd(dev, pd);
  673. return status;
  674. }
  675. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  676. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  677. {
  678. int status;
  679. mr->hwmr.fr_mr = 0;
  680. mr->hwmr.local_rd = 1;
  681. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  682. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  683. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  684. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  685. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  686. mr->hwmr.num_pbls = num_pbls;
  687. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  688. if (status)
  689. return status;
  690. mr->ibmr.lkey = mr->hwmr.lkey;
  691. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  692. mr->ibmr.rkey = mr->hwmr.lkey;
  693. return 0;
  694. }
  695. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  696. {
  697. int status;
  698. struct ocrdma_mr *mr;
  699. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  700. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  701. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  702. pr_err("%s err, invalid access rights\n", __func__);
  703. return ERR_PTR(-EINVAL);
  704. }
  705. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  706. if (!mr)
  707. return ERR_PTR(-ENOMEM);
  708. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  709. OCRDMA_ADDR_CHECK_DISABLE);
  710. if (status) {
  711. kfree(mr);
  712. return ERR_PTR(status);
  713. }
  714. return &mr->ibmr;
  715. }
  716. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  717. struct ocrdma_hw_mr *mr)
  718. {
  719. struct pci_dev *pdev = dev->nic_info.pdev;
  720. int i = 0;
  721. if (mr->pbl_table) {
  722. for (i = 0; i < mr->num_pbls; i++) {
  723. if (!mr->pbl_table[i].va)
  724. continue;
  725. dma_free_coherent(&pdev->dev, mr->pbl_size,
  726. mr->pbl_table[i].va,
  727. mr->pbl_table[i].pa);
  728. }
  729. kfree(mr->pbl_table);
  730. mr->pbl_table = NULL;
  731. }
  732. }
  733. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  734. u32 num_pbes)
  735. {
  736. u32 num_pbls = 0;
  737. u32 idx = 0;
  738. int status = 0;
  739. u32 pbl_size;
  740. do {
  741. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  742. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  743. status = -EFAULT;
  744. break;
  745. }
  746. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  747. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  748. idx++;
  749. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  750. mr->hwmr.num_pbes = num_pbes;
  751. mr->hwmr.num_pbls = num_pbls;
  752. mr->hwmr.pbl_size = pbl_size;
  753. return status;
  754. }
  755. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  756. {
  757. int status = 0;
  758. int i;
  759. u32 dma_len = mr->pbl_size;
  760. struct pci_dev *pdev = dev->nic_info.pdev;
  761. void *va;
  762. dma_addr_t pa;
  763. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  764. mr->num_pbls, GFP_KERNEL);
  765. if (!mr->pbl_table)
  766. return -ENOMEM;
  767. for (i = 0; i < mr->num_pbls; i++) {
  768. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  769. if (!va) {
  770. ocrdma_free_mr_pbl_tbl(dev, mr);
  771. status = -ENOMEM;
  772. break;
  773. }
  774. memset(va, 0, dma_len);
  775. mr->pbl_table[i].va = va;
  776. mr->pbl_table[i].pa = pa;
  777. }
  778. return status;
  779. }
  780. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  781. u32 num_pbes)
  782. {
  783. struct ocrdma_pbe *pbe;
  784. struct scatterlist *sg;
  785. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  786. struct ib_umem *umem = mr->umem;
  787. int shift, pg_cnt, pages, pbe_cnt, entry, total_num_pbes = 0;
  788. if (!mr->hwmr.num_pbes)
  789. return;
  790. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  791. pbe_cnt = 0;
  792. shift = ilog2(umem->page_size);
  793. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  794. pages = sg_dma_len(sg) >> shift;
  795. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  796. /* store the page address in pbe */
  797. pbe->pa_lo =
  798. cpu_to_le32(sg_dma_address
  799. (sg) +
  800. (umem->page_size * pg_cnt));
  801. pbe->pa_hi =
  802. cpu_to_le32(upper_32_bits
  803. ((sg_dma_address
  804. (sg) +
  805. umem->page_size * pg_cnt)));
  806. pbe_cnt += 1;
  807. total_num_pbes += 1;
  808. pbe++;
  809. /* if done building pbes, issue the mbx cmd. */
  810. if (total_num_pbes == num_pbes)
  811. return;
  812. /* if the given pbl is full storing the pbes,
  813. * move to next pbl.
  814. */
  815. if (pbe_cnt ==
  816. (mr->hwmr.pbl_size / sizeof(u64))) {
  817. pbl_tbl++;
  818. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  819. pbe_cnt = 0;
  820. }
  821. }
  822. }
  823. }
  824. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  825. u64 usr_addr, int acc, struct ib_udata *udata)
  826. {
  827. int status = -ENOMEM;
  828. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  829. struct ocrdma_mr *mr;
  830. struct ocrdma_pd *pd;
  831. u32 num_pbes;
  832. pd = get_ocrdma_pd(ibpd);
  833. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  834. return ERR_PTR(-EINVAL);
  835. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  836. if (!mr)
  837. return ERR_PTR(status);
  838. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  839. if (IS_ERR(mr->umem)) {
  840. status = -EFAULT;
  841. goto umem_err;
  842. }
  843. num_pbes = ib_umem_page_count(mr->umem);
  844. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  845. if (status)
  846. goto umem_err;
  847. mr->hwmr.pbe_size = mr->umem->page_size;
  848. mr->hwmr.fbo = ib_umem_offset(mr->umem);
  849. mr->hwmr.va = usr_addr;
  850. mr->hwmr.len = len;
  851. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  852. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  853. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  854. mr->hwmr.local_rd = 1;
  855. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  856. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  857. if (status)
  858. goto umem_err;
  859. build_user_pbes(dev, mr, num_pbes);
  860. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  861. if (status)
  862. goto mbx_err;
  863. mr->ibmr.lkey = mr->hwmr.lkey;
  864. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  865. mr->ibmr.rkey = mr->hwmr.lkey;
  866. return &mr->ibmr;
  867. mbx_err:
  868. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  869. umem_err:
  870. kfree(mr);
  871. return ERR_PTR(status);
  872. }
  873. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  874. {
  875. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  876. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  877. (void) ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  878. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  879. /* it could be user registered memory. */
  880. if (mr->umem)
  881. ib_umem_release(mr->umem);
  882. kfree(mr);
  883. /* Don't stop cleanup, in case FW is unresponsive */
  884. if (dev->mqe_ctx.fw_error_state) {
  885. pr_err("%s(%d) fw not responding.\n",
  886. __func__, dev->id);
  887. }
  888. return 0;
  889. }
  890. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  891. struct ib_udata *udata,
  892. struct ib_ucontext *ib_ctx)
  893. {
  894. int status;
  895. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  896. struct ocrdma_create_cq_uresp uresp;
  897. memset(&uresp, 0, sizeof(uresp));
  898. uresp.cq_id = cq->id;
  899. uresp.page_size = PAGE_ALIGN(cq->len);
  900. uresp.num_pages = 1;
  901. uresp.max_hw_cqe = cq->max_hw_cqe;
  902. uresp.page_addr[0] = virt_to_phys(cq->va);
  903. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  904. uresp.db_page_size = dev->nic_info.db_page_size;
  905. uresp.phase_change = cq->phase_change ? 1 : 0;
  906. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  907. if (status) {
  908. pr_err("%s(%d) copy error cqid=0x%x.\n",
  909. __func__, dev->id, cq->id);
  910. goto err;
  911. }
  912. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  913. if (status)
  914. goto err;
  915. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  916. if (status) {
  917. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  918. goto err;
  919. }
  920. cq->ucontext = uctx;
  921. err:
  922. return status;
  923. }
  924. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev,
  925. const struct ib_cq_init_attr *attr,
  926. struct ib_ucontext *ib_ctx,
  927. struct ib_udata *udata)
  928. {
  929. int entries = attr->cqe;
  930. struct ocrdma_cq *cq;
  931. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  932. struct ocrdma_ucontext *uctx = NULL;
  933. u16 pd_id = 0;
  934. int status;
  935. struct ocrdma_create_cq_ureq ureq;
  936. if (attr->flags)
  937. return ERR_PTR(-EINVAL);
  938. if (udata) {
  939. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  940. return ERR_PTR(-EFAULT);
  941. } else
  942. ureq.dpp_cq = 0;
  943. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  944. if (!cq)
  945. return ERR_PTR(-ENOMEM);
  946. spin_lock_init(&cq->cq_lock);
  947. spin_lock_init(&cq->comp_handler_lock);
  948. INIT_LIST_HEAD(&cq->sq_head);
  949. INIT_LIST_HEAD(&cq->rq_head);
  950. cq->first_arm = true;
  951. if (ib_ctx) {
  952. uctx = get_ocrdma_ucontext(ib_ctx);
  953. pd_id = uctx->cntxt_pd->id;
  954. }
  955. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  956. if (status) {
  957. kfree(cq);
  958. return ERR_PTR(status);
  959. }
  960. if (ib_ctx) {
  961. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  962. if (status)
  963. goto ctx_err;
  964. }
  965. cq->phase = OCRDMA_CQE_VALID;
  966. dev->cq_tbl[cq->id] = cq;
  967. return &cq->ibcq;
  968. ctx_err:
  969. ocrdma_mbx_destroy_cq(dev, cq);
  970. kfree(cq);
  971. return ERR_PTR(status);
  972. }
  973. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  974. struct ib_udata *udata)
  975. {
  976. int status = 0;
  977. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  978. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  979. status = -EINVAL;
  980. return status;
  981. }
  982. ibcq->cqe = new_cnt;
  983. return status;
  984. }
  985. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  986. {
  987. int cqe_cnt;
  988. int valid_count = 0;
  989. unsigned long flags;
  990. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  991. struct ocrdma_cqe *cqe = NULL;
  992. cqe = cq->va;
  993. cqe_cnt = cq->cqe_cnt;
  994. /* Last irq might have scheduled a polling thread
  995. * sync-up with it before hard flushing.
  996. */
  997. spin_lock_irqsave(&cq->cq_lock, flags);
  998. while (cqe_cnt) {
  999. if (is_cqe_valid(cq, cqe))
  1000. valid_count++;
  1001. cqe++;
  1002. cqe_cnt--;
  1003. }
  1004. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  1005. spin_unlock_irqrestore(&cq->cq_lock, flags);
  1006. }
  1007. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  1008. {
  1009. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  1010. struct ocrdma_eq *eq = NULL;
  1011. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  1012. int pdid = 0;
  1013. u32 irq, indx;
  1014. dev->cq_tbl[cq->id] = NULL;
  1015. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  1016. if (indx == -EINVAL)
  1017. BUG();
  1018. eq = &dev->eq_tbl[indx];
  1019. irq = ocrdma_get_irq(dev, eq);
  1020. synchronize_irq(irq);
  1021. ocrdma_flush_cq(cq);
  1022. (void)ocrdma_mbx_destroy_cq(dev, cq);
  1023. if (cq->ucontext) {
  1024. pdid = cq->ucontext->cntxt_pd->id;
  1025. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  1026. PAGE_ALIGN(cq->len));
  1027. ocrdma_del_mmap(cq->ucontext,
  1028. ocrdma_get_db_addr(dev, pdid),
  1029. dev->nic_info.db_page_size);
  1030. }
  1031. kfree(cq);
  1032. return 0;
  1033. }
  1034. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1035. {
  1036. int status = -EINVAL;
  1037. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  1038. dev->qp_tbl[qp->id] = qp;
  1039. status = 0;
  1040. }
  1041. return status;
  1042. }
  1043. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1044. {
  1045. dev->qp_tbl[qp->id] = NULL;
  1046. }
  1047. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  1048. struct ib_qp_init_attr *attrs)
  1049. {
  1050. if ((attrs->qp_type != IB_QPT_GSI) &&
  1051. (attrs->qp_type != IB_QPT_RC) &&
  1052. (attrs->qp_type != IB_QPT_UC) &&
  1053. (attrs->qp_type != IB_QPT_UD)) {
  1054. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  1055. __func__, dev->id, attrs->qp_type);
  1056. return -EINVAL;
  1057. }
  1058. /* Skip the check for QP1 to support CM size of 128 */
  1059. if ((attrs->qp_type != IB_QPT_GSI) &&
  1060. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  1061. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  1062. __func__, dev->id, attrs->cap.max_send_wr);
  1063. pr_err("%s(%d) supported send_wr=0x%x\n",
  1064. __func__, dev->id, dev->attr.max_wqe);
  1065. return -EINVAL;
  1066. }
  1067. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  1068. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  1069. __func__, dev->id, attrs->cap.max_recv_wr);
  1070. pr_err("%s(%d) supported recv_wr=0x%x\n",
  1071. __func__, dev->id, dev->attr.max_rqe);
  1072. return -EINVAL;
  1073. }
  1074. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  1075. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  1076. __func__, dev->id, attrs->cap.max_inline_data);
  1077. pr_err("%s(%d) supported inline data size=0x%x\n",
  1078. __func__, dev->id, dev->attr.max_inline_data);
  1079. return -EINVAL;
  1080. }
  1081. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  1082. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  1083. __func__, dev->id, attrs->cap.max_send_sge);
  1084. pr_err("%s(%d) supported send_sge=0x%x\n",
  1085. __func__, dev->id, dev->attr.max_send_sge);
  1086. return -EINVAL;
  1087. }
  1088. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  1089. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  1090. __func__, dev->id, attrs->cap.max_recv_sge);
  1091. pr_err("%s(%d) supported recv_sge=0x%x\n",
  1092. __func__, dev->id, dev->attr.max_recv_sge);
  1093. return -EINVAL;
  1094. }
  1095. /* unprivileged user space cannot create special QP */
  1096. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  1097. pr_err
  1098. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  1099. __func__, dev->id, attrs->qp_type);
  1100. return -EINVAL;
  1101. }
  1102. /* allow creating only one GSI type of QP */
  1103. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  1104. pr_err("%s(%d) GSI special QPs already created.\n",
  1105. __func__, dev->id);
  1106. return -EINVAL;
  1107. }
  1108. /* verify consumer QPs are not trying to use GSI QP's CQ */
  1109. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  1110. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  1111. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  1112. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  1113. __func__, dev->id);
  1114. return -EINVAL;
  1115. }
  1116. }
  1117. return 0;
  1118. }
  1119. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  1120. struct ib_udata *udata, int dpp_offset,
  1121. int dpp_credit_lmt, int srq)
  1122. {
  1123. int status = 0;
  1124. u64 usr_db;
  1125. struct ocrdma_create_qp_uresp uresp;
  1126. struct ocrdma_pd *pd = qp->pd;
  1127. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  1128. memset(&uresp, 0, sizeof(uresp));
  1129. usr_db = dev->nic_info.unmapped_db +
  1130. (pd->id * dev->nic_info.db_page_size);
  1131. uresp.qp_id = qp->id;
  1132. uresp.sq_dbid = qp->sq.dbid;
  1133. uresp.num_sq_pages = 1;
  1134. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  1135. uresp.sq_page_addr[0] = virt_to_phys(qp->sq.va);
  1136. uresp.num_wqe_allocated = qp->sq.max_cnt;
  1137. if (!srq) {
  1138. uresp.rq_dbid = qp->rq.dbid;
  1139. uresp.num_rq_pages = 1;
  1140. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  1141. uresp.rq_page_addr[0] = virt_to_phys(qp->rq.va);
  1142. uresp.num_rqe_allocated = qp->rq.max_cnt;
  1143. }
  1144. uresp.db_page_addr = usr_db;
  1145. uresp.db_page_size = dev->nic_info.db_page_size;
  1146. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  1147. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1148. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  1149. if (qp->dpp_enabled) {
  1150. uresp.dpp_credit = dpp_credit_lmt;
  1151. uresp.dpp_offset = dpp_offset;
  1152. }
  1153. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1154. if (status) {
  1155. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  1156. goto err;
  1157. }
  1158. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  1159. uresp.sq_page_size);
  1160. if (status)
  1161. goto err;
  1162. if (!srq) {
  1163. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1164. uresp.rq_page_size);
  1165. if (status)
  1166. goto rq_map_err;
  1167. }
  1168. return status;
  1169. rq_map_err:
  1170. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1171. err:
  1172. return status;
  1173. }
  1174. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1175. struct ocrdma_pd *pd)
  1176. {
  1177. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1178. qp->sq_db = dev->nic_info.db +
  1179. (pd->id * dev->nic_info.db_page_size) +
  1180. OCRDMA_DB_GEN2_SQ_OFFSET;
  1181. qp->rq_db = dev->nic_info.db +
  1182. (pd->id * dev->nic_info.db_page_size) +
  1183. OCRDMA_DB_GEN2_RQ_OFFSET;
  1184. } else {
  1185. qp->sq_db = dev->nic_info.db +
  1186. (pd->id * dev->nic_info.db_page_size) +
  1187. OCRDMA_DB_SQ_OFFSET;
  1188. qp->rq_db = dev->nic_info.db +
  1189. (pd->id * dev->nic_info.db_page_size) +
  1190. OCRDMA_DB_RQ_OFFSET;
  1191. }
  1192. }
  1193. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1194. {
  1195. qp->wqe_wr_id_tbl =
  1196. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1197. GFP_KERNEL);
  1198. if (qp->wqe_wr_id_tbl == NULL)
  1199. return -ENOMEM;
  1200. qp->rqe_wr_id_tbl =
  1201. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1202. if (qp->rqe_wr_id_tbl == NULL)
  1203. return -ENOMEM;
  1204. return 0;
  1205. }
  1206. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1207. struct ocrdma_pd *pd,
  1208. struct ib_qp_init_attr *attrs)
  1209. {
  1210. qp->pd = pd;
  1211. spin_lock_init(&qp->q_lock);
  1212. INIT_LIST_HEAD(&qp->sq_entry);
  1213. INIT_LIST_HEAD(&qp->rq_entry);
  1214. qp->qp_type = attrs->qp_type;
  1215. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1216. qp->max_inline_data = attrs->cap.max_inline_data;
  1217. qp->sq.max_sges = attrs->cap.max_send_sge;
  1218. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1219. qp->state = OCRDMA_QPS_RST;
  1220. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1221. }
  1222. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1223. struct ib_qp_init_attr *attrs)
  1224. {
  1225. if (attrs->qp_type == IB_QPT_GSI) {
  1226. dev->gsi_qp_created = 1;
  1227. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1228. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1229. }
  1230. }
  1231. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1232. struct ib_qp_init_attr *attrs,
  1233. struct ib_udata *udata)
  1234. {
  1235. int status;
  1236. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1237. struct ocrdma_qp *qp;
  1238. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1239. struct ocrdma_create_qp_ureq ureq;
  1240. u16 dpp_credit_lmt, dpp_offset;
  1241. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1242. if (status)
  1243. goto gen_err;
  1244. memset(&ureq, 0, sizeof(ureq));
  1245. if (udata) {
  1246. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1247. return ERR_PTR(-EFAULT);
  1248. }
  1249. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1250. if (!qp) {
  1251. status = -ENOMEM;
  1252. goto gen_err;
  1253. }
  1254. ocrdma_set_qp_init_params(qp, pd, attrs);
  1255. if (udata == NULL)
  1256. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1257. OCRDMA_QP_FAST_REG);
  1258. mutex_lock(&dev->dev_lock);
  1259. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1260. ureq.dpp_cq_id,
  1261. &dpp_offset, &dpp_credit_lmt);
  1262. if (status)
  1263. goto mbx_err;
  1264. /* user space QP's wr_id table are managed in library */
  1265. if (udata == NULL) {
  1266. status = ocrdma_alloc_wr_id_tbl(qp);
  1267. if (status)
  1268. goto map_err;
  1269. }
  1270. status = ocrdma_add_qpn_map(dev, qp);
  1271. if (status)
  1272. goto map_err;
  1273. ocrdma_set_qp_db(dev, qp, pd);
  1274. if (udata) {
  1275. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1276. dpp_credit_lmt,
  1277. (attrs->srq != NULL));
  1278. if (status)
  1279. goto cpy_err;
  1280. }
  1281. ocrdma_store_gsi_qp_cq(dev, attrs);
  1282. qp->ibqp.qp_num = qp->id;
  1283. mutex_unlock(&dev->dev_lock);
  1284. return &qp->ibqp;
  1285. cpy_err:
  1286. ocrdma_del_qpn_map(dev, qp);
  1287. map_err:
  1288. ocrdma_mbx_destroy_qp(dev, qp);
  1289. mbx_err:
  1290. mutex_unlock(&dev->dev_lock);
  1291. kfree(qp->wqe_wr_id_tbl);
  1292. kfree(qp->rqe_wr_id_tbl);
  1293. kfree(qp);
  1294. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1295. gen_err:
  1296. return ERR_PTR(status);
  1297. }
  1298. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1299. int attr_mask)
  1300. {
  1301. int status = 0;
  1302. struct ocrdma_qp *qp;
  1303. struct ocrdma_dev *dev;
  1304. enum ib_qp_state old_qps;
  1305. qp = get_ocrdma_qp(ibqp);
  1306. dev = get_ocrdma_dev(ibqp->device);
  1307. if (attr_mask & IB_QP_STATE)
  1308. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1309. /* if new and previous states are same hw doesn't need to
  1310. * know about it.
  1311. */
  1312. if (status < 0)
  1313. return status;
  1314. status = ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1315. return status;
  1316. }
  1317. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1318. int attr_mask, struct ib_udata *udata)
  1319. {
  1320. unsigned long flags;
  1321. int status = -EINVAL;
  1322. struct ocrdma_qp *qp;
  1323. struct ocrdma_dev *dev;
  1324. enum ib_qp_state old_qps, new_qps;
  1325. qp = get_ocrdma_qp(ibqp);
  1326. dev = get_ocrdma_dev(ibqp->device);
  1327. /* syncronize with multiple context trying to change, retrive qps */
  1328. mutex_lock(&dev->dev_lock);
  1329. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1330. spin_lock_irqsave(&qp->q_lock, flags);
  1331. old_qps = get_ibqp_state(qp->state);
  1332. if (attr_mask & IB_QP_STATE)
  1333. new_qps = attr->qp_state;
  1334. else
  1335. new_qps = old_qps;
  1336. spin_unlock_irqrestore(&qp->q_lock, flags);
  1337. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask,
  1338. IB_LINK_LAYER_ETHERNET)) {
  1339. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1340. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1341. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1342. old_qps, new_qps);
  1343. goto param_err;
  1344. }
  1345. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1346. if (status > 0)
  1347. status = 0;
  1348. param_err:
  1349. mutex_unlock(&dev->dev_lock);
  1350. return status;
  1351. }
  1352. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1353. {
  1354. switch (mtu) {
  1355. case 256:
  1356. return IB_MTU_256;
  1357. case 512:
  1358. return IB_MTU_512;
  1359. case 1024:
  1360. return IB_MTU_1024;
  1361. case 2048:
  1362. return IB_MTU_2048;
  1363. case 4096:
  1364. return IB_MTU_4096;
  1365. default:
  1366. return IB_MTU_1024;
  1367. }
  1368. }
  1369. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1370. {
  1371. int ib_qp_acc_flags = 0;
  1372. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1373. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1374. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1375. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1376. return ib_qp_acc_flags;
  1377. }
  1378. int ocrdma_query_qp(struct ib_qp *ibqp,
  1379. struct ib_qp_attr *qp_attr,
  1380. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1381. {
  1382. int status;
  1383. u32 qp_state;
  1384. struct ocrdma_qp_params params;
  1385. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1386. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1387. memset(&params, 0, sizeof(params));
  1388. mutex_lock(&dev->dev_lock);
  1389. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1390. mutex_unlock(&dev->dev_lock);
  1391. if (status)
  1392. goto mbx_err;
  1393. if (qp->qp_type == IB_QPT_UD)
  1394. qp_attr->qkey = params.qkey;
  1395. qp_attr->path_mtu =
  1396. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1397. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1398. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1399. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1400. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1401. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1402. qp_attr->dest_qp_num =
  1403. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1404. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1405. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1406. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1407. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1408. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1409. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1410. qp_init_attr->cap = qp_attr->cap;
  1411. memcpy(&qp_attr->ah_attr.grh.dgid, &params.dgid[0],
  1412. sizeof(params.dgid));
  1413. qp_attr->ah_attr.grh.flow_label = params.rnt_rc_sl_fl &
  1414. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK;
  1415. qp_attr->ah_attr.grh.sgid_index = qp->sgid_idx;
  1416. qp_attr->ah_attr.grh.hop_limit = (params.hop_lmt_rq_psn &
  1417. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1418. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT;
  1419. qp_attr->ah_attr.grh.traffic_class = (params.tclass_sq_psn &
  1420. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1421. OCRDMA_QP_PARAMS_TCLASS_SHIFT;
  1422. qp_attr->ah_attr.ah_flags = IB_AH_GRH;
  1423. qp_attr->ah_attr.port_num = 1;
  1424. qp_attr->ah_attr.sl = (params.rnt_rc_sl_fl &
  1425. OCRDMA_QP_PARAMS_SL_MASK) >>
  1426. OCRDMA_QP_PARAMS_SL_SHIFT;
  1427. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1428. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1429. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1430. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1431. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1432. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1433. qp_attr->retry_cnt =
  1434. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1435. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1436. qp_attr->min_rnr_timer = 0;
  1437. qp_attr->pkey_index = 0;
  1438. qp_attr->port_num = 1;
  1439. qp_attr->ah_attr.src_path_bits = 0;
  1440. qp_attr->ah_attr.static_rate = 0;
  1441. qp_attr->alt_pkey_index = 0;
  1442. qp_attr->alt_port_num = 0;
  1443. qp_attr->alt_timeout = 0;
  1444. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1445. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1446. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1447. qp_attr->qp_state = get_ibqp_state(qp_state);
  1448. qp_attr->cur_qp_state = qp_attr->qp_state;
  1449. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1450. qp_attr->max_dest_rd_atomic =
  1451. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1452. qp_attr->max_rd_atomic =
  1453. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1454. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1455. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1456. /* Sync driver QP state with FW */
  1457. ocrdma_qp_state_change(qp, qp_attr->qp_state, NULL);
  1458. mbx_err:
  1459. return status;
  1460. }
  1461. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, unsigned int idx)
  1462. {
  1463. unsigned int i = idx / 32;
  1464. u32 mask = (1U << (idx % 32));
  1465. srq->idx_bit_fields[i] ^= mask;
  1466. }
  1467. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1468. {
  1469. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1470. }
  1471. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1472. {
  1473. return (qp->sq.tail == qp->sq.head);
  1474. }
  1475. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1476. {
  1477. return (qp->rq.tail == qp->rq.head);
  1478. }
  1479. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1480. {
  1481. return q->va + (q->head * q->entry_size);
  1482. }
  1483. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1484. u32 idx)
  1485. {
  1486. return q->va + (idx * q->entry_size);
  1487. }
  1488. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1489. {
  1490. q->head = (q->head + 1) & q->max_wqe_idx;
  1491. }
  1492. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1493. {
  1494. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1495. }
  1496. /* discard the cqe for a given QP */
  1497. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1498. {
  1499. unsigned long cq_flags;
  1500. unsigned long flags;
  1501. int discard_cnt = 0;
  1502. u32 cur_getp, stop_getp;
  1503. struct ocrdma_cqe *cqe;
  1504. u32 qpn = 0, wqe_idx = 0;
  1505. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1506. /* traverse through the CQEs in the hw CQ,
  1507. * find the matching CQE for a given qp,
  1508. * mark the matching one discarded by clearing qpn.
  1509. * ring the doorbell in the poll_cq() as
  1510. * we don't complete out of order cqe.
  1511. */
  1512. cur_getp = cq->getp;
  1513. /* find upto when do we reap the cq. */
  1514. stop_getp = cur_getp;
  1515. do {
  1516. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1517. break;
  1518. cqe = cq->va + cur_getp;
  1519. /* if (a) done reaping whole hw cq, or
  1520. * (b) qp_xq becomes empty.
  1521. * then exit
  1522. */
  1523. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1524. /* if previously discarded cqe found, skip that too. */
  1525. /* check for matching qp */
  1526. if (qpn == 0 || qpn != qp->id)
  1527. goto skip_cqe;
  1528. if (is_cqe_for_sq(cqe)) {
  1529. ocrdma_hwq_inc_tail(&qp->sq);
  1530. } else {
  1531. if (qp->srq) {
  1532. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1533. OCRDMA_CQE_BUFTAG_SHIFT) &
  1534. qp->srq->rq.max_wqe_idx;
  1535. if (wqe_idx < 1)
  1536. BUG();
  1537. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1538. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1539. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1540. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1541. } else {
  1542. ocrdma_hwq_inc_tail(&qp->rq);
  1543. }
  1544. }
  1545. /* mark cqe discarded so that it is not picked up later
  1546. * in the poll_cq().
  1547. */
  1548. discard_cnt += 1;
  1549. cqe->cmn.qpn = 0;
  1550. skip_cqe:
  1551. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1552. } while (cur_getp != stop_getp);
  1553. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1554. }
  1555. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1556. {
  1557. int found = false;
  1558. unsigned long flags;
  1559. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1560. /* sync with any active CQ poll */
  1561. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1562. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1563. if (found)
  1564. list_del(&qp->sq_entry);
  1565. if (!qp->srq) {
  1566. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1567. if (found)
  1568. list_del(&qp->rq_entry);
  1569. }
  1570. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1571. }
  1572. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1573. {
  1574. struct ocrdma_pd *pd;
  1575. struct ocrdma_qp *qp;
  1576. struct ocrdma_dev *dev;
  1577. struct ib_qp_attr attrs;
  1578. int attr_mask;
  1579. unsigned long flags;
  1580. qp = get_ocrdma_qp(ibqp);
  1581. dev = get_ocrdma_dev(ibqp->device);
  1582. pd = qp->pd;
  1583. /* change the QP state to ERROR */
  1584. if (qp->state != OCRDMA_QPS_RST) {
  1585. attrs.qp_state = IB_QPS_ERR;
  1586. attr_mask = IB_QP_STATE;
  1587. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1588. }
  1589. /* ensure that CQEs for newly created QP (whose id may be same with
  1590. * one which just getting destroyed are same), dont get
  1591. * discarded until the old CQEs are discarded.
  1592. */
  1593. mutex_lock(&dev->dev_lock);
  1594. (void) ocrdma_mbx_destroy_qp(dev, qp);
  1595. /*
  1596. * acquire CQ lock while destroy is in progress, in order to
  1597. * protect against proessing in-flight CQEs for this QP.
  1598. */
  1599. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1600. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1601. spin_lock(&qp->rq_cq->cq_lock);
  1602. ocrdma_del_qpn_map(dev, qp);
  1603. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1604. spin_unlock(&qp->rq_cq->cq_lock);
  1605. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1606. if (!pd->uctx) {
  1607. ocrdma_discard_cqes(qp, qp->sq_cq);
  1608. ocrdma_discard_cqes(qp, qp->rq_cq);
  1609. }
  1610. mutex_unlock(&dev->dev_lock);
  1611. if (pd->uctx) {
  1612. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1613. PAGE_ALIGN(qp->sq.len));
  1614. if (!qp->srq)
  1615. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1616. PAGE_ALIGN(qp->rq.len));
  1617. }
  1618. ocrdma_del_flush_qp(qp);
  1619. kfree(qp->wqe_wr_id_tbl);
  1620. kfree(qp->rqe_wr_id_tbl);
  1621. kfree(qp);
  1622. return 0;
  1623. }
  1624. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1625. struct ib_udata *udata)
  1626. {
  1627. int status;
  1628. struct ocrdma_create_srq_uresp uresp;
  1629. memset(&uresp, 0, sizeof(uresp));
  1630. uresp.rq_dbid = srq->rq.dbid;
  1631. uresp.num_rq_pages = 1;
  1632. uresp.rq_page_addr[0] = virt_to_phys(srq->rq.va);
  1633. uresp.rq_page_size = srq->rq.len;
  1634. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1635. (srq->pd->id * dev->nic_info.db_page_size);
  1636. uresp.db_page_size = dev->nic_info.db_page_size;
  1637. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1638. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1639. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1640. uresp.db_shift = 24;
  1641. } else {
  1642. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1643. uresp.db_shift = 16;
  1644. }
  1645. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1646. if (status)
  1647. return status;
  1648. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1649. uresp.rq_page_size);
  1650. if (status)
  1651. return status;
  1652. return status;
  1653. }
  1654. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1655. struct ib_srq_init_attr *init_attr,
  1656. struct ib_udata *udata)
  1657. {
  1658. int status = -ENOMEM;
  1659. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1660. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1661. struct ocrdma_srq *srq;
  1662. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1663. return ERR_PTR(-EINVAL);
  1664. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1665. return ERR_PTR(-EINVAL);
  1666. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1667. if (!srq)
  1668. return ERR_PTR(status);
  1669. spin_lock_init(&srq->q_lock);
  1670. srq->pd = pd;
  1671. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1672. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1673. if (status)
  1674. goto err;
  1675. if (udata == NULL) {
  1676. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1677. GFP_KERNEL);
  1678. if (srq->rqe_wr_id_tbl == NULL)
  1679. goto arm_err;
  1680. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1681. (srq->rq.max_cnt % 32 ? 1 : 0);
  1682. srq->idx_bit_fields =
  1683. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1684. if (srq->idx_bit_fields == NULL)
  1685. goto arm_err;
  1686. memset(srq->idx_bit_fields, 0xff,
  1687. srq->bit_fields_len * sizeof(u32));
  1688. }
  1689. if (init_attr->attr.srq_limit) {
  1690. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1691. if (status)
  1692. goto arm_err;
  1693. }
  1694. if (udata) {
  1695. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1696. if (status)
  1697. goto arm_err;
  1698. }
  1699. return &srq->ibsrq;
  1700. arm_err:
  1701. ocrdma_mbx_destroy_srq(dev, srq);
  1702. err:
  1703. kfree(srq->rqe_wr_id_tbl);
  1704. kfree(srq->idx_bit_fields);
  1705. kfree(srq);
  1706. return ERR_PTR(status);
  1707. }
  1708. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1709. struct ib_srq_attr *srq_attr,
  1710. enum ib_srq_attr_mask srq_attr_mask,
  1711. struct ib_udata *udata)
  1712. {
  1713. int status = 0;
  1714. struct ocrdma_srq *srq;
  1715. srq = get_ocrdma_srq(ibsrq);
  1716. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1717. status = -EINVAL;
  1718. else
  1719. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1720. return status;
  1721. }
  1722. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1723. {
  1724. int status;
  1725. struct ocrdma_srq *srq;
  1726. srq = get_ocrdma_srq(ibsrq);
  1727. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1728. return status;
  1729. }
  1730. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1731. {
  1732. int status;
  1733. struct ocrdma_srq *srq;
  1734. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1735. srq = get_ocrdma_srq(ibsrq);
  1736. status = ocrdma_mbx_destroy_srq(dev, srq);
  1737. if (srq->pd->uctx)
  1738. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1739. PAGE_ALIGN(srq->rq.len));
  1740. kfree(srq->idx_bit_fields);
  1741. kfree(srq->rqe_wr_id_tbl);
  1742. kfree(srq);
  1743. return status;
  1744. }
  1745. /* unprivileged verbs and their support functions. */
  1746. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1747. struct ocrdma_hdr_wqe *hdr,
  1748. struct ib_send_wr *wr)
  1749. {
  1750. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1751. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1752. struct ocrdma_ah *ah = get_ocrdma_ah(wr->wr.ud.ah);
  1753. ud_hdr->rsvd_dest_qpn = wr->wr.ud.remote_qpn;
  1754. if (qp->qp_type == IB_QPT_GSI)
  1755. ud_hdr->qkey = qp->qkey;
  1756. else
  1757. ud_hdr->qkey = wr->wr.ud.remote_qkey;
  1758. ud_hdr->rsvd_ahid = ah->id;
  1759. if (ah->av->valid & OCRDMA_AV_VLAN_VALID)
  1760. hdr->cw |= (OCRDMA_FLAG_AH_VLAN_PR << OCRDMA_WQE_FLAGS_SHIFT);
  1761. }
  1762. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1763. struct ocrdma_sge *sge, int num_sge,
  1764. struct ib_sge *sg_list)
  1765. {
  1766. int i;
  1767. for (i = 0; i < num_sge; i++) {
  1768. sge[i].lrkey = sg_list[i].lkey;
  1769. sge[i].addr_lo = sg_list[i].addr;
  1770. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1771. sge[i].len = sg_list[i].length;
  1772. hdr->total_len += sg_list[i].length;
  1773. }
  1774. if (num_sge == 0)
  1775. memset(sge, 0, sizeof(*sge));
  1776. }
  1777. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1778. {
  1779. uint32_t total_len = 0, i;
  1780. for (i = 0; i < num_sge; i++)
  1781. total_len += sg_list[i].length;
  1782. return total_len;
  1783. }
  1784. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1785. struct ocrdma_hdr_wqe *hdr,
  1786. struct ocrdma_sge *sge,
  1787. struct ib_send_wr *wr, u32 wqe_size)
  1788. {
  1789. int i;
  1790. char *dpp_addr;
  1791. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1792. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1793. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1794. pr_err("%s() supported_len=0x%x,\n"
  1795. " unsupported len req=0x%x\n", __func__,
  1796. qp->max_inline_data, hdr->total_len);
  1797. return -EINVAL;
  1798. }
  1799. dpp_addr = (char *)sge;
  1800. for (i = 0; i < wr->num_sge; i++) {
  1801. memcpy(dpp_addr,
  1802. (void *)(unsigned long)wr->sg_list[i].addr,
  1803. wr->sg_list[i].length);
  1804. dpp_addr += wr->sg_list[i].length;
  1805. }
  1806. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1807. if (0 == hdr->total_len)
  1808. wqe_size += sizeof(struct ocrdma_sge);
  1809. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1810. } else {
  1811. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1812. if (wr->num_sge)
  1813. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1814. else
  1815. wqe_size += sizeof(struct ocrdma_sge);
  1816. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1817. }
  1818. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1819. return 0;
  1820. }
  1821. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1822. struct ib_send_wr *wr)
  1823. {
  1824. int status;
  1825. struct ocrdma_sge *sge;
  1826. u32 wqe_size = sizeof(*hdr);
  1827. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1828. ocrdma_build_ud_hdr(qp, hdr, wr);
  1829. sge = (struct ocrdma_sge *)(hdr + 2);
  1830. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1831. } else {
  1832. sge = (struct ocrdma_sge *)(hdr + 1);
  1833. }
  1834. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1835. return status;
  1836. }
  1837. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1838. struct ib_send_wr *wr)
  1839. {
  1840. int status;
  1841. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1842. struct ocrdma_sge *sge = ext_rw + 1;
  1843. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1844. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1845. if (status)
  1846. return status;
  1847. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1848. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1849. ext_rw->lrkey = wr->wr.rdma.rkey;
  1850. ext_rw->len = hdr->total_len;
  1851. return 0;
  1852. }
  1853. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1854. struct ib_send_wr *wr)
  1855. {
  1856. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1857. struct ocrdma_sge *sge = ext_rw + 1;
  1858. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1859. sizeof(struct ocrdma_hdr_wqe);
  1860. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1861. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1862. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1863. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1864. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1865. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1866. ext_rw->lrkey = wr->wr.rdma.rkey;
  1867. ext_rw->len = hdr->total_len;
  1868. }
  1869. static void build_frmr_pbes(struct ib_send_wr *wr, struct ocrdma_pbl *pbl_tbl,
  1870. struct ocrdma_hw_mr *hwmr)
  1871. {
  1872. int i;
  1873. u64 buf_addr = 0;
  1874. int num_pbes;
  1875. struct ocrdma_pbe *pbe;
  1876. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1877. num_pbes = 0;
  1878. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  1879. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  1880. /* number of pbes can be more for one OS buf, when
  1881. * buffers are of different sizes.
  1882. * split the ib_buf to one or more pbes.
  1883. */
  1884. buf_addr = wr->wr.fast_reg.page_list->page_list[i];
  1885. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1886. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1887. num_pbes += 1;
  1888. pbe++;
  1889. /* if the pbl is full storing the pbes,
  1890. * move to next pbl.
  1891. */
  1892. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  1893. pbl_tbl++;
  1894. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1895. }
  1896. }
  1897. return;
  1898. }
  1899. static int get_encoded_page_size(int pg_sz)
  1900. {
  1901. /* Max size is 256M 4096 << 16 */
  1902. int i = 0;
  1903. for (; i < 17; i++)
  1904. if (pg_sz == (4096 << i))
  1905. break;
  1906. return i;
  1907. }
  1908. static int ocrdma_build_fr(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1909. struct ib_send_wr *wr)
  1910. {
  1911. u64 fbo;
  1912. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1913. struct ocrdma_mr *mr;
  1914. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1915. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1916. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1917. if (wr->wr.fast_reg.page_list_len > dev->attr.max_pages_per_frmr)
  1918. return -EINVAL;
  1919. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1920. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1921. if (wr->wr.fast_reg.page_list_len == 0)
  1922. BUG();
  1923. if (wr->wr.fast_reg.access_flags & IB_ACCESS_LOCAL_WRITE)
  1924. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1925. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_WRITE)
  1926. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1927. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_READ)
  1928. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1929. hdr->lkey = wr->wr.fast_reg.rkey;
  1930. hdr->total_len = wr->wr.fast_reg.length;
  1931. fbo = wr->wr.fast_reg.iova_start -
  1932. (wr->wr.fast_reg.page_list->page_list[0] & PAGE_MASK);
  1933. fast_reg->va_hi = upper_32_bits(wr->wr.fast_reg.iova_start);
  1934. fast_reg->va_lo = (u32) (wr->wr.fast_reg.iova_start & 0xffffffff);
  1935. fast_reg->fbo_hi = upper_32_bits(fbo);
  1936. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1937. fast_reg->num_sges = wr->wr.fast_reg.page_list_len;
  1938. fast_reg->size_sge =
  1939. get_encoded_page_size(1 << wr->wr.fast_reg.page_shift);
  1940. mr = (struct ocrdma_mr *) (unsigned long)
  1941. dev->stag_arr[(hdr->lkey >> 8) & (OCRDMA_MAX_STAG - 1)];
  1942. build_frmr_pbes(wr, mr->hwmr.pbl_table, &mr->hwmr);
  1943. return 0;
  1944. }
  1945. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1946. {
  1947. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1948. iowrite32(val, qp->sq_db);
  1949. }
  1950. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1951. struct ib_send_wr **bad_wr)
  1952. {
  1953. int status = 0;
  1954. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1955. struct ocrdma_hdr_wqe *hdr;
  1956. unsigned long flags;
  1957. spin_lock_irqsave(&qp->q_lock, flags);
  1958. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1959. spin_unlock_irqrestore(&qp->q_lock, flags);
  1960. *bad_wr = wr;
  1961. return -EINVAL;
  1962. }
  1963. while (wr) {
  1964. if (qp->qp_type == IB_QPT_UD &&
  1965. (wr->opcode != IB_WR_SEND &&
  1966. wr->opcode != IB_WR_SEND_WITH_IMM)) {
  1967. *bad_wr = wr;
  1968. status = -EINVAL;
  1969. break;
  1970. }
  1971. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1972. wr->num_sge > qp->sq.max_sges) {
  1973. *bad_wr = wr;
  1974. status = -ENOMEM;
  1975. break;
  1976. }
  1977. hdr = ocrdma_hwq_head(&qp->sq);
  1978. hdr->cw = 0;
  1979. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1980. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1981. if (wr->send_flags & IB_SEND_FENCE)
  1982. hdr->cw |=
  1983. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1984. if (wr->send_flags & IB_SEND_SOLICITED)
  1985. hdr->cw |=
  1986. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1987. hdr->total_len = 0;
  1988. switch (wr->opcode) {
  1989. case IB_WR_SEND_WITH_IMM:
  1990. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1991. hdr->immdt = ntohl(wr->ex.imm_data);
  1992. case IB_WR_SEND:
  1993. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1994. ocrdma_build_send(qp, hdr, wr);
  1995. break;
  1996. case IB_WR_SEND_WITH_INV:
  1997. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1998. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1999. hdr->lkey = wr->ex.invalidate_rkey;
  2000. status = ocrdma_build_send(qp, hdr, wr);
  2001. break;
  2002. case IB_WR_RDMA_WRITE_WITH_IMM:
  2003. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  2004. hdr->immdt = ntohl(wr->ex.imm_data);
  2005. case IB_WR_RDMA_WRITE:
  2006. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  2007. status = ocrdma_build_write(qp, hdr, wr);
  2008. break;
  2009. case IB_WR_RDMA_READ:
  2010. ocrdma_build_read(qp, hdr, wr);
  2011. break;
  2012. case IB_WR_LOCAL_INV:
  2013. hdr->cw |=
  2014. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  2015. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  2016. sizeof(struct ocrdma_sge)) /
  2017. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  2018. hdr->lkey = wr->ex.invalidate_rkey;
  2019. break;
  2020. case IB_WR_FAST_REG_MR:
  2021. status = ocrdma_build_fr(qp, hdr, wr);
  2022. break;
  2023. default:
  2024. status = -EINVAL;
  2025. break;
  2026. }
  2027. if (status) {
  2028. *bad_wr = wr;
  2029. break;
  2030. }
  2031. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  2032. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  2033. else
  2034. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  2035. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  2036. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  2037. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  2038. /* make sure wqe is written before adapter can access it */
  2039. wmb();
  2040. /* inform hw to start processing it */
  2041. ocrdma_ring_sq_db(qp);
  2042. /* update pointer, counter for next wr */
  2043. ocrdma_hwq_inc_head(&qp->sq);
  2044. wr = wr->next;
  2045. }
  2046. spin_unlock_irqrestore(&qp->q_lock, flags);
  2047. return status;
  2048. }
  2049. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  2050. {
  2051. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  2052. iowrite32(val, qp->rq_db);
  2053. }
  2054. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  2055. u16 tag)
  2056. {
  2057. u32 wqe_size = 0;
  2058. struct ocrdma_sge *sge;
  2059. if (wr->num_sge)
  2060. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  2061. else
  2062. wqe_size = sizeof(*sge) + sizeof(*rqe);
  2063. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  2064. OCRDMA_WQE_SIZE_SHIFT);
  2065. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  2066. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  2067. rqe->total_len = 0;
  2068. rqe->rsvd_tag = tag;
  2069. sge = (struct ocrdma_sge *)(rqe + 1);
  2070. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  2071. ocrdma_cpu_to_le32(rqe, wqe_size);
  2072. }
  2073. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  2074. struct ib_recv_wr **bad_wr)
  2075. {
  2076. int status = 0;
  2077. unsigned long flags;
  2078. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  2079. struct ocrdma_hdr_wqe *rqe;
  2080. spin_lock_irqsave(&qp->q_lock, flags);
  2081. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  2082. spin_unlock_irqrestore(&qp->q_lock, flags);
  2083. *bad_wr = wr;
  2084. return -EINVAL;
  2085. }
  2086. while (wr) {
  2087. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  2088. wr->num_sge > qp->rq.max_sges) {
  2089. *bad_wr = wr;
  2090. status = -ENOMEM;
  2091. break;
  2092. }
  2093. rqe = ocrdma_hwq_head(&qp->rq);
  2094. ocrdma_build_rqe(rqe, wr, 0);
  2095. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  2096. /* make sure rqe is written before adapter can access it */
  2097. wmb();
  2098. /* inform hw to start processing it */
  2099. ocrdma_ring_rq_db(qp);
  2100. /* update pointer, counter for next wr */
  2101. ocrdma_hwq_inc_head(&qp->rq);
  2102. wr = wr->next;
  2103. }
  2104. spin_unlock_irqrestore(&qp->q_lock, flags);
  2105. return status;
  2106. }
  2107. /* cqe for srq's rqe can potentially arrive out of order.
  2108. * index gives the entry in the shadow table where to store
  2109. * the wr_id. tag/index is returned in cqe to reference back
  2110. * for a given rqe.
  2111. */
  2112. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  2113. {
  2114. int row = 0;
  2115. int indx = 0;
  2116. for (row = 0; row < srq->bit_fields_len; row++) {
  2117. if (srq->idx_bit_fields[row]) {
  2118. indx = ffs(srq->idx_bit_fields[row]);
  2119. indx = (row * 32) + (indx - 1);
  2120. if (indx >= srq->rq.max_cnt)
  2121. BUG();
  2122. ocrdma_srq_toggle_bit(srq, indx);
  2123. break;
  2124. }
  2125. }
  2126. if (row == srq->bit_fields_len)
  2127. BUG();
  2128. return indx + 1; /* Use from index 1 */
  2129. }
  2130. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  2131. {
  2132. u32 val = srq->rq.dbid | (1 << 16);
  2133. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  2134. }
  2135. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  2136. struct ib_recv_wr **bad_wr)
  2137. {
  2138. int status = 0;
  2139. unsigned long flags;
  2140. struct ocrdma_srq *srq;
  2141. struct ocrdma_hdr_wqe *rqe;
  2142. u16 tag;
  2143. srq = get_ocrdma_srq(ibsrq);
  2144. spin_lock_irqsave(&srq->q_lock, flags);
  2145. while (wr) {
  2146. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  2147. wr->num_sge > srq->rq.max_sges) {
  2148. status = -ENOMEM;
  2149. *bad_wr = wr;
  2150. break;
  2151. }
  2152. tag = ocrdma_srq_get_idx(srq);
  2153. rqe = ocrdma_hwq_head(&srq->rq);
  2154. ocrdma_build_rqe(rqe, wr, tag);
  2155. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  2156. /* make sure rqe is written before adapter can perform DMA */
  2157. wmb();
  2158. /* inform hw to start processing it */
  2159. ocrdma_ring_srq_db(srq);
  2160. /* update pointer, counter for next wr */
  2161. ocrdma_hwq_inc_head(&srq->rq);
  2162. wr = wr->next;
  2163. }
  2164. spin_unlock_irqrestore(&srq->q_lock, flags);
  2165. return status;
  2166. }
  2167. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  2168. {
  2169. enum ib_wc_status ibwc_status;
  2170. switch (status) {
  2171. case OCRDMA_CQE_GENERAL_ERR:
  2172. ibwc_status = IB_WC_GENERAL_ERR;
  2173. break;
  2174. case OCRDMA_CQE_LOC_LEN_ERR:
  2175. ibwc_status = IB_WC_LOC_LEN_ERR;
  2176. break;
  2177. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2178. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2179. break;
  2180. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2181. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2182. break;
  2183. case OCRDMA_CQE_LOC_PROT_ERR:
  2184. ibwc_status = IB_WC_LOC_PROT_ERR;
  2185. break;
  2186. case OCRDMA_CQE_WR_FLUSH_ERR:
  2187. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2188. break;
  2189. case OCRDMA_CQE_MW_BIND_ERR:
  2190. ibwc_status = IB_WC_MW_BIND_ERR;
  2191. break;
  2192. case OCRDMA_CQE_BAD_RESP_ERR:
  2193. ibwc_status = IB_WC_BAD_RESP_ERR;
  2194. break;
  2195. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2196. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2197. break;
  2198. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2199. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2200. break;
  2201. case OCRDMA_CQE_REM_ACCESS_ERR:
  2202. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2203. break;
  2204. case OCRDMA_CQE_REM_OP_ERR:
  2205. ibwc_status = IB_WC_REM_OP_ERR;
  2206. break;
  2207. case OCRDMA_CQE_RETRY_EXC_ERR:
  2208. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2209. break;
  2210. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2211. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2212. break;
  2213. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2214. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2215. break;
  2216. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2217. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2218. break;
  2219. case OCRDMA_CQE_REM_ABORT_ERR:
  2220. ibwc_status = IB_WC_REM_ABORT_ERR;
  2221. break;
  2222. case OCRDMA_CQE_INV_EECN_ERR:
  2223. ibwc_status = IB_WC_INV_EECN_ERR;
  2224. break;
  2225. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2226. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2227. break;
  2228. case OCRDMA_CQE_FATAL_ERR:
  2229. ibwc_status = IB_WC_FATAL_ERR;
  2230. break;
  2231. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2232. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2233. break;
  2234. default:
  2235. ibwc_status = IB_WC_GENERAL_ERR;
  2236. break;
  2237. }
  2238. return ibwc_status;
  2239. }
  2240. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2241. u32 wqe_idx)
  2242. {
  2243. struct ocrdma_hdr_wqe *hdr;
  2244. struct ocrdma_sge *rw;
  2245. int opcode;
  2246. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2247. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2248. /* Undo the hdr->cw swap */
  2249. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2250. switch (opcode) {
  2251. case OCRDMA_WRITE:
  2252. ibwc->opcode = IB_WC_RDMA_WRITE;
  2253. break;
  2254. case OCRDMA_READ:
  2255. rw = (struct ocrdma_sge *)(hdr + 1);
  2256. ibwc->opcode = IB_WC_RDMA_READ;
  2257. ibwc->byte_len = rw->len;
  2258. break;
  2259. case OCRDMA_SEND:
  2260. ibwc->opcode = IB_WC_SEND;
  2261. break;
  2262. case OCRDMA_FR_MR:
  2263. ibwc->opcode = IB_WC_FAST_REG_MR;
  2264. break;
  2265. case OCRDMA_LKEY_INV:
  2266. ibwc->opcode = IB_WC_LOCAL_INV;
  2267. break;
  2268. default:
  2269. ibwc->status = IB_WC_GENERAL_ERR;
  2270. pr_err("%s() invalid opcode received = 0x%x\n",
  2271. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2272. break;
  2273. }
  2274. }
  2275. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2276. struct ocrdma_cqe *cqe)
  2277. {
  2278. if (is_cqe_for_sq(cqe)) {
  2279. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2280. cqe->flags_status_srcqpn) &
  2281. ~OCRDMA_CQE_STATUS_MASK);
  2282. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2283. cqe->flags_status_srcqpn) |
  2284. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2285. OCRDMA_CQE_STATUS_SHIFT));
  2286. } else {
  2287. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2288. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2289. cqe->flags_status_srcqpn) &
  2290. ~OCRDMA_CQE_UD_STATUS_MASK);
  2291. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2292. cqe->flags_status_srcqpn) |
  2293. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2294. OCRDMA_CQE_UD_STATUS_SHIFT));
  2295. } else {
  2296. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2297. cqe->flags_status_srcqpn) &
  2298. ~OCRDMA_CQE_STATUS_MASK);
  2299. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2300. cqe->flags_status_srcqpn) |
  2301. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2302. OCRDMA_CQE_STATUS_SHIFT));
  2303. }
  2304. }
  2305. }
  2306. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2307. struct ocrdma_qp *qp, int status)
  2308. {
  2309. bool expand = false;
  2310. ibwc->byte_len = 0;
  2311. ibwc->qp = &qp->ibqp;
  2312. ibwc->status = ocrdma_to_ibwc_err(status);
  2313. ocrdma_flush_qp(qp);
  2314. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2315. /* if wqe/rqe pending for which cqe needs to be returned,
  2316. * trigger inflating it.
  2317. */
  2318. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2319. expand = true;
  2320. ocrdma_set_cqe_status_flushed(qp, cqe);
  2321. }
  2322. return expand;
  2323. }
  2324. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2325. struct ocrdma_qp *qp, int status)
  2326. {
  2327. ibwc->opcode = IB_WC_RECV;
  2328. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2329. ocrdma_hwq_inc_tail(&qp->rq);
  2330. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2331. }
  2332. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2333. struct ocrdma_qp *qp, int status)
  2334. {
  2335. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2336. ocrdma_hwq_inc_tail(&qp->sq);
  2337. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2338. }
  2339. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2340. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2341. bool *polled, bool *stop)
  2342. {
  2343. bool expand;
  2344. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2345. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2346. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2347. if (status < OCRDMA_MAX_CQE_ERR)
  2348. atomic_inc(&dev->cqe_err_stats[status]);
  2349. /* when hw sq is empty, but rq is not empty, so we continue
  2350. * to keep the cqe in order to get the cq event again.
  2351. */
  2352. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2353. /* when cq for rq and sq is same, it is safe to return
  2354. * flush cqe for RQEs.
  2355. */
  2356. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2357. *polled = true;
  2358. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2359. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2360. } else {
  2361. /* stop processing further cqe as this cqe is used for
  2362. * triggering cq event on buddy cq of RQ.
  2363. * When QP is destroyed, this cqe will be removed
  2364. * from the cq's hardware q.
  2365. */
  2366. *polled = false;
  2367. *stop = true;
  2368. expand = false;
  2369. }
  2370. } else if (is_hw_sq_empty(qp)) {
  2371. /* Do nothing */
  2372. expand = false;
  2373. *polled = false;
  2374. *stop = false;
  2375. } else {
  2376. *polled = true;
  2377. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2378. }
  2379. return expand;
  2380. }
  2381. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2382. struct ocrdma_cqe *cqe,
  2383. struct ib_wc *ibwc, bool *polled)
  2384. {
  2385. bool expand = false;
  2386. int tail = qp->sq.tail;
  2387. u32 wqe_idx;
  2388. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2389. *polled = false; /* WC cannot be consumed yet */
  2390. } else {
  2391. ibwc->status = IB_WC_SUCCESS;
  2392. ibwc->wc_flags = 0;
  2393. ibwc->qp = &qp->ibqp;
  2394. ocrdma_update_wc(qp, ibwc, tail);
  2395. *polled = true;
  2396. }
  2397. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2398. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2399. if (tail != wqe_idx)
  2400. expand = true; /* Coalesced CQE can't be consumed yet */
  2401. ocrdma_hwq_inc_tail(&qp->sq);
  2402. return expand;
  2403. }
  2404. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2405. struct ib_wc *ibwc, bool *polled, bool *stop)
  2406. {
  2407. int status;
  2408. bool expand;
  2409. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2410. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2411. if (status == OCRDMA_CQE_SUCCESS)
  2412. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2413. else
  2414. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2415. return expand;
  2416. }
  2417. static int ocrdma_update_ud_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe)
  2418. {
  2419. int status;
  2420. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2421. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2422. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2423. OCRDMA_CQE_SRCQP_MASK;
  2424. ibwc->pkey_index = le32_to_cpu(cqe->ud.rxlen_pkey) &
  2425. OCRDMA_CQE_PKEY_MASK;
  2426. ibwc->wc_flags = IB_WC_GRH;
  2427. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2428. OCRDMA_CQE_UD_XFER_LEN_SHIFT);
  2429. return status;
  2430. }
  2431. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2432. struct ocrdma_cqe *cqe,
  2433. struct ocrdma_qp *qp)
  2434. {
  2435. unsigned long flags;
  2436. struct ocrdma_srq *srq;
  2437. u32 wqe_idx;
  2438. srq = get_ocrdma_srq(qp->ibqp.srq);
  2439. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2440. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2441. if (wqe_idx < 1)
  2442. BUG();
  2443. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2444. spin_lock_irqsave(&srq->q_lock, flags);
  2445. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2446. spin_unlock_irqrestore(&srq->q_lock, flags);
  2447. ocrdma_hwq_inc_tail(&srq->rq);
  2448. }
  2449. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2450. struct ib_wc *ibwc, bool *polled, bool *stop,
  2451. int status)
  2452. {
  2453. bool expand;
  2454. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2455. if (status < OCRDMA_MAX_CQE_ERR)
  2456. atomic_inc(&dev->cqe_err_stats[status]);
  2457. /* when hw_rq is empty, but wq is not empty, so continue
  2458. * to keep the cqe to get the cq event again.
  2459. */
  2460. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2461. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2462. *polled = true;
  2463. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2464. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2465. } else {
  2466. *polled = false;
  2467. *stop = true;
  2468. expand = false;
  2469. }
  2470. } else if (is_hw_rq_empty(qp)) {
  2471. /* Do nothing */
  2472. expand = false;
  2473. *polled = false;
  2474. *stop = false;
  2475. } else {
  2476. *polled = true;
  2477. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2478. }
  2479. return expand;
  2480. }
  2481. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2482. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2483. {
  2484. ibwc->opcode = IB_WC_RECV;
  2485. ibwc->qp = &qp->ibqp;
  2486. ibwc->status = IB_WC_SUCCESS;
  2487. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2488. ocrdma_update_ud_rcqe(ibwc, cqe);
  2489. else
  2490. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2491. if (is_cqe_imm(cqe)) {
  2492. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2493. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2494. } else if (is_cqe_wr_imm(cqe)) {
  2495. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2496. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2497. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2498. } else if (is_cqe_invalidated(cqe)) {
  2499. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2500. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2501. }
  2502. if (qp->ibqp.srq) {
  2503. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2504. } else {
  2505. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2506. ocrdma_hwq_inc_tail(&qp->rq);
  2507. }
  2508. }
  2509. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2510. struct ib_wc *ibwc, bool *polled, bool *stop)
  2511. {
  2512. int status;
  2513. bool expand = false;
  2514. ibwc->wc_flags = 0;
  2515. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2516. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2517. OCRDMA_CQE_UD_STATUS_MASK) >>
  2518. OCRDMA_CQE_UD_STATUS_SHIFT;
  2519. } else {
  2520. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2521. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2522. }
  2523. if (status == OCRDMA_CQE_SUCCESS) {
  2524. *polled = true;
  2525. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2526. } else {
  2527. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2528. status);
  2529. }
  2530. return expand;
  2531. }
  2532. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2533. u16 cur_getp)
  2534. {
  2535. if (cq->phase_change) {
  2536. if (cur_getp == 0)
  2537. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2538. } else {
  2539. /* clear valid bit */
  2540. cqe->flags_status_srcqpn = 0;
  2541. }
  2542. }
  2543. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2544. struct ib_wc *ibwc)
  2545. {
  2546. u16 qpn = 0;
  2547. int i = 0;
  2548. bool expand = false;
  2549. int polled_hw_cqes = 0;
  2550. struct ocrdma_qp *qp = NULL;
  2551. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2552. struct ocrdma_cqe *cqe;
  2553. u16 cur_getp; bool polled = false; bool stop = false;
  2554. cur_getp = cq->getp;
  2555. while (num_entries) {
  2556. cqe = cq->va + cur_getp;
  2557. /* check whether valid cqe or not */
  2558. if (!is_cqe_valid(cq, cqe))
  2559. break;
  2560. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2561. /* ignore discarded cqe */
  2562. if (qpn == 0)
  2563. goto skip_cqe;
  2564. qp = dev->qp_tbl[qpn];
  2565. BUG_ON(qp == NULL);
  2566. if (is_cqe_for_sq(cqe)) {
  2567. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2568. &stop);
  2569. } else {
  2570. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2571. &stop);
  2572. }
  2573. if (expand)
  2574. goto expand_cqe;
  2575. if (stop)
  2576. goto stop_cqe;
  2577. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2578. cqe->cmn.qpn = 0;
  2579. skip_cqe:
  2580. polled_hw_cqes += 1;
  2581. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2582. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2583. expand_cqe:
  2584. if (polled) {
  2585. num_entries -= 1;
  2586. i += 1;
  2587. ibwc = ibwc + 1;
  2588. polled = false;
  2589. }
  2590. }
  2591. stop_cqe:
  2592. cq->getp = cur_getp;
  2593. if (cq->deferred_arm) {
  2594. ocrdma_ring_cq_db(dev, cq->id, true, cq->deferred_sol,
  2595. polled_hw_cqes);
  2596. cq->deferred_arm = false;
  2597. cq->deferred_sol = false;
  2598. } else {
  2599. /* We need to pop the CQE. No need to arm */
  2600. ocrdma_ring_cq_db(dev, cq->id, false, cq->deferred_sol,
  2601. polled_hw_cqes);
  2602. cq->deferred_sol = false;
  2603. }
  2604. return i;
  2605. }
  2606. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2607. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2608. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2609. {
  2610. int err_cqes = 0;
  2611. while (num_entries) {
  2612. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2613. break;
  2614. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2615. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2616. ocrdma_hwq_inc_tail(&qp->sq);
  2617. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2618. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2619. ocrdma_hwq_inc_tail(&qp->rq);
  2620. } else {
  2621. return err_cqes;
  2622. }
  2623. ibwc->byte_len = 0;
  2624. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2625. ibwc = ibwc + 1;
  2626. err_cqes += 1;
  2627. num_entries -= 1;
  2628. }
  2629. return err_cqes;
  2630. }
  2631. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2632. {
  2633. int cqes_to_poll = num_entries;
  2634. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2635. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2636. int num_os_cqe = 0, err_cqes = 0;
  2637. struct ocrdma_qp *qp;
  2638. unsigned long flags;
  2639. /* poll cqes from adapter CQ */
  2640. spin_lock_irqsave(&cq->cq_lock, flags);
  2641. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2642. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2643. cqes_to_poll -= num_os_cqe;
  2644. if (cqes_to_poll) {
  2645. wc = wc + num_os_cqe;
  2646. /* adapter returns single error cqe when qp moves to
  2647. * error state. So insert error cqes with wc_status as
  2648. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2649. * respectively which uses this CQ.
  2650. */
  2651. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2652. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2653. if (cqes_to_poll == 0)
  2654. break;
  2655. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2656. cqes_to_poll -= err_cqes;
  2657. num_os_cqe += err_cqes;
  2658. wc = wc + err_cqes;
  2659. }
  2660. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2661. }
  2662. return num_os_cqe;
  2663. }
  2664. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2665. {
  2666. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2667. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2668. u16 cq_id;
  2669. unsigned long flags;
  2670. bool arm_needed = false, sol_needed = false;
  2671. cq_id = cq->id;
  2672. spin_lock_irqsave(&cq->cq_lock, flags);
  2673. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2674. arm_needed = true;
  2675. if (cq_flags & IB_CQ_SOLICITED)
  2676. sol_needed = true;
  2677. if (cq->first_arm) {
  2678. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2679. cq->first_arm = false;
  2680. }
  2681. cq->deferred_arm = true;
  2682. cq->deferred_sol = sol_needed;
  2683. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2684. return 0;
  2685. }
  2686. struct ib_mr *ocrdma_alloc_mr(struct ib_pd *ibpd,
  2687. enum ib_mr_type mr_type,
  2688. u32 max_num_sg)
  2689. {
  2690. int status;
  2691. struct ocrdma_mr *mr;
  2692. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2693. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2694. if (mr_type != IB_MR_TYPE_MEM_REG)
  2695. return ERR_PTR(-EINVAL);
  2696. if (max_num_sg > dev->attr.max_pages_per_frmr)
  2697. return ERR_PTR(-EINVAL);
  2698. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2699. if (!mr)
  2700. return ERR_PTR(-ENOMEM);
  2701. status = ocrdma_get_pbl_info(dev, mr, max_num_sg);
  2702. if (status)
  2703. goto pbl_err;
  2704. mr->hwmr.fr_mr = 1;
  2705. mr->hwmr.remote_rd = 0;
  2706. mr->hwmr.remote_wr = 0;
  2707. mr->hwmr.local_rd = 0;
  2708. mr->hwmr.local_wr = 0;
  2709. mr->hwmr.mw_bind = 0;
  2710. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2711. if (status)
  2712. goto pbl_err;
  2713. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2714. if (status)
  2715. goto mbx_err;
  2716. mr->ibmr.rkey = mr->hwmr.lkey;
  2717. mr->ibmr.lkey = mr->hwmr.lkey;
  2718. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2719. (unsigned long) mr;
  2720. return &mr->ibmr;
  2721. mbx_err:
  2722. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2723. pbl_err:
  2724. kfree(mr);
  2725. return ERR_PTR(-ENOMEM);
  2726. }
  2727. struct ib_fast_reg_page_list *ocrdma_alloc_frmr_page_list(struct ib_device
  2728. *ibdev,
  2729. int page_list_len)
  2730. {
  2731. struct ib_fast_reg_page_list *frmr_list;
  2732. int size;
  2733. size = sizeof(*frmr_list) + (page_list_len * sizeof(u64));
  2734. frmr_list = kzalloc(size, GFP_KERNEL);
  2735. if (!frmr_list)
  2736. return ERR_PTR(-ENOMEM);
  2737. frmr_list->page_list = (u64 *)(frmr_list + 1);
  2738. return frmr_list;
  2739. }
  2740. void ocrdma_free_frmr_page_list(struct ib_fast_reg_page_list *page_list)
  2741. {
  2742. kfree(page_list);
  2743. }
  2744. #define MAX_KERNEL_PBE_SIZE 65536
  2745. static inline int count_kernel_pbes(struct ib_phys_buf *buf_list,
  2746. int buf_cnt, u32 *pbe_size)
  2747. {
  2748. u64 total_size = 0;
  2749. u64 buf_size = 0;
  2750. int i;
  2751. *pbe_size = roundup(buf_list[0].size, PAGE_SIZE);
  2752. *pbe_size = roundup_pow_of_two(*pbe_size);
  2753. /* find the smallest PBE size that we can have */
  2754. for (i = 0; i < buf_cnt; i++) {
  2755. /* first addr may not be page aligned, so ignore checking */
  2756. if ((i != 0) && ((buf_list[i].addr & ~PAGE_MASK) ||
  2757. (buf_list[i].size & ~PAGE_MASK))) {
  2758. return 0;
  2759. }
  2760. /* if configured PBE size is greater then the chosen one,
  2761. * reduce the PBE size.
  2762. */
  2763. buf_size = roundup(buf_list[i].size, PAGE_SIZE);
  2764. /* pbe_size has to be even multiple of 4K 1,2,4,8...*/
  2765. buf_size = roundup_pow_of_two(buf_size);
  2766. if (*pbe_size > buf_size)
  2767. *pbe_size = buf_size;
  2768. total_size += buf_size;
  2769. }
  2770. *pbe_size = *pbe_size > MAX_KERNEL_PBE_SIZE ?
  2771. (MAX_KERNEL_PBE_SIZE) : (*pbe_size);
  2772. /* num_pbes = total_size / (*pbe_size); this is implemented below. */
  2773. return total_size >> ilog2(*pbe_size);
  2774. }
  2775. static void build_kernel_pbes(struct ib_phys_buf *buf_list, int ib_buf_cnt,
  2776. u32 pbe_size, struct ocrdma_pbl *pbl_tbl,
  2777. struct ocrdma_hw_mr *hwmr)
  2778. {
  2779. int i;
  2780. int idx;
  2781. int pbes_per_buf = 0;
  2782. u64 buf_addr = 0;
  2783. int num_pbes;
  2784. struct ocrdma_pbe *pbe;
  2785. int total_num_pbes = 0;
  2786. if (!hwmr->num_pbes)
  2787. return;
  2788. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2789. num_pbes = 0;
  2790. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  2791. for (i = 0; i < ib_buf_cnt; i++) {
  2792. buf_addr = buf_list[i].addr;
  2793. pbes_per_buf =
  2794. roundup_pow_of_two(roundup(buf_list[i].size, PAGE_SIZE)) /
  2795. pbe_size;
  2796. hwmr->len += buf_list[i].size;
  2797. /* number of pbes can be more for one OS buf, when
  2798. * buffers are of different sizes.
  2799. * split the ib_buf to one or more pbes.
  2800. */
  2801. for (idx = 0; idx < pbes_per_buf; idx++) {
  2802. /* we program always page aligned addresses,
  2803. * first unaligned address is taken care by fbo.
  2804. */
  2805. if (i == 0) {
  2806. /* for non zero fbo, assign the
  2807. * start of the page.
  2808. */
  2809. pbe->pa_lo =
  2810. cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  2811. pbe->pa_hi =
  2812. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2813. } else {
  2814. pbe->pa_lo =
  2815. cpu_to_le32((u32) (buf_addr & 0xffffffff));
  2816. pbe->pa_hi =
  2817. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2818. }
  2819. buf_addr += pbe_size;
  2820. num_pbes += 1;
  2821. total_num_pbes += 1;
  2822. pbe++;
  2823. if (total_num_pbes == hwmr->num_pbes)
  2824. goto mr_tbl_done;
  2825. /* if the pbl is full storing the pbes,
  2826. * move to next pbl.
  2827. */
  2828. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  2829. pbl_tbl++;
  2830. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2831. num_pbes = 0;
  2832. }
  2833. }
  2834. }
  2835. mr_tbl_done:
  2836. return;
  2837. }
  2838. struct ib_mr *ocrdma_reg_kernel_mr(struct ib_pd *ibpd,
  2839. struct ib_phys_buf *buf_list,
  2840. int buf_cnt, int acc, u64 *iova_start)
  2841. {
  2842. int status = -ENOMEM;
  2843. struct ocrdma_mr *mr;
  2844. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2845. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2846. u32 num_pbes;
  2847. u32 pbe_size = 0;
  2848. if ((acc & IB_ACCESS_REMOTE_WRITE) && !(acc & IB_ACCESS_LOCAL_WRITE))
  2849. return ERR_PTR(-EINVAL);
  2850. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2851. if (!mr)
  2852. return ERR_PTR(status);
  2853. num_pbes = count_kernel_pbes(buf_list, buf_cnt, &pbe_size);
  2854. if (num_pbes == 0) {
  2855. status = -EINVAL;
  2856. goto pbl_err;
  2857. }
  2858. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  2859. if (status)
  2860. goto pbl_err;
  2861. mr->hwmr.pbe_size = pbe_size;
  2862. mr->hwmr.fbo = *iova_start - (buf_list[0].addr & PAGE_MASK);
  2863. mr->hwmr.va = *iova_start;
  2864. mr->hwmr.local_rd = 1;
  2865. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  2866. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  2867. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  2868. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  2869. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  2870. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2871. if (status)
  2872. goto pbl_err;
  2873. build_kernel_pbes(buf_list, buf_cnt, pbe_size, mr->hwmr.pbl_table,
  2874. &mr->hwmr);
  2875. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  2876. if (status)
  2877. goto mbx_err;
  2878. mr->ibmr.lkey = mr->hwmr.lkey;
  2879. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  2880. mr->ibmr.rkey = mr->hwmr.lkey;
  2881. return &mr->ibmr;
  2882. mbx_err:
  2883. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2884. pbl_err:
  2885. kfree(mr);
  2886. return ERR_PTR(status);
  2887. }