main.c 77 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <net/ipv6.h>
  42. #include <net/addrconf.h>
  43. #include <rdma/ib_smi.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_addr.h>
  46. #include <rdma/ib_cache.h>
  47. #include <net/bonding.h>
  48. #include <linux/mlx4/driver.h>
  49. #include <linux/mlx4/cmd.h>
  50. #include <linux/mlx4/qp.h>
  51. #include "mlx4_ib.h"
  52. #include "user.h"
  53. #define DRV_NAME MLX4_IB_DRV_NAME
  54. #define DRV_VERSION "2.2-1"
  55. #define DRV_RELDATE "Feb 2014"
  56. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  57. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  58. #define MLX4_IB_CARD_REV_A0 0xA0
  59. MODULE_AUTHOR("Roland Dreier");
  60. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  61. MODULE_LICENSE("Dual BSD/GPL");
  62. MODULE_VERSION(DRV_VERSION);
  63. int mlx4_ib_sm_guid_assign = 0;
  64. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  65. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  66. static const char mlx4_ib_version[] =
  67. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  68. DRV_VERSION " (" DRV_RELDATE ")\n";
  69. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  70. static struct workqueue_struct *wq;
  71. static void init_query_mad(struct ib_smp *mad)
  72. {
  73. mad->base_version = 1;
  74. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  75. mad->class_version = 1;
  76. mad->method = IB_MGMT_METHOD_GET;
  77. }
  78. static int check_flow_steering_support(struct mlx4_dev *dev)
  79. {
  80. int eth_num_ports = 0;
  81. int ib_num_ports = 0;
  82. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  83. if (dmfs) {
  84. int i;
  85. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  86. eth_num_ports++;
  87. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  88. ib_num_ports++;
  89. dmfs &= (!ib_num_ports ||
  90. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  91. (!eth_num_ports ||
  92. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  93. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  94. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  95. dmfs = 0;
  96. }
  97. }
  98. return dmfs;
  99. }
  100. static int num_ib_ports(struct mlx4_dev *dev)
  101. {
  102. int ib_ports = 0;
  103. int i;
  104. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  105. ib_ports++;
  106. return ib_ports;
  107. }
  108. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  109. {
  110. struct mlx4_ib_dev *ibdev = to_mdev(device);
  111. struct net_device *dev;
  112. rcu_read_lock();
  113. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  114. if (dev) {
  115. if (mlx4_is_bonded(ibdev->dev)) {
  116. struct net_device *upper = NULL;
  117. upper = netdev_master_upper_dev_get_rcu(dev);
  118. if (upper) {
  119. struct net_device *active;
  120. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  121. if (active)
  122. dev = active;
  123. }
  124. }
  125. }
  126. if (dev)
  127. dev_hold(dev);
  128. rcu_read_unlock();
  129. return dev;
  130. }
  131. static int mlx4_ib_update_gids(struct gid_entry *gids,
  132. struct mlx4_ib_dev *ibdev,
  133. u8 port_num)
  134. {
  135. struct mlx4_cmd_mailbox *mailbox;
  136. int err;
  137. struct mlx4_dev *dev = ibdev->dev;
  138. int i;
  139. union ib_gid *gid_tbl;
  140. mailbox = mlx4_alloc_cmd_mailbox(dev);
  141. if (IS_ERR(mailbox))
  142. return -ENOMEM;
  143. gid_tbl = mailbox->buf;
  144. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  145. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  146. err = mlx4_cmd(dev, mailbox->dma,
  147. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  148. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  149. MLX4_CMD_WRAPPED);
  150. if (mlx4_is_bonded(dev))
  151. err += mlx4_cmd(dev, mailbox->dma,
  152. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  153. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  154. MLX4_CMD_WRAPPED);
  155. mlx4_free_cmd_mailbox(dev, mailbox);
  156. return err;
  157. }
  158. static int mlx4_ib_add_gid(struct ib_device *device,
  159. u8 port_num,
  160. unsigned int index,
  161. const union ib_gid *gid,
  162. const struct ib_gid_attr *attr,
  163. void **context)
  164. {
  165. struct mlx4_ib_dev *ibdev = to_mdev(device);
  166. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  167. struct mlx4_port_gid_table *port_gid_table;
  168. int free = -1, found = -1;
  169. int ret = 0;
  170. int hw_update = 0;
  171. int i;
  172. struct gid_entry *gids = NULL;
  173. if (!rdma_cap_roce_gid_table(device, port_num))
  174. return -EINVAL;
  175. if (port_num > MLX4_MAX_PORTS)
  176. return -EINVAL;
  177. if (!context)
  178. return -EINVAL;
  179. port_gid_table = &iboe->gids[port_num - 1];
  180. spin_lock_bh(&iboe->lock);
  181. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  182. if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid))) {
  183. found = i;
  184. break;
  185. }
  186. if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
  187. free = i; /* HW has space */
  188. }
  189. if (found < 0) {
  190. if (free < 0) {
  191. ret = -ENOSPC;
  192. } else {
  193. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  194. if (!port_gid_table->gids[free].ctx) {
  195. ret = -ENOMEM;
  196. } else {
  197. *context = port_gid_table->gids[free].ctx;
  198. memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
  199. port_gid_table->gids[free].ctx->real_index = free;
  200. port_gid_table->gids[free].ctx->refcount = 1;
  201. hw_update = 1;
  202. }
  203. }
  204. } else {
  205. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  206. *context = ctx;
  207. ctx->refcount++;
  208. }
  209. if (!ret && hw_update) {
  210. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  211. if (!gids) {
  212. ret = -ENOMEM;
  213. } else {
  214. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  215. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  216. }
  217. }
  218. spin_unlock_bh(&iboe->lock);
  219. if (!ret && hw_update) {
  220. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  221. kfree(gids);
  222. }
  223. return ret;
  224. }
  225. static int mlx4_ib_del_gid(struct ib_device *device,
  226. u8 port_num,
  227. unsigned int index,
  228. void **context)
  229. {
  230. struct gid_cache_context *ctx = *context;
  231. struct mlx4_ib_dev *ibdev = to_mdev(device);
  232. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  233. struct mlx4_port_gid_table *port_gid_table;
  234. int ret = 0;
  235. int hw_update = 0;
  236. struct gid_entry *gids = NULL;
  237. if (!rdma_cap_roce_gid_table(device, port_num))
  238. return -EINVAL;
  239. if (port_num > MLX4_MAX_PORTS)
  240. return -EINVAL;
  241. port_gid_table = &iboe->gids[port_num - 1];
  242. spin_lock_bh(&iboe->lock);
  243. if (ctx) {
  244. ctx->refcount--;
  245. if (!ctx->refcount) {
  246. unsigned int real_index = ctx->real_index;
  247. memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
  248. kfree(port_gid_table->gids[real_index].ctx);
  249. port_gid_table->gids[real_index].ctx = NULL;
  250. hw_update = 1;
  251. }
  252. }
  253. if (!ret && hw_update) {
  254. int i;
  255. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  256. if (!gids) {
  257. ret = -ENOMEM;
  258. } else {
  259. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  260. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  261. }
  262. }
  263. spin_unlock_bh(&iboe->lock);
  264. if (!ret && hw_update) {
  265. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  266. kfree(gids);
  267. }
  268. return ret;
  269. }
  270. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  271. u8 port_num, int index)
  272. {
  273. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  274. struct gid_cache_context *ctx = NULL;
  275. union ib_gid gid;
  276. struct mlx4_port_gid_table *port_gid_table;
  277. int real_index = -EINVAL;
  278. int i;
  279. int ret;
  280. unsigned long flags;
  281. if (port_num > MLX4_MAX_PORTS)
  282. return -EINVAL;
  283. if (mlx4_is_bonded(ibdev->dev))
  284. port_num = 1;
  285. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  286. return index;
  287. ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid);
  288. if (ret)
  289. return ret;
  290. if (!memcmp(&gid, &zgid, sizeof(gid)))
  291. return -EINVAL;
  292. spin_lock_irqsave(&iboe->lock, flags);
  293. port_gid_table = &iboe->gids[port_num - 1];
  294. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  295. if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid))) {
  296. ctx = port_gid_table->gids[i].ctx;
  297. break;
  298. }
  299. if (ctx)
  300. real_index = ctx->real_index;
  301. spin_unlock_irqrestore(&iboe->lock, flags);
  302. return real_index;
  303. }
  304. static int mlx4_ib_query_device(struct ib_device *ibdev,
  305. struct ib_device_attr *props,
  306. struct ib_udata *uhw)
  307. {
  308. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  309. struct ib_smp *in_mad = NULL;
  310. struct ib_smp *out_mad = NULL;
  311. int err = -ENOMEM;
  312. int have_ib_ports;
  313. struct mlx4_uverbs_ex_query_device cmd;
  314. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  315. struct mlx4_clock_params clock_params;
  316. if (uhw->inlen) {
  317. if (uhw->inlen < sizeof(cmd))
  318. return -EINVAL;
  319. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  320. if (err)
  321. return err;
  322. if (cmd.comp_mask)
  323. return -EINVAL;
  324. if (cmd.reserved)
  325. return -EINVAL;
  326. }
  327. resp.response_length = offsetof(typeof(resp), response_length) +
  328. sizeof(resp.response_length);
  329. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  330. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  331. if (!in_mad || !out_mad)
  332. goto out;
  333. init_query_mad(in_mad);
  334. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  335. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  336. 1, NULL, NULL, in_mad, out_mad);
  337. if (err)
  338. goto out;
  339. memset(props, 0, sizeof *props);
  340. have_ib_ports = num_ib_ports(dev->dev);
  341. props->fw_ver = dev->dev->caps.fw_ver;
  342. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  343. IB_DEVICE_PORT_ACTIVE_EVENT |
  344. IB_DEVICE_SYS_IMAGE_GUID |
  345. IB_DEVICE_RC_RNR_NAK_GEN |
  346. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  347. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  348. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  349. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  350. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  351. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  352. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  353. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  354. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  355. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  356. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  357. if (dev->dev->caps.max_gso_sz &&
  358. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  359. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  360. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  361. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  362. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  363. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  364. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  365. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  366. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  367. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  368. props->device_cap_flags |= IB_DEVICE_XRC;
  369. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  370. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  371. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  372. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  373. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  374. else
  375. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  376. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  377. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  378. }
  379. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  380. 0xffffff;
  381. props->vendor_part_id = dev->dev->persist->pdev->device;
  382. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  383. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  384. props->max_mr_size = ~0ull;
  385. props->page_size_cap = dev->dev->caps.page_size_cap;
  386. props->max_qp = dev->dev->quotas.qp;
  387. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  388. props->max_sge = min(dev->dev->caps.max_sq_sg,
  389. dev->dev->caps.max_rq_sg);
  390. props->max_sge_rd = props->max_sge;
  391. props->max_cq = dev->dev->quotas.cq;
  392. props->max_cqe = dev->dev->caps.max_cqes;
  393. props->max_mr = dev->dev->quotas.mpt;
  394. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  395. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  396. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  397. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  398. props->max_srq = dev->dev->quotas.srq;
  399. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  400. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  401. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  402. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  403. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  404. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  405. props->masked_atomic_cap = props->atomic_cap;
  406. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  407. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  408. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  409. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  410. props->max_mcast_grp;
  411. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  412. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  413. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  414. if (!mlx4_is_slave(dev->dev))
  415. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  416. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  417. resp.response_length += sizeof(resp.hca_core_clock_offset);
  418. if (!err && !mlx4_is_slave(dev->dev)) {
  419. resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
  420. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  421. }
  422. }
  423. if (uhw->outlen) {
  424. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  425. if (err)
  426. goto out;
  427. }
  428. out:
  429. kfree(in_mad);
  430. kfree(out_mad);
  431. return err;
  432. }
  433. static enum rdma_link_layer
  434. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  435. {
  436. struct mlx4_dev *dev = to_mdev(device)->dev;
  437. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  438. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  439. }
  440. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  441. struct ib_port_attr *props, int netw_view)
  442. {
  443. struct ib_smp *in_mad = NULL;
  444. struct ib_smp *out_mad = NULL;
  445. int ext_active_speed;
  446. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  447. int err = -ENOMEM;
  448. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  449. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  450. if (!in_mad || !out_mad)
  451. goto out;
  452. init_query_mad(in_mad);
  453. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  454. in_mad->attr_mod = cpu_to_be32(port);
  455. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  456. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  457. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  458. in_mad, out_mad);
  459. if (err)
  460. goto out;
  461. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  462. props->lmc = out_mad->data[34] & 0x7;
  463. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  464. props->sm_sl = out_mad->data[36] & 0xf;
  465. props->state = out_mad->data[32] & 0xf;
  466. props->phys_state = out_mad->data[33] >> 4;
  467. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  468. if (netw_view)
  469. props->gid_tbl_len = out_mad->data[50];
  470. else
  471. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  472. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  473. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  474. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  475. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  476. props->active_width = out_mad->data[31] & 0xf;
  477. props->active_speed = out_mad->data[35] >> 4;
  478. props->max_mtu = out_mad->data[41] & 0xf;
  479. props->active_mtu = out_mad->data[36] >> 4;
  480. props->subnet_timeout = out_mad->data[51] & 0x1f;
  481. props->max_vl_num = out_mad->data[37] >> 4;
  482. props->init_type_reply = out_mad->data[41] >> 4;
  483. /* Check if extended speeds (EDR/FDR/...) are supported */
  484. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  485. ext_active_speed = out_mad->data[62] >> 4;
  486. switch (ext_active_speed) {
  487. case 1:
  488. props->active_speed = IB_SPEED_FDR;
  489. break;
  490. case 2:
  491. props->active_speed = IB_SPEED_EDR;
  492. break;
  493. }
  494. }
  495. /* If reported active speed is QDR, check if is FDR-10 */
  496. if (props->active_speed == IB_SPEED_QDR) {
  497. init_query_mad(in_mad);
  498. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  499. in_mad->attr_mod = cpu_to_be32(port);
  500. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  501. NULL, NULL, in_mad, out_mad);
  502. if (err)
  503. goto out;
  504. /* Checking LinkSpeedActive for FDR-10 */
  505. if (out_mad->data[15] & 0x1)
  506. props->active_speed = IB_SPEED_FDR10;
  507. }
  508. /* Avoid wrong speed value returned by FW if the IB link is down. */
  509. if (props->state == IB_PORT_DOWN)
  510. props->active_speed = IB_SPEED_SDR;
  511. out:
  512. kfree(in_mad);
  513. kfree(out_mad);
  514. return err;
  515. }
  516. static u8 state_to_phys_state(enum ib_port_state state)
  517. {
  518. return state == IB_PORT_ACTIVE ? 5 : 3;
  519. }
  520. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  521. struct ib_port_attr *props, int netw_view)
  522. {
  523. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  524. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  525. struct net_device *ndev;
  526. enum ib_mtu tmp;
  527. struct mlx4_cmd_mailbox *mailbox;
  528. int err = 0;
  529. int is_bonded = mlx4_is_bonded(mdev->dev);
  530. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  531. if (IS_ERR(mailbox))
  532. return PTR_ERR(mailbox);
  533. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  534. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  535. MLX4_CMD_WRAPPED);
  536. if (err)
  537. goto out;
  538. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
  539. IB_WIDTH_4X : IB_WIDTH_1X;
  540. props->active_speed = IB_SPEED_QDR;
  541. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
  542. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  543. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  544. props->pkey_tbl_len = 1;
  545. props->max_mtu = IB_MTU_4096;
  546. props->max_vl_num = 2;
  547. props->state = IB_PORT_DOWN;
  548. props->phys_state = state_to_phys_state(props->state);
  549. props->active_mtu = IB_MTU_256;
  550. spin_lock_bh(&iboe->lock);
  551. ndev = iboe->netdevs[port - 1];
  552. if (ndev && is_bonded) {
  553. rcu_read_lock(); /* required to get upper dev */
  554. ndev = netdev_master_upper_dev_get_rcu(ndev);
  555. rcu_read_unlock();
  556. }
  557. if (!ndev)
  558. goto out_unlock;
  559. tmp = iboe_get_mtu(ndev->mtu);
  560. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  561. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  562. IB_PORT_ACTIVE : IB_PORT_DOWN;
  563. props->phys_state = state_to_phys_state(props->state);
  564. out_unlock:
  565. spin_unlock_bh(&iboe->lock);
  566. out:
  567. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  568. return err;
  569. }
  570. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  571. struct ib_port_attr *props, int netw_view)
  572. {
  573. int err;
  574. memset(props, 0, sizeof *props);
  575. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  576. ib_link_query_port(ibdev, port, props, netw_view) :
  577. eth_link_query_port(ibdev, port, props, netw_view);
  578. return err;
  579. }
  580. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  581. struct ib_port_attr *props)
  582. {
  583. /* returns host view */
  584. return __mlx4_ib_query_port(ibdev, port, props, 0);
  585. }
  586. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  587. union ib_gid *gid, int netw_view)
  588. {
  589. struct ib_smp *in_mad = NULL;
  590. struct ib_smp *out_mad = NULL;
  591. int err = -ENOMEM;
  592. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  593. int clear = 0;
  594. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  595. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  596. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  597. if (!in_mad || !out_mad)
  598. goto out;
  599. init_query_mad(in_mad);
  600. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  601. in_mad->attr_mod = cpu_to_be32(port);
  602. if (mlx4_is_mfunc(dev->dev) && netw_view)
  603. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  604. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  605. if (err)
  606. goto out;
  607. memcpy(gid->raw, out_mad->data + 8, 8);
  608. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  609. if (index) {
  610. /* For any index > 0, return the null guid */
  611. err = 0;
  612. clear = 1;
  613. goto out;
  614. }
  615. }
  616. init_query_mad(in_mad);
  617. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  618. in_mad->attr_mod = cpu_to_be32(index / 8);
  619. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  620. NULL, NULL, in_mad, out_mad);
  621. if (err)
  622. goto out;
  623. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  624. out:
  625. if (clear)
  626. memset(gid->raw + 8, 0, 8);
  627. kfree(in_mad);
  628. kfree(out_mad);
  629. return err;
  630. }
  631. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  632. union ib_gid *gid)
  633. {
  634. int ret;
  635. if (rdma_protocol_ib(ibdev, port))
  636. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  637. if (!rdma_protocol_roce(ibdev, port))
  638. return -ENODEV;
  639. if (!rdma_cap_roce_gid_table(ibdev, port))
  640. return -ENODEV;
  641. ret = ib_get_cached_gid(ibdev, port, index, gid);
  642. if (ret == -EAGAIN) {
  643. memcpy(gid, &zgid, sizeof(*gid));
  644. return 0;
  645. }
  646. return ret;
  647. }
  648. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  649. u16 *pkey, int netw_view)
  650. {
  651. struct ib_smp *in_mad = NULL;
  652. struct ib_smp *out_mad = NULL;
  653. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  654. int err = -ENOMEM;
  655. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  656. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  657. if (!in_mad || !out_mad)
  658. goto out;
  659. init_query_mad(in_mad);
  660. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  661. in_mad->attr_mod = cpu_to_be32(index / 32);
  662. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  663. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  664. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  665. in_mad, out_mad);
  666. if (err)
  667. goto out;
  668. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  669. out:
  670. kfree(in_mad);
  671. kfree(out_mad);
  672. return err;
  673. }
  674. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  675. {
  676. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  677. }
  678. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  679. struct ib_device_modify *props)
  680. {
  681. struct mlx4_cmd_mailbox *mailbox;
  682. unsigned long flags;
  683. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  684. return -EOPNOTSUPP;
  685. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  686. return 0;
  687. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  688. return -EOPNOTSUPP;
  689. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  690. memcpy(ibdev->node_desc, props->node_desc, 64);
  691. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  692. /*
  693. * If possible, pass node desc to FW, so it can generate
  694. * a 144 trap. If cmd fails, just ignore.
  695. */
  696. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  697. if (IS_ERR(mailbox))
  698. return 0;
  699. memcpy(mailbox->buf, props->node_desc, 64);
  700. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  701. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  702. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  703. return 0;
  704. }
  705. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  706. u32 cap_mask)
  707. {
  708. struct mlx4_cmd_mailbox *mailbox;
  709. int err;
  710. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  711. if (IS_ERR(mailbox))
  712. return PTR_ERR(mailbox);
  713. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  714. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  715. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  716. } else {
  717. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  718. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  719. }
  720. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  721. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  722. MLX4_CMD_WRAPPED);
  723. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  724. return err;
  725. }
  726. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  727. struct ib_port_modify *props)
  728. {
  729. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  730. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  731. struct ib_port_attr attr;
  732. u32 cap_mask;
  733. int err;
  734. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  735. * of whether port link layer is ETH or IB. For ETH ports, qkey
  736. * violations and port capabilities are not meaningful.
  737. */
  738. if (is_eth)
  739. return 0;
  740. mutex_lock(&mdev->cap_mask_mutex);
  741. err = mlx4_ib_query_port(ibdev, port, &attr);
  742. if (err)
  743. goto out;
  744. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  745. ~props->clr_port_cap_mask;
  746. err = mlx4_ib_SET_PORT(mdev, port,
  747. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  748. cap_mask);
  749. out:
  750. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  751. return err;
  752. }
  753. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  754. struct ib_udata *udata)
  755. {
  756. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  757. struct mlx4_ib_ucontext *context;
  758. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  759. struct mlx4_ib_alloc_ucontext_resp resp;
  760. int err;
  761. if (!dev->ib_active)
  762. return ERR_PTR(-EAGAIN);
  763. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  764. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  765. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  766. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  767. } else {
  768. resp.dev_caps = dev->dev->caps.userspace_caps;
  769. resp.qp_tab_size = dev->dev->caps.num_qps;
  770. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  771. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  772. resp.cqe_size = dev->dev->caps.cqe_size;
  773. }
  774. context = kzalloc(sizeof(*context), GFP_KERNEL);
  775. if (!context)
  776. return ERR_PTR(-ENOMEM);
  777. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  778. if (err) {
  779. kfree(context);
  780. return ERR_PTR(err);
  781. }
  782. INIT_LIST_HEAD(&context->db_page_list);
  783. mutex_init(&context->db_page_mutex);
  784. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  785. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  786. else
  787. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  788. if (err) {
  789. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  790. kfree(context);
  791. return ERR_PTR(-EFAULT);
  792. }
  793. return &context->ibucontext;
  794. }
  795. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  796. {
  797. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  798. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  799. kfree(context);
  800. return 0;
  801. }
  802. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  803. {
  804. /* vma_open is called when a new VMA is created on top of our VMA.
  805. * This is done through either mremap flow or split_vma (usually due
  806. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  807. * vma, as this VMA is strongly hardware related. Therefore we set the
  808. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  809. * calling us again and trying to do incorrect actions. We assume that
  810. * the original vma size is exactly a single page that there will be no
  811. * "splitting" operations on.
  812. */
  813. area->vm_ops = NULL;
  814. }
  815. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  816. {
  817. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  818. /* It's guaranteed that all VMAs opened on a FD are closed before the
  819. * file itself is closed, therefore no sync is needed with the regular
  820. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  821. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  822. * The close operation is usually called under mm->mmap_sem except when
  823. * process is exiting. The exiting case is handled explicitly as part
  824. * of mlx4_ib_disassociate_ucontext.
  825. */
  826. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  827. area->vm_private_data;
  828. /* set the vma context pointer to null in the mlx4_ib driver's private
  829. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  830. */
  831. mlx4_ib_vma_priv_data->vma = NULL;
  832. }
  833. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  834. .open = mlx4_ib_vma_open,
  835. .close = mlx4_ib_vma_close
  836. };
  837. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  838. {
  839. int i;
  840. int ret = 0;
  841. struct vm_area_struct *vma;
  842. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  843. struct task_struct *owning_process = NULL;
  844. struct mm_struct *owning_mm = NULL;
  845. owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
  846. if (!owning_process)
  847. return;
  848. owning_mm = get_task_mm(owning_process);
  849. if (!owning_mm) {
  850. pr_info("no mm, disassociate ucontext is pending task termination\n");
  851. while (1) {
  852. /* make sure that task is dead before returning, it may
  853. * prevent a rare case of module down in parallel to a
  854. * call to mlx4_ib_vma_close.
  855. */
  856. put_task_struct(owning_process);
  857. msleep(1);
  858. owning_process = get_pid_task(ibcontext->tgid,
  859. PIDTYPE_PID);
  860. if (!owning_process ||
  861. owning_process->state == TASK_DEAD) {
  862. pr_info("disassociate ucontext done, task was terminated\n");
  863. /* in case task was dead need to release the task struct */
  864. if (owning_process)
  865. put_task_struct(owning_process);
  866. return;
  867. }
  868. }
  869. }
  870. /* need to protect from a race on closing the vma as part of
  871. * mlx4_ib_vma_close().
  872. */
  873. down_read(&owning_mm->mmap_sem);
  874. for (i = 0; i < HW_BAR_COUNT; i++) {
  875. vma = context->hw_bar_info[i].vma;
  876. if (!vma)
  877. continue;
  878. ret = zap_vma_ptes(context->hw_bar_info[i].vma,
  879. context->hw_bar_info[i].vma->vm_start,
  880. PAGE_SIZE);
  881. if (ret) {
  882. pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
  883. BUG_ON(1);
  884. }
  885. /* context going to be destroyed, should not access ops any more */
  886. context->hw_bar_info[i].vma->vm_ops = NULL;
  887. }
  888. up_read(&owning_mm->mmap_sem);
  889. mmput(owning_mm);
  890. put_task_struct(owning_process);
  891. }
  892. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  893. struct mlx4_ib_vma_private_data *vma_private_data)
  894. {
  895. vma_private_data->vma = vma;
  896. vma->vm_private_data = vma_private_data;
  897. vma->vm_ops = &mlx4_ib_vm_ops;
  898. }
  899. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  900. {
  901. struct mlx4_ib_dev *dev = to_mdev(context->device);
  902. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  903. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  904. return -EINVAL;
  905. if (vma->vm_pgoff == 0) {
  906. /* We prevent double mmaping on same context */
  907. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  908. return -EINVAL;
  909. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  910. if (io_remap_pfn_range(vma, vma->vm_start,
  911. to_mucontext(context)->uar.pfn,
  912. PAGE_SIZE, vma->vm_page_prot))
  913. return -EAGAIN;
  914. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  915. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  916. /* We prevent double mmaping on same context */
  917. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  918. return -EINVAL;
  919. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  920. if (io_remap_pfn_range(vma, vma->vm_start,
  921. to_mucontext(context)->uar.pfn +
  922. dev->dev->caps.num_uars,
  923. PAGE_SIZE, vma->vm_page_prot))
  924. return -EAGAIN;
  925. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  926. } else if (vma->vm_pgoff == 3) {
  927. struct mlx4_clock_params params;
  928. int ret;
  929. /* We prevent double mmaping on same context */
  930. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  931. return -EINVAL;
  932. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  933. if (ret)
  934. return ret;
  935. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  936. if (io_remap_pfn_range(vma, vma->vm_start,
  937. (pci_resource_start(dev->dev->persist->pdev,
  938. params.bar) +
  939. params.offset)
  940. >> PAGE_SHIFT,
  941. PAGE_SIZE, vma->vm_page_prot))
  942. return -EAGAIN;
  943. mlx4_ib_set_vma_data(vma,
  944. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  945. } else {
  946. return -EINVAL;
  947. }
  948. return 0;
  949. }
  950. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  951. struct ib_ucontext *context,
  952. struct ib_udata *udata)
  953. {
  954. struct mlx4_ib_pd *pd;
  955. int err;
  956. pd = kmalloc(sizeof *pd, GFP_KERNEL);
  957. if (!pd)
  958. return ERR_PTR(-ENOMEM);
  959. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  960. if (err) {
  961. kfree(pd);
  962. return ERR_PTR(err);
  963. }
  964. if (context)
  965. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  966. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  967. kfree(pd);
  968. return ERR_PTR(-EFAULT);
  969. }
  970. return &pd->ibpd;
  971. }
  972. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  973. {
  974. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  975. kfree(pd);
  976. return 0;
  977. }
  978. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  979. struct ib_ucontext *context,
  980. struct ib_udata *udata)
  981. {
  982. struct mlx4_ib_xrcd *xrcd;
  983. struct ib_cq_init_attr cq_attr = {};
  984. int err;
  985. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  986. return ERR_PTR(-ENOSYS);
  987. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  988. if (!xrcd)
  989. return ERR_PTR(-ENOMEM);
  990. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  991. if (err)
  992. goto err1;
  993. xrcd->pd = ib_alloc_pd(ibdev);
  994. if (IS_ERR(xrcd->pd)) {
  995. err = PTR_ERR(xrcd->pd);
  996. goto err2;
  997. }
  998. cq_attr.cqe = 1;
  999. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1000. if (IS_ERR(xrcd->cq)) {
  1001. err = PTR_ERR(xrcd->cq);
  1002. goto err3;
  1003. }
  1004. return &xrcd->ibxrcd;
  1005. err3:
  1006. ib_dealloc_pd(xrcd->pd);
  1007. err2:
  1008. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1009. err1:
  1010. kfree(xrcd);
  1011. return ERR_PTR(err);
  1012. }
  1013. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1014. {
  1015. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1016. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1017. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1018. kfree(xrcd);
  1019. return 0;
  1020. }
  1021. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1022. {
  1023. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1024. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1025. struct mlx4_ib_gid_entry *ge;
  1026. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1027. if (!ge)
  1028. return -ENOMEM;
  1029. ge->gid = *gid;
  1030. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1031. ge->port = mqp->port;
  1032. ge->added = 1;
  1033. }
  1034. mutex_lock(&mqp->mutex);
  1035. list_add_tail(&ge->list, &mqp->gid_list);
  1036. mutex_unlock(&mqp->mutex);
  1037. return 0;
  1038. }
  1039. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1040. union ib_gid *gid)
  1041. {
  1042. struct net_device *ndev;
  1043. int ret = 0;
  1044. if (!mqp->port)
  1045. return 0;
  1046. spin_lock_bh(&mdev->iboe.lock);
  1047. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1048. if (ndev)
  1049. dev_hold(ndev);
  1050. spin_unlock_bh(&mdev->iboe.lock);
  1051. if (ndev) {
  1052. ret = 1;
  1053. dev_put(ndev);
  1054. }
  1055. return ret;
  1056. }
  1057. struct mlx4_ib_steering {
  1058. struct list_head list;
  1059. struct mlx4_flow_reg_id reg_id;
  1060. union ib_gid gid;
  1061. };
  1062. static int parse_flow_attr(struct mlx4_dev *dev,
  1063. u32 qp_num,
  1064. union ib_flow_spec *ib_spec,
  1065. struct _rule_hw *mlx4_spec)
  1066. {
  1067. enum mlx4_net_trans_rule_id type;
  1068. switch (ib_spec->type) {
  1069. case IB_FLOW_SPEC_ETH:
  1070. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1071. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1072. ETH_ALEN);
  1073. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1074. ETH_ALEN);
  1075. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1076. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1077. break;
  1078. case IB_FLOW_SPEC_IB:
  1079. type = MLX4_NET_TRANS_RULE_ID_IB;
  1080. mlx4_spec->ib.l3_qpn =
  1081. cpu_to_be32(qp_num);
  1082. mlx4_spec->ib.qpn_mask =
  1083. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1084. break;
  1085. case IB_FLOW_SPEC_IPV4:
  1086. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1087. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1088. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1089. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1090. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1091. break;
  1092. case IB_FLOW_SPEC_TCP:
  1093. case IB_FLOW_SPEC_UDP:
  1094. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1095. MLX4_NET_TRANS_RULE_ID_TCP :
  1096. MLX4_NET_TRANS_RULE_ID_UDP;
  1097. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1098. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1099. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1100. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1101. break;
  1102. default:
  1103. return -EINVAL;
  1104. }
  1105. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1106. mlx4_hw_rule_sz(dev, type) < 0)
  1107. return -EINVAL;
  1108. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1109. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1110. return mlx4_hw_rule_sz(dev, type);
  1111. }
  1112. struct default_rules {
  1113. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1114. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1115. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1116. __u8 link_layer;
  1117. };
  1118. static const struct default_rules default_table[] = {
  1119. {
  1120. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1121. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1122. .rules_create_list = {IB_FLOW_SPEC_IB},
  1123. .link_layer = IB_LINK_LAYER_INFINIBAND
  1124. }
  1125. };
  1126. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1127. struct ib_flow_attr *flow_attr)
  1128. {
  1129. int i, j, k;
  1130. void *ib_flow;
  1131. const struct default_rules *pdefault_rules = default_table;
  1132. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1133. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1134. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1135. memset(&field_types, 0, sizeof(field_types));
  1136. if (link_layer != pdefault_rules->link_layer)
  1137. continue;
  1138. ib_flow = flow_attr + 1;
  1139. /* we assume the specs are sorted */
  1140. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1141. j < flow_attr->num_of_specs; k++) {
  1142. union ib_flow_spec *current_flow =
  1143. (union ib_flow_spec *)ib_flow;
  1144. /* same layer but different type */
  1145. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1146. (pdefault_rules->mandatory_fields[k] &
  1147. IB_FLOW_SPEC_LAYER_MASK)) &&
  1148. (current_flow->type !=
  1149. pdefault_rules->mandatory_fields[k]))
  1150. goto out;
  1151. /* same layer, try match next one */
  1152. if (current_flow->type ==
  1153. pdefault_rules->mandatory_fields[k]) {
  1154. j++;
  1155. ib_flow +=
  1156. ((union ib_flow_spec *)ib_flow)->size;
  1157. }
  1158. }
  1159. ib_flow = flow_attr + 1;
  1160. for (j = 0; j < flow_attr->num_of_specs;
  1161. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1162. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1163. /* same layer and same type */
  1164. if (((union ib_flow_spec *)ib_flow)->type ==
  1165. pdefault_rules->mandatory_not_fields[k])
  1166. goto out;
  1167. return i;
  1168. }
  1169. out:
  1170. return -1;
  1171. }
  1172. static int __mlx4_ib_create_default_rules(
  1173. struct mlx4_ib_dev *mdev,
  1174. struct ib_qp *qp,
  1175. const struct default_rules *pdefault_rules,
  1176. struct _rule_hw *mlx4_spec) {
  1177. int size = 0;
  1178. int i;
  1179. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1180. int ret;
  1181. union ib_flow_spec ib_spec;
  1182. switch (pdefault_rules->rules_create_list[i]) {
  1183. case 0:
  1184. /* no rule */
  1185. continue;
  1186. case IB_FLOW_SPEC_IB:
  1187. ib_spec.type = IB_FLOW_SPEC_IB;
  1188. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1189. break;
  1190. default:
  1191. /* invalid rule */
  1192. return -EINVAL;
  1193. }
  1194. /* We must put empty rule, qpn is being ignored */
  1195. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1196. mlx4_spec);
  1197. if (ret < 0) {
  1198. pr_info("invalid parsing\n");
  1199. return -EINVAL;
  1200. }
  1201. mlx4_spec = (void *)mlx4_spec + ret;
  1202. size += ret;
  1203. }
  1204. return size;
  1205. }
  1206. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1207. int domain,
  1208. enum mlx4_net_trans_promisc_mode flow_type,
  1209. u64 *reg_id)
  1210. {
  1211. int ret, i;
  1212. int size = 0;
  1213. void *ib_flow;
  1214. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1215. struct mlx4_cmd_mailbox *mailbox;
  1216. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1217. int default_flow;
  1218. static const u16 __mlx4_domain[] = {
  1219. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1220. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1221. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1222. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1223. };
  1224. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1225. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1226. return -EINVAL;
  1227. }
  1228. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1229. pr_err("Invalid domain value %d\n", domain);
  1230. return -EINVAL;
  1231. }
  1232. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1233. return -EINVAL;
  1234. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1235. if (IS_ERR(mailbox))
  1236. return PTR_ERR(mailbox);
  1237. ctrl = mailbox->buf;
  1238. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1239. flow_attr->priority);
  1240. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1241. ctrl->port = flow_attr->port;
  1242. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1243. ib_flow = flow_attr + 1;
  1244. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1245. /* Add default flows */
  1246. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1247. if (default_flow >= 0) {
  1248. ret = __mlx4_ib_create_default_rules(
  1249. mdev, qp, default_table + default_flow,
  1250. mailbox->buf + size);
  1251. if (ret < 0) {
  1252. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1253. return -EINVAL;
  1254. }
  1255. size += ret;
  1256. }
  1257. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1258. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1259. mailbox->buf + size);
  1260. if (ret < 0) {
  1261. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1262. return -EINVAL;
  1263. }
  1264. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1265. size += ret;
  1266. }
  1267. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1268. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1269. MLX4_CMD_WRAPPED);
  1270. if (ret == -ENOMEM)
  1271. pr_err("mcg table is full. Fail to register network rule.\n");
  1272. else if (ret == -ENXIO)
  1273. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1274. else if (ret)
  1275. pr_err("Invalid argumant. Fail to register network rule.\n");
  1276. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1277. return ret;
  1278. }
  1279. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1280. {
  1281. int err;
  1282. err = mlx4_cmd(dev, reg_id, 0, 0,
  1283. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1284. MLX4_CMD_WRAPPED);
  1285. if (err)
  1286. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1287. reg_id);
  1288. return err;
  1289. }
  1290. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1291. u64 *reg_id)
  1292. {
  1293. void *ib_flow;
  1294. union ib_flow_spec *ib_spec;
  1295. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1296. int err = 0;
  1297. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1298. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1299. return 0; /* do nothing */
  1300. ib_flow = flow_attr + 1;
  1301. ib_spec = (union ib_flow_spec *)ib_flow;
  1302. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1303. return 0; /* do nothing */
  1304. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1305. flow_attr->port, qp->qp_num,
  1306. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1307. reg_id);
  1308. return err;
  1309. }
  1310. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1311. struct ib_flow_attr *flow_attr,
  1312. int domain)
  1313. {
  1314. int err = 0, i = 0, j = 0;
  1315. struct mlx4_ib_flow *mflow;
  1316. enum mlx4_net_trans_promisc_mode type[2];
  1317. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1318. int is_bonded = mlx4_is_bonded(dev);
  1319. memset(type, 0, sizeof(type));
  1320. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1321. if (!mflow) {
  1322. err = -ENOMEM;
  1323. goto err_free;
  1324. }
  1325. switch (flow_attr->type) {
  1326. case IB_FLOW_ATTR_NORMAL:
  1327. type[0] = MLX4_FS_REGULAR;
  1328. break;
  1329. case IB_FLOW_ATTR_ALL_DEFAULT:
  1330. type[0] = MLX4_FS_ALL_DEFAULT;
  1331. break;
  1332. case IB_FLOW_ATTR_MC_DEFAULT:
  1333. type[0] = MLX4_FS_MC_DEFAULT;
  1334. break;
  1335. case IB_FLOW_ATTR_SNIFFER:
  1336. type[0] = MLX4_FS_UC_SNIFFER;
  1337. type[1] = MLX4_FS_MC_SNIFFER;
  1338. break;
  1339. default:
  1340. err = -EINVAL;
  1341. goto err_free;
  1342. }
  1343. while (i < ARRAY_SIZE(type) && type[i]) {
  1344. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1345. &mflow->reg_id[i].id);
  1346. if (err)
  1347. goto err_create_flow;
  1348. if (is_bonded) {
  1349. /* Application always sees one port so the mirror rule
  1350. * must be on port #2
  1351. */
  1352. flow_attr->port = 2;
  1353. err = __mlx4_ib_create_flow(qp, flow_attr,
  1354. domain, type[j],
  1355. &mflow->reg_id[j].mirror);
  1356. flow_attr->port = 1;
  1357. if (err)
  1358. goto err_create_flow;
  1359. j++;
  1360. }
  1361. i++;
  1362. }
  1363. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1364. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1365. &mflow->reg_id[i].id);
  1366. if (err)
  1367. goto err_create_flow;
  1368. if (is_bonded) {
  1369. flow_attr->port = 2;
  1370. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1371. &mflow->reg_id[j].mirror);
  1372. flow_attr->port = 1;
  1373. if (err)
  1374. goto err_create_flow;
  1375. j++;
  1376. }
  1377. /* function to create mirror rule */
  1378. i++;
  1379. }
  1380. return &mflow->ibflow;
  1381. err_create_flow:
  1382. while (i) {
  1383. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1384. mflow->reg_id[i].id);
  1385. i--;
  1386. }
  1387. while (j) {
  1388. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1389. mflow->reg_id[j].mirror);
  1390. j--;
  1391. }
  1392. err_free:
  1393. kfree(mflow);
  1394. return ERR_PTR(err);
  1395. }
  1396. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1397. {
  1398. int err, ret = 0;
  1399. int i = 0;
  1400. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1401. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1402. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1403. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1404. if (err)
  1405. ret = err;
  1406. if (mflow->reg_id[i].mirror) {
  1407. err = __mlx4_ib_destroy_flow(mdev->dev,
  1408. mflow->reg_id[i].mirror);
  1409. if (err)
  1410. ret = err;
  1411. }
  1412. i++;
  1413. }
  1414. kfree(mflow);
  1415. return ret;
  1416. }
  1417. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1418. {
  1419. int err;
  1420. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1421. struct mlx4_dev *dev = mdev->dev;
  1422. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1423. struct mlx4_ib_steering *ib_steering = NULL;
  1424. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1425. struct mlx4_flow_reg_id reg_id;
  1426. if (mdev->dev->caps.steering_mode ==
  1427. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1428. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1429. if (!ib_steering)
  1430. return -ENOMEM;
  1431. }
  1432. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1433. !!(mqp->flags &
  1434. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1435. prot, &reg_id.id);
  1436. if (err) {
  1437. pr_err("multicast attach op failed, err %d\n", err);
  1438. goto err_malloc;
  1439. }
  1440. reg_id.mirror = 0;
  1441. if (mlx4_is_bonded(dev)) {
  1442. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1443. (mqp->port == 1) ? 2 : 1,
  1444. !!(mqp->flags &
  1445. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1446. prot, &reg_id.mirror);
  1447. if (err)
  1448. goto err_add;
  1449. }
  1450. err = add_gid_entry(ibqp, gid);
  1451. if (err)
  1452. goto err_add;
  1453. if (ib_steering) {
  1454. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1455. ib_steering->reg_id = reg_id;
  1456. mutex_lock(&mqp->mutex);
  1457. list_add(&ib_steering->list, &mqp->steering_rules);
  1458. mutex_unlock(&mqp->mutex);
  1459. }
  1460. return 0;
  1461. err_add:
  1462. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1463. prot, reg_id.id);
  1464. if (reg_id.mirror)
  1465. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1466. prot, reg_id.mirror);
  1467. err_malloc:
  1468. kfree(ib_steering);
  1469. return err;
  1470. }
  1471. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1472. {
  1473. struct mlx4_ib_gid_entry *ge;
  1474. struct mlx4_ib_gid_entry *tmp;
  1475. struct mlx4_ib_gid_entry *ret = NULL;
  1476. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1477. if (!memcmp(raw, ge->gid.raw, 16)) {
  1478. ret = ge;
  1479. break;
  1480. }
  1481. }
  1482. return ret;
  1483. }
  1484. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1485. {
  1486. int err;
  1487. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1488. struct mlx4_dev *dev = mdev->dev;
  1489. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1490. struct net_device *ndev;
  1491. struct mlx4_ib_gid_entry *ge;
  1492. struct mlx4_flow_reg_id reg_id = {0, 0};
  1493. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1494. if (mdev->dev->caps.steering_mode ==
  1495. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1496. struct mlx4_ib_steering *ib_steering;
  1497. mutex_lock(&mqp->mutex);
  1498. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1499. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1500. list_del(&ib_steering->list);
  1501. break;
  1502. }
  1503. }
  1504. mutex_unlock(&mqp->mutex);
  1505. if (&ib_steering->list == &mqp->steering_rules) {
  1506. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1507. return -EINVAL;
  1508. }
  1509. reg_id = ib_steering->reg_id;
  1510. kfree(ib_steering);
  1511. }
  1512. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1513. prot, reg_id.id);
  1514. if (err)
  1515. return err;
  1516. if (mlx4_is_bonded(dev)) {
  1517. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1518. prot, reg_id.mirror);
  1519. if (err)
  1520. return err;
  1521. }
  1522. mutex_lock(&mqp->mutex);
  1523. ge = find_gid_entry(mqp, gid->raw);
  1524. if (ge) {
  1525. spin_lock_bh(&mdev->iboe.lock);
  1526. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1527. if (ndev)
  1528. dev_hold(ndev);
  1529. spin_unlock_bh(&mdev->iboe.lock);
  1530. if (ndev)
  1531. dev_put(ndev);
  1532. list_del(&ge->list);
  1533. kfree(ge);
  1534. } else
  1535. pr_warn("could not find mgid entry\n");
  1536. mutex_unlock(&mqp->mutex);
  1537. return 0;
  1538. }
  1539. static int init_node_data(struct mlx4_ib_dev *dev)
  1540. {
  1541. struct ib_smp *in_mad = NULL;
  1542. struct ib_smp *out_mad = NULL;
  1543. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1544. int err = -ENOMEM;
  1545. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1546. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1547. if (!in_mad || !out_mad)
  1548. goto out;
  1549. init_query_mad(in_mad);
  1550. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1551. if (mlx4_is_master(dev->dev))
  1552. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1553. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1554. if (err)
  1555. goto out;
  1556. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  1557. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1558. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1559. if (err)
  1560. goto out;
  1561. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1562. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1563. out:
  1564. kfree(in_mad);
  1565. kfree(out_mad);
  1566. return err;
  1567. }
  1568. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1569. char *buf)
  1570. {
  1571. struct mlx4_ib_dev *dev =
  1572. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1573. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1574. }
  1575. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  1576. char *buf)
  1577. {
  1578. struct mlx4_ib_dev *dev =
  1579. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1580. return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
  1581. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  1582. (int) dev->dev->caps.fw_ver & 0xffff);
  1583. }
  1584. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1585. char *buf)
  1586. {
  1587. struct mlx4_ib_dev *dev =
  1588. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1589. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1590. }
  1591. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1592. char *buf)
  1593. {
  1594. struct mlx4_ib_dev *dev =
  1595. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1596. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1597. dev->dev->board_id);
  1598. }
  1599. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1600. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  1601. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1602. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1603. static struct device_attribute *mlx4_class_attributes[] = {
  1604. &dev_attr_hw_rev,
  1605. &dev_attr_fw_ver,
  1606. &dev_attr_hca_type,
  1607. &dev_attr_board_id
  1608. };
  1609. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1610. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1611. struct net_device *dev,
  1612. int port)
  1613. {
  1614. u64 new_smac = 0;
  1615. u64 release_mac = MLX4_IB_INVALID_MAC;
  1616. struct mlx4_ib_qp *qp;
  1617. read_lock(&dev_base_lock);
  1618. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  1619. read_unlock(&dev_base_lock);
  1620. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  1621. /* no need for update QP1 and mac registration in non-SRIOV */
  1622. if (!mlx4_is_mfunc(ibdev->dev))
  1623. return;
  1624. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  1625. qp = ibdev->qp1_proxy[port - 1];
  1626. if (qp) {
  1627. int new_smac_index;
  1628. u64 old_smac;
  1629. struct mlx4_update_qp_params update_params;
  1630. mutex_lock(&qp->mutex);
  1631. old_smac = qp->pri.smac;
  1632. if (new_smac == old_smac)
  1633. goto unlock;
  1634. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  1635. if (new_smac_index < 0)
  1636. goto unlock;
  1637. update_params.smac_index = new_smac_index;
  1638. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  1639. &update_params)) {
  1640. release_mac = new_smac;
  1641. goto unlock;
  1642. }
  1643. /* if old port was zero, no mac was yet registered for this QP */
  1644. if (qp->pri.smac_port)
  1645. release_mac = old_smac;
  1646. qp->pri.smac = new_smac;
  1647. qp->pri.smac_port = port;
  1648. qp->pri.smac_index = new_smac_index;
  1649. }
  1650. unlock:
  1651. if (release_mac != MLX4_IB_INVALID_MAC)
  1652. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  1653. if (qp)
  1654. mutex_unlock(&qp->mutex);
  1655. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  1656. }
  1657. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  1658. struct net_device *dev,
  1659. unsigned long event)
  1660. {
  1661. struct mlx4_ib_iboe *iboe;
  1662. int update_qps_port = -1;
  1663. int port;
  1664. ASSERT_RTNL();
  1665. iboe = &ibdev->iboe;
  1666. spin_lock_bh(&iboe->lock);
  1667. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  1668. iboe->netdevs[port - 1] =
  1669. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  1670. if (dev == iboe->netdevs[port - 1] &&
  1671. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  1672. event == NETDEV_UP || event == NETDEV_CHANGE))
  1673. update_qps_port = port;
  1674. }
  1675. spin_unlock_bh(&iboe->lock);
  1676. if (update_qps_port > 0)
  1677. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  1678. }
  1679. static int mlx4_ib_netdev_event(struct notifier_block *this,
  1680. unsigned long event, void *ptr)
  1681. {
  1682. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  1683. struct mlx4_ib_dev *ibdev;
  1684. if (!net_eq(dev_net(dev), &init_net))
  1685. return NOTIFY_DONE;
  1686. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  1687. mlx4_ib_scan_netdevs(ibdev, dev, event);
  1688. return NOTIFY_DONE;
  1689. }
  1690. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  1691. {
  1692. int port;
  1693. int slave;
  1694. int i;
  1695. if (mlx4_is_master(ibdev->dev)) {
  1696. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  1697. ++slave) {
  1698. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1699. for (i = 0;
  1700. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1701. ++i) {
  1702. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  1703. /* master has the identity virt2phys pkey mapping */
  1704. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  1705. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  1706. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  1707. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  1708. }
  1709. }
  1710. }
  1711. /* initialize pkey cache */
  1712. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1713. for (i = 0;
  1714. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1715. ++i)
  1716. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  1717. (i) ? 0 : 0xFFFF;
  1718. }
  1719. }
  1720. }
  1721. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  1722. {
  1723. int i, j, eq = 0, total_eqs = 0;
  1724. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  1725. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  1726. if (!ibdev->eq_table)
  1727. return;
  1728. for (i = 1; i <= dev->caps.num_ports; i++) {
  1729. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  1730. j++, total_eqs++) {
  1731. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  1732. continue;
  1733. ibdev->eq_table[eq] = total_eqs;
  1734. if (!mlx4_assign_eq(dev, i,
  1735. &ibdev->eq_table[eq]))
  1736. eq++;
  1737. else
  1738. ibdev->eq_table[eq] = -1;
  1739. }
  1740. }
  1741. for (i = eq; i < dev->caps.num_comp_vectors;
  1742. ibdev->eq_table[i++] = -1)
  1743. ;
  1744. /* Advertise the new number of EQs to clients */
  1745. ibdev->ib_dev.num_comp_vectors = eq;
  1746. }
  1747. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  1748. {
  1749. int i;
  1750. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  1751. /* no eqs were allocated */
  1752. if (!ibdev->eq_table)
  1753. return;
  1754. /* Reset the advertised EQ number */
  1755. ibdev->ib_dev.num_comp_vectors = 0;
  1756. for (i = 0; i < total_eqs; i++)
  1757. mlx4_release_eq(dev, ibdev->eq_table[i]);
  1758. kfree(ibdev->eq_table);
  1759. ibdev->eq_table = NULL;
  1760. }
  1761. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  1762. struct ib_port_immutable *immutable)
  1763. {
  1764. struct ib_port_attr attr;
  1765. int err;
  1766. err = mlx4_ib_query_port(ibdev, port_num, &attr);
  1767. if (err)
  1768. return err;
  1769. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  1770. immutable->gid_tbl_len = attr.gid_tbl_len;
  1771. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND)
  1772. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  1773. else
  1774. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  1775. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  1776. return 0;
  1777. }
  1778. static void *mlx4_ib_add(struct mlx4_dev *dev)
  1779. {
  1780. struct mlx4_ib_dev *ibdev;
  1781. int num_ports = 0;
  1782. int i, j;
  1783. int err;
  1784. struct mlx4_ib_iboe *iboe;
  1785. int ib_num_ports = 0;
  1786. int num_req_counters;
  1787. int allocated;
  1788. u32 counter_index;
  1789. pr_info_once("%s", mlx4_ib_version);
  1790. num_ports = 0;
  1791. mlx4_foreach_ib_transport_port(i, dev)
  1792. num_ports++;
  1793. /* No point in registering a device with no ports... */
  1794. if (num_ports == 0)
  1795. return NULL;
  1796. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  1797. if (!ibdev) {
  1798. dev_err(&dev->persist->pdev->dev,
  1799. "Device struct alloc failed\n");
  1800. return NULL;
  1801. }
  1802. iboe = &ibdev->iboe;
  1803. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  1804. goto err_dealloc;
  1805. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  1806. goto err_pd;
  1807. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  1808. PAGE_SIZE);
  1809. if (!ibdev->uar_map)
  1810. goto err_uar;
  1811. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  1812. ibdev->dev = dev;
  1813. ibdev->bond_next_port = 0;
  1814. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  1815. ibdev->ib_dev.owner = THIS_MODULE;
  1816. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1817. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  1818. ibdev->num_ports = num_ports;
  1819. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  1820. 1 : ibdev->num_ports;
  1821. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  1822. ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
  1823. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  1824. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  1825. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  1826. if (dev->caps.userspace_caps)
  1827. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  1828. else
  1829. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  1830. ibdev->ib_dev.uverbs_cmd_mask =
  1831. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1832. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1833. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1834. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1835. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1836. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1837. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  1838. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1839. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1840. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1841. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1842. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1843. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1844. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1845. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1846. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1847. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1848. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1849. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1850. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1851. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1852. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1853. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1854. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1855. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  1856. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  1857. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  1858. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  1859. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  1860. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  1861. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  1862. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  1863. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  1864. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  1865. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  1866. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  1867. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  1868. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  1869. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  1870. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  1871. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  1872. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  1873. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  1874. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  1875. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  1876. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  1877. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  1878. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  1879. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  1880. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  1881. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  1882. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  1883. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  1884. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  1885. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  1886. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  1887. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  1888. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  1889. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  1890. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  1891. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  1892. ibdev->ib_dev.alloc_fast_reg_page_list = mlx4_ib_alloc_fast_reg_page_list;
  1893. ibdev->ib_dev.free_fast_reg_page_list = mlx4_ib_free_fast_reg_page_list;
  1894. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  1895. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  1896. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  1897. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  1898. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  1899. if (!mlx4_is_slave(ibdev->dev)) {
  1900. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  1901. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  1902. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  1903. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  1904. }
  1905. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  1906. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  1907. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  1908. ibdev->ib_dev.bind_mw = mlx4_ib_bind_mw;
  1909. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  1910. ibdev->ib_dev.uverbs_cmd_mask |=
  1911. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  1912. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  1913. }
  1914. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  1915. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  1916. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  1917. ibdev->ib_dev.uverbs_cmd_mask |=
  1918. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1919. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1920. }
  1921. if (check_flow_steering_support(dev)) {
  1922. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  1923. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  1924. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  1925. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  1926. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  1927. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  1928. }
  1929. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  1930. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  1931. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ);
  1932. mlx4_ib_alloc_eqs(dev, ibdev);
  1933. spin_lock_init(&iboe->lock);
  1934. if (init_node_data(ibdev))
  1935. goto err_map;
  1936. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  1937. for (i = 0; i < num_req_counters; ++i) {
  1938. mutex_init(&ibdev->qp1_proxy_lock[i]);
  1939. allocated = 0;
  1940. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  1941. IB_LINK_LAYER_ETHERNET) {
  1942. err = mlx4_counter_alloc(ibdev->dev, &counter_index);
  1943. /* if failed to allocate a new counter, use default */
  1944. if (err)
  1945. counter_index =
  1946. mlx4_get_default_counter_index(dev,
  1947. i + 1);
  1948. else
  1949. allocated = 1;
  1950. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  1951. counter_index = mlx4_get_default_counter_index(dev,
  1952. i + 1);
  1953. }
  1954. ibdev->counters[i].index = counter_index;
  1955. ibdev->counters[i].allocated = allocated;
  1956. pr_info("counter index %d for port %d allocated %d\n",
  1957. counter_index, i + 1, allocated);
  1958. }
  1959. if (mlx4_is_bonded(dev))
  1960. for (i = 1; i < ibdev->num_ports ; ++i) {
  1961. ibdev->counters[i].index = ibdev->counters[0].index;
  1962. ibdev->counters[i].allocated = 0;
  1963. }
  1964. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  1965. ib_num_ports++;
  1966. spin_lock_init(&ibdev->sm_lock);
  1967. mutex_init(&ibdev->cap_mask_mutex);
  1968. INIT_LIST_HEAD(&ibdev->qp_list);
  1969. spin_lock_init(&ibdev->reset_flow_resource_lock);
  1970. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  1971. ib_num_ports) {
  1972. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  1973. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  1974. MLX4_IB_UC_STEER_QPN_ALIGN,
  1975. &ibdev->steer_qpn_base, 0);
  1976. if (err)
  1977. goto err_counter;
  1978. ibdev->ib_uc_qpns_bitmap =
  1979. kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
  1980. sizeof(long),
  1981. GFP_KERNEL);
  1982. if (!ibdev->ib_uc_qpns_bitmap) {
  1983. dev_err(&dev->persist->pdev->dev,
  1984. "bit map alloc failed\n");
  1985. goto err_steer_qp_release;
  1986. }
  1987. bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
  1988. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  1989. dev, ibdev->steer_qpn_base,
  1990. ibdev->steer_qpn_base +
  1991. ibdev->steer_qpn_count - 1);
  1992. if (err)
  1993. goto err_steer_free_bitmap;
  1994. }
  1995. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  1996. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  1997. if (ib_register_device(&ibdev->ib_dev, NULL))
  1998. goto err_steer_free_bitmap;
  1999. if (mlx4_ib_mad_init(ibdev))
  2000. goto err_reg;
  2001. if (mlx4_ib_init_sriov(ibdev))
  2002. goto err_mad;
  2003. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
  2004. if (!iboe->nb.notifier_call) {
  2005. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2006. err = register_netdevice_notifier(&iboe->nb);
  2007. if (err) {
  2008. iboe->nb.notifier_call = NULL;
  2009. goto err_notif;
  2010. }
  2011. }
  2012. }
  2013. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2014. if (device_create_file(&ibdev->ib_dev.dev,
  2015. mlx4_class_attributes[j]))
  2016. goto err_notif;
  2017. }
  2018. ibdev->ib_active = true;
  2019. if (mlx4_is_mfunc(ibdev->dev))
  2020. init_pkeys(ibdev);
  2021. /* create paravirt contexts for any VFs which are active */
  2022. if (mlx4_is_master(ibdev->dev)) {
  2023. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2024. if (j == mlx4_master_func_num(ibdev->dev))
  2025. continue;
  2026. if (mlx4_is_slave_active(ibdev->dev, j))
  2027. do_slave_init(ibdev, j, 1);
  2028. }
  2029. }
  2030. return ibdev;
  2031. err_notif:
  2032. if (ibdev->iboe.nb.notifier_call) {
  2033. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2034. pr_warn("failure unregistering notifier\n");
  2035. ibdev->iboe.nb.notifier_call = NULL;
  2036. }
  2037. flush_workqueue(wq);
  2038. mlx4_ib_close_sriov(ibdev);
  2039. err_mad:
  2040. mlx4_ib_mad_cleanup(ibdev);
  2041. err_reg:
  2042. ib_unregister_device(&ibdev->ib_dev);
  2043. err_steer_free_bitmap:
  2044. kfree(ibdev->ib_uc_qpns_bitmap);
  2045. err_steer_qp_release:
  2046. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  2047. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2048. ibdev->steer_qpn_count);
  2049. err_counter:
  2050. for (i = 0; i < ibdev->num_ports; ++i) {
  2051. if (ibdev->counters[i].index != -1 &&
  2052. ibdev->counters[i].allocated)
  2053. mlx4_counter_free(ibdev->dev,
  2054. ibdev->counters[i].index);
  2055. }
  2056. err_map:
  2057. iounmap(ibdev->uar_map);
  2058. err_uar:
  2059. mlx4_uar_free(dev, &ibdev->priv_uar);
  2060. err_pd:
  2061. mlx4_pd_free(dev, ibdev->priv_pdn);
  2062. err_dealloc:
  2063. ib_dealloc_device(&ibdev->ib_dev);
  2064. return NULL;
  2065. }
  2066. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2067. {
  2068. int offset;
  2069. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2070. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2071. dev->steer_qpn_count,
  2072. get_count_order(count));
  2073. if (offset < 0)
  2074. return offset;
  2075. *qpn = dev->steer_qpn_base + offset;
  2076. return 0;
  2077. }
  2078. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2079. {
  2080. if (!qpn ||
  2081. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2082. return;
  2083. BUG_ON(qpn < dev->steer_qpn_base);
  2084. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2085. qpn - dev->steer_qpn_base,
  2086. get_count_order(count));
  2087. }
  2088. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2089. int is_attach)
  2090. {
  2091. int err;
  2092. size_t flow_size;
  2093. struct ib_flow_attr *flow = NULL;
  2094. struct ib_flow_spec_ib *ib_spec;
  2095. if (is_attach) {
  2096. flow_size = sizeof(struct ib_flow_attr) +
  2097. sizeof(struct ib_flow_spec_ib);
  2098. flow = kzalloc(flow_size, GFP_KERNEL);
  2099. if (!flow)
  2100. return -ENOMEM;
  2101. flow->port = mqp->port;
  2102. flow->num_of_specs = 1;
  2103. flow->size = flow_size;
  2104. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2105. ib_spec->type = IB_FLOW_SPEC_IB;
  2106. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2107. /* Add an empty rule for IB L2 */
  2108. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2109. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2110. IB_FLOW_DOMAIN_NIC,
  2111. MLX4_FS_REGULAR,
  2112. &mqp->reg_id);
  2113. } else {
  2114. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2115. }
  2116. kfree(flow);
  2117. return err;
  2118. }
  2119. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2120. {
  2121. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2122. int p;
  2123. ibdev->ib_active = false;
  2124. flush_workqueue(wq);
  2125. mlx4_ib_close_sriov(ibdev);
  2126. mlx4_ib_mad_cleanup(ibdev);
  2127. ib_unregister_device(&ibdev->ib_dev);
  2128. if (ibdev->iboe.nb.notifier_call) {
  2129. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2130. pr_warn("failure unregistering notifier\n");
  2131. ibdev->iboe.nb.notifier_call = NULL;
  2132. }
  2133. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
  2134. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2135. ibdev->steer_qpn_count);
  2136. kfree(ibdev->ib_uc_qpns_bitmap);
  2137. }
  2138. iounmap(ibdev->uar_map);
  2139. for (p = 0; p < ibdev->num_ports; ++p)
  2140. if (ibdev->counters[p].index != -1 &&
  2141. ibdev->counters[p].allocated)
  2142. mlx4_counter_free(ibdev->dev, ibdev->counters[p].index);
  2143. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2144. mlx4_CLOSE_PORT(dev, p);
  2145. mlx4_ib_free_eqs(dev, ibdev);
  2146. mlx4_uar_free(dev, &ibdev->priv_uar);
  2147. mlx4_pd_free(dev, ibdev->priv_pdn);
  2148. ib_dealloc_device(&ibdev->ib_dev);
  2149. }
  2150. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2151. {
  2152. struct mlx4_ib_demux_work **dm = NULL;
  2153. struct mlx4_dev *dev = ibdev->dev;
  2154. int i;
  2155. unsigned long flags;
  2156. struct mlx4_active_ports actv_ports;
  2157. unsigned int ports;
  2158. unsigned int first_port;
  2159. if (!mlx4_is_master(dev))
  2160. return;
  2161. actv_ports = mlx4_get_active_ports(dev, slave);
  2162. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2163. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2164. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2165. if (!dm) {
  2166. pr_err("failed to allocate memory for tunneling qp update\n");
  2167. return;
  2168. }
  2169. for (i = 0; i < ports; i++) {
  2170. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2171. if (!dm[i]) {
  2172. pr_err("failed to allocate memory for tunneling qp update work struct\n");
  2173. while (--i >= 0)
  2174. kfree(dm[i]);
  2175. goto out;
  2176. }
  2177. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2178. dm[i]->port = first_port + i + 1;
  2179. dm[i]->slave = slave;
  2180. dm[i]->do_init = do_init;
  2181. dm[i]->dev = ibdev;
  2182. }
  2183. /* initialize or tear down tunnel QPs for the slave */
  2184. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2185. if (!ibdev->sriov.is_going_down) {
  2186. for (i = 0; i < ports; i++)
  2187. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2188. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2189. } else {
  2190. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2191. for (i = 0; i < ports; i++)
  2192. kfree(dm[i]);
  2193. }
  2194. out:
  2195. kfree(dm);
  2196. return;
  2197. }
  2198. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2199. {
  2200. struct mlx4_ib_qp *mqp;
  2201. unsigned long flags_qp;
  2202. unsigned long flags_cq;
  2203. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2204. struct list_head cq_notify_list;
  2205. struct mlx4_cq *mcq;
  2206. unsigned long flags;
  2207. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2208. INIT_LIST_HEAD(&cq_notify_list);
  2209. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2210. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2211. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2212. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2213. if (mqp->sq.tail != mqp->sq.head) {
  2214. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2215. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2216. if (send_mcq->mcq.comp &&
  2217. mqp->ibqp.send_cq->comp_handler) {
  2218. if (!send_mcq->mcq.reset_notify_added) {
  2219. send_mcq->mcq.reset_notify_added = 1;
  2220. list_add_tail(&send_mcq->mcq.reset_notify,
  2221. &cq_notify_list);
  2222. }
  2223. }
  2224. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2225. }
  2226. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2227. /* Now, handle the QP's receive queue */
  2228. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2229. /* no handling is needed for SRQ */
  2230. if (!mqp->ibqp.srq) {
  2231. if (mqp->rq.tail != mqp->rq.head) {
  2232. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2233. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2234. if (recv_mcq->mcq.comp &&
  2235. mqp->ibqp.recv_cq->comp_handler) {
  2236. if (!recv_mcq->mcq.reset_notify_added) {
  2237. recv_mcq->mcq.reset_notify_added = 1;
  2238. list_add_tail(&recv_mcq->mcq.reset_notify,
  2239. &cq_notify_list);
  2240. }
  2241. }
  2242. spin_unlock_irqrestore(&recv_mcq->lock,
  2243. flags_cq);
  2244. }
  2245. }
  2246. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2247. }
  2248. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2249. mcq->comp(mcq);
  2250. }
  2251. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2252. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2253. }
  2254. static void handle_bonded_port_state_event(struct work_struct *work)
  2255. {
  2256. struct ib_event_work *ew =
  2257. container_of(work, struct ib_event_work, work);
  2258. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2259. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2260. int i;
  2261. struct ib_event ibev;
  2262. kfree(ew);
  2263. spin_lock_bh(&ibdev->iboe.lock);
  2264. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2265. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2266. enum ib_port_state curr_port_state;
  2267. if (!curr_netdev)
  2268. continue;
  2269. curr_port_state =
  2270. (netif_running(curr_netdev) &&
  2271. netif_carrier_ok(curr_netdev)) ?
  2272. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2273. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2274. curr_port_state : IB_PORT_ACTIVE;
  2275. }
  2276. spin_unlock_bh(&ibdev->iboe.lock);
  2277. ibev.device = &ibdev->ib_dev;
  2278. ibev.element.port_num = 1;
  2279. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2280. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2281. ib_dispatch_event(&ibev);
  2282. }
  2283. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2284. enum mlx4_dev_event event, unsigned long param)
  2285. {
  2286. struct ib_event ibev;
  2287. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2288. struct mlx4_eqe *eqe = NULL;
  2289. struct ib_event_work *ew;
  2290. int p = 0;
  2291. if (mlx4_is_bonded(dev) &&
  2292. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2293. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2294. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2295. if (!ew)
  2296. return;
  2297. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2298. ew->ib_dev = ibdev;
  2299. queue_work(wq, &ew->work);
  2300. return;
  2301. }
  2302. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2303. eqe = (struct mlx4_eqe *)param;
  2304. else
  2305. p = (int) param;
  2306. switch (event) {
  2307. case MLX4_DEV_EVENT_PORT_UP:
  2308. if (p > ibdev->num_ports)
  2309. return;
  2310. if (mlx4_is_master(dev) &&
  2311. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2312. IB_LINK_LAYER_INFINIBAND) {
  2313. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2314. }
  2315. ibev.event = IB_EVENT_PORT_ACTIVE;
  2316. break;
  2317. case MLX4_DEV_EVENT_PORT_DOWN:
  2318. if (p > ibdev->num_ports)
  2319. return;
  2320. ibev.event = IB_EVENT_PORT_ERR;
  2321. break;
  2322. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2323. ibdev->ib_active = false;
  2324. ibev.event = IB_EVENT_DEVICE_FATAL;
  2325. mlx4_ib_handle_catas_error(ibdev);
  2326. break;
  2327. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2328. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2329. if (!ew) {
  2330. pr_err("failed to allocate memory for events work\n");
  2331. break;
  2332. }
  2333. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2334. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2335. ew->ib_dev = ibdev;
  2336. /* need to queue only for port owner, which uses GEN_EQE */
  2337. if (mlx4_is_master(dev))
  2338. queue_work(wq, &ew->work);
  2339. else
  2340. handle_port_mgmt_change_event(&ew->work);
  2341. return;
  2342. case MLX4_DEV_EVENT_SLAVE_INIT:
  2343. /* here, p is the slave id */
  2344. do_slave_init(ibdev, p, 1);
  2345. if (mlx4_is_master(dev)) {
  2346. int i;
  2347. for (i = 1; i <= ibdev->num_ports; i++) {
  2348. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2349. == IB_LINK_LAYER_INFINIBAND)
  2350. mlx4_ib_slave_alias_guid_event(ibdev,
  2351. p, i,
  2352. 1);
  2353. }
  2354. }
  2355. return;
  2356. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2357. if (mlx4_is_master(dev)) {
  2358. int i;
  2359. for (i = 1; i <= ibdev->num_ports; i++) {
  2360. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2361. == IB_LINK_LAYER_INFINIBAND)
  2362. mlx4_ib_slave_alias_guid_event(ibdev,
  2363. p, i,
  2364. 0);
  2365. }
  2366. }
  2367. /* here, p is the slave id */
  2368. do_slave_init(ibdev, p, 0);
  2369. return;
  2370. default:
  2371. return;
  2372. }
  2373. ibev.device = ibdev_ptr;
  2374. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2375. ib_dispatch_event(&ibev);
  2376. }
  2377. static struct mlx4_interface mlx4_ib_interface = {
  2378. .add = mlx4_ib_add,
  2379. .remove = mlx4_ib_remove,
  2380. .event = mlx4_ib_event,
  2381. .protocol = MLX4_PROT_IB_IPV6,
  2382. .flags = MLX4_INTFF_BONDING
  2383. };
  2384. static int __init mlx4_ib_init(void)
  2385. {
  2386. int err;
  2387. wq = create_singlethread_workqueue("mlx4_ib");
  2388. if (!wq)
  2389. return -ENOMEM;
  2390. err = mlx4_ib_mcg_init();
  2391. if (err)
  2392. goto clean_wq;
  2393. err = mlx4_register_interface(&mlx4_ib_interface);
  2394. if (err)
  2395. goto clean_mcg;
  2396. return 0;
  2397. clean_mcg:
  2398. mlx4_ib_mcg_destroy();
  2399. clean_wq:
  2400. destroy_workqueue(wq);
  2401. return err;
  2402. }
  2403. static void __exit mlx4_ib_cleanup(void)
  2404. {
  2405. mlx4_unregister_interface(&mlx4_ib_interface);
  2406. mlx4_ib_mcg_destroy();
  2407. destroy_workqueue(wq);
  2408. }
  2409. module_init(mlx4_ib_init);
  2410. module_exit(mlx4_ib_cleanup);