base.c 4.1 KB

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  1. /*
  2. * Copyright 2015 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs <bskeggs@redhat.com>
  23. */
  24. #include "priv.h"
  25. #include "agp.h"
  26. #include <core/option.h>
  27. #include <core/pci.h>
  28. #include <subdev/mc.h>
  29. u32
  30. nvkm_pci_rd32(struct nvkm_pci *pci, u16 addr)
  31. {
  32. return pci->func->rd32(pci, addr);
  33. }
  34. void
  35. nvkm_pci_wr08(struct nvkm_pci *pci, u16 addr, u8 data)
  36. {
  37. pci->func->wr08(pci, addr, data);
  38. }
  39. void
  40. nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data)
  41. {
  42. pci->func->wr32(pci, addr, data);
  43. }
  44. void
  45. nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
  46. {
  47. u32 data = nvkm_pci_rd32(pci, 0x0050);
  48. if (shadow)
  49. data |= 0x00000001;
  50. else
  51. data &= ~0x00000001;
  52. nvkm_pci_wr32(pci, 0x0050, data);
  53. }
  54. static irqreturn_t
  55. nvkm_pci_intr(int irq, void *arg)
  56. {
  57. struct nvkm_pci *pci = arg;
  58. struct nvkm_mc *mc = pci->subdev.device->mc;
  59. bool handled = false;
  60. if (likely(mc)) {
  61. nvkm_mc_intr_unarm(mc);
  62. if (pci->msi)
  63. pci->func->msi_rearm(pci);
  64. nvkm_mc_intr(mc, &handled);
  65. nvkm_mc_intr_rearm(mc);
  66. }
  67. return handled ? IRQ_HANDLED : IRQ_NONE;
  68. }
  69. static int
  70. nvkm_pci_fini(struct nvkm_subdev *subdev, bool suspend)
  71. {
  72. struct nvkm_pci *pci = nvkm_pci(subdev);
  73. if (pci->irq >= 0) {
  74. free_irq(pci->irq, pci);
  75. pci->irq = -1;
  76. };
  77. if (pci->agp.bridge)
  78. nvkm_agp_fini(pci);
  79. return 0;
  80. }
  81. static int
  82. nvkm_pci_preinit(struct nvkm_subdev *subdev)
  83. {
  84. struct nvkm_pci *pci = nvkm_pci(subdev);
  85. if (pci->agp.bridge)
  86. nvkm_agp_preinit(pci);
  87. return 0;
  88. }
  89. static int
  90. nvkm_pci_init(struct nvkm_subdev *subdev)
  91. {
  92. struct nvkm_pci *pci = nvkm_pci(subdev);
  93. struct pci_dev *pdev = pci->pdev;
  94. int ret;
  95. if (pci->agp.bridge) {
  96. ret = nvkm_agp_init(pci);
  97. if (ret)
  98. return ret;
  99. }
  100. ret = request_irq(pdev->irq, nvkm_pci_intr, IRQF_SHARED, "nvkm", pci);
  101. if (ret)
  102. return ret;
  103. pci->irq = pdev->irq;
  104. return ret;
  105. }
  106. static void *
  107. nvkm_pci_dtor(struct nvkm_subdev *subdev)
  108. {
  109. struct nvkm_pci *pci = nvkm_pci(subdev);
  110. nvkm_agp_dtor(pci);
  111. if (pci->msi)
  112. pci_disable_msi(pci->pdev);
  113. return nvkm_pci(subdev);
  114. }
  115. static const struct nvkm_subdev_func
  116. nvkm_pci_func = {
  117. .dtor = nvkm_pci_dtor,
  118. .preinit = nvkm_pci_preinit,
  119. .init = nvkm_pci_init,
  120. .fini = nvkm_pci_fini,
  121. };
  122. int
  123. nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device,
  124. int index, struct nvkm_pci **ppci)
  125. {
  126. struct nvkm_pci *pci;
  127. if (!(pci = *ppci = kzalloc(sizeof(**ppci), GFP_KERNEL)))
  128. return -ENOMEM;
  129. nvkm_subdev_ctor(&nvkm_pci_func, device, index, 0, &pci->subdev);
  130. pci->func = func;
  131. pci->pdev = device->func->pci(device)->pdev;
  132. pci->irq = -1;
  133. if (device->type == NVKM_DEVICE_AGP)
  134. nvkm_agp_ctor(pci);
  135. switch (pci->pdev->device & 0x0ff0) {
  136. case 0x00f0:
  137. case 0x02e0:
  138. /* BR02? NFI how these would be handled yet exactly */
  139. break;
  140. default:
  141. switch (device->chipset) {
  142. case 0xaa:
  143. /* reported broken, nv also disable it */
  144. break;
  145. default:
  146. pci->msi = true;
  147. break;
  148. }
  149. }
  150. pci->msi = nvkm_boolopt(device->cfgopt, "NvMSI", pci->msi);
  151. if (pci->msi && func->msi_rearm) {
  152. pci->msi = pci_enable_msi(pci->pdev) == 0;
  153. if (pci->msi)
  154. nvkm_debug(&pci->subdev, "MSI enabled\n");
  155. } else {
  156. pci->msi = false;
  157. }
  158. return 0;
  159. }