cpufeature.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102
  1. /*
  2. * Contains CPU feature definitions
  3. *
  4. * Copyright (C) 2015 ARM Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "alternatives: " fmt
  19. #include <linux/types.h>
  20. #include <asm/cpu.h>
  21. #include <asm/cpufeature.h>
  22. #include <asm/processor.h>
  23. static bool
  24. feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
  25. {
  26. int val = cpuid_feature_extract_field(reg, entry->field_pos);
  27. return val >= entry->min_field_value;
  28. }
  29. #define __ID_FEAT_CHK(reg) \
  30. static bool __maybe_unused \
  31. has_##reg##_feature(const struct arm64_cpu_capabilities *entry) \
  32. { \
  33. u64 val; \
  34. \
  35. val = read_cpuid(reg##_el1); \
  36. return feature_matches(val, entry); \
  37. }
  38. __ID_FEAT_CHK(id_aa64pfr0);
  39. __ID_FEAT_CHK(id_aa64mmfr1);
  40. __ID_FEAT_CHK(id_aa64isar0);
  41. static const struct arm64_cpu_capabilities arm64_features[] = {
  42. {
  43. .desc = "GIC system register CPU interface",
  44. .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
  45. .matches = has_id_aa64pfr0_feature,
  46. .field_pos = 24,
  47. .min_field_value = 1,
  48. },
  49. #ifdef CONFIG_ARM64_PAN
  50. {
  51. .desc = "Privileged Access Never",
  52. .capability = ARM64_HAS_PAN,
  53. .matches = has_id_aa64mmfr1_feature,
  54. .field_pos = 20,
  55. .min_field_value = 1,
  56. .enable = cpu_enable_pan,
  57. },
  58. #endif /* CONFIG_ARM64_PAN */
  59. #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
  60. {
  61. .desc = "LSE atomic instructions",
  62. .capability = ARM64_HAS_LSE_ATOMICS,
  63. .matches = has_id_aa64isar0_feature,
  64. .field_pos = 20,
  65. .min_field_value = 2,
  66. },
  67. #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
  68. {},
  69. };
  70. void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
  71. const char *info)
  72. {
  73. int i;
  74. for (i = 0; caps[i].desc; i++) {
  75. if (!caps[i].matches(&caps[i]))
  76. continue;
  77. if (!cpus_have_cap(caps[i].capability))
  78. pr_info("%s %s\n", info, caps[i].desc);
  79. cpus_set_cap(caps[i].capability);
  80. }
  81. /* second pass allows enable() to consider interacting capabilities */
  82. for (i = 0; caps[i].desc; i++) {
  83. if (cpus_have_cap(caps[i].capability) && caps[i].enable)
  84. caps[i].enable();
  85. }
  86. }
  87. void check_local_cpu_features(void)
  88. {
  89. check_cpu_capabilities(arm64_features, "detected feature:");
  90. }