devices.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218
  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <mach/udc.h>
  9. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  10. #include <linux/platform_data/video-pxafb.h>
  11. #include <linux/platform_data/mmc-pxamci.h>
  12. #include <linux/platform_data/irda-pxaficp.h>
  13. #include <mach/irqs.h>
  14. #include <linux/platform_data/usb-ohci-pxa27x.h>
  15. #include <linux/platform_data/keypad-pxa27x.h>
  16. #include <linux/platform_data/camera-pxa.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <linux/platform_data/mmp_dma.h>
  20. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  21. #include "devices.h"
  22. #include "generic.h"
  23. void __init pxa_register_device(struct platform_device *dev, void *data)
  24. {
  25. int ret;
  26. dev->dev.platform_data = data;
  27. ret = platform_device_register(dev);
  28. if (ret)
  29. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  30. }
  31. static struct resource pxa_resource_pmu = {
  32. .start = IRQ_PMU,
  33. .end = IRQ_PMU,
  34. .flags = IORESOURCE_IRQ,
  35. };
  36. struct platform_device pxa_device_pmu = {
  37. .name = "xscale-pmu",
  38. .id = -1,
  39. .resource = &pxa_resource_pmu,
  40. .num_resources = 1,
  41. };
  42. static struct resource pxamci_resources[] = {
  43. [0] = {
  44. .start = 0x41100000,
  45. .end = 0x41100fff,
  46. .flags = IORESOURCE_MEM,
  47. },
  48. [1] = {
  49. .start = IRQ_MMC,
  50. .end = IRQ_MMC,
  51. .flags = IORESOURCE_IRQ,
  52. },
  53. [2] = {
  54. .start = 21,
  55. .end = 21,
  56. .flags = IORESOURCE_DMA,
  57. },
  58. [3] = {
  59. .start = 22,
  60. .end = 22,
  61. .flags = IORESOURCE_DMA,
  62. },
  63. };
  64. static u64 pxamci_dmamask = 0xffffffffUL;
  65. struct platform_device pxa_device_mci = {
  66. .name = "pxa2xx-mci",
  67. .id = 0,
  68. .dev = {
  69. .dma_mask = &pxamci_dmamask,
  70. .coherent_dma_mask = 0xffffffff,
  71. },
  72. .num_resources = ARRAY_SIZE(pxamci_resources),
  73. .resource = pxamci_resources,
  74. };
  75. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  76. {
  77. pxa_register_device(&pxa_device_mci, info);
  78. }
  79. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  80. .gpio_pullup = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  167. {
  168. pxa_device_fb.dev.parent = parent;
  169. pxa_register_device(&pxa_device_fb, info);
  170. }
  171. static struct resource pxa_resource_ffuart[] = {
  172. {
  173. .start = 0x40100000,
  174. .end = 0x40100023,
  175. .flags = IORESOURCE_MEM,
  176. }, {
  177. .start = IRQ_FFUART,
  178. .end = IRQ_FFUART,
  179. .flags = IORESOURCE_IRQ,
  180. }
  181. };
  182. struct platform_device pxa_device_ffuart = {
  183. .name = "pxa2xx-uart",
  184. .id = 0,
  185. .resource = pxa_resource_ffuart,
  186. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  187. };
  188. void __init pxa_set_ffuart_info(void *info)
  189. {
  190. pxa_register_device(&pxa_device_ffuart, info);
  191. }
  192. static struct resource pxa_resource_btuart[] = {
  193. {
  194. .start = 0x40200000,
  195. .end = 0x40200023,
  196. .flags = IORESOURCE_MEM,
  197. }, {
  198. .start = IRQ_BTUART,
  199. .end = IRQ_BTUART,
  200. .flags = IORESOURCE_IRQ,
  201. }
  202. };
  203. struct platform_device pxa_device_btuart = {
  204. .name = "pxa2xx-uart",
  205. .id = 1,
  206. .resource = pxa_resource_btuart,
  207. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  208. };
  209. void __init pxa_set_btuart_info(void *info)
  210. {
  211. pxa_register_device(&pxa_device_btuart, info);
  212. }
  213. static struct resource pxa_resource_stuart[] = {
  214. {
  215. .start = 0x40700000,
  216. .end = 0x40700023,
  217. .flags = IORESOURCE_MEM,
  218. }, {
  219. .start = IRQ_STUART,
  220. .end = IRQ_STUART,
  221. .flags = IORESOURCE_IRQ,
  222. }
  223. };
  224. struct platform_device pxa_device_stuart = {
  225. .name = "pxa2xx-uart",
  226. .id = 2,
  227. .resource = pxa_resource_stuart,
  228. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  229. };
  230. void __init pxa_set_stuart_info(void *info)
  231. {
  232. pxa_register_device(&pxa_device_stuart, info);
  233. }
  234. static struct resource pxa_resource_hwuart[] = {
  235. {
  236. .start = 0x41600000,
  237. .end = 0x4160002F,
  238. .flags = IORESOURCE_MEM,
  239. }, {
  240. .start = IRQ_HWUART,
  241. .end = IRQ_HWUART,
  242. .flags = IORESOURCE_IRQ,
  243. }
  244. };
  245. struct platform_device pxa_device_hwuart = {
  246. .name = "pxa2xx-uart",
  247. .id = 3,
  248. .resource = pxa_resource_hwuart,
  249. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  250. };
  251. void __init pxa_set_hwuart_info(void *info)
  252. {
  253. if (cpu_is_pxa255())
  254. pxa_register_device(&pxa_device_hwuart, info);
  255. else
  256. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  257. }
  258. static struct resource pxai2c_resources[] = {
  259. {
  260. .start = 0x40301680,
  261. .end = 0x403016a3,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = IRQ_I2C,
  265. .end = IRQ_I2C,
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. struct platform_device pxa_device_i2c = {
  270. .name = "pxa2xx-i2c",
  271. .id = 0,
  272. .resource = pxai2c_resources,
  273. .num_resources = ARRAY_SIZE(pxai2c_resources),
  274. };
  275. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  276. {
  277. pxa_register_device(&pxa_device_i2c, info);
  278. }
  279. #ifdef CONFIG_PXA27x
  280. static struct resource pxa27x_resources_i2c_power[] = {
  281. {
  282. .start = 0x40f00180,
  283. .end = 0x40f001a3,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = IRQ_PWRI2C,
  287. .end = IRQ_PWRI2C,
  288. .flags = IORESOURCE_IRQ,
  289. },
  290. };
  291. struct platform_device pxa27x_device_i2c_power = {
  292. .name = "pxa2xx-i2c",
  293. .id = 1,
  294. .resource = pxa27x_resources_i2c_power,
  295. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  296. };
  297. #endif
  298. static struct resource pxai2s_resources[] = {
  299. {
  300. .start = 0x40400000,
  301. .end = 0x40400083,
  302. .flags = IORESOURCE_MEM,
  303. }, {
  304. .start = IRQ_I2S,
  305. .end = IRQ_I2S,
  306. .flags = IORESOURCE_IRQ,
  307. },
  308. };
  309. struct platform_device pxa_device_i2s = {
  310. .name = "pxa2xx-i2s",
  311. .id = -1,
  312. .resource = pxai2s_resources,
  313. .num_resources = ARRAY_SIZE(pxai2s_resources),
  314. };
  315. struct platform_device pxa_device_asoc_ssp1 = {
  316. .name = "pxa-ssp-dai",
  317. .id = 0,
  318. };
  319. struct platform_device pxa_device_asoc_ssp2= {
  320. .name = "pxa-ssp-dai",
  321. .id = 1,
  322. };
  323. struct platform_device pxa_device_asoc_ssp3 = {
  324. .name = "pxa-ssp-dai",
  325. .id = 2,
  326. };
  327. struct platform_device pxa_device_asoc_ssp4 = {
  328. .name = "pxa-ssp-dai",
  329. .id = 3,
  330. };
  331. struct platform_device pxa_device_asoc_platform = {
  332. .name = "pxa-pcm-audio",
  333. .id = -1,
  334. };
  335. static u64 pxaficp_dmamask = ~(u32)0;
  336. static struct resource pxa_ir_resources[] = {
  337. [0] = {
  338. .start = IRQ_STUART,
  339. .end = IRQ_STUART,
  340. .flags = IORESOURCE_IRQ,
  341. },
  342. [1] = {
  343. .start = IRQ_ICP,
  344. .end = IRQ_ICP,
  345. .flags = IORESOURCE_IRQ,
  346. },
  347. };
  348. struct platform_device pxa_device_ficp = {
  349. .name = "pxa2xx-ir",
  350. .id = -1,
  351. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  352. .resource = pxa_ir_resources,
  353. .dev = {
  354. .dma_mask = &pxaficp_dmamask,
  355. .coherent_dma_mask = 0xffffffff,
  356. },
  357. };
  358. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  359. {
  360. pxa_register_device(&pxa_device_ficp, info);
  361. }
  362. static struct resource pxa_rtc_resources[] = {
  363. [0] = {
  364. .start = 0x40900000,
  365. .end = 0x40900000 + 0x3b,
  366. .flags = IORESOURCE_MEM,
  367. },
  368. [1] = {
  369. .start = IRQ_RTC1Hz,
  370. .end = IRQ_RTC1Hz,
  371. .name = "rtc 1Hz",
  372. .flags = IORESOURCE_IRQ,
  373. },
  374. [2] = {
  375. .start = IRQ_RTCAlrm,
  376. .end = IRQ_RTCAlrm,
  377. .name = "rtc alarm",
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. };
  381. struct platform_device pxa_device_rtc = {
  382. .name = "pxa-rtc",
  383. .id = -1,
  384. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  385. .resource = pxa_rtc_resources,
  386. };
  387. struct platform_device sa1100_device_rtc = {
  388. .name = "sa1100-rtc",
  389. .id = -1,
  390. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  391. .resource = pxa_rtc_resources,
  392. };
  393. static struct resource pxa_ac97_resources[] = {
  394. [0] = {
  395. .start = 0x40500000,
  396. .end = 0x40500000 + 0xfff,
  397. .flags = IORESOURCE_MEM,
  398. },
  399. [1] = {
  400. .start = IRQ_AC97,
  401. .end = IRQ_AC97,
  402. .flags = IORESOURCE_IRQ,
  403. },
  404. };
  405. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  406. struct platform_device pxa_device_ac97 = {
  407. .name = "pxa2xx-ac97",
  408. .id = -1,
  409. .dev = {
  410. .dma_mask = &pxa_ac97_dmamask,
  411. .coherent_dma_mask = 0xffffffff,
  412. },
  413. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  414. .resource = pxa_ac97_resources,
  415. };
  416. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  417. {
  418. pxa_register_device(&pxa_device_ac97, ops);
  419. }
  420. #ifdef CONFIG_PXA25x
  421. static struct resource pxa25x_resource_pwm0[] = {
  422. [0] = {
  423. .start = 0x40b00000,
  424. .end = 0x40b0000f,
  425. .flags = IORESOURCE_MEM,
  426. },
  427. };
  428. struct platform_device pxa25x_device_pwm0 = {
  429. .name = "pxa25x-pwm",
  430. .id = 0,
  431. .resource = pxa25x_resource_pwm0,
  432. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  433. };
  434. static struct resource pxa25x_resource_pwm1[] = {
  435. [0] = {
  436. .start = 0x40c00000,
  437. .end = 0x40c0000f,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. };
  441. struct platform_device pxa25x_device_pwm1 = {
  442. .name = "pxa25x-pwm",
  443. .id = 1,
  444. .resource = pxa25x_resource_pwm1,
  445. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  446. };
  447. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  448. static struct resource pxa25x_resource_ssp[] = {
  449. [0] = {
  450. .start = 0x41000000,
  451. .end = 0x4100001f,
  452. .flags = IORESOURCE_MEM,
  453. },
  454. [1] = {
  455. .start = IRQ_SSP,
  456. .end = IRQ_SSP,
  457. .flags = IORESOURCE_IRQ,
  458. },
  459. [2] = {
  460. /* DRCMR for RX */
  461. .start = 13,
  462. .end = 13,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. [3] = {
  466. /* DRCMR for TX */
  467. .start = 14,
  468. .end = 14,
  469. .flags = IORESOURCE_DMA,
  470. },
  471. };
  472. struct platform_device pxa25x_device_ssp = {
  473. .name = "pxa25x-ssp",
  474. .id = 0,
  475. .dev = {
  476. .dma_mask = &pxa25x_ssp_dma_mask,
  477. .coherent_dma_mask = DMA_BIT_MASK(32),
  478. },
  479. .resource = pxa25x_resource_ssp,
  480. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  481. };
  482. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  483. static struct resource pxa25x_resource_nssp[] = {
  484. [0] = {
  485. .start = 0x41400000,
  486. .end = 0x4140002f,
  487. .flags = IORESOURCE_MEM,
  488. },
  489. [1] = {
  490. .start = IRQ_NSSP,
  491. .end = IRQ_NSSP,
  492. .flags = IORESOURCE_IRQ,
  493. },
  494. [2] = {
  495. /* DRCMR for RX */
  496. .start = 15,
  497. .end = 15,
  498. .flags = IORESOURCE_DMA,
  499. },
  500. [3] = {
  501. /* DRCMR for TX */
  502. .start = 16,
  503. .end = 16,
  504. .flags = IORESOURCE_DMA,
  505. },
  506. };
  507. struct platform_device pxa25x_device_nssp = {
  508. .name = "pxa25x-nssp",
  509. .id = 1,
  510. .dev = {
  511. .dma_mask = &pxa25x_nssp_dma_mask,
  512. .coherent_dma_mask = DMA_BIT_MASK(32),
  513. },
  514. .resource = pxa25x_resource_nssp,
  515. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  516. };
  517. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  518. static struct resource pxa25x_resource_assp[] = {
  519. [0] = {
  520. .start = 0x41500000,
  521. .end = 0x4150002f,
  522. .flags = IORESOURCE_MEM,
  523. },
  524. [1] = {
  525. .start = IRQ_ASSP,
  526. .end = IRQ_ASSP,
  527. .flags = IORESOURCE_IRQ,
  528. },
  529. [2] = {
  530. /* DRCMR for RX */
  531. .start = 23,
  532. .end = 23,
  533. .flags = IORESOURCE_DMA,
  534. },
  535. [3] = {
  536. /* DRCMR for TX */
  537. .start = 24,
  538. .end = 24,
  539. .flags = IORESOURCE_DMA,
  540. },
  541. };
  542. struct platform_device pxa25x_device_assp = {
  543. /* ASSP is basically equivalent to NSSP */
  544. .name = "pxa25x-nssp",
  545. .id = 2,
  546. .dev = {
  547. .dma_mask = &pxa25x_assp_dma_mask,
  548. .coherent_dma_mask = DMA_BIT_MASK(32),
  549. },
  550. .resource = pxa25x_resource_assp,
  551. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  552. };
  553. #endif /* CONFIG_PXA25x */
  554. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  555. static struct resource pxa27x_resource_camera[] = {
  556. [0] = {
  557. .start = 0x50000000,
  558. .end = 0x50000fff,
  559. .flags = IORESOURCE_MEM,
  560. },
  561. [1] = {
  562. .start = IRQ_CAMERA,
  563. .end = IRQ_CAMERA,
  564. .flags = IORESOURCE_IRQ,
  565. },
  566. };
  567. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  568. static struct platform_device pxa27x_device_camera = {
  569. .name = "pxa27x-camera",
  570. .id = 0, /* This is used to put cameras on this interface */
  571. .dev = {
  572. .dma_mask = &pxa27x_dma_mask_camera,
  573. .coherent_dma_mask = 0xffffffff,
  574. },
  575. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  576. .resource = pxa27x_resource_camera,
  577. };
  578. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  579. {
  580. pxa_register_device(&pxa27x_device_camera, info);
  581. }
  582. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  583. static struct resource pxa27x_resource_ohci[] = {
  584. [0] = {
  585. .start = 0x4C000000,
  586. .end = 0x4C00ff6f,
  587. .flags = IORESOURCE_MEM,
  588. },
  589. [1] = {
  590. .start = IRQ_USBH1,
  591. .end = IRQ_USBH1,
  592. .flags = IORESOURCE_IRQ,
  593. },
  594. };
  595. struct platform_device pxa27x_device_ohci = {
  596. .name = "pxa27x-ohci",
  597. .id = -1,
  598. .dev = {
  599. .dma_mask = &pxa27x_ohci_dma_mask,
  600. .coherent_dma_mask = DMA_BIT_MASK(32),
  601. },
  602. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  603. .resource = pxa27x_resource_ohci,
  604. };
  605. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  606. {
  607. pxa_register_device(&pxa27x_device_ohci, info);
  608. }
  609. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  610. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  611. static struct resource pxa27x_resource_keypad[] = {
  612. [0] = {
  613. .start = 0x41500000,
  614. .end = 0x4150004c,
  615. .flags = IORESOURCE_MEM,
  616. },
  617. [1] = {
  618. .start = IRQ_KEYPAD,
  619. .end = IRQ_KEYPAD,
  620. .flags = IORESOURCE_IRQ,
  621. },
  622. };
  623. struct platform_device pxa27x_device_keypad = {
  624. .name = "pxa27x-keypad",
  625. .id = -1,
  626. .resource = pxa27x_resource_keypad,
  627. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  628. };
  629. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  630. {
  631. pxa_register_device(&pxa27x_device_keypad, info);
  632. }
  633. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  634. static struct resource pxa27x_resource_ssp1[] = {
  635. [0] = {
  636. .start = 0x41000000,
  637. .end = 0x4100003f,
  638. .flags = IORESOURCE_MEM,
  639. },
  640. [1] = {
  641. .start = IRQ_SSP,
  642. .end = IRQ_SSP,
  643. .flags = IORESOURCE_IRQ,
  644. },
  645. [2] = {
  646. /* DRCMR for RX */
  647. .start = 13,
  648. .end = 13,
  649. .flags = IORESOURCE_DMA,
  650. },
  651. [3] = {
  652. /* DRCMR for TX */
  653. .start = 14,
  654. .end = 14,
  655. .flags = IORESOURCE_DMA,
  656. },
  657. };
  658. struct platform_device pxa27x_device_ssp1 = {
  659. .name = "pxa27x-ssp",
  660. .id = 0,
  661. .dev = {
  662. .dma_mask = &pxa27x_ssp1_dma_mask,
  663. .coherent_dma_mask = DMA_BIT_MASK(32),
  664. },
  665. .resource = pxa27x_resource_ssp1,
  666. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  667. };
  668. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  669. static struct resource pxa27x_resource_ssp2[] = {
  670. [0] = {
  671. .start = 0x41700000,
  672. .end = 0x4170003f,
  673. .flags = IORESOURCE_MEM,
  674. },
  675. [1] = {
  676. .start = IRQ_SSP2,
  677. .end = IRQ_SSP2,
  678. .flags = IORESOURCE_IRQ,
  679. },
  680. [2] = {
  681. /* DRCMR for RX */
  682. .start = 15,
  683. .end = 15,
  684. .flags = IORESOURCE_DMA,
  685. },
  686. [3] = {
  687. /* DRCMR for TX */
  688. .start = 16,
  689. .end = 16,
  690. .flags = IORESOURCE_DMA,
  691. },
  692. };
  693. struct platform_device pxa27x_device_ssp2 = {
  694. .name = "pxa27x-ssp",
  695. .id = 1,
  696. .dev = {
  697. .dma_mask = &pxa27x_ssp2_dma_mask,
  698. .coherent_dma_mask = DMA_BIT_MASK(32),
  699. },
  700. .resource = pxa27x_resource_ssp2,
  701. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  702. };
  703. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  704. static struct resource pxa27x_resource_ssp3[] = {
  705. [0] = {
  706. .start = 0x41900000,
  707. .end = 0x4190003f,
  708. .flags = IORESOURCE_MEM,
  709. },
  710. [1] = {
  711. .start = IRQ_SSP3,
  712. .end = IRQ_SSP3,
  713. .flags = IORESOURCE_IRQ,
  714. },
  715. [2] = {
  716. /* DRCMR for RX */
  717. .start = 66,
  718. .end = 66,
  719. .flags = IORESOURCE_DMA,
  720. },
  721. [3] = {
  722. /* DRCMR for TX */
  723. .start = 67,
  724. .end = 67,
  725. .flags = IORESOURCE_DMA,
  726. },
  727. };
  728. struct platform_device pxa27x_device_ssp3 = {
  729. .name = "pxa27x-ssp",
  730. .id = 2,
  731. .dev = {
  732. .dma_mask = &pxa27x_ssp3_dma_mask,
  733. .coherent_dma_mask = DMA_BIT_MASK(32),
  734. },
  735. .resource = pxa27x_resource_ssp3,
  736. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  737. };
  738. static struct resource pxa27x_resource_pwm0[] = {
  739. [0] = {
  740. .start = 0x40b00000,
  741. .end = 0x40b0001f,
  742. .flags = IORESOURCE_MEM,
  743. },
  744. };
  745. struct platform_device pxa27x_device_pwm0 = {
  746. .name = "pxa27x-pwm",
  747. .id = 0,
  748. .resource = pxa27x_resource_pwm0,
  749. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  750. };
  751. static struct resource pxa27x_resource_pwm1[] = {
  752. [0] = {
  753. .start = 0x40c00000,
  754. .end = 0x40c0001f,
  755. .flags = IORESOURCE_MEM,
  756. },
  757. };
  758. struct platform_device pxa27x_device_pwm1 = {
  759. .name = "pxa27x-pwm",
  760. .id = 1,
  761. .resource = pxa27x_resource_pwm1,
  762. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  763. };
  764. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  765. #ifdef CONFIG_PXA3xx
  766. static struct resource pxa3xx_resources_mci2[] = {
  767. [0] = {
  768. .start = 0x42000000,
  769. .end = 0x42000fff,
  770. .flags = IORESOURCE_MEM,
  771. },
  772. [1] = {
  773. .start = IRQ_MMC2,
  774. .end = IRQ_MMC2,
  775. .flags = IORESOURCE_IRQ,
  776. },
  777. [2] = {
  778. .start = 93,
  779. .end = 93,
  780. .flags = IORESOURCE_DMA,
  781. },
  782. [3] = {
  783. .start = 94,
  784. .end = 94,
  785. .flags = IORESOURCE_DMA,
  786. },
  787. };
  788. struct platform_device pxa3xx_device_mci2 = {
  789. .name = "pxa2xx-mci",
  790. .id = 1,
  791. .dev = {
  792. .dma_mask = &pxamci_dmamask,
  793. .coherent_dma_mask = 0xffffffff,
  794. },
  795. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  796. .resource = pxa3xx_resources_mci2,
  797. };
  798. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  799. {
  800. pxa_register_device(&pxa3xx_device_mci2, info);
  801. }
  802. static struct resource pxa3xx_resources_mci3[] = {
  803. [0] = {
  804. .start = 0x42500000,
  805. .end = 0x42500fff,
  806. .flags = IORESOURCE_MEM,
  807. },
  808. [1] = {
  809. .start = IRQ_MMC3,
  810. .end = IRQ_MMC3,
  811. .flags = IORESOURCE_IRQ,
  812. },
  813. [2] = {
  814. .start = 100,
  815. .end = 100,
  816. .flags = IORESOURCE_DMA,
  817. },
  818. [3] = {
  819. .start = 101,
  820. .end = 101,
  821. .flags = IORESOURCE_DMA,
  822. },
  823. };
  824. struct platform_device pxa3xx_device_mci3 = {
  825. .name = "pxa2xx-mci",
  826. .id = 2,
  827. .dev = {
  828. .dma_mask = &pxamci_dmamask,
  829. .coherent_dma_mask = 0xffffffff,
  830. },
  831. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  832. .resource = pxa3xx_resources_mci3,
  833. };
  834. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  835. {
  836. pxa_register_device(&pxa3xx_device_mci3, info);
  837. }
  838. static struct resource pxa3xx_resources_gcu[] = {
  839. {
  840. .start = 0x54000000,
  841. .end = 0x54000fff,
  842. .flags = IORESOURCE_MEM,
  843. },
  844. {
  845. .start = IRQ_GCU,
  846. .end = IRQ_GCU,
  847. .flags = IORESOURCE_IRQ,
  848. },
  849. };
  850. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  851. struct platform_device pxa3xx_device_gcu = {
  852. .name = "pxa3xx-gcu",
  853. .id = -1,
  854. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  855. .resource = pxa3xx_resources_gcu,
  856. .dev = {
  857. .dma_mask = &pxa3xx_gcu_dmamask,
  858. .coherent_dma_mask = 0xffffffff,
  859. },
  860. };
  861. #endif /* CONFIG_PXA3xx */
  862. #if defined(CONFIG_PXA3xx)
  863. static struct resource pxa3xx_resources_i2c_power[] = {
  864. {
  865. .start = 0x40f500c0,
  866. .end = 0x40f500d3,
  867. .flags = IORESOURCE_MEM,
  868. }, {
  869. .start = IRQ_PWRI2C,
  870. .end = IRQ_PWRI2C,
  871. .flags = IORESOURCE_IRQ,
  872. },
  873. };
  874. struct platform_device pxa3xx_device_i2c_power = {
  875. .name = "pxa3xx-pwri2c",
  876. .id = 1,
  877. .resource = pxa3xx_resources_i2c_power,
  878. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  879. };
  880. static struct resource pxa3xx_resources_nand[] = {
  881. [0] = {
  882. .start = 0x43100000,
  883. .end = 0x43100053,
  884. .flags = IORESOURCE_MEM,
  885. },
  886. [1] = {
  887. .start = IRQ_NAND,
  888. .end = IRQ_NAND,
  889. .flags = IORESOURCE_IRQ,
  890. },
  891. [2] = {
  892. /* DRCMR for Data DMA */
  893. .start = 97,
  894. .end = 97,
  895. .flags = IORESOURCE_DMA,
  896. },
  897. [3] = {
  898. /* DRCMR for Command DMA */
  899. .start = 99,
  900. .end = 99,
  901. .flags = IORESOURCE_DMA,
  902. },
  903. };
  904. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  905. struct platform_device pxa3xx_device_nand = {
  906. .name = "pxa3xx-nand",
  907. .id = -1,
  908. .dev = {
  909. .dma_mask = &pxa3xx_nand_dma_mask,
  910. .coherent_dma_mask = DMA_BIT_MASK(32),
  911. },
  912. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  913. .resource = pxa3xx_resources_nand,
  914. };
  915. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  916. {
  917. pxa_register_device(&pxa3xx_device_nand, info);
  918. }
  919. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  920. static struct resource pxa3xx_resource_ssp4[] = {
  921. [0] = {
  922. .start = 0x41a00000,
  923. .end = 0x41a0003f,
  924. .flags = IORESOURCE_MEM,
  925. },
  926. [1] = {
  927. .start = IRQ_SSP4,
  928. .end = IRQ_SSP4,
  929. .flags = IORESOURCE_IRQ,
  930. },
  931. [2] = {
  932. /* DRCMR for RX */
  933. .start = 2,
  934. .end = 2,
  935. .flags = IORESOURCE_DMA,
  936. },
  937. [3] = {
  938. /* DRCMR for TX */
  939. .start = 3,
  940. .end = 3,
  941. .flags = IORESOURCE_DMA,
  942. },
  943. };
  944. /*
  945. * PXA3xx SSP is basically equivalent to PXA27x.
  946. * However, we need to register the device by the correct name in order to
  947. * make the driver set the correct internal type, hence we provide specific
  948. * platform_devices for each of them.
  949. */
  950. struct platform_device pxa3xx_device_ssp1 = {
  951. .name = "pxa3xx-ssp",
  952. .id = 0,
  953. .dev = {
  954. .dma_mask = &pxa27x_ssp1_dma_mask,
  955. .coherent_dma_mask = DMA_BIT_MASK(32),
  956. },
  957. .resource = pxa27x_resource_ssp1,
  958. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  959. };
  960. struct platform_device pxa3xx_device_ssp2 = {
  961. .name = "pxa3xx-ssp",
  962. .id = 1,
  963. .dev = {
  964. .dma_mask = &pxa27x_ssp2_dma_mask,
  965. .coherent_dma_mask = DMA_BIT_MASK(32),
  966. },
  967. .resource = pxa27x_resource_ssp2,
  968. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  969. };
  970. struct platform_device pxa3xx_device_ssp3 = {
  971. .name = "pxa3xx-ssp",
  972. .id = 2,
  973. .dev = {
  974. .dma_mask = &pxa27x_ssp3_dma_mask,
  975. .coherent_dma_mask = DMA_BIT_MASK(32),
  976. },
  977. .resource = pxa27x_resource_ssp3,
  978. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  979. };
  980. struct platform_device pxa3xx_device_ssp4 = {
  981. .name = "pxa3xx-ssp",
  982. .id = 3,
  983. .dev = {
  984. .dma_mask = &pxa3xx_ssp4_dma_mask,
  985. .coherent_dma_mask = DMA_BIT_MASK(32),
  986. },
  987. .resource = pxa3xx_resource_ssp4,
  988. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  989. };
  990. #endif /* CONFIG_PXA3xx */
  991. struct resource pxa_resource_gpio[] = {
  992. {
  993. .start = 0x40e00000,
  994. .end = 0x40e0ffff,
  995. .flags = IORESOURCE_MEM,
  996. }, {
  997. .start = IRQ_GPIO0,
  998. .end = IRQ_GPIO0,
  999. .name = "gpio0",
  1000. .flags = IORESOURCE_IRQ,
  1001. }, {
  1002. .start = IRQ_GPIO1,
  1003. .end = IRQ_GPIO1,
  1004. .name = "gpio1",
  1005. .flags = IORESOURCE_IRQ,
  1006. }, {
  1007. .start = IRQ_GPIO_2_x,
  1008. .end = IRQ_GPIO_2_x,
  1009. .name = "gpio_mux",
  1010. .flags = IORESOURCE_IRQ,
  1011. },
  1012. };
  1013. struct platform_device pxa25x_device_gpio = {
  1014. #ifdef CONFIG_CPU_PXA26x
  1015. .name = "pxa26x-gpio",
  1016. #else
  1017. .name = "pxa25x-gpio",
  1018. #endif
  1019. .id = -1,
  1020. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1021. .resource = pxa_resource_gpio,
  1022. };
  1023. struct platform_device pxa27x_device_gpio = {
  1024. .name = "pxa27x-gpio",
  1025. .id = -1,
  1026. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1027. .resource = pxa_resource_gpio,
  1028. };
  1029. struct platform_device pxa3xx_device_gpio = {
  1030. .name = "pxa3xx-gpio",
  1031. .id = -1,
  1032. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1033. .resource = pxa_resource_gpio,
  1034. };
  1035. struct platform_device pxa93x_device_gpio = {
  1036. .name = "pxa93x-gpio",
  1037. .id = -1,
  1038. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1039. .resource = pxa_resource_gpio,
  1040. };
  1041. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  1042. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  1043. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  1044. {
  1045. struct platform_device *pd;
  1046. pd = platform_device_alloc("pxa2xx-spi", id);
  1047. if (pd == NULL) {
  1048. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  1049. id);
  1050. return;
  1051. }
  1052. pd->dev.platform_data = info;
  1053. platform_device_add(pd);
  1054. }
  1055. static struct mmp_dma_platdata pxa_dma_pdata = {
  1056. .dma_channels = 0,
  1057. };
  1058. static struct resource pxa_dma_resource[] = {
  1059. [0] = {
  1060. .start = 0x40000000,
  1061. .end = 0x4000ffff,
  1062. .flags = IORESOURCE_MEM,
  1063. },
  1064. [1] = {
  1065. .start = IRQ_DMA,
  1066. .end = IRQ_DMA,
  1067. .flags = IORESOURCE_IRQ,
  1068. },
  1069. };
  1070. static u64 pxadma_dmamask = 0xffffffffUL;
  1071. static struct platform_device pxa2xx_pxa_dma = {
  1072. .name = "pxa-dma",
  1073. .id = 0,
  1074. .dev = {
  1075. .dma_mask = &pxadma_dmamask,
  1076. .coherent_dma_mask = 0xffffffff,
  1077. },
  1078. .num_resources = ARRAY_SIZE(pxa_dma_resource),
  1079. .resource = pxa_dma_resource,
  1080. };
  1081. void __init pxa2xx_set_dmac_info(int nb_channels)
  1082. {
  1083. pxa_dma_pdata.dma_channels = nb_channels;
  1084. pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
  1085. }