smp.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * RajeshwarR: Dec 11, 2007
  9. * -- Added support for Inter Processor Interrupts
  10. *
  11. * Vineetg: Nov 1st, 2007
  12. * -- Initial Write (Borrowed heavily from ARM)
  13. */
  14. #include <linux/spinlock.h>
  15. #include <linux/sched.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/profile.h>
  18. #include <linux/mm.h>
  19. #include <linux/cpu.h>
  20. #include <linux/irq.h>
  21. #include <linux/atomic.h>
  22. #include <linux/cpumask.h>
  23. #include <linux/reboot.h>
  24. #include <asm/processor.h>
  25. #include <asm/setup.h>
  26. #include <asm/mach_desc.h>
  27. #ifndef CONFIG_ARC_HAS_LLSC
  28. arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  29. arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  30. #endif
  31. struct plat_smp_ops __weak plat_smp_ops;
  32. /* XXX: per cpu ? Only needed once in early seconday boot */
  33. struct task_struct *secondary_idle_tsk;
  34. /* Called from start_kernel */
  35. void __init smp_prepare_boot_cpu(void)
  36. {
  37. }
  38. /*
  39. * Initialise the CPU possible map early - this describes the CPUs
  40. * which may be present or become present in the system.
  41. */
  42. void __init smp_init_cpus(void)
  43. {
  44. unsigned int i;
  45. for (i = 0; i < NR_CPUS; i++)
  46. set_cpu_possible(i, true);
  47. }
  48. /* called from init ( ) => process 1 */
  49. void __init smp_prepare_cpus(unsigned int max_cpus)
  50. {
  51. int i;
  52. /*
  53. * Initialise the present map, which describes the set of CPUs
  54. * actually populated at the present time.
  55. */
  56. for (i = 0; i < max_cpus; i++)
  57. set_cpu_present(i, true);
  58. }
  59. void __init smp_cpus_done(unsigned int max_cpus)
  60. {
  61. }
  62. /*
  63. * After power-up, a non Master CPU needs to wait for Master to kick start it
  64. *
  65. * The default implementation halts
  66. *
  67. * This relies on platform specific support allowing Master to directly set
  68. * this CPU's PC (to be @first_lines_of_secondary() and kick start it.
  69. *
  70. * In lack of such h/w assist, platforms can override this function
  71. * - make this function busy-spin on a token, eventually set by Master
  72. * (from arc_platform_smp_wakeup_cpu())
  73. * - Once token is available, jump to @first_lines_of_secondary
  74. * (using inline asm).
  75. *
  76. * Alert: can NOT use stack here as it has not been determined/setup for CPU.
  77. * If it turns out to be elaborate, it's better to code it in assembly
  78. *
  79. */
  80. void __weak arc_platform_smp_wait_to_boot(int cpu)
  81. {
  82. /*
  83. * As a hack for debugging - since debugger will single-step over the
  84. * FLAG insn - wrap the halt itself it in a self loop
  85. */
  86. __asm__ __volatile__(
  87. "1: \n"
  88. " flag 1 \n"
  89. " b 1b \n");
  90. }
  91. const char *arc_platform_smp_cpuinfo(void)
  92. {
  93. return plat_smp_ops.info ? : "";
  94. }
  95. /*
  96. * The very first "C" code executed by secondary
  97. * Called from asm stub in head.S
  98. * "current"/R25 already setup by low level boot code
  99. */
  100. void start_kernel_secondary(void)
  101. {
  102. struct mm_struct *mm = &init_mm;
  103. unsigned int cpu = smp_processor_id();
  104. /* MMU, Caches, Vector Table, Interrupts etc */
  105. setup_processor();
  106. atomic_inc(&mm->mm_users);
  107. atomic_inc(&mm->mm_count);
  108. current->active_mm = mm;
  109. cpumask_set_cpu(cpu, mm_cpumask(mm));
  110. notify_cpu_starting(cpu);
  111. set_cpu_online(cpu, true);
  112. pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu);
  113. if (machine_desc->init_smp)
  114. machine_desc->init_smp(cpu);
  115. arc_local_timer_setup();
  116. local_irq_enable();
  117. preempt_disable();
  118. cpu_startup_entry(CPUHP_ONLINE);
  119. }
  120. /*
  121. * Called from kernel_init( ) -> smp_init( ) - for each CPU
  122. *
  123. * At this point, Secondary Processor is "HALT"ed:
  124. * -It booted, but was halted in head.S
  125. * -It was configured to halt-on-reset
  126. * So need to wake it up.
  127. *
  128. * Essential requirements being where to run from (PC) and stack (SP)
  129. */
  130. int __cpu_up(unsigned int cpu, struct task_struct *idle)
  131. {
  132. unsigned long wait_till;
  133. secondary_idle_tsk = idle;
  134. pr_info("Idle Task [%d] %p", cpu, idle);
  135. pr_info("Trying to bring up CPU%u ...\n", cpu);
  136. if (plat_smp_ops.cpu_kick)
  137. plat_smp_ops.cpu_kick(cpu,
  138. (unsigned long)first_lines_of_secondary);
  139. /* wait for 1 sec after kicking the secondary */
  140. wait_till = jiffies + HZ;
  141. while (time_before(jiffies, wait_till)) {
  142. if (cpu_online(cpu))
  143. break;
  144. }
  145. if (!cpu_online(cpu)) {
  146. pr_info("Timeout: CPU%u FAILED to comeup !!!\n", cpu);
  147. return -1;
  148. }
  149. secondary_idle_tsk = NULL;
  150. return 0;
  151. }
  152. /*
  153. * not supported here
  154. */
  155. int setup_profiling_timer(unsigned int multiplier)
  156. {
  157. return -EINVAL;
  158. }
  159. /*****************************************************************************/
  160. /* Inter Processor Interrupt Handling */
  161. /*****************************************************************************/
  162. enum ipi_msg_type {
  163. IPI_EMPTY = 0,
  164. IPI_RESCHEDULE = 1,
  165. IPI_CALL_FUNC,
  166. IPI_CPU_STOP,
  167. };
  168. /*
  169. * In arches with IRQ for each msg type (above), receiver can use IRQ-id to
  170. * figure out what msg was sent. For those which don't (ARC has dedicated IPI
  171. * IRQ), the msg-type needs to be conveyed via per-cpu data
  172. */
  173. static DEFINE_PER_CPU(unsigned long, ipi_data);
  174. static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg)
  175. {
  176. unsigned long __percpu *ipi_data_ptr = per_cpu_ptr(&ipi_data, cpu);
  177. unsigned long old, new;
  178. unsigned long flags;
  179. pr_debug("%d Sending msg [%d] to %d\n", smp_processor_id(), msg, cpu);
  180. local_irq_save(flags);
  181. /*
  182. * Atomically write new msg bit (in case others are writing too),
  183. * and read back old value
  184. */
  185. do {
  186. new = old = ACCESS_ONCE(*ipi_data_ptr);
  187. new |= 1U << msg;
  188. } while (cmpxchg(ipi_data_ptr, old, new) != old);
  189. /*
  190. * Call the platform specific IPI kick function, but avoid if possible:
  191. * Only do so if there's no pending msg from other concurrent sender(s).
  192. * Otherwise, recevier will see this msg as well when it takes the
  193. * IPI corresponding to that msg. This is true, even if it is already in
  194. * IPI handler, because !@old means it has not yet dequeued the msg(s)
  195. * so @new msg can be a free-loader
  196. */
  197. if (plat_smp_ops.ipi_send && !old)
  198. plat_smp_ops.ipi_send(cpu);
  199. local_irq_restore(flags);
  200. }
  201. static void ipi_send_msg(const struct cpumask *callmap, enum ipi_msg_type msg)
  202. {
  203. unsigned int cpu;
  204. for_each_cpu(cpu, callmap)
  205. ipi_send_msg_one(cpu, msg);
  206. }
  207. void smp_send_reschedule(int cpu)
  208. {
  209. ipi_send_msg_one(cpu, IPI_RESCHEDULE);
  210. }
  211. void smp_send_stop(void)
  212. {
  213. struct cpumask targets;
  214. cpumask_copy(&targets, cpu_online_mask);
  215. cpumask_clear_cpu(smp_processor_id(), &targets);
  216. ipi_send_msg(&targets, IPI_CPU_STOP);
  217. }
  218. void arch_send_call_function_single_ipi(int cpu)
  219. {
  220. ipi_send_msg_one(cpu, IPI_CALL_FUNC);
  221. }
  222. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  223. {
  224. ipi_send_msg(mask, IPI_CALL_FUNC);
  225. }
  226. /*
  227. * ipi_cpu_stop - handle IPI from smp_send_stop()
  228. */
  229. static void ipi_cpu_stop(void)
  230. {
  231. machine_halt();
  232. }
  233. static inline int __do_IPI(unsigned long msg)
  234. {
  235. int rc = 0;
  236. switch (msg) {
  237. case IPI_RESCHEDULE:
  238. scheduler_ipi();
  239. break;
  240. case IPI_CALL_FUNC:
  241. generic_smp_call_function_interrupt();
  242. break;
  243. case IPI_CPU_STOP:
  244. ipi_cpu_stop();
  245. break;
  246. default:
  247. rc = 1;
  248. }
  249. return rc;
  250. }
  251. /*
  252. * arch-common ISR to handle for inter-processor interrupts
  253. * Has hooks for platform specific IPI
  254. */
  255. irqreturn_t do_IPI(int irq, void *dev_id)
  256. {
  257. unsigned long pending;
  258. unsigned long __maybe_unused copy;
  259. pr_debug("IPI [%ld] received on cpu %d\n",
  260. *this_cpu_ptr(&ipi_data), smp_processor_id());
  261. if (plat_smp_ops.ipi_clear)
  262. plat_smp_ops.ipi_clear(irq);
  263. /*
  264. * "dequeue" the msg corresponding to this IPI (and possibly other
  265. * piggybacked msg from elided IPIs: see ipi_send_msg_one() above)
  266. */
  267. copy = pending = xchg(this_cpu_ptr(&ipi_data), 0);
  268. do {
  269. unsigned long msg = __ffs(pending);
  270. int rc;
  271. rc = __do_IPI(msg);
  272. #ifdef CONFIG_ARC_IPI_DBG
  273. /* IPI received but no valid @msg */
  274. if (rc)
  275. pr_info("IPI with bogus msg %ld in %ld\n", msg, copy);
  276. #endif
  277. pending &= ~(1U << msg);
  278. } while (pending);
  279. return IRQ_HANDLED;
  280. }
  281. /*
  282. * API called by platform code to hookup arch-common ISR to their IPI IRQ
  283. */
  284. static DEFINE_PER_CPU(int, ipi_dev);
  285. int smp_ipi_irq_setup(int cpu, int irq)
  286. {
  287. int *dev = per_cpu_ptr(&ipi_dev, cpu);
  288. arc_request_percpu_irq(irq, cpu, do_IPI, "IPI Interrupt", dev);
  289. return 0;
  290. }