omap_drv.c 20 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/wait.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. /*
  33. * mode config funcs
  34. */
  35. /* Notes about mapping DSS and DRM entities:
  36. * CRTC: overlay
  37. * encoder: manager.. with some extension to allow one primary CRTC
  38. * and zero or more video CRTC's to be mapped to one encoder?
  39. * connector: dssdev.. manager can be attached/detached from different
  40. * devices
  41. */
  42. static void omap_fb_output_poll_changed(struct drm_device *dev)
  43. {
  44. struct omap_drm_private *priv = dev->dev_private;
  45. DBG("dev=%p", dev);
  46. if (priv->fbdev)
  47. drm_fb_helper_hotplug_event(priv->fbdev);
  48. }
  49. struct omap_atomic_state_commit {
  50. struct work_struct work;
  51. struct drm_device *dev;
  52. struct drm_atomic_state *state;
  53. u32 crtcs;
  54. };
  55. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  56. struct drm_atomic_state *old_state)
  57. {
  58. struct drm_crtc_state *old_crtc_state;
  59. struct drm_crtc *crtc;
  60. unsigned int i;
  61. int ret;
  62. for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  63. if (!crtc->state->enable)
  64. continue;
  65. ret = omap_crtc_wait_pending(crtc);
  66. if (!ret)
  67. dev_warn(dev->dev,
  68. "atomic complete timeout (pipe %u)!\n", i);
  69. }
  70. }
  71. static void omap_atomic_complete(struct omap_atomic_state_commit *commit)
  72. {
  73. struct drm_device *dev = commit->dev;
  74. struct omap_drm_private *priv = dev->dev_private;
  75. struct drm_atomic_state *old_state = commit->state;
  76. /* Apply the atomic update. */
  77. priv->dispc_ops->runtime_get();
  78. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  79. /* With the current dss dispc implementation we have to enable
  80. * the new modeset before we can commit planes. The dispc ovl
  81. * configuration relies on the video mode configuration been
  82. * written into the HW when the ovl configuration is
  83. * calculated.
  84. *
  85. * This approach is not ideal because after a mode change the
  86. * plane update is executed only after the first vblank
  87. * interrupt. The dispc implementation should be fixed so that
  88. * it is able use uncommitted drm state information.
  89. */
  90. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  91. omap_atomic_wait_for_completion(dev, old_state);
  92. drm_atomic_helper_commit_planes(dev, old_state, 0);
  93. omap_atomic_wait_for_completion(dev, old_state);
  94. drm_atomic_helper_cleanup_planes(dev, old_state);
  95. priv->dispc_ops->runtime_put();
  96. drm_atomic_state_put(old_state);
  97. /* Complete the commit, wake up any waiter. */
  98. spin_lock(&priv->commit.lock);
  99. priv->commit.pending &= ~commit->crtcs;
  100. spin_unlock(&priv->commit.lock);
  101. wake_up_all(&priv->commit.wait);
  102. kfree(commit);
  103. }
  104. static void omap_atomic_work(struct work_struct *work)
  105. {
  106. struct omap_atomic_state_commit *commit =
  107. container_of(work, struct omap_atomic_state_commit, work);
  108. omap_atomic_complete(commit);
  109. }
  110. static bool omap_atomic_is_pending(struct omap_drm_private *priv,
  111. struct omap_atomic_state_commit *commit)
  112. {
  113. bool pending;
  114. spin_lock(&priv->commit.lock);
  115. pending = priv->commit.pending & commit->crtcs;
  116. spin_unlock(&priv->commit.lock);
  117. return pending;
  118. }
  119. static int omap_atomic_commit(struct drm_device *dev,
  120. struct drm_atomic_state *state, bool nonblock)
  121. {
  122. struct omap_drm_private *priv = dev->dev_private;
  123. struct omap_atomic_state_commit *commit;
  124. struct drm_crtc *crtc;
  125. struct drm_crtc_state *crtc_state;
  126. int i, ret;
  127. ret = drm_atomic_helper_prepare_planes(dev, state);
  128. if (ret)
  129. return ret;
  130. /* Allocate the commit object. */
  131. commit = kzalloc(sizeof(*commit), GFP_KERNEL);
  132. if (commit == NULL) {
  133. ret = -ENOMEM;
  134. goto error;
  135. }
  136. INIT_WORK(&commit->work, omap_atomic_work);
  137. commit->dev = dev;
  138. commit->state = state;
  139. /* Wait until all affected CRTCs have completed previous commits and
  140. * mark them as pending.
  141. */
  142. for_each_crtc_in_state(state, crtc, crtc_state, i)
  143. commit->crtcs |= drm_crtc_mask(crtc);
  144. wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
  145. spin_lock(&priv->commit.lock);
  146. priv->commit.pending |= commit->crtcs;
  147. spin_unlock(&priv->commit.lock);
  148. /* Swap the state, this is the point of no return. */
  149. drm_atomic_helper_swap_state(state, true);
  150. drm_atomic_state_get(state);
  151. if (nonblock)
  152. schedule_work(&commit->work);
  153. else
  154. omap_atomic_complete(commit);
  155. return 0;
  156. error:
  157. drm_atomic_helper_cleanup_planes(dev, state);
  158. return ret;
  159. }
  160. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  161. .fb_create = omap_framebuffer_create,
  162. .output_poll_changed = omap_fb_output_poll_changed,
  163. .atomic_check = drm_atomic_helper_check,
  164. .atomic_commit = omap_atomic_commit,
  165. };
  166. static int get_connector_type(struct omap_dss_device *dssdev)
  167. {
  168. switch (dssdev->type) {
  169. case OMAP_DISPLAY_TYPE_HDMI:
  170. return DRM_MODE_CONNECTOR_HDMIA;
  171. case OMAP_DISPLAY_TYPE_DVI:
  172. return DRM_MODE_CONNECTOR_DVID;
  173. case OMAP_DISPLAY_TYPE_DSI:
  174. return DRM_MODE_CONNECTOR_DSI;
  175. default:
  176. return DRM_MODE_CONNECTOR_Unknown;
  177. }
  178. }
  179. static void omap_disconnect_dssdevs(void)
  180. {
  181. struct omap_dss_device *dssdev = NULL;
  182. for_each_dss_dev(dssdev)
  183. dssdev->driver->disconnect(dssdev);
  184. }
  185. static int omap_connect_dssdevs(void)
  186. {
  187. int r;
  188. struct omap_dss_device *dssdev = NULL;
  189. if (!omapdss_stack_is_ready())
  190. return -EPROBE_DEFER;
  191. for_each_dss_dev(dssdev) {
  192. r = dssdev->driver->connect(dssdev);
  193. if (r == -EPROBE_DEFER) {
  194. omap_dss_put_device(dssdev);
  195. goto cleanup;
  196. } else if (r) {
  197. dev_warn(dssdev->dev, "could not connect display: %s\n",
  198. dssdev->name);
  199. }
  200. }
  201. return 0;
  202. cleanup:
  203. /*
  204. * if we are deferring probe, we disconnect the devices we previously
  205. * connected
  206. */
  207. omap_disconnect_dssdevs();
  208. return r;
  209. }
  210. static int omap_modeset_init_properties(struct drm_device *dev)
  211. {
  212. struct omap_drm_private *priv = dev->dev_private;
  213. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
  214. if (!priv->zorder_prop)
  215. return -ENOMEM;
  216. return 0;
  217. }
  218. static int omap_modeset_init(struct drm_device *dev)
  219. {
  220. struct omap_drm_private *priv = dev->dev_private;
  221. struct omap_dss_device *dssdev = NULL;
  222. int num_ovls = priv->dispc_ops->get_num_ovls();
  223. int num_mgrs = priv->dispc_ops->get_num_mgrs();
  224. int num_crtcs, crtc_idx, plane_idx;
  225. int ret;
  226. u32 plane_crtc_mask;
  227. drm_mode_config_init(dev);
  228. ret = omap_modeset_init_properties(dev);
  229. if (ret < 0)
  230. return ret;
  231. /*
  232. * This function creates exactly one connector, encoder, crtc,
  233. * and primary plane per each connected dss-device. Each
  234. * connector->encoder->crtc chain is expected to be separate
  235. * and each crtc is connect to a single dss-channel. If the
  236. * configuration does not match the expectations or exceeds
  237. * the available resources, the configuration is rejected.
  238. */
  239. num_crtcs = 0;
  240. for_each_dss_dev(dssdev)
  241. if (omapdss_device_is_connected(dssdev))
  242. num_crtcs++;
  243. if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
  244. num_crtcs > ARRAY_SIZE(priv->crtcs) ||
  245. num_crtcs > ARRAY_SIZE(priv->planes) ||
  246. num_crtcs > ARRAY_SIZE(priv->encoders) ||
  247. num_crtcs > ARRAY_SIZE(priv->connectors)) {
  248. dev_err(dev->dev, "%s(): Too many connected displays\n",
  249. __func__);
  250. return -EINVAL;
  251. }
  252. /* All planes can be put to any CRTC */
  253. plane_crtc_mask = (1 << num_crtcs) - 1;
  254. dssdev = NULL;
  255. crtc_idx = 0;
  256. plane_idx = 0;
  257. for_each_dss_dev(dssdev) {
  258. struct drm_connector *connector;
  259. struct drm_encoder *encoder;
  260. struct drm_plane *plane;
  261. struct drm_crtc *crtc;
  262. if (!omapdss_device_is_connected(dssdev))
  263. continue;
  264. encoder = omap_encoder_init(dev, dssdev);
  265. if (!encoder)
  266. return -ENOMEM;
  267. connector = omap_connector_init(dev,
  268. get_connector_type(dssdev), dssdev, encoder);
  269. if (!connector)
  270. return -ENOMEM;
  271. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
  272. plane_crtc_mask);
  273. if (IS_ERR(plane))
  274. return PTR_ERR(plane);
  275. crtc = omap_crtc_init(dev, plane, dssdev);
  276. if (IS_ERR(crtc))
  277. return PTR_ERR(crtc);
  278. drm_mode_connector_attach_encoder(connector, encoder);
  279. encoder->possible_crtcs = (1 << crtc_idx);
  280. priv->crtcs[priv->num_crtcs++] = crtc;
  281. priv->planes[priv->num_planes++] = plane;
  282. priv->encoders[priv->num_encoders++] = encoder;
  283. priv->connectors[priv->num_connectors++] = connector;
  284. plane_idx++;
  285. crtc_idx++;
  286. }
  287. /*
  288. * Create normal planes for the remaining overlays:
  289. */
  290. for (; plane_idx < num_ovls; plane_idx++) {
  291. struct drm_plane *plane;
  292. if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
  293. return -EINVAL;
  294. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
  295. plane_crtc_mask);
  296. if (IS_ERR(plane))
  297. return PTR_ERR(plane);
  298. priv->planes[priv->num_planes++] = plane;
  299. }
  300. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  301. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  302. priv->num_connectors);
  303. dev->mode_config.min_width = 8;
  304. dev->mode_config.min_height = 2;
  305. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  306. * to fill in these limits properly on different OMAP generations..
  307. */
  308. dev->mode_config.max_width = 2048;
  309. dev->mode_config.max_height = 2048;
  310. dev->mode_config.funcs = &omap_mode_config_funcs;
  311. drm_mode_config_reset(dev);
  312. omap_drm_irq_install(dev);
  313. return 0;
  314. }
  315. /*
  316. * drm ioctl funcs
  317. */
  318. static int ioctl_get_param(struct drm_device *dev, void *data,
  319. struct drm_file *file_priv)
  320. {
  321. struct omap_drm_private *priv = dev->dev_private;
  322. struct drm_omap_param *args = data;
  323. DBG("%p: param=%llu", dev, args->param);
  324. switch (args->param) {
  325. case OMAP_PARAM_CHIPSET_ID:
  326. args->value = priv->omaprev;
  327. break;
  328. default:
  329. DBG("unknown parameter %lld", args->param);
  330. return -EINVAL;
  331. }
  332. return 0;
  333. }
  334. static int ioctl_set_param(struct drm_device *dev, void *data,
  335. struct drm_file *file_priv)
  336. {
  337. struct drm_omap_param *args = data;
  338. switch (args->param) {
  339. default:
  340. DBG("unknown parameter %lld", args->param);
  341. return -EINVAL;
  342. }
  343. return 0;
  344. }
  345. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  346. static int ioctl_gem_new(struct drm_device *dev, void *data,
  347. struct drm_file *file_priv)
  348. {
  349. struct drm_omap_gem_new *args = data;
  350. u32 flags = args->flags & OMAP_BO_USER_MASK;
  351. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  352. args->size.bytes, flags);
  353. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  354. &args->handle);
  355. }
  356. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  357. struct drm_file *file_priv)
  358. {
  359. struct drm_omap_gem_cpu_prep *args = data;
  360. struct drm_gem_object *obj;
  361. int ret;
  362. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  363. obj = drm_gem_object_lookup(file_priv, args->handle);
  364. if (!obj)
  365. return -ENOENT;
  366. ret = omap_gem_op_sync(obj, args->op);
  367. if (!ret)
  368. ret = omap_gem_op_start(obj, args->op);
  369. drm_gem_object_unreference_unlocked(obj);
  370. return ret;
  371. }
  372. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  373. struct drm_file *file_priv)
  374. {
  375. struct drm_omap_gem_cpu_fini *args = data;
  376. struct drm_gem_object *obj;
  377. int ret;
  378. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  379. obj = drm_gem_object_lookup(file_priv, args->handle);
  380. if (!obj)
  381. return -ENOENT;
  382. /* XXX flushy, flushy */
  383. ret = 0;
  384. if (!ret)
  385. ret = omap_gem_op_finish(obj, args->op);
  386. drm_gem_object_unreference_unlocked(obj);
  387. return ret;
  388. }
  389. static int ioctl_gem_info(struct drm_device *dev, void *data,
  390. struct drm_file *file_priv)
  391. {
  392. struct drm_omap_gem_info *args = data;
  393. struct drm_gem_object *obj;
  394. int ret = 0;
  395. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  396. obj = drm_gem_object_lookup(file_priv, args->handle);
  397. if (!obj)
  398. return -ENOENT;
  399. args->size = omap_gem_mmap_size(obj);
  400. args->offset = omap_gem_mmap_offset(obj);
  401. drm_gem_object_unreference_unlocked(obj);
  402. return ret;
  403. }
  404. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  405. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
  406. DRM_AUTH | DRM_RENDER_ALLOW),
  407. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
  408. DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
  409. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
  410. DRM_AUTH | DRM_RENDER_ALLOW),
  411. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep,
  412. DRM_AUTH | DRM_RENDER_ALLOW),
  413. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini,
  414. DRM_AUTH | DRM_RENDER_ALLOW),
  415. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
  416. DRM_AUTH | DRM_RENDER_ALLOW),
  417. };
  418. /*
  419. * drm driver funcs
  420. */
  421. static int dev_open(struct drm_device *dev, struct drm_file *file)
  422. {
  423. file->driver_priv = NULL;
  424. DBG("open: dev=%p, file=%p", dev, file);
  425. return 0;
  426. }
  427. /**
  428. * lastclose - clean up after all DRM clients have exited
  429. * @dev: DRM device
  430. *
  431. * Take care of cleaning up after all DRM clients have exited. In the
  432. * mode setting case, we want to restore the kernel's initial mode (just
  433. * in case the last client left us in a bad state).
  434. */
  435. static void dev_lastclose(struct drm_device *dev)
  436. {
  437. int i;
  438. /* we don't support vga_switcheroo.. so just make sure the fbdev
  439. * mode is active
  440. */
  441. struct omap_drm_private *priv = dev->dev_private;
  442. int ret;
  443. DBG("lastclose: dev=%p", dev);
  444. /* need to restore default rotation state.. not sure
  445. * if there is a cleaner way to restore properties to
  446. * default state? Maybe a flag that properties should
  447. * automatically be restored to default state on
  448. * lastclose?
  449. */
  450. for (i = 0; i < priv->num_crtcs; i++) {
  451. struct drm_crtc *crtc = priv->crtcs[i];
  452. if (!crtc->primary->rotation_property)
  453. continue;
  454. drm_object_property_set_value(&crtc->base,
  455. crtc->primary->rotation_property,
  456. DRM_MODE_ROTATE_0);
  457. }
  458. for (i = 0; i < priv->num_planes; i++) {
  459. struct drm_plane *plane = priv->planes[i];
  460. if (!plane->rotation_property)
  461. continue;
  462. drm_object_property_set_value(&plane->base,
  463. plane->rotation_property,
  464. DRM_MODE_ROTATE_0);
  465. }
  466. if (priv->fbdev) {
  467. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  468. if (ret)
  469. DBG("failed to restore crtc mode");
  470. }
  471. }
  472. static const struct vm_operations_struct omap_gem_vm_ops = {
  473. .fault = omap_gem_fault,
  474. .open = drm_gem_vm_open,
  475. .close = drm_gem_vm_close,
  476. };
  477. static const struct file_operations omapdriver_fops = {
  478. .owner = THIS_MODULE,
  479. .open = drm_open,
  480. .unlocked_ioctl = drm_ioctl,
  481. .release = drm_release,
  482. .mmap = omap_gem_mmap,
  483. .poll = drm_poll,
  484. .read = drm_read,
  485. .llseek = noop_llseek,
  486. };
  487. static struct drm_driver omap_drm_driver = {
  488. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  489. DRIVER_ATOMIC | DRIVER_RENDER,
  490. .open = dev_open,
  491. .lastclose = dev_lastclose,
  492. #ifdef CONFIG_DEBUG_FS
  493. .debugfs_init = omap_debugfs_init,
  494. #endif
  495. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  496. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  497. .gem_prime_export = omap_gem_prime_export,
  498. .gem_prime_import = omap_gem_prime_import,
  499. .gem_free_object = omap_gem_free_object,
  500. .gem_vm_ops = &omap_gem_vm_ops,
  501. .dumb_create = omap_gem_dumb_create,
  502. .dumb_map_offset = omap_gem_dumb_map_offset,
  503. .dumb_destroy = drm_gem_dumb_destroy,
  504. .ioctls = ioctls,
  505. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  506. .fops = &omapdriver_fops,
  507. .name = DRIVER_NAME,
  508. .desc = DRIVER_DESC,
  509. .date = DRIVER_DATE,
  510. .major = DRIVER_MAJOR,
  511. .minor = DRIVER_MINOR,
  512. .patchlevel = DRIVER_PATCHLEVEL,
  513. };
  514. static int pdev_probe(struct platform_device *pdev)
  515. {
  516. struct omap_drm_platform_data *pdata = pdev->dev.platform_data;
  517. struct omap_drm_private *priv;
  518. struct drm_device *ddev;
  519. unsigned int i;
  520. int ret;
  521. DBG("%s", pdev->name);
  522. if (omapdss_is_initialized() == false)
  523. return -EPROBE_DEFER;
  524. omap_crtc_pre_init();
  525. ret = omap_connect_dssdevs();
  526. if (ret)
  527. goto err_crtc_uninit;
  528. /* Allocate and initialize the driver private structure. */
  529. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  530. if (!priv) {
  531. ret = -ENOMEM;
  532. goto err_disconnect_dssdevs;
  533. }
  534. priv->dispc_ops = dispc_get_ops();
  535. priv->omaprev = pdata->omaprev;
  536. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  537. init_waitqueue_head(&priv->commit.wait);
  538. spin_lock_init(&priv->commit.lock);
  539. spin_lock_init(&priv->list_lock);
  540. INIT_LIST_HEAD(&priv->obj_list);
  541. /* Allocate and initialize the DRM device. */
  542. ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
  543. if (IS_ERR(ddev)) {
  544. ret = PTR_ERR(ddev);
  545. goto err_free_priv;
  546. }
  547. ddev->dev_private = priv;
  548. platform_set_drvdata(pdev, ddev);
  549. omap_gem_init(ddev);
  550. ret = omap_modeset_init(ddev);
  551. if (ret) {
  552. dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  553. goto err_free_drm_dev;
  554. }
  555. /* Initialize vblank handling, start with all CRTCs disabled. */
  556. ret = drm_vblank_init(ddev, priv->num_crtcs);
  557. if (ret) {
  558. dev_err(&pdev->dev, "could not init vblank\n");
  559. goto err_cleanup_modeset;
  560. }
  561. for (i = 0; i < priv->num_crtcs; i++)
  562. drm_crtc_vblank_off(priv->crtcs[i]);
  563. priv->fbdev = omap_fbdev_init(ddev);
  564. drm_kms_helper_poll_init(ddev);
  565. /*
  566. * Register the DRM device with the core and the connectors with
  567. * sysfs.
  568. */
  569. ret = drm_dev_register(ddev, 0);
  570. if (ret)
  571. goto err_cleanup_helpers;
  572. return 0;
  573. err_cleanup_helpers:
  574. drm_kms_helper_poll_fini(ddev);
  575. if (priv->fbdev)
  576. omap_fbdev_free(ddev);
  577. err_cleanup_modeset:
  578. drm_mode_config_cleanup(ddev);
  579. omap_drm_irq_uninstall(ddev);
  580. err_free_drm_dev:
  581. omap_gem_deinit(ddev);
  582. drm_dev_unref(ddev);
  583. err_free_priv:
  584. destroy_workqueue(priv->wq);
  585. kfree(priv);
  586. err_disconnect_dssdevs:
  587. omap_disconnect_dssdevs();
  588. err_crtc_uninit:
  589. omap_crtc_pre_uninit();
  590. return ret;
  591. }
  592. static int pdev_remove(struct platform_device *pdev)
  593. {
  594. struct drm_device *ddev = platform_get_drvdata(pdev);
  595. struct omap_drm_private *priv = ddev->dev_private;
  596. DBG("");
  597. drm_dev_unregister(ddev);
  598. drm_kms_helper_poll_fini(ddev);
  599. if (priv->fbdev)
  600. omap_fbdev_free(ddev);
  601. drm_atomic_helper_shutdown(ddev);
  602. drm_mode_config_cleanup(ddev);
  603. omap_drm_irq_uninstall(ddev);
  604. omap_gem_deinit(ddev);
  605. drm_dev_unref(ddev);
  606. destroy_workqueue(priv->wq);
  607. kfree(priv);
  608. omap_disconnect_dssdevs();
  609. omap_crtc_pre_uninit();
  610. return 0;
  611. }
  612. #ifdef CONFIG_PM_SLEEP
  613. static int omap_drm_suspend_all_displays(void)
  614. {
  615. struct omap_dss_device *dssdev = NULL;
  616. for_each_dss_dev(dssdev) {
  617. if (!dssdev->driver)
  618. continue;
  619. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  620. dssdev->driver->disable(dssdev);
  621. dssdev->activate_after_resume = true;
  622. } else {
  623. dssdev->activate_after_resume = false;
  624. }
  625. }
  626. return 0;
  627. }
  628. static int omap_drm_resume_all_displays(void)
  629. {
  630. struct omap_dss_device *dssdev = NULL;
  631. for_each_dss_dev(dssdev) {
  632. if (!dssdev->driver)
  633. continue;
  634. if (dssdev->activate_after_resume) {
  635. dssdev->driver->enable(dssdev);
  636. dssdev->activate_after_resume = false;
  637. }
  638. }
  639. return 0;
  640. }
  641. static int omap_drm_suspend(struct device *dev)
  642. {
  643. struct drm_device *drm_dev = dev_get_drvdata(dev);
  644. drm_kms_helper_poll_disable(drm_dev);
  645. drm_modeset_lock_all(drm_dev);
  646. omap_drm_suspend_all_displays();
  647. drm_modeset_unlock_all(drm_dev);
  648. return 0;
  649. }
  650. static int omap_drm_resume(struct device *dev)
  651. {
  652. struct drm_device *drm_dev = dev_get_drvdata(dev);
  653. drm_modeset_lock_all(drm_dev);
  654. omap_drm_resume_all_displays();
  655. drm_modeset_unlock_all(drm_dev);
  656. drm_kms_helper_poll_enable(drm_dev);
  657. return omap_gem_resume(dev);
  658. }
  659. #endif
  660. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  661. static struct platform_driver pdev = {
  662. .driver = {
  663. .name = DRIVER_NAME,
  664. .pm = &omapdrm_pm_ops,
  665. },
  666. .probe = pdev_probe,
  667. .remove = pdev_remove,
  668. };
  669. static struct platform_driver * const drivers[] = {
  670. &omap_dmm_driver,
  671. &pdev,
  672. };
  673. static int __init omap_drm_init(void)
  674. {
  675. DBG("init");
  676. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  677. }
  678. static void __exit omap_drm_fini(void)
  679. {
  680. DBG("fini");
  681. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  682. }
  683. /* need late_initcall() so we load after dss_driver's are loaded */
  684. late_initcall(omap_drm_init);
  685. module_exit(omap_drm_fini);
  686. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  687. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  688. MODULE_ALIAS("platform:" DRIVER_NAME);
  689. MODULE_LICENSE("GPL v2");