atmel_usba_udc.c 58 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458
  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk/at91_pmc.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/slab.h>
  17. #include <linux/device.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/list.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regmap.h>
  23. #include <linux/ctype.h>
  24. #include <linux/usb/ch9.h>
  25. #include <linux/usb/gadget.h>
  26. #include <linux/usb/atmel_usba_udc.h>
  27. #include <linux/delay.h>
  28. #include <linux/of.h>
  29. #include <linux/of_gpio.h>
  30. #include "atmel_usba_udc.h"
  31. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  32. #include <linux/debugfs.h>
  33. #include <linux/uaccess.h>
  34. static int queue_dbg_open(struct inode *inode, struct file *file)
  35. {
  36. struct usba_ep *ep = inode->i_private;
  37. struct usba_request *req, *req_copy;
  38. struct list_head *queue_data;
  39. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  40. if (!queue_data)
  41. return -ENOMEM;
  42. INIT_LIST_HEAD(queue_data);
  43. spin_lock_irq(&ep->udc->lock);
  44. list_for_each_entry(req, &ep->queue, queue) {
  45. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  46. if (!req_copy)
  47. goto fail;
  48. list_add_tail(&req_copy->queue, queue_data);
  49. }
  50. spin_unlock_irq(&ep->udc->lock);
  51. file->private_data = queue_data;
  52. return 0;
  53. fail:
  54. spin_unlock_irq(&ep->udc->lock);
  55. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  56. list_del(&req->queue);
  57. kfree(req);
  58. }
  59. kfree(queue_data);
  60. return -ENOMEM;
  61. }
  62. /*
  63. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  64. *
  65. * b: buffer address
  66. * l: buffer length
  67. * I/i: interrupt/no interrupt
  68. * Z/z: zero/no zero
  69. * S/s: short ok/short not ok
  70. * s: status
  71. * n: nr_packets
  72. * F/f: submitted/not submitted to FIFO
  73. * D/d: using/not using DMA
  74. * L/l: last transaction/not last transaction
  75. */
  76. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  77. size_t nbytes, loff_t *ppos)
  78. {
  79. struct list_head *queue = file->private_data;
  80. struct usba_request *req, *tmp_req;
  81. size_t len, remaining, actual = 0;
  82. char tmpbuf[38];
  83. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  84. return -EFAULT;
  85. inode_lock(file_inode(file));
  86. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  87. len = snprintf(tmpbuf, sizeof(tmpbuf),
  88. "%8p %08x %c%c%c %5d %c%c%c\n",
  89. req->req.buf, req->req.length,
  90. req->req.no_interrupt ? 'i' : 'I',
  91. req->req.zero ? 'Z' : 'z',
  92. req->req.short_not_ok ? 's' : 'S',
  93. req->req.status,
  94. req->submitted ? 'F' : 'f',
  95. req->using_dma ? 'D' : 'd',
  96. req->last_transaction ? 'L' : 'l');
  97. len = min(len, sizeof(tmpbuf));
  98. if (len > nbytes)
  99. break;
  100. list_del(&req->queue);
  101. kfree(req);
  102. remaining = __copy_to_user(buf, tmpbuf, len);
  103. actual += len - remaining;
  104. if (remaining)
  105. break;
  106. nbytes -= len;
  107. buf += len;
  108. }
  109. inode_unlock(file_inode(file));
  110. return actual;
  111. }
  112. static int queue_dbg_release(struct inode *inode, struct file *file)
  113. {
  114. struct list_head *queue_data = file->private_data;
  115. struct usba_request *req, *tmp_req;
  116. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  117. list_del(&req->queue);
  118. kfree(req);
  119. }
  120. kfree(queue_data);
  121. return 0;
  122. }
  123. static int regs_dbg_open(struct inode *inode, struct file *file)
  124. {
  125. struct usba_udc *udc;
  126. unsigned int i;
  127. u32 *data;
  128. int ret = -ENOMEM;
  129. inode_lock(inode);
  130. udc = inode->i_private;
  131. data = kmalloc(inode->i_size, GFP_KERNEL);
  132. if (!data)
  133. goto out;
  134. spin_lock_irq(&udc->lock);
  135. for (i = 0; i < inode->i_size / 4; i++)
  136. data[i] = usba_io_readl(udc->regs + i * 4);
  137. spin_unlock_irq(&udc->lock);
  138. file->private_data = data;
  139. ret = 0;
  140. out:
  141. inode_unlock(inode);
  142. return ret;
  143. }
  144. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  145. size_t nbytes, loff_t *ppos)
  146. {
  147. struct inode *inode = file_inode(file);
  148. int ret;
  149. inode_lock(inode);
  150. ret = simple_read_from_buffer(buf, nbytes, ppos,
  151. file->private_data,
  152. file_inode(file)->i_size);
  153. inode_unlock(inode);
  154. return ret;
  155. }
  156. static int regs_dbg_release(struct inode *inode, struct file *file)
  157. {
  158. kfree(file->private_data);
  159. return 0;
  160. }
  161. const struct file_operations queue_dbg_fops = {
  162. .owner = THIS_MODULE,
  163. .open = queue_dbg_open,
  164. .llseek = no_llseek,
  165. .read = queue_dbg_read,
  166. .release = queue_dbg_release,
  167. };
  168. const struct file_operations regs_dbg_fops = {
  169. .owner = THIS_MODULE,
  170. .open = regs_dbg_open,
  171. .llseek = generic_file_llseek,
  172. .read = regs_dbg_read,
  173. .release = regs_dbg_release,
  174. };
  175. static void usba_ep_init_debugfs(struct usba_udc *udc,
  176. struct usba_ep *ep)
  177. {
  178. struct dentry *ep_root;
  179. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  180. if (!ep_root)
  181. goto err_root;
  182. ep->debugfs_dir = ep_root;
  183. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  184. ep, &queue_dbg_fops);
  185. if (!ep->debugfs_queue)
  186. goto err_queue;
  187. if (ep->can_dma) {
  188. ep->debugfs_dma_status
  189. = debugfs_create_u32("dma_status", 0400, ep_root,
  190. &ep->last_dma_status);
  191. if (!ep->debugfs_dma_status)
  192. goto err_dma_status;
  193. }
  194. if (ep_is_control(ep)) {
  195. ep->debugfs_state
  196. = debugfs_create_u32("state", 0400, ep_root,
  197. &ep->state);
  198. if (!ep->debugfs_state)
  199. goto err_state;
  200. }
  201. return;
  202. err_state:
  203. if (ep->can_dma)
  204. debugfs_remove(ep->debugfs_dma_status);
  205. err_dma_status:
  206. debugfs_remove(ep->debugfs_queue);
  207. err_queue:
  208. debugfs_remove(ep_root);
  209. err_root:
  210. dev_err(&ep->udc->pdev->dev,
  211. "failed to create debugfs directory for %s\n", ep->ep.name);
  212. }
  213. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  214. {
  215. debugfs_remove(ep->debugfs_queue);
  216. debugfs_remove(ep->debugfs_dma_status);
  217. debugfs_remove(ep->debugfs_state);
  218. debugfs_remove(ep->debugfs_dir);
  219. ep->debugfs_dma_status = NULL;
  220. ep->debugfs_dir = NULL;
  221. }
  222. static void usba_init_debugfs(struct usba_udc *udc)
  223. {
  224. struct dentry *root, *regs;
  225. struct resource *regs_resource;
  226. root = debugfs_create_dir(udc->gadget.name, NULL);
  227. if (IS_ERR(root) || !root)
  228. goto err_root;
  229. udc->debugfs_root = root;
  230. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  231. CTRL_IOMEM_ID);
  232. if (regs_resource) {
  233. regs = debugfs_create_file_size("regs", 0400, root, udc,
  234. &regs_dbg_fops,
  235. resource_size(regs_resource));
  236. if (!regs)
  237. goto err_regs;
  238. udc->debugfs_regs = regs;
  239. }
  240. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  241. return;
  242. err_regs:
  243. debugfs_remove(root);
  244. err_root:
  245. udc->debugfs_root = NULL;
  246. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  247. }
  248. static void usba_cleanup_debugfs(struct usba_udc *udc)
  249. {
  250. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  251. debugfs_remove(udc->debugfs_regs);
  252. debugfs_remove(udc->debugfs_root);
  253. udc->debugfs_regs = NULL;
  254. udc->debugfs_root = NULL;
  255. }
  256. #else
  257. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  258. struct usba_ep *ep)
  259. {
  260. }
  261. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  262. {
  263. }
  264. static inline void usba_init_debugfs(struct usba_udc *udc)
  265. {
  266. }
  267. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  268. {
  269. }
  270. #endif
  271. static ushort fifo_mode;
  272. /* "modprobe ... fifo_mode=1" etc */
  273. module_param(fifo_mode, ushort, 0x0);
  274. MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
  275. /* mode 0 - uses autoconfig */
  276. /* mode 1 - fits in 8KB, generic max fifo configuration */
  277. static struct usba_fifo_cfg mode_1_cfg[] = {
  278. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  279. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
  280. { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, },
  281. { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, },
  282. { .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, },
  283. { .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, },
  284. { .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, },
  285. };
  286. /* mode 2 - fits in 8KB, performance max fifo configuration */
  287. static struct usba_fifo_cfg mode_2_cfg[] = {
  288. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  289. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, },
  290. { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, },
  291. { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, },
  292. };
  293. /* mode 3 - fits in 8KB, mixed fifo configuration */
  294. static struct usba_fifo_cfg mode_3_cfg[] = {
  295. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  296. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
  297. { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
  298. { .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, },
  299. { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
  300. { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
  301. { .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, },
  302. };
  303. /* mode 4 - fits in 8KB, custom fifo configuration */
  304. static struct usba_fifo_cfg mode_4_cfg[] = {
  305. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  306. { .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, },
  307. { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
  308. { .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, },
  309. { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
  310. { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
  311. { .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, },
  312. { .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, },
  313. { .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, },
  314. };
  315. /* Add additional configurations here */
  316. int usba_config_fifo_table(struct usba_udc *udc)
  317. {
  318. int n;
  319. switch (fifo_mode) {
  320. default:
  321. fifo_mode = 0;
  322. case 0:
  323. udc->fifo_cfg = NULL;
  324. n = 0;
  325. break;
  326. case 1:
  327. udc->fifo_cfg = mode_1_cfg;
  328. n = ARRAY_SIZE(mode_1_cfg);
  329. break;
  330. case 2:
  331. udc->fifo_cfg = mode_2_cfg;
  332. n = ARRAY_SIZE(mode_2_cfg);
  333. break;
  334. case 3:
  335. udc->fifo_cfg = mode_3_cfg;
  336. n = ARRAY_SIZE(mode_3_cfg);
  337. break;
  338. case 4:
  339. udc->fifo_cfg = mode_4_cfg;
  340. n = ARRAY_SIZE(mode_4_cfg);
  341. break;
  342. }
  343. DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
  344. return n;
  345. }
  346. static inline u32 usba_int_enb_get(struct usba_udc *udc)
  347. {
  348. return udc->int_enb_cache;
  349. }
  350. static inline void usba_int_enb_set(struct usba_udc *udc, u32 val)
  351. {
  352. usba_writel(udc, INT_ENB, val);
  353. udc->int_enb_cache = val;
  354. }
  355. static int vbus_is_present(struct usba_udc *udc)
  356. {
  357. if (gpio_is_valid(udc->vbus_pin))
  358. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  359. /* No Vbus detection: Assume always present */
  360. return 1;
  361. }
  362. static void toggle_bias(struct usba_udc *udc, int is_on)
  363. {
  364. if (udc->errata && udc->errata->toggle_bias)
  365. udc->errata->toggle_bias(udc, is_on);
  366. }
  367. static void generate_bias_pulse(struct usba_udc *udc)
  368. {
  369. if (!udc->bias_pulse_needed)
  370. return;
  371. if (udc->errata && udc->errata->pulse_bias)
  372. udc->errata->pulse_bias(udc);
  373. udc->bias_pulse_needed = false;
  374. }
  375. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  376. {
  377. unsigned int transaction_len;
  378. transaction_len = req->req.length - req->req.actual;
  379. req->last_transaction = 1;
  380. if (transaction_len > ep->ep.maxpacket) {
  381. transaction_len = ep->ep.maxpacket;
  382. req->last_transaction = 0;
  383. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  384. req->last_transaction = 0;
  385. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  386. ep->ep.name, req, transaction_len,
  387. req->last_transaction ? ", done" : "");
  388. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  389. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  390. req->req.actual += transaction_len;
  391. }
  392. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  393. {
  394. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  395. ep->ep.name, req, req->req.length);
  396. req->req.actual = 0;
  397. req->submitted = 1;
  398. if (req->using_dma) {
  399. if (req->req.length == 0) {
  400. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  401. return;
  402. }
  403. if (req->req.zero)
  404. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  405. else
  406. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  407. usba_dma_writel(ep, ADDRESS, req->req.dma);
  408. usba_dma_writel(ep, CONTROL, req->ctrl);
  409. } else {
  410. next_fifo_transaction(ep, req);
  411. if (req->last_transaction) {
  412. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  413. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  414. } else {
  415. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  416. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  417. }
  418. }
  419. }
  420. static void submit_next_request(struct usba_ep *ep)
  421. {
  422. struct usba_request *req;
  423. if (list_empty(&ep->queue)) {
  424. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  425. return;
  426. }
  427. req = list_entry(ep->queue.next, struct usba_request, queue);
  428. if (!req->submitted)
  429. submit_request(ep, req);
  430. }
  431. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  432. {
  433. ep->state = STATUS_STAGE_IN;
  434. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  435. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  436. }
  437. static void receive_data(struct usba_ep *ep)
  438. {
  439. struct usba_udc *udc = ep->udc;
  440. struct usba_request *req;
  441. unsigned long status;
  442. unsigned int bytecount, nr_busy;
  443. int is_complete = 0;
  444. status = usba_ep_readl(ep, STA);
  445. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  446. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  447. while (nr_busy > 0) {
  448. if (list_empty(&ep->queue)) {
  449. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  450. break;
  451. }
  452. req = list_entry(ep->queue.next,
  453. struct usba_request, queue);
  454. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  455. if (status & (1 << 31))
  456. is_complete = 1;
  457. if (req->req.actual + bytecount >= req->req.length) {
  458. is_complete = 1;
  459. bytecount = req->req.length - req->req.actual;
  460. }
  461. memcpy_fromio(req->req.buf + req->req.actual,
  462. ep->fifo, bytecount);
  463. req->req.actual += bytecount;
  464. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  465. if (is_complete) {
  466. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  467. req->req.status = 0;
  468. list_del_init(&req->queue);
  469. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  470. spin_unlock(&udc->lock);
  471. usb_gadget_giveback_request(&ep->ep, &req->req);
  472. spin_lock(&udc->lock);
  473. }
  474. status = usba_ep_readl(ep, STA);
  475. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  476. if (is_complete && ep_is_control(ep)) {
  477. send_status(udc, ep);
  478. break;
  479. }
  480. }
  481. }
  482. static void
  483. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  484. {
  485. struct usba_udc *udc = ep->udc;
  486. WARN_ON(!list_empty(&req->queue));
  487. if (req->req.status == -EINPROGRESS)
  488. req->req.status = status;
  489. if (req->using_dma)
  490. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  491. DBG(DBG_GADGET | DBG_REQ,
  492. "%s: req %p complete: status %d, actual %u\n",
  493. ep->ep.name, req, req->req.status, req->req.actual);
  494. spin_unlock(&udc->lock);
  495. usb_gadget_giveback_request(&ep->ep, &req->req);
  496. spin_lock(&udc->lock);
  497. }
  498. static void
  499. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  500. {
  501. struct usba_request *req, *tmp_req;
  502. list_for_each_entry_safe(req, tmp_req, list, queue) {
  503. list_del_init(&req->queue);
  504. request_complete(ep, req, status);
  505. }
  506. }
  507. static int
  508. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  509. {
  510. struct usba_ep *ep = to_usba_ep(_ep);
  511. struct usba_udc *udc = ep->udc;
  512. unsigned long flags, maxpacket;
  513. unsigned int nr_trans;
  514. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  515. maxpacket = usb_endpoint_maxp(desc);
  516. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  517. || ep->index == 0
  518. || desc->bDescriptorType != USB_DT_ENDPOINT
  519. || maxpacket == 0
  520. || maxpacket > ep->fifo_size) {
  521. DBG(DBG_ERR, "ep_enable: Invalid argument");
  522. return -EINVAL;
  523. }
  524. ep->is_isoc = 0;
  525. ep->is_in = 0;
  526. DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
  527. ep->ep.name, ep->ept_cfg, maxpacket);
  528. if (usb_endpoint_dir_in(desc)) {
  529. ep->is_in = 1;
  530. ep->ept_cfg |= USBA_EPT_DIR_IN;
  531. }
  532. switch (usb_endpoint_type(desc)) {
  533. case USB_ENDPOINT_XFER_CONTROL:
  534. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  535. break;
  536. case USB_ENDPOINT_XFER_ISOC:
  537. if (!ep->can_isoc) {
  538. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  539. ep->ep.name);
  540. return -EINVAL;
  541. }
  542. /*
  543. * Bits 11:12 specify number of _additional_
  544. * transactions per microframe.
  545. */
  546. nr_trans = usb_endpoint_maxp_mult(desc);
  547. if (nr_trans > 3)
  548. return -EINVAL;
  549. ep->is_isoc = 1;
  550. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  551. ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  552. break;
  553. case USB_ENDPOINT_XFER_BULK:
  554. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  555. break;
  556. case USB_ENDPOINT_XFER_INT:
  557. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  558. break;
  559. }
  560. spin_lock_irqsave(&ep->udc->lock, flags);
  561. ep->ep.desc = desc;
  562. ep->ep.maxpacket = maxpacket;
  563. usba_ep_writel(ep, CFG, ep->ept_cfg);
  564. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  565. if (ep->can_dma) {
  566. u32 ctrl;
  567. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  568. USBA_BF(EPT_INT, 1 << ep->index) |
  569. USBA_BF(DMA_INT, 1 << ep->index));
  570. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  571. usba_ep_writel(ep, CTL_ENB, ctrl);
  572. } else {
  573. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  574. USBA_BF(EPT_INT, 1 << ep->index));
  575. }
  576. spin_unlock_irqrestore(&udc->lock, flags);
  577. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  578. (unsigned long)usba_ep_readl(ep, CFG));
  579. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  580. (unsigned long)usba_int_enb_get(udc));
  581. return 0;
  582. }
  583. static int usba_ep_disable(struct usb_ep *_ep)
  584. {
  585. struct usba_ep *ep = to_usba_ep(_ep);
  586. struct usba_udc *udc = ep->udc;
  587. LIST_HEAD(req_list);
  588. unsigned long flags;
  589. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  590. spin_lock_irqsave(&udc->lock, flags);
  591. if (!ep->ep.desc) {
  592. spin_unlock_irqrestore(&udc->lock, flags);
  593. /* REVISIT because this driver disables endpoints in
  594. * reset_all_endpoints() before calling disconnect(),
  595. * most gadget drivers would trigger this non-error ...
  596. */
  597. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  598. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  599. ep->ep.name);
  600. return -EINVAL;
  601. }
  602. ep->ep.desc = NULL;
  603. list_splice_init(&ep->queue, &req_list);
  604. if (ep->can_dma) {
  605. usba_dma_writel(ep, CONTROL, 0);
  606. usba_dma_writel(ep, ADDRESS, 0);
  607. usba_dma_readl(ep, STATUS);
  608. }
  609. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  610. usba_int_enb_set(udc, usba_int_enb_get(udc) &
  611. ~USBA_BF(EPT_INT, 1 << ep->index));
  612. request_complete_list(ep, &req_list, -ESHUTDOWN);
  613. spin_unlock_irqrestore(&udc->lock, flags);
  614. return 0;
  615. }
  616. static struct usb_request *
  617. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  618. {
  619. struct usba_request *req;
  620. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  621. req = kzalloc(sizeof(*req), gfp_flags);
  622. if (!req)
  623. return NULL;
  624. INIT_LIST_HEAD(&req->queue);
  625. return &req->req;
  626. }
  627. static void
  628. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  629. {
  630. struct usba_request *req = to_usba_req(_req);
  631. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  632. kfree(req);
  633. }
  634. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  635. struct usba_request *req, gfp_t gfp_flags)
  636. {
  637. unsigned long flags;
  638. int ret;
  639. DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
  640. ep->ep.name, req->req.length, &req->req.dma,
  641. req->req.zero ? 'Z' : 'z',
  642. req->req.short_not_ok ? 'S' : 's',
  643. req->req.no_interrupt ? 'I' : 'i');
  644. if (req->req.length > 0x10000) {
  645. /* Lengths from 0 to 65536 (inclusive) are supported */
  646. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  647. return -EINVAL;
  648. }
  649. ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
  650. if (ret)
  651. return ret;
  652. req->using_dma = 1;
  653. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  654. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  655. | USBA_DMA_END_BUF_EN;
  656. if (!ep->is_in)
  657. req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  658. /*
  659. * Add this request to the queue and submit for DMA if
  660. * possible. Check if we're still alive first -- we may have
  661. * received a reset since last time we checked.
  662. */
  663. ret = -ESHUTDOWN;
  664. spin_lock_irqsave(&udc->lock, flags);
  665. if (ep->ep.desc) {
  666. if (list_empty(&ep->queue))
  667. submit_request(ep, req);
  668. list_add_tail(&req->queue, &ep->queue);
  669. ret = 0;
  670. }
  671. spin_unlock_irqrestore(&udc->lock, flags);
  672. return ret;
  673. }
  674. static int
  675. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  676. {
  677. struct usba_request *req = to_usba_req(_req);
  678. struct usba_ep *ep = to_usba_ep(_ep);
  679. struct usba_udc *udc = ep->udc;
  680. unsigned long flags;
  681. int ret;
  682. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  683. ep->ep.name, req, _req->length);
  684. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  685. !ep->ep.desc)
  686. return -ESHUTDOWN;
  687. req->submitted = 0;
  688. req->using_dma = 0;
  689. req->last_transaction = 0;
  690. _req->status = -EINPROGRESS;
  691. _req->actual = 0;
  692. if (ep->can_dma)
  693. return queue_dma(udc, ep, req, gfp_flags);
  694. /* May have received a reset since last time we checked */
  695. ret = -ESHUTDOWN;
  696. spin_lock_irqsave(&udc->lock, flags);
  697. if (ep->ep.desc) {
  698. list_add_tail(&req->queue, &ep->queue);
  699. if ((!ep_is_control(ep) && ep->is_in) ||
  700. (ep_is_control(ep)
  701. && (ep->state == DATA_STAGE_IN
  702. || ep->state == STATUS_STAGE_IN)))
  703. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  704. else
  705. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  706. ret = 0;
  707. }
  708. spin_unlock_irqrestore(&udc->lock, flags);
  709. return ret;
  710. }
  711. static void
  712. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  713. {
  714. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  715. }
  716. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  717. {
  718. unsigned int timeout;
  719. u32 status;
  720. /*
  721. * Stop the DMA controller. When writing both CH_EN
  722. * and LINK to 0, the other bits are not affected.
  723. */
  724. usba_dma_writel(ep, CONTROL, 0);
  725. /* Wait for the FIFO to empty */
  726. for (timeout = 40; timeout; --timeout) {
  727. status = usba_dma_readl(ep, STATUS);
  728. if (!(status & USBA_DMA_CH_EN))
  729. break;
  730. udelay(1);
  731. }
  732. if (pstatus)
  733. *pstatus = status;
  734. if (timeout == 0) {
  735. dev_err(&ep->udc->pdev->dev,
  736. "%s: timed out waiting for DMA FIFO to empty\n",
  737. ep->ep.name);
  738. return -ETIMEDOUT;
  739. }
  740. return 0;
  741. }
  742. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  743. {
  744. struct usba_ep *ep = to_usba_ep(_ep);
  745. struct usba_udc *udc = ep->udc;
  746. struct usba_request *req;
  747. unsigned long flags;
  748. u32 status;
  749. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  750. ep->ep.name, req);
  751. spin_lock_irqsave(&udc->lock, flags);
  752. list_for_each_entry(req, &ep->queue, queue) {
  753. if (&req->req == _req)
  754. break;
  755. }
  756. if (&req->req != _req) {
  757. spin_unlock_irqrestore(&udc->lock, flags);
  758. return -EINVAL;
  759. }
  760. if (req->using_dma) {
  761. /*
  762. * If this request is currently being transferred,
  763. * stop the DMA controller and reset the FIFO.
  764. */
  765. if (ep->queue.next == &req->queue) {
  766. status = usba_dma_readl(ep, STATUS);
  767. if (status & USBA_DMA_CH_EN)
  768. stop_dma(ep, &status);
  769. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  770. ep->last_dma_status = status;
  771. #endif
  772. usba_writel(udc, EPT_RST, 1 << ep->index);
  773. usba_update_req(ep, req, status);
  774. }
  775. }
  776. /*
  777. * Errors should stop the queue from advancing until the
  778. * completion function returns.
  779. */
  780. list_del_init(&req->queue);
  781. request_complete(ep, req, -ECONNRESET);
  782. /* Process the next request if any */
  783. submit_next_request(ep);
  784. spin_unlock_irqrestore(&udc->lock, flags);
  785. return 0;
  786. }
  787. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  788. {
  789. struct usba_ep *ep = to_usba_ep(_ep);
  790. struct usba_udc *udc = ep->udc;
  791. unsigned long flags;
  792. int ret = 0;
  793. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  794. value ? "set" : "clear");
  795. if (!ep->ep.desc) {
  796. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  797. ep->ep.name);
  798. return -ENODEV;
  799. }
  800. if (ep->is_isoc) {
  801. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  802. ep->ep.name);
  803. return -ENOTTY;
  804. }
  805. spin_lock_irqsave(&udc->lock, flags);
  806. /*
  807. * We can't halt IN endpoints while there are still data to be
  808. * transferred
  809. */
  810. if (!list_empty(&ep->queue)
  811. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  812. & USBA_BF(BUSY_BANKS, -1L))))) {
  813. ret = -EAGAIN;
  814. } else {
  815. if (value)
  816. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  817. else
  818. usba_ep_writel(ep, CLR_STA,
  819. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  820. usba_ep_readl(ep, STA);
  821. }
  822. spin_unlock_irqrestore(&udc->lock, flags);
  823. return ret;
  824. }
  825. static int usba_ep_fifo_status(struct usb_ep *_ep)
  826. {
  827. struct usba_ep *ep = to_usba_ep(_ep);
  828. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  829. }
  830. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  831. {
  832. struct usba_ep *ep = to_usba_ep(_ep);
  833. struct usba_udc *udc = ep->udc;
  834. usba_writel(udc, EPT_RST, 1 << ep->index);
  835. }
  836. static const struct usb_ep_ops usba_ep_ops = {
  837. .enable = usba_ep_enable,
  838. .disable = usba_ep_disable,
  839. .alloc_request = usba_ep_alloc_request,
  840. .free_request = usba_ep_free_request,
  841. .queue = usba_ep_queue,
  842. .dequeue = usba_ep_dequeue,
  843. .set_halt = usba_ep_set_halt,
  844. .fifo_status = usba_ep_fifo_status,
  845. .fifo_flush = usba_ep_fifo_flush,
  846. };
  847. static int usba_udc_get_frame(struct usb_gadget *gadget)
  848. {
  849. struct usba_udc *udc = to_usba_udc(gadget);
  850. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  851. }
  852. static int usba_udc_wakeup(struct usb_gadget *gadget)
  853. {
  854. struct usba_udc *udc = to_usba_udc(gadget);
  855. unsigned long flags;
  856. u32 ctrl;
  857. int ret = -EINVAL;
  858. spin_lock_irqsave(&udc->lock, flags);
  859. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  860. ctrl = usba_readl(udc, CTRL);
  861. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  862. ret = 0;
  863. }
  864. spin_unlock_irqrestore(&udc->lock, flags);
  865. return ret;
  866. }
  867. static int
  868. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  869. {
  870. struct usba_udc *udc = to_usba_udc(gadget);
  871. unsigned long flags;
  872. gadget->is_selfpowered = (is_selfpowered != 0);
  873. spin_lock_irqsave(&udc->lock, flags);
  874. if (is_selfpowered)
  875. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  876. else
  877. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  878. spin_unlock_irqrestore(&udc->lock, flags);
  879. return 0;
  880. }
  881. static int atmel_usba_start(struct usb_gadget *gadget,
  882. struct usb_gadget_driver *driver);
  883. static int atmel_usba_stop(struct usb_gadget *gadget);
  884. static struct usb_ep *atmel_usba_match_ep(
  885. struct usb_gadget *gadget,
  886. struct usb_endpoint_descriptor *desc,
  887. struct usb_ss_ep_comp_descriptor *ep_comp
  888. )
  889. {
  890. struct usb_ep *_ep;
  891. struct usba_ep *ep;
  892. /* Look at endpoints until an unclaimed one looks usable */
  893. list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
  894. if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
  895. goto found_ep;
  896. }
  897. /* Fail */
  898. return NULL;
  899. found_ep:
  900. if (fifo_mode == 0) {
  901. /* Optimize hw fifo size based on ep type and other info */
  902. ep = to_usba_ep(_ep);
  903. switch (usb_endpoint_type(desc)) {
  904. case USB_ENDPOINT_XFER_CONTROL:
  905. break;
  906. case USB_ENDPOINT_XFER_ISOC:
  907. ep->fifo_size = 1024;
  908. ep->nr_banks = 2;
  909. break;
  910. case USB_ENDPOINT_XFER_BULK:
  911. ep->fifo_size = 512;
  912. ep->nr_banks = 1;
  913. break;
  914. case USB_ENDPOINT_XFER_INT:
  915. if (desc->wMaxPacketSize == 0)
  916. ep->fifo_size =
  917. roundup_pow_of_two(_ep->maxpacket_limit);
  918. else
  919. ep->fifo_size =
  920. roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
  921. ep->nr_banks = 1;
  922. break;
  923. }
  924. /* It might be a little bit late to set this */
  925. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  926. /* Generate ept_cfg basd on FIFO size and number of banks */
  927. if (ep->fifo_size <= 8)
  928. ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  929. else
  930. /* LSB is bit 1, not 0 */
  931. ep->ept_cfg =
  932. USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
  933. ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
  934. ep->udc->configured_ep++;
  935. }
  936. return _ep;
  937. }
  938. static const struct usb_gadget_ops usba_udc_ops = {
  939. .get_frame = usba_udc_get_frame,
  940. .wakeup = usba_udc_wakeup,
  941. .set_selfpowered = usba_udc_set_selfpowered,
  942. .udc_start = atmel_usba_start,
  943. .udc_stop = atmel_usba_stop,
  944. .match_ep = atmel_usba_match_ep,
  945. };
  946. static struct usb_endpoint_descriptor usba_ep0_desc = {
  947. .bLength = USB_DT_ENDPOINT_SIZE,
  948. .bDescriptorType = USB_DT_ENDPOINT,
  949. .bEndpointAddress = 0,
  950. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  951. .wMaxPacketSize = cpu_to_le16(64),
  952. /* FIXME: I have no idea what to put here */
  953. .bInterval = 1,
  954. };
  955. static struct usb_gadget usba_gadget_template = {
  956. .ops = &usba_udc_ops,
  957. .max_speed = USB_SPEED_HIGH,
  958. .name = "atmel_usba_udc",
  959. };
  960. /*
  961. * Called with interrupts disabled and udc->lock held.
  962. */
  963. static void reset_all_endpoints(struct usba_udc *udc)
  964. {
  965. struct usba_ep *ep;
  966. struct usba_request *req, *tmp_req;
  967. usba_writel(udc, EPT_RST, ~0UL);
  968. ep = to_usba_ep(udc->gadget.ep0);
  969. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  970. list_del_init(&req->queue);
  971. request_complete(ep, req, -ECONNRESET);
  972. }
  973. }
  974. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  975. {
  976. struct usba_ep *ep;
  977. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  978. return to_usba_ep(udc->gadget.ep0);
  979. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  980. u8 bEndpointAddress;
  981. if (!ep->ep.desc)
  982. continue;
  983. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  984. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  985. continue;
  986. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  987. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  988. return ep;
  989. }
  990. return NULL;
  991. }
  992. /* Called with interrupts disabled and udc->lock held */
  993. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  994. {
  995. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  996. ep->state = WAIT_FOR_SETUP;
  997. }
  998. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  999. {
  1000. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  1001. return 1;
  1002. return 0;
  1003. }
  1004. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  1005. {
  1006. u32 regval;
  1007. DBG(DBG_BUS, "setting address %u...\n", addr);
  1008. regval = usba_readl(udc, CTRL);
  1009. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  1010. usba_writel(udc, CTRL, regval);
  1011. }
  1012. static int do_test_mode(struct usba_udc *udc)
  1013. {
  1014. static const char test_packet_buffer[] = {
  1015. /* JKJKJKJK * 9 */
  1016. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1017. /* JJKKJJKK * 8 */
  1018. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  1019. /* JJKKJJKK * 8 */
  1020. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  1021. /* JJJJJJJKKKKKKK * 8 */
  1022. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  1023. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  1024. /* JJJJJJJK * 8 */
  1025. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  1026. /* {JKKKKKKK * 10}, JK */
  1027. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  1028. };
  1029. struct usba_ep *ep;
  1030. struct device *dev = &udc->pdev->dev;
  1031. int test_mode;
  1032. test_mode = udc->test_mode;
  1033. /* Start from a clean slate */
  1034. reset_all_endpoints(udc);
  1035. switch (test_mode) {
  1036. case 0x0100:
  1037. /* Test_J */
  1038. usba_writel(udc, TST, USBA_TST_J_MODE);
  1039. dev_info(dev, "Entering Test_J mode...\n");
  1040. break;
  1041. case 0x0200:
  1042. /* Test_K */
  1043. usba_writel(udc, TST, USBA_TST_K_MODE);
  1044. dev_info(dev, "Entering Test_K mode...\n");
  1045. break;
  1046. case 0x0300:
  1047. /*
  1048. * Test_SE0_NAK: Force high-speed mode and set up ep0
  1049. * for Bulk IN transfers
  1050. */
  1051. ep = &udc->usba_ep[0];
  1052. usba_writel(udc, TST,
  1053. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  1054. usba_ep_writel(ep, CFG,
  1055. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  1056. | USBA_EPT_DIR_IN
  1057. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1058. | USBA_BF(BK_NUMBER, 1));
  1059. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1060. set_protocol_stall(udc, ep);
  1061. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  1062. } else {
  1063. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1064. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  1065. }
  1066. break;
  1067. case 0x0400:
  1068. /* Test_Packet */
  1069. ep = &udc->usba_ep[0];
  1070. usba_ep_writel(ep, CFG,
  1071. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  1072. | USBA_EPT_DIR_IN
  1073. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1074. | USBA_BF(BK_NUMBER, 1));
  1075. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1076. set_protocol_stall(udc, ep);
  1077. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  1078. } else {
  1079. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1080. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  1081. memcpy_toio(ep->fifo, test_packet_buffer,
  1082. sizeof(test_packet_buffer));
  1083. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1084. dev_info(dev, "Entering Test_Packet mode...\n");
  1085. }
  1086. break;
  1087. default:
  1088. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  1089. return -EINVAL;
  1090. }
  1091. return 0;
  1092. }
  1093. /* Avoid overly long expressions */
  1094. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  1095. {
  1096. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1097. return true;
  1098. return false;
  1099. }
  1100. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1101. {
  1102. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  1103. return true;
  1104. return false;
  1105. }
  1106. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1107. {
  1108. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1109. return true;
  1110. return false;
  1111. }
  1112. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1113. struct usb_ctrlrequest *crq)
  1114. {
  1115. int retval = 0;
  1116. switch (crq->bRequest) {
  1117. case USB_REQ_GET_STATUS: {
  1118. u16 status;
  1119. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1120. status = cpu_to_le16(udc->devstatus);
  1121. } else if (crq->bRequestType
  1122. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1123. status = cpu_to_le16(0);
  1124. } else if (crq->bRequestType
  1125. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1126. struct usba_ep *target;
  1127. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1128. if (!target)
  1129. goto stall;
  1130. status = 0;
  1131. if (is_stalled(udc, target))
  1132. status |= cpu_to_le16(1);
  1133. } else
  1134. goto delegate;
  1135. /* Write directly to the FIFO. No queueing is done. */
  1136. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1137. goto stall;
  1138. ep->state = DATA_STAGE_IN;
  1139. usba_io_writew(status, ep->fifo);
  1140. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1141. break;
  1142. }
  1143. case USB_REQ_CLEAR_FEATURE: {
  1144. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1145. if (feature_is_dev_remote_wakeup(crq))
  1146. udc->devstatus
  1147. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1148. else
  1149. /* Can't CLEAR_FEATURE TEST_MODE */
  1150. goto stall;
  1151. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1152. struct usba_ep *target;
  1153. if (crq->wLength != cpu_to_le16(0)
  1154. || !feature_is_ep_halt(crq))
  1155. goto stall;
  1156. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1157. if (!target)
  1158. goto stall;
  1159. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1160. if (target->index != 0)
  1161. usba_ep_writel(target, CLR_STA,
  1162. USBA_TOGGLE_CLR);
  1163. } else {
  1164. goto delegate;
  1165. }
  1166. send_status(udc, ep);
  1167. break;
  1168. }
  1169. case USB_REQ_SET_FEATURE: {
  1170. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1171. if (feature_is_dev_test_mode(crq)) {
  1172. send_status(udc, ep);
  1173. ep->state = STATUS_STAGE_TEST;
  1174. udc->test_mode = le16_to_cpu(crq->wIndex);
  1175. return 0;
  1176. } else if (feature_is_dev_remote_wakeup(crq)) {
  1177. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1178. } else {
  1179. goto stall;
  1180. }
  1181. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1182. struct usba_ep *target;
  1183. if (crq->wLength != cpu_to_le16(0)
  1184. || !feature_is_ep_halt(crq))
  1185. goto stall;
  1186. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1187. if (!target)
  1188. goto stall;
  1189. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1190. } else
  1191. goto delegate;
  1192. send_status(udc, ep);
  1193. break;
  1194. }
  1195. case USB_REQ_SET_ADDRESS:
  1196. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1197. goto delegate;
  1198. set_address(udc, le16_to_cpu(crq->wValue));
  1199. send_status(udc, ep);
  1200. ep->state = STATUS_STAGE_ADDR;
  1201. break;
  1202. default:
  1203. delegate:
  1204. spin_unlock(&udc->lock);
  1205. retval = udc->driver->setup(&udc->gadget, crq);
  1206. spin_lock(&udc->lock);
  1207. }
  1208. return retval;
  1209. stall:
  1210. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1211. "halting endpoint...\n",
  1212. ep->ep.name, crq->bRequestType, crq->bRequest,
  1213. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1214. le16_to_cpu(crq->wLength));
  1215. set_protocol_stall(udc, ep);
  1216. return -1;
  1217. }
  1218. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1219. {
  1220. struct usba_request *req;
  1221. u32 epstatus;
  1222. u32 epctrl;
  1223. restart:
  1224. epstatus = usba_ep_readl(ep, STA);
  1225. epctrl = usba_ep_readl(ep, CTL);
  1226. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1227. ep->ep.name, ep->state, epstatus, epctrl);
  1228. req = NULL;
  1229. if (!list_empty(&ep->queue))
  1230. req = list_entry(ep->queue.next,
  1231. struct usba_request, queue);
  1232. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1233. if (req->submitted)
  1234. next_fifo_transaction(ep, req);
  1235. else
  1236. submit_request(ep, req);
  1237. if (req->last_transaction) {
  1238. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1239. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1240. }
  1241. goto restart;
  1242. }
  1243. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1244. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1245. switch (ep->state) {
  1246. case DATA_STAGE_IN:
  1247. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1248. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1249. ep->state = STATUS_STAGE_OUT;
  1250. break;
  1251. case STATUS_STAGE_ADDR:
  1252. /* Activate our new address */
  1253. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1254. | USBA_FADDR_EN));
  1255. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1256. ep->state = WAIT_FOR_SETUP;
  1257. break;
  1258. case STATUS_STAGE_IN:
  1259. if (req) {
  1260. list_del_init(&req->queue);
  1261. request_complete(ep, req, 0);
  1262. submit_next_request(ep);
  1263. }
  1264. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1265. ep->state = WAIT_FOR_SETUP;
  1266. break;
  1267. case STATUS_STAGE_TEST:
  1268. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1269. ep->state = WAIT_FOR_SETUP;
  1270. if (do_test_mode(udc))
  1271. set_protocol_stall(udc, ep);
  1272. break;
  1273. default:
  1274. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1275. "halting endpoint...\n",
  1276. ep->ep.name, ep->state);
  1277. set_protocol_stall(udc, ep);
  1278. break;
  1279. }
  1280. goto restart;
  1281. }
  1282. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1283. switch (ep->state) {
  1284. case STATUS_STAGE_OUT:
  1285. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1286. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1287. if (req) {
  1288. list_del_init(&req->queue);
  1289. request_complete(ep, req, 0);
  1290. }
  1291. ep->state = WAIT_FOR_SETUP;
  1292. break;
  1293. case DATA_STAGE_OUT:
  1294. receive_data(ep);
  1295. break;
  1296. default:
  1297. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1298. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1299. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1300. "halting endpoint...\n",
  1301. ep->ep.name, ep->state);
  1302. set_protocol_stall(udc, ep);
  1303. break;
  1304. }
  1305. goto restart;
  1306. }
  1307. if (epstatus & USBA_RX_SETUP) {
  1308. union {
  1309. struct usb_ctrlrequest crq;
  1310. unsigned long data[2];
  1311. } crq;
  1312. unsigned int pkt_len;
  1313. int ret;
  1314. if (ep->state != WAIT_FOR_SETUP) {
  1315. /*
  1316. * Didn't expect a SETUP packet at this
  1317. * point. Clean up any pending requests (which
  1318. * may be successful).
  1319. */
  1320. int status = -EPROTO;
  1321. /*
  1322. * RXRDY and TXCOMP are dropped when SETUP
  1323. * packets arrive. Just pretend we received
  1324. * the status packet.
  1325. */
  1326. if (ep->state == STATUS_STAGE_OUT
  1327. || ep->state == STATUS_STAGE_IN) {
  1328. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1329. status = 0;
  1330. }
  1331. if (req) {
  1332. list_del_init(&req->queue);
  1333. request_complete(ep, req, status);
  1334. }
  1335. }
  1336. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1337. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1338. if (pkt_len != sizeof(crq)) {
  1339. pr_warn("udc: Invalid packet length %u (expected %zu)\n",
  1340. pkt_len, sizeof(crq));
  1341. set_protocol_stall(udc, ep);
  1342. return;
  1343. }
  1344. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1345. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1346. /* Free up one bank in the FIFO so that we can
  1347. * generate or receive a reply right away. */
  1348. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1349. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1350. ep->state, crq.crq.bRequestType,
  1351. crq.crq.bRequest); */
  1352. if (crq.crq.bRequestType & USB_DIR_IN) {
  1353. /*
  1354. * The USB 2.0 spec states that "if wLength is
  1355. * zero, there is no data transfer phase."
  1356. * However, testusb #14 seems to actually
  1357. * expect a data phase even if wLength = 0...
  1358. */
  1359. ep->state = DATA_STAGE_IN;
  1360. } else {
  1361. if (crq.crq.wLength != cpu_to_le16(0))
  1362. ep->state = DATA_STAGE_OUT;
  1363. else
  1364. ep->state = STATUS_STAGE_IN;
  1365. }
  1366. ret = -1;
  1367. if (ep->index == 0)
  1368. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1369. else {
  1370. spin_unlock(&udc->lock);
  1371. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1372. spin_lock(&udc->lock);
  1373. }
  1374. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1375. crq.crq.bRequestType, crq.crq.bRequest,
  1376. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1377. if (ret < 0) {
  1378. /* Let the host know that we failed */
  1379. set_protocol_stall(udc, ep);
  1380. }
  1381. }
  1382. }
  1383. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1384. {
  1385. struct usba_request *req;
  1386. u32 epstatus;
  1387. u32 epctrl;
  1388. epstatus = usba_ep_readl(ep, STA);
  1389. epctrl = usba_ep_readl(ep, CTL);
  1390. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1391. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1392. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1393. if (list_empty(&ep->queue)) {
  1394. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1395. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1396. return;
  1397. }
  1398. req = list_entry(ep->queue.next, struct usba_request, queue);
  1399. if (req->using_dma) {
  1400. /* Send a zero-length packet */
  1401. usba_ep_writel(ep, SET_STA,
  1402. USBA_TX_PK_RDY);
  1403. usba_ep_writel(ep, CTL_DIS,
  1404. USBA_TX_PK_RDY);
  1405. list_del_init(&req->queue);
  1406. submit_next_request(ep);
  1407. request_complete(ep, req, 0);
  1408. } else {
  1409. if (req->submitted)
  1410. next_fifo_transaction(ep, req);
  1411. else
  1412. submit_request(ep, req);
  1413. if (req->last_transaction) {
  1414. list_del_init(&req->queue);
  1415. submit_next_request(ep);
  1416. request_complete(ep, req, 0);
  1417. }
  1418. }
  1419. epstatus = usba_ep_readl(ep, STA);
  1420. epctrl = usba_ep_readl(ep, CTL);
  1421. }
  1422. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1423. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1424. receive_data(ep);
  1425. }
  1426. }
  1427. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1428. {
  1429. struct usba_request *req;
  1430. u32 status, control, pending;
  1431. status = usba_dma_readl(ep, STATUS);
  1432. control = usba_dma_readl(ep, CONTROL);
  1433. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1434. ep->last_dma_status = status;
  1435. #endif
  1436. pending = status & control;
  1437. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1438. if (status & USBA_DMA_CH_EN) {
  1439. dev_err(&udc->pdev->dev,
  1440. "DMA_CH_EN is set after transfer is finished!\n");
  1441. dev_err(&udc->pdev->dev,
  1442. "status=%#08x, pending=%#08x, control=%#08x\n",
  1443. status, pending, control);
  1444. /*
  1445. * try to pretend nothing happened. We might have to
  1446. * do something here...
  1447. */
  1448. }
  1449. if (list_empty(&ep->queue))
  1450. /* Might happen if a reset comes along at the right moment */
  1451. return;
  1452. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1453. req = list_entry(ep->queue.next, struct usba_request, queue);
  1454. usba_update_req(ep, req, status);
  1455. list_del_init(&req->queue);
  1456. submit_next_request(ep);
  1457. request_complete(ep, req, 0);
  1458. }
  1459. }
  1460. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1461. {
  1462. struct usba_udc *udc = devid;
  1463. u32 status, int_enb;
  1464. u32 dma_status;
  1465. u32 ep_status;
  1466. spin_lock(&udc->lock);
  1467. int_enb = usba_int_enb_get(udc);
  1468. status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
  1469. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1470. if (status & USBA_DET_SUSPEND) {
  1471. toggle_bias(udc, 0);
  1472. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1473. usba_int_enb_set(udc, int_enb | USBA_WAKE_UP);
  1474. udc->bias_pulse_needed = true;
  1475. DBG(DBG_BUS, "Suspend detected\n");
  1476. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1477. && udc->driver && udc->driver->suspend) {
  1478. spin_unlock(&udc->lock);
  1479. udc->driver->suspend(&udc->gadget);
  1480. spin_lock(&udc->lock);
  1481. }
  1482. }
  1483. if (status & USBA_WAKE_UP) {
  1484. toggle_bias(udc, 1);
  1485. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1486. usba_int_enb_set(udc, int_enb & ~USBA_WAKE_UP);
  1487. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1488. }
  1489. if (status & USBA_END_OF_RESUME) {
  1490. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1491. generate_bias_pulse(udc);
  1492. DBG(DBG_BUS, "Resume detected\n");
  1493. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1494. && udc->driver && udc->driver->resume) {
  1495. spin_unlock(&udc->lock);
  1496. udc->driver->resume(&udc->gadget);
  1497. spin_lock(&udc->lock);
  1498. }
  1499. }
  1500. dma_status = USBA_BFEXT(DMA_INT, status);
  1501. if (dma_status) {
  1502. int i;
  1503. for (i = 1; i <= USBA_NR_DMAS; i++)
  1504. if (dma_status & (1 << i))
  1505. usba_dma_irq(udc, &udc->usba_ep[i]);
  1506. }
  1507. ep_status = USBA_BFEXT(EPT_INT, status);
  1508. if (ep_status) {
  1509. int i;
  1510. for (i = 0; i < udc->num_ep; i++)
  1511. if (ep_status & (1 << i)) {
  1512. if (ep_is_control(&udc->usba_ep[i]))
  1513. usba_control_irq(udc, &udc->usba_ep[i]);
  1514. else
  1515. usba_ep_irq(udc, &udc->usba_ep[i]);
  1516. }
  1517. }
  1518. if (status & USBA_END_OF_RESET) {
  1519. struct usba_ep *ep0, *ep;
  1520. int i, n;
  1521. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1522. generate_bias_pulse(udc);
  1523. reset_all_endpoints(udc);
  1524. if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
  1525. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1526. spin_unlock(&udc->lock);
  1527. usb_gadget_udc_reset(&udc->gadget, udc->driver);
  1528. spin_lock(&udc->lock);
  1529. }
  1530. if (status & USBA_HIGH_SPEED)
  1531. udc->gadget.speed = USB_SPEED_HIGH;
  1532. else
  1533. udc->gadget.speed = USB_SPEED_FULL;
  1534. DBG(DBG_BUS, "%s bus reset detected\n",
  1535. usb_speed_string(udc->gadget.speed));
  1536. ep0 = &udc->usba_ep[0];
  1537. ep0->ep.desc = &usba_ep0_desc;
  1538. ep0->state = WAIT_FOR_SETUP;
  1539. usba_ep_writel(ep0, CFG,
  1540. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1541. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1542. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1543. usba_ep_writel(ep0, CTL_ENB,
  1544. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1545. usba_int_enb_set(udc, int_enb | USBA_BF(EPT_INT, 1) |
  1546. USBA_DET_SUSPEND | USBA_END_OF_RESUME);
  1547. /*
  1548. * Unclear why we hit this irregularly, e.g. in usbtest,
  1549. * but it's clearly harmless...
  1550. */
  1551. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1552. dev_dbg(&udc->pdev->dev,
  1553. "ODD: EP0 configuration is invalid!\n");
  1554. /* Preallocate other endpoints */
  1555. n = fifo_mode ? udc->num_ep : udc->configured_ep;
  1556. for (i = 1; i < n; i++) {
  1557. ep = &udc->usba_ep[i];
  1558. usba_ep_writel(ep, CFG, ep->ept_cfg);
  1559. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
  1560. dev_dbg(&udc->pdev->dev,
  1561. "ODD: EP%d configuration is invalid!\n", i);
  1562. }
  1563. }
  1564. spin_unlock(&udc->lock);
  1565. return IRQ_HANDLED;
  1566. }
  1567. static int start_clock(struct usba_udc *udc)
  1568. {
  1569. int ret;
  1570. if (udc->clocked)
  1571. return 0;
  1572. ret = clk_prepare_enable(udc->pclk);
  1573. if (ret)
  1574. return ret;
  1575. ret = clk_prepare_enable(udc->hclk);
  1576. if (ret) {
  1577. clk_disable_unprepare(udc->pclk);
  1578. return ret;
  1579. }
  1580. udc->clocked = true;
  1581. return 0;
  1582. }
  1583. static void stop_clock(struct usba_udc *udc)
  1584. {
  1585. if (!udc->clocked)
  1586. return;
  1587. clk_disable_unprepare(udc->hclk);
  1588. clk_disable_unprepare(udc->pclk);
  1589. udc->clocked = false;
  1590. }
  1591. static int usba_start(struct usba_udc *udc)
  1592. {
  1593. unsigned long flags;
  1594. int ret;
  1595. ret = start_clock(udc);
  1596. if (ret)
  1597. return ret;
  1598. spin_lock_irqsave(&udc->lock, flags);
  1599. toggle_bias(udc, 1);
  1600. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1601. usba_int_enb_set(udc, USBA_END_OF_RESET);
  1602. spin_unlock_irqrestore(&udc->lock, flags);
  1603. return 0;
  1604. }
  1605. static void usba_stop(struct usba_udc *udc)
  1606. {
  1607. unsigned long flags;
  1608. spin_lock_irqsave(&udc->lock, flags);
  1609. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1610. reset_all_endpoints(udc);
  1611. /* This will also disable the DP pullup */
  1612. toggle_bias(udc, 0);
  1613. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1614. spin_unlock_irqrestore(&udc->lock, flags);
  1615. stop_clock(udc);
  1616. }
  1617. static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
  1618. {
  1619. struct usba_udc *udc = devid;
  1620. int vbus;
  1621. /* debounce */
  1622. udelay(10);
  1623. mutex_lock(&udc->vbus_mutex);
  1624. vbus = vbus_is_present(udc);
  1625. if (vbus != udc->vbus_prev) {
  1626. if (vbus) {
  1627. usba_start(udc);
  1628. } else {
  1629. usba_stop(udc);
  1630. if (udc->driver->disconnect)
  1631. udc->driver->disconnect(&udc->gadget);
  1632. }
  1633. udc->vbus_prev = vbus;
  1634. }
  1635. mutex_unlock(&udc->vbus_mutex);
  1636. return IRQ_HANDLED;
  1637. }
  1638. static int atmel_usba_start(struct usb_gadget *gadget,
  1639. struct usb_gadget_driver *driver)
  1640. {
  1641. int ret;
  1642. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1643. unsigned long flags;
  1644. spin_lock_irqsave(&udc->lock, flags);
  1645. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1646. udc->driver = driver;
  1647. spin_unlock_irqrestore(&udc->lock, flags);
  1648. mutex_lock(&udc->vbus_mutex);
  1649. if (gpio_is_valid(udc->vbus_pin))
  1650. enable_irq(gpio_to_irq(udc->vbus_pin));
  1651. /* If Vbus is present, enable the controller and wait for reset */
  1652. udc->vbus_prev = vbus_is_present(udc);
  1653. if (udc->vbus_prev) {
  1654. ret = usba_start(udc);
  1655. if (ret)
  1656. goto err;
  1657. }
  1658. mutex_unlock(&udc->vbus_mutex);
  1659. return 0;
  1660. err:
  1661. if (gpio_is_valid(udc->vbus_pin))
  1662. disable_irq(gpio_to_irq(udc->vbus_pin));
  1663. mutex_unlock(&udc->vbus_mutex);
  1664. spin_lock_irqsave(&udc->lock, flags);
  1665. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1666. udc->driver = NULL;
  1667. spin_unlock_irqrestore(&udc->lock, flags);
  1668. return ret;
  1669. }
  1670. static int atmel_usba_stop(struct usb_gadget *gadget)
  1671. {
  1672. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1673. if (gpio_is_valid(udc->vbus_pin))
  1674. disable_irq(gpio_to_irq(udc->vbus_pin));
  1675. if (fifo_mode == 0)
  1676. udc->configured_ep = 1;
  1677. usba_stop(udc);
  1678. udc->driver = NULL;
  1679. return 0;
  1680. }
  1681. #ifdef CONFIG_OF
  1682. static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
  1683. {
  1684. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1685. is_on ? AT91_PMC_BIASEN : 0);
  1686. }
  1687. static void at91sam9g45_pulse_bias(struct usba_udc *udc)
  1688. {
  1689. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
  1690. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1691. AT91_PMC_BIASEN);
  1692. }
  1693. static const struct usba_udc_errata at91sam9rl_errata = {
  1694. .toggle_bias = at91sam9rl_toggle_bias,
  1695. };
  1696. static const struct usba_udc_errata at91sam9g45_errata = {
  1697. .pulse_bias = at91sam9g45_pulse_bias,
  1698. };
  1699. static const struct of_device_id atmel_udc_dt_ids[] = {
  1700. { .compatible = "atmel,at91sam9rl-udc", .data = &at91sam9rl_errata },
  1701. { .compatible = "atmel,at91sam9g45-udc", .data = &at91sam9g45_errata },
  1702. { .compatible = "atmel,sama5d3-udc" },
  1703. { /* sentinel */ }
  1704. };
  1705. MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
  1706. static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
  1707. struct usba_udc *udc)
  1708. {
  1709. u32 val;
  1710. const char *name;
  1711. enum of_gpio_flags flags;
  1712. struct device_node *np = pdev->dev.of_node;
  1713. const struct of_device_id *match;
  1714. struct device_node *pp;
  1715. int i, ret;
  1716. struct usba_ep *eps, *ep;
  1717. match = of_match_node(atmel_udc_dt_ids, np);
  1718. if (!match)
  1719. return ERR_PTR(-EINVAL);
  1720. udc->errata = match->data;
  1721. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
  1722. if (IS_ERR(udc->pmc))
  1723. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
  1724. if (udc->errata && IS_ERR(udc->pmc))
  1725. return ERR_CAST(udc->pmc);
  1726. udc->num_ep = 0;
  1727. udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
  1728. &flags);
  1729. udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
  1730. if (fifo_mode == 0) {
  1731. pp = NULL;
  1732. while ((pp = of_get_next_child(np, pp)))
  1733. udc->num_ep++;
  1734. udc->configured_ep = 1;
  1735. } else
  1736. udc->num_ep = usba_config_fifo_table(udc);
  1737. eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
  1738. GFP_KERNEL);
  1739. if (!eps)
  1740. return ERR_PTR(-ENOMEM);
  1741. udc->gadget.ep0 = &eps[0].ep;
  1742. INIT_LIST_HEAD(&eps[0].ep.ep_list);
  1743. pp = NULL;
  1744. i = 0;
  1745. while ((pp = of_get_next_child(np, pp)) && i < udc->num_ep) {
  1746. ep = &eps[i];
  1747. ret = of_property_read_u32(pp, "reg", &val);
  1748. if (ret) {
  1749. dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
  1750. goto err;
  1751. }
  1752. ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : val;
  1753. ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
  1754. if (ret) {
  1755. dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
  1756. goto err;
  1757. }
  1758. ep->fifo_size = fifo_mode ? udc->fifo_cfg[i].fifo_size : val;
  1759. ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
  1760. if (ret) {
  1761. dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
  1762. goto err;
  1763. }
  1764. ep->nr_banks = fifo_mode ? udc->fifo_cfg[i].nr_banks : val;
  1765. ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
  1766. ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
  1767. ret = of_property_read_string(pp, "name", &name);
  1768. if (ret) {
  1769. dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);
  1770. goto err;
  1771. }
  1772. sprintf(ep->name, "ep%d", ep->index);
  1773. ep->ep.name = ep->name;
  1774. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1775. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1776. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1777. ep->ep.ops = &usba_ep_ops;
  1778. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  1779. ep->udc = udc;
  1780. INIT_LIST_HEAD(&ep->queue);
  1781. if (ep->index == 0) {
  1782. ep->ep.caps.type_control = true;
  1783. } else {
  1784. ep->ep.caps.type_iso = ep->can_isoc;
  1785. ep->ep.caps.type_bulk = true;
  1786. ep->ep.caps.type_int = true;
  1787. }
  1788. ep->ep.caps.dir_in = true;
  1789. ep->ep.caps.dir_out = true;
  1790. if (fifo_mode != 0) {
  1791. /*
  1792. * Generate ept_cfg based on FIFO size and
  1793. * banks number
  1794. */
  1795. if (ep->fifo_size <= 8)
  1796. ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  1797. else
  1798. /* LSB is bit 1, not 0 */
  1799. ep->ept_cfg =
  1800. USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
  1801. ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
  1802. }
  1803. if (i)
  1804. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1805. i++;
  1806. }
  1807. if (i == 0) {
  1808. dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
  1809. ret = -EINVAL;
  1810. goto err;
  1811. }
  1812. return eps;
  1813. err:
  1814. return ERR_PTR(ret);
  1815. }
  1816. #else
  1817. static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
  1818. struct usba_udc *udc)
  1819. {
  1820. return ERR_PTR(-ENOSYS);
  1821. }
  1822. #endif
  1823. static struct usba_ep * usba_udc_pdata(struct platform_device *pdev,
  1824. struct usba_udc *udc)
  1825. {
  1826. struct usba_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1827. struct usba_ep *eps;
  1828. int i;
  1829. if (!pdata)
  1830. return ERR_PTR(-ENXIO);
  1831. eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
  1832. GFP_KERNEL);
  1833. if (!eps)
  1834. return ERR_PTR(-ENOMEM);
  1835. udc->gadget.ep0 = &eps[0].ep;
  1836. udc->vbus_pin = pdata->vbus_pin;
  1837. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1838. udc->num_ep = pdata->num_ep;
  1839. INIT_LIST_HEAD(&eps[0].ep.ep_list);
  1840. for (i = 0; i < pdata->num_ep; i++) {
  1841. struct usba_ep *ep = &eps[i];
  1842. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1843. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1844. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1845. ep->ep.ops = &usba_ep_ops;
  1846. ep->ep.name = pdata->ep[i].name;
  1847. ep->fifo_size = pdata->ep[i].fifo_size;
  1848. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  1849. ep->udc = udc;
  1850. INIT_LIST_HEAD(&ep->queue);
  1851. ep->nr_banks = pdata->ep[i].nr_banks;
  1852. ep->index = pdata->ep[i].index;
  1853. ep->can_dma = pdata->ep[i].can_dma;
  1854. ep->can_isoc = pdata->ep[i].can_isoc;
  1855. if (i == 0) {
  1856. ep->ep.caps.type_control = true;
  1857. } else {
  1858. ep->ep.caps.type_iso = ep->can_isoc;
  1859. ep->ep.caps.type_bulk = true;
  1860. ep->ep.caps.type_int = true;
  1861. }
  1862. ep->ep.caps.dir_in = true;
  1863. ep->ep.caps.dir_out = true;
  1864. if (i)
  1865. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1866. }
  1867. return eps;
  1868. }
  1869. static int usba_udc_probe(struct platform_device *pdev)
  1870. {
  1871. struct resource *regs, *fifo;
  1872. struct clk *pclk, *hclk;
  1873. struct usba_udc *udc;
  1874. int irq, ret, i;
  1875. udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
  1876. if (!udc)
  1877. return -ENOMEM;
  1878. udc->gadget = usba_gadget_template;
  1879. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1880. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1881. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1882. if (!regs || !fifo)
  1883. return -ENXIO;
  1884. irq = platform_get_irq(pdev, 0);
  1885. if (irq < 0)
  1886. return irq;
  1887. pclk = devm_clk_get(&pdev->dev, "pclk");
  1888. if (IS_ERR(pclk))
  1889. return PTR_ERR(pclk);
  1890. hclk = devm_clk_get(&pdev->dev, "hclk");
  1891. if (IS_ERR(hclk))
  1892. return PTR_ERR(hclk);
  1893. spin_lock_init(&udc->lock);
  1894. mutex_init(&udc->vbus_mutex);
  1895. udc->pdev = pdev;
  1896. udc->pclk = pclk;
  1897. udc->hclk = hclk;
  1898. udc->vbus_pin = -ENODEV;
  1899. ret = -ENOMEM;
  1900. udc->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
  1901. if (!udc->regs) {
  1902. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1903. return ret;
  1904. }
  1905. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1906. (unsigned long)regs->start, udc->regs);
  1907. udc->fifo = devm_ioremap(&pdev->dev, fifo->start, resource_size(fifo));
  1908. if (!udc->fifo) {
  1909. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1910. return ret;
  1911. }
  1912. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1913. (unsigned long)fifo->start, udc->fifo);
  1914. platform_set_drvdata(pdev, udc);
  1915. /* Make sure we start from a clean slate */
  1916. ret = clk_prepare_enable(pclk);
  1917. if (ret) {
  1918. dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
  1919. return ret;
  1920. }
  1921. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1922. clk_disable_unprepare(pclk);
  1923. if (pdev->dev.of_node)
  1924. udc->usba_ep = atmel_udc_of_init(pdev, udc);
  1925. else
  1926. udc->usba_ep = usba_udc_pdata(pdev, udc);
  1927. toggle_bias(udc, 0);
  1928. if (IS_ERR(udc->usba_ep))
  1929. return PTR_ERR(udc->usba_ep);
  1930. ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
  1931. "atmel_usba_udc", udc);
  1932. if (ret) {
  1933. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1934. irq, ret);
  1935. return ret;
  1936. }
  1937. udc->irq = irq;
  1938. if (gpio_is_valid(udc->vbus_pin)) {
  1939. if (!devm_gpio_request(&pdev->dev, udc->vbus_pin, "atmel_usba_udc")) {
  1940. irq_set_status_flags(gpio_to_irq(udc->vbus_pin),
  1941. IRQ_NOAUTOEN);
  1942. ret = devm_request_threaded_irq(&pdev->dev,
  1943. gpio_to_irq(udc->vbus_pin), NULL,
  1944. usba_vbus_irq_thread, IRQF_ONESHOT,
  1945. "atmel_usba_udc", udc);
  1946. if (ret) {
  1947. udc->vbus_pin = -ENODEV;
  1948. dev_warn(&udc->pdev->dev,
  1949. "failed to request vbus irq; "
  1950. "assuming always on\n");
  1951. }
  1952. } else {
  1953. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1954. udc->vbus_pin = -EINVAL;
  1955. }
  1956. }
  1957. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1958. if (ret)
  1959. return ret;
  1960. device_init_wakeup(&pdev->dev, 1);
  1961. usba_init_debugfs(udc);
  1962. for (i = 1; i < udc->num_ep; i++)
  1963. usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
  1964. return 0;
  1965. }
  1966. static int usba_udc_remove(struct platform_device *pdev)
  1967. {
  1968. struct usba_udc *udc;
  1969. int i;
  1970. udc = platform_get_drvdata(pdev);
  1971. device_init_wakeup(&pdev->dev, 0);
  1972. usb_del_gadget_udc(&udc->gadget);
  1973. for (i = 1; i < udc->num_ep; i++)
  1974. usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
  1975. usba_cleanup_debugfs(udc);
  1976. return 0;
  1977. }
  1978. #ifdef CONFIG_PM_SLEEP
  1979. static int usba_udc_suspend(struct device *dev)
  1980. {
  1981. struct usba_udc *udc = dev_get_drvdata(dev);
  1982. /* Not started */
  1983. if (!udc->driver)
  1984. return 0;
  1985. mutex_lock(&udc->vbus_mutex);
  1986. if (!device_may_wakeup(dev)) {
  1987. usba_stop(udc);
  1988. goto out;
  1989. }
  1990. /*
  1991. * Device may wake up. We stay clocked if we failed
  1992. * to request vbus irq, assuming always on.
  1993. */
  1994. if (gpio_is_valid(udc->vbus_pin)) {
  1995. usba_stop(udc);
  1996. enable_irq_wake(gpio_to_irq(udc->vbus_pin));
  1997. }
  1998. out:
  1999. mutex_unlock(&udc->vbus_mutex);
  2000. return 0;
  2001. }
  2002. static int usba_udc_resume(struct device *dev)
  2003. {
  2004. struct usba_udc *udc = dev_get_drvdata(dev);
  2005. /* Not started */
  2006. if (!udc->driver)
  2007. return 0;
  2008. if (device_may_wakeup(dev) && gpio_is_valid(udc->vbus_pin))
  2009. disable_irq_wake(gpio_to_irq(udc->vbus_pin));
  2010. /* If Vbus is present, enable the controller and wait for reset */
  2011. mutex_lock(&udc->vbus_mutex);
  2012. udc->vbus_prev = vbus_is_present(udc);
  2013. if (udc->vbus_prev)
  2014. usba_start(udc);
  2015. mutex_unlock(&udc->vbus_mutex);
  2016. return 0;
  2017. }
  2018. #endif
  2019. static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
  2020. static struct platform_driver udc_driver = {
  2021. .remove = usba_udc_remove,
  2022. .driver = {
  2023. .name = "atmel_usba_udc",
  2024. .pm = &usba_udc_pm_ops,
  2025. .of_match_table = of_match_ptr(atmel_udc_dt_ids),
  2026. },
  2027. };
  2028. module_platform_driver_probe(udc_driver, usba_udc_probe);
  2029. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  2030. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  2031. MODULE_LICENSE("GPL");
  2032. MODULE_ALIAS("platform:atmel_usba_udc");