octeon_droq.c 25 KB

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  1. /**********************************************************************
  2. * Author: Cavium, Inc.
  3. *
  4. * Contact: support@cavium.com
  5. * Please include "LiquidIO" in the subject.
  6. *
  7. * Copyright (c) 2003-2016 Cavium, Inc.
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more details.
  17. ***********************************************************************/
  18. #include <linux/pci.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/vmalloc.h>
  21. #include "liquidio_common.h"
  22. #include "octeon_droq.h"
  23. #include "octeon_iq.h"
  24. #include "response_manager.h"
  25. #include "octeon_device.h"
  26. #include "octeon_main.h"
  27. #include "octeon_network.h"
  28. #include "cn66xx_regs.h"
  29. #include "cn66xx_device.h"
  30. #include "cn23xx_pf_device.h"
  31. #include "cn23xx_vf_device.h"
  32. struct niclist {
  33. struct list_head list;
  34. void *ptr;
  35. };
  36. struct __dispatch {
  37. struct list_head list;
  38. struct octeon_recv_info *rinfo;
  39. octeon_dispatch_fn_t disp_fn;
  40. };
  41. /** Get the argument that the user set when registering dispatch
  42. * function for a given opcode/subcode.
  43. * @param octeon_dev - the octeon device pointer.
  44. * @param opcode - the opcode for which the dispatch argument
  45. * is to be checked.
  46. * @param subcode - the subcode for which the dispatch argument
  47. * is to be checked.
  48. * @return Success: void * (argument to the dispatch function)
  49. * @return Failure: NULL
  50. *
  51. */
  52. static inline void *octeon_get_dispatch_arg(struct octeon_device *octeon_dev,
  53. u16 opcode, u16 subcode)
  54. {
  55. int idx;
  56. struct list_head *dispatch;
  57. void *fn_arg = NULL;
  58. u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
  59. idx = combined_opcode & OCTEON_OPCODE_MASK;
  60. spin_lock_bh(&octeon_dev->dispatch.lock);
  61. if (octeon_dev->dispatch.count == 0) {
  62. spin_unlock_bh(&octeon_dev->dispatch.lock);
  63. return NULL;
  64. }
  65. if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
  66. fn_arg = octeon_dev->dispatch.dlist[idx].arg;
  67. } else {
  68. list_for_each(dispatch,
  69. &octeon_dev->dispatch.dlist[idx].list) {
  70. if (((struct octeon_dispatch *)dispatch)->opcode ==
  71. combined_opcode) {
  72. fn_arg = ((struct octeon_dispatch *)
  73. dispatch)->arg;
  74. break;
  75. }
  76. }
  77. }
  78. spin_unlock_bh(&octeon_dev->dispatch.lock);
  79. return fn_arg;
  80. }
  81. /** Check for packets on Droq. This function should be called with lock held.
  82. * @param droq - Droq on which count is checked.
  83. * @return Returns packet count.
  84. */
  85. u32 octeon_droq_check_hw_for_pkts(struct octeon_droq *droq)
  86. {
  87. u32 pkt_count = 0;
  88. u32 last_count;
  89. pkt_count = readl(droq->pkts_sent_reg);
  90. last_count = pkt_count - droq->pkt_count;
  91. droq->pkt_count = pkt_count;
  92. /* we shall write to cnts at napi irq enable or end of droq tasklet */
  93. if (last_count)
  94. atomic_add(last_count, &droq->pkts_pending);
  95. return last_count;
  96. }
  97. static void octeon_droq_compute_max_packet_bufs(struct octeon_droq *droq)
  98. {
  99. u32 count = 0;
  100. /* max_empty_descs is the max. no. of descs that can have no buffers.
  101. * If the empty desc count goes beyond this value, we cannot safely
  102. * read in a 64K packet sent by Octeon
  103. * (64K is max pkt size from Octeon)
  104. */
  105. droq->max_empty_descs = 0;
  106. do {
  107. droq->max_empty_descs++;
  108. count += droq->buffer_size;
  109. } while (count < (64 * 1024));
  110. droq->max_empty_descs = droq->max_count - droq->max_empty_descs;
  111. }
  112. static void octeon_droq_reset_indices(struct octeon_droq *droq)
  113. {
  114. droq->read_idx = 0;
  115. droq->write_idx = 0;
  116. droq->refill_idx = 0;
  117. droq->refill_count = 0;
  118. atomic_set(&droq->pkts_pending, 0);
  119. }
  120. static void
  121. octeon_droq_destroy_ring_buffers(struct octeon_device *oct,
  122. struct octeon_droq *droq)
  123. {
  124. u32 i;
  125. struct octeon_skb_page_info *pg_info;
  126. for (i = 0; i < droq->max_count; i++) {
  127. pg_info = &droq->recv_buf_list[i].pg_info;
  128. if (pg_info->dma)
  129. lio_unmap_ring(oct->pci_dev,
  130. (u64)pg_info->dma);
  131. pg_info->dma = 0;
  132. if (pg_info->page)
  133. recv_buffer_destroy(droq->recv_buf_list[i].buffer,
  134. pg_info);
  135. droq->recv_buf_list[i].buffer = NULL;
  136. }
  137. octeon_droq_reset_indices(droq);
  138. }
  139. static int
  140. octeon_droq_setup_ring_buffers(struct octeon_device *oct,
  141. struct octeon_droq *droq)
  142. {
  143. u32 i;
  144. void *buf;
  145. struct octeon_droq_desc *desc_ring = droq->desc_ring;
  146. for (i = 0; i < droq->max_count; i++) {
  147. buf = recv_buffer_alloc(oct, &droq->recv_buf_list[i].pg_info);
  148. if (!buf) {
  149. dev_err(&oct->pci_dev->dev, "%s buffer alloc failed\n",
  150. __func__);
  151. droq->stats.rx_alloc_failure++;
  152. return -ENOMEM;
  153. }
  154. droq->recv_buf_list[i].buffer = buf;
  155. droq->recv_buf_list[i].data = get_rbd(buf);
  156. droq->info_list[i].length = 0;
  157. /* map ring buffers into memory */
  158. desc_ring[i].info_ptr = lio_map_ring_info(droq, i);
  159. desc_ring[i].buffer_ptr =
  160. lio_map_ring(droq->recv_buf_list[i].buffer);
  161. }
  162. octeon_droq_reset_indices(droq);
  163. octeon_droq_compute_max_packet_bufs(droq);
  164. return 0;
  165. }
  166. int octeon_delete_droq(struct octeon_device *oct, u32 q_no)
  167. {
  168. struct octeon_droq *droq = oct->droq[q_no];
  169. dev_dbg(&oct->pci_dev->dev, "%s[%d]\n", __func__, q_no);
  170. octeon_droq_destroy_ring_buffers(oct, droq);
  171. vfree(droq->recv_buf_list);
  172. if (droq->info_base_addr)
  173. lio_free_info_buffer(oct, droq);
  174. if (droq->desc_ring)
  175. lio_dma_free(oct, (droq->max_count * OCT_DROQ_DESC_SIZE),
  176. droq->desc_ring, droq->desc_ring_dma);
  177. memset(droq, 0, OCT_DROQ_SIZE);
  178. return 0;
  179. }
  180. int octeon_init_droq(struct octeon_device *oct,
  181. u32 q_no,
  182. u32 num_descs,
  183. u32 desc_size,
  184. void *app_ctx)
  185. {
  186. struct octeon_droq *droq;
  187. u32 desc_ring_size = 0, c_num_descs = 0, c_buf_size = 0;
  188. u32 c_pkts_per_intr = 0, c_refill_threshold = 0;
  189. int orig_node = dev_to_node(&oct->pci_dev->dev);
  190. int numa_node = cpu_to_node(q_no % num_online_cpus());
  191. dev_dbg(&oct->pci_dev->dev, "%s[%d]\n", __func__, q_no);
  192. droq = oct->droq[q_no];
  193. memset(droq, 0, OCT_DROQ_SIZE);
  194. droq->oct_dev = oct;
  195. droq->q_no = q_no;
  196. if (app_ctx)
  197. droq->app_ctx = app_ctx;
  198. else
  199. droq->app_ctx = (void *)(size_t)q_no;
  200. c_num_descs = num_descs;
  201. c_buf_size = desc_size;
  202. if (OCTEON_CN6XXX(oct)) {
  203. struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
  204. c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf6x);
  205. c_refill_threshold =
  206. (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf6x);
  207. } else if (OCTEON_CN23XX_PF(oct)) {
  208. struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf);
  209. c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf23);
  210. c_refill_threshold = (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf23);
  211. } else if (OCTEON_CN23XX_VF(oct)) {
  212. struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_vf);
  213. c_pkts_per_intr = (u32)CFG_GET_OQ_PKTS_PER_INTR(conf23);
  214. c_refill_threshold = (u32)CFG_GET_OQ_REFILL_THRESHOLD(conf23);
  215. } else {
  216. return 1;
  217. }
  218. droq->max_count = c_num_descs;
  219. droq->buffer_size = c_buf_size;
  220. desc_ring_size = droq->max_count * OCT_DROQ_DESC_SIZE;
  221. set_dev_node(&oct->pci_dev->dev, numa_node);
  222. droq->desc_ring = lio_dma_alloc(oct, desc_ring_size,
  223. (dma_addr_t *)&droq->desc_ring_dma);
  224. set_dev_node(&oct->pci_dev->dev, orig_node);
  225. if (!droq->desc_ring)
  226. droq->desc_ring = lio_dma_alloc(oct, desc_ring_size,
  227. (dma_addr_t *)&droq->desc_ring_dma);
  228. if (!droq->desc_ring) {
  229. dev_err(&oct->pci_dev->dev,
  230. "Output queue %d ring alloc failed\n", q_no);
  231. return 1;
  232. }
  233. dev_dbg(&oct->pci_dev->dev, "droq[%d]: desc_ring: virt: 0x%p, dma: %lx\n",
  234. q_no, droq->desc_ring, droq->desc_ring_dma);
  235. dev_dbg(&oct->pci_dev->dev, "droq[%d]: num_desc: %d\n", q_no,
  236. droq->max_count);
  237. droq->info_list = lio_alloc_info_buffer(oct, droq);
  238. if (!droq->info_list) {
  239. dev_err(&oct->pci_dev->dev, "Cannot allocate memory for info list.\n");
  240. lio_dma_free(oct, (droq->max_count * OCT_DROQ_DESC_SIZE),
  241. droq->desc_ring, droq->desc_ring_dma);
  242. return 1;
  243. }
  244. droq->recv_buf_list = (struct octeon_recv_buffer *)
  245. vmalloc_node(droq->max_count *
  246. OCT_DROQ_RECVBUF_SIZE,
  247. numa_node);
  248. if (!droq->recv_buf_list)
  249. droq->recv_buf_list = (struct octeon_recv_buffer *)
  250. vmalloc(droq->max_count *
  251. OCT_DROQ_RECVBUF_SIZE);
  252. if (!droq->recv_buf_list) {
  253. dev_err(&oct->pci_dev->dev, "Output queue recv buf list alloc failed\n");
  254. goto init_droq_fail;
  255. }
  256. if (octeon_droq_setup_ring_buffers(oct, droq))
  257. goto init_droq_fail;
  258. droq->pkts_per_intr = c_pkts_per_intr;
  259. droq->refill_threshold = c_refill_threshold;
  260. dev_dbg(&oct->pci_dev->dev, "DROQ INIT: max_empty_descs: %d\n",
  261. droq->max_empty_descs);
  262. spin_lock_init(&droq->lock);
  263. INIT_LIST_HEAD(&droq->dispatch_list);
  264. /* For 56xx Pass1, this function won't be called, so no checks. */
  265. oct->fn_list.setup_oq_regs(oct, q_no);
  266. oct->io_qmask.oq |= BIT_ULL(q_no);
  267. return 0;
  268. init_droq_fail:
  269. octeon_delete_droq(oct, q_no);
  270. return 1;
  271. }
  272. /* octeon_create_recv_info
  273. * Parameters:
  274. * octeon_dev - pointer to the octeon device structure
  275. * droq - droq in which the packet arrived.
  276. * buf_cnt - no. of buffers used by the packet.
  277. * idx - index in the descriptor for the first buffer in the packet.
  278. * Description:
  279. * Allocates a recv_info_t and copies the buffer addresses for packet data
  280. * into the recv_pkt space which starts at an 8B offset from recv_info_t.
  281. * Flags the descriptors for refill later. If available descriptors go
  282. * below the threshold to receive a 64K pkt, new buffers are first allocated
  283. * before the recv_pkt_t is created.
  284. * This routine will be called in interrupt context.
  285. * Returns:
  286. * Success: Pointer to recv_info_t
  287. * Failure: NULL.
  288. * Locks:
  289. * The droq->lock is held when this routine is called.
  290. */
  291. static inline struct octeon_recv_info *octeon_create_recv_info(
  292. struct octeon_device *octeon_dev,
  293. struct octeon_droq *droq,
  294. u32 buf_cnt,
  295. u32 idx)
  296. {
  297. struct octeon_droq_info *info;
  298. struct octeon_recv_pkt *recv_pkt;
  299. struct octeon_recv_info *recv_info;
  300. u32 i, bytes_left;
  301. struct octeon_skb_page_info *pg_info;
  302. info = &droq->info_list[idx];
  303. recv_info = octeon_alloc_recv_info(sizeof(struct __dispatch));
  304. if (!recv_info)
  305. return NULL;
  306. recv_pkt = recv_info->recv_pkt;
  307. recv_pkt->rh = info->rh;
  308. recv_pkt->length = (u32)info->length;
  309. recv_pkt->buffer_count = (u16)buf_cnt;
  310. recv_pkt->octeon_id = (u16)octeon_dev->octeon_id;
  311. i = 0;
  312. bytes_left = (u32)info->length;
  313. while (buf_cnt) {
  314. {
  315. pg_info = &droq->recv_buf_list[idx].pg_info;
  316. lio_unmap_ring(octeon_dev->pci_dev,
  317. (u64)pg_info->dma);
  318. pg_info->page = NULL;
  319. pg_info->dma = 0;
  320. }
  321. recv_pkt->buffer_size[i] =
  322. (bytes_left >=
  323. droq->buffer_size) ? droq->buffer_size : bytes_left;
  324. recv_pkt->buffer_ptr[i] = droq->recv_buf_list[idx].buffer;
  325. droq->recv_buf_list[idx].buffer = NULL;
  326. idx = incr_index(idx, 1, droq->max_count);
  327. bytes_left -= droq->buffer_size;
  328. i++;
  329. buf_cnt--;
  330. }
  331. return recv_info;
  332. }
  333. /* If we were not able to refill all buffers, try to move around
  334. * the buffers that were not dispatched.
  335. */
  336. static inline u32
  337. octeon_droq_refill_pullup_descs(struct octeon_droq *droq,
  338. struct octeon_droq_desc *desc_ring)
  339. {
  340. u32 desc_refilled = 0;
  341. u32 refill_index = droq->refill_idx;
  342. while (refill_index != droq->read_idx) {
  343. if (droq->recv_buf_list[refill_index].buffer) {
  344. droq->recv_buf_list[droq->refill_idx].buffer =
  345. droq->recv_buf_list[refill_index].buffer;
  346. droq->recv_buf_list[droq->refill_idx].data =
  347. droq->recv_buf_list[refill_index].data;
  348. desc_ring[droq->refill_idx].buffer_ptr =
  349. desc_ring[refill_index].buffer_ptr;
  350. droq->recv_buf_list[refill_index].buffer = NULL;
  351. desc_ring[refill_index].buffer_ptr = 0;
  352. do {
  353. droq->refill_idx = incr_index(droq->refill_idx,
  354. 1,
  355. droq->max_count);
  356. desc_refilled++;
  357. droq->refill_count--;
  358. } while (droq->recv_buf_list[droq->refill_idx].
  359. buffer);
  360. }
  361. refill_index = incr_index(refill_index, 1, droq->max_count);
  362. } /* while */
  363. return desc_refilled;
  364. }
  365. /* octeon_droq_refill
  366. * Parameters:
  367. * droq - droq in which descriptors require new buffers.
  368. * Description:
  369. * Called during normal DROQ processing in interrupt mode or by the poll
  370. * thread to refill the descriptors from which buffers were dispatched
  371. * to upper layers. Attempts to allocate new buffers. If that fails, moves
  372. * up buffers (that were not dispatched) to form a contiguous ring.
  373. * Returns:
  374. * No of descriptors refilled.
  375. * Locks:
  376. * This routine is called with droq->lock held.
  377. */
  378. static u32
  379. octeon_droq_refill(struct octeon_device *octeon_dev, struct octeon_droq *droq)
  380. {
  381. struct octeon_droq_desc *desc_ring;
  382. void *buf = NULL;
  383. u8 *data;
  384. u32 desc_refilled = 0;
  385. struct octeon_skb_page_info *pg_info;
  386. desc_ring = droq->desc_ring;
  387. while (droq->refill_count && (desc_refilled < droq->max_count)) {
  388. /* If a valid buffer exists (happens if there is no dispatch),
  389. * reuse
  390. * the buffer, else allocate.
  391. */
  392. if (!droq->recv_buf_list[droq->refill_idx].buffer) {
  393. pg_info =
  394. &droq->recv_buf_list[droq->refill_idx].pg_info;
  395. /* Either recycle the existing pages or go for
  396. * new page alloc
  397. */
  398. if (pg_info->page)
  399. buf = recv_buffer_reuse(octeon_dev, pg_info);
  400. else
  401. buf = recv_buffer_alloc(octeon_dev, pg_info);
  402. /* If a buffer could not be allocated, no point in
  403. * continuing
  404. */
  405. if (!buf) {
  406. droq->stats.rx_alloc_failure++;
  407. break;
  408. }
  409. droq->recv_buf_list[droq->refill_idx].buffer =
  410. buf;
  411. data = get_rbd(buf);
  412. } else {
  413. data = get_rbd(droq->recv_buf_list
  414. [droq->refill_idx].buffer);
  415. }
  416. droq->recv_buf_list[droq->refill_idx].data = data;
  417. desc_ring[droq->refill_idx].buffer_ptr =
  418. lio_map_ring(droq->recv_buf_list[droq->
  419. refill_idx].buffer);
  420. /* Reset any previous values in the length field. */
  421. droq->info_list[droq->refill_idx].length = 0;
  422. droq->refill_idx = incr_index(droq->refill_idx, 1,
  423. droq->max_count);
  424. desc_refilled++;
  425. droq->refill_count--;
  426. }
  427. if (droq->refill_count)
  428. desc_refilled +=
  429. octeon_droq_refill_pullup_descs(droq, desc_ring);
  430. /* if droq->refill_count
  431. * The refill count would not change in pass two. We only moved buffers
  432. * to close the gap in the ring, but we would still have the same no. of
  433. * buffers to refill.
  434. */
  435. return desc_refilled;
  436. }
  437. static inline u32
  438. octeon_droq_get_bufcount(u32 buf_size, u32 total_len)
  439. {
  440. u32 buf_cnt = 0;
  441. while (total_len > (buf_size * buf_cnt))
  442. buf_cnt++;
  443. return buf_cnt;
  444. }
  445. static int
  446. octeon_droq_dispatch_pkt(struct octeon_device *oct,
  447. struct octeon_droq *droq,
  448. union octeon_rh *rh,
  449. struct octeon_droq_info *info)
  450. {
  451. u32 cnt;
  452. octeon_dispatch_fn_t disp_fn;
  453. struct octeon_recv_info *rinfo;
  454. cnt = octeon_droq_get_bufcount(droq->buffer_size, (u32)info->length);
  455. disp_fn = octeon_get_dispatch(oct, (u16)rh->r.opcode,
  456. (u16)rh->r.subcode);
  457. if (disp_fn) {
  458. rinfo = octeon_create_recv_info(oct, droq, cnt, droq->read_idx);
  459. if (rinfo) {
  460. struct __dispatch *rdisp = rinfo->rsvd;
  461. rdisp->rinfo = rinfo;
  462. rdisp->disp_fn = disp_fn;
  463. rinfo->recv_pkt->rh = *rh;
  464. list_add_tail(&rdisp->list,
  465. &droq->dispatch_list);
  466. } else {
  467. droq->stats.dropped_nomem++;
  468. }
  469. } else {
  470. dev_err(&oct->pci_dev->dev, "DROQ: No dispatch function (opcode %u/%u)\n",
  471. (unsigned int)rh->r.opcode,
  472. (unsigned int)rh->r.subcode);
  473. droq->stats.dropped_nodispatch++;
  474. }
  475. return cnt;
  476. }
  477. static inline void octeon_droq_drop_packets(struct octeon_device *oct,
  478. struct octeon_droq *droq,
  479. u32 cnt)
  480. {
  481. u32 i = 0, buf_cnt;
  482. struct octeon_droq_info *info;
  483. for (i = 0; i < cnt; i++) {
  484. info = &droq->info_list[droq->read_idx];
  485. octeon_swap_8B_data((u64 *)info, 2);
  486. if (info->length) {
  487. info->length -= OCT_RH_SIZE;
  488. droq->stats.bytes_received += info->length;
  489. buf_cnt = octeon_droq_get_bufcount(droq->buffer_size,
  490. (u32)info->length);
  491. } else {
  492. dev_err(&oct->pci_dev->dev, "DROQ: In drop: pkt with len 0\n");
  493. buf_cnt = 1;
  494. }
  495. droq->read_idx = incr_index(droq->read_idx, buf_cnt,
  496. droq->max_count);
  497. droq->refill_count += buf_cnt;
  498. }
  499. }
  500. static u32
  501. octeon_droq_fast_process_packets(struct octeon_device *oct,
  502. struct octeon_droq *droq,
  503. u32 pkts_to_process)
  504. {
  505. struct octeon_droq_info *info;
  506. union octeon_rh *rh;
  507. u32 pkt, total_len = 0, pkt_count;
  508. pkt_count = pkts_to_process;
  509. for (pkt = 0; pkt < pkt_count; pkt++) {
  510. u32 pkt_len = 0;
  511. struct sk_buff *nicbuf = NULL;
  512. struct octeon_skb_page_info *pg_info;
  513. void *buf;
  514. info = &droq->info_list[droq->read_idx];
  515. octeon_swap_8B_data((u64 *)info, 2);
  516. if (!info->length) {
  517. dev_err(&oct->pci_dev->dev,
  518. "DROQ[%d] idx: %d len:0, pkt_cnt: %d\n",
  519. droq->q_no, droq->read_idx, pkt_count);
  520. print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS,
  521. (u8 *)info,
  522. OCT_DROQ_INFO_SIZE);
  523. break;
  524. }
  525. /* Len of resp hdr in included in the received data len. */
  526. info->length -= OCT_RH_SIZE;
  527. rh = &info->rh;
  528. total_len += (u32)info->length;
  529. if (opcode_slow_path(rh)) {
  530. u32 buf_cnt;
  531. buf_cnt = octeon_droq_dispatch_pkt(oct, droq, rh, info);
  532. droq->read_idx = incr_index(droq->read_idx,
  533. buf_cnt, droq->max_count);
  534. droq->refill_count += buf_cnt;
  535. } else {
  536. if (info->length <= droq->buffer_size) {
  537. pkt_len = (u32)info->length;
  538. nicbuf = droq->recv_buf_list[
  539. droq->read_idx].buffer;
  540. pg_info = &droq->recv_buf_list[
  541. droq->read_idx].pg_info;
  542. if (recv_buffer_recycle(oct, pg_info))
  543. pg_info->page = NULL;
  544. droq->recv_buf_list[droq->read_idx].buffer =
  545. NULL;
  546. droq->read_idx = incr_index(droq->read_idx, 1,
  547. droq->max_count);
  548. droq->refill_count++;
  549. } else {
  550. nicbuf = octeon_fast_packet_alloc((u32)
  551. info->length);
  552. pkt_len = 0;
  553. /* nicbuf allocation can fail. We'll handle it
  554. * inside the loop.
  555. */
  556. while (pkt_len < info->length) {
  557. int cpy_len, idx = droq->read_idx;
  558. cpy_len = ((pkt_len + droq->buffer_size)
  559. > info->length) ?
  560. ((u32)info->length - pkt_len) :
  561. droq->buffer_size;
  562. if (nicbuf) {
  563. octeon_fast_packet_next(droq,
  564. nicbuf,
  565. cpy_len,
  566. idx);
  567. buf = droq->recv_buf_list[idx].
  568. buffer;
  569. recv_buffer_fast_free(buf);
  570. droq->recv_buf_list[idx].buffer
  571. = NULL;
  572. } else {
  573. droq->stats.rx_alloc_failure++;
  574. }
  575. pkt_len += cpy_len;
  576. droq->read_idx =
  577. incr_index(droq->read_idx, 1,
  578. droq->max_count);
  579. droq->refill_count++;
  580. }
  581. }
  582. if (nicbuf) {
  583. if (droq->ops.fptr) {
  584. droq->ops.fptr(oct->octeon_id,
  585. nicbuf, pkt_len,
  586. rh, &droq->napi,
  587. droq->ops.farg);
  588. } else {
  589. recv_buffer_free(nicbuf);
  590. }
  591. }
  592. }
  593. if (droq->refill_count >= droq->refill_threshold) {
  594. int desc_refilled = octeon_droq_refill(oct, droq);
  595. /* Flush the droq descriptor data to memory to be sure
  596. * that when we update the credits the data in memory
  597. * is accurate.
  598. */
  599. wmb();
  600. writel((desc_refilled), droq->pkts_credit_reg);
  601. /* make sure mmio write completes */
  602. mmiowb();
  603. }
  604. } /* for (each packet)... */
  605. /* Increment refill_count by the number of buffers processed. */
  606. droq->stats.pkts_received += pkt;
  607. droq->stats.bytes_received += total_len;
  608. if ((droq->ops.drop_on_max) && (pkts_to_process - pkt)) {
  609. octeon_droq_drop_packets(oct, droq, (pkts_to_process - pkt));
  610. droq->stats.dropped_toomany += (pkts_to_process - pkt);
  611. return pkts_to_process;
  612. }
  613. return pkt;
  614. }
  615. int
  616. octeon_droq_process_packets(struct octeon_device *oct,
  617. struct octeon_droq *droq,
  618. u32 budget)
  619. {
  620. u32 pkt_count = 0, pkts_processed = 0;
  621. struct list_head *tmp, *tmp2;
  622. /* Grab the droq lock */
  623. spin_lock(&droq->lock);
  624. octeon_droq_check_hw_for_pkts(droq);
  625. pkt_count = atomic_read(&droq->pkts_pending);
  626. if (!pkt_count) {
  627. spin_unlock(&droq->lock);
  628. return 0;
  629. }
  630. if (pkt_count > budget)
  631. pkt_count = budget;
  632. pkts_processed = octeon_droq_fast_process_packets(oct, droq, pkt_count);
  633. atomic_sub(pkts_processed, &droq->pkts_pending);
  634. /* Release the spin lock */
  635. spin_unlock(&droq->lock);
  636. list_for_each_safe(tmp, tmp2, &droq->dispatch_list) {
  637. struct __dispatch *rdisp = (struct __dispatch *)tmp;
  638. list_del(tmp);
  639. rdisp->disp_fn(rdisp->rinfo,
  640. octeon_get_dispatch_arg
  641. (oct,
  642. (u16)rdisp->rinfo->recv_pkt->rh.r.opcode,
  643. (u16)rdisp->rinfo->recv_pkt->rh.r.subcode));
  644. }
  645. /* If there are packets pending. schedule tasklet again */
  646. if (atomic_read(&droq->pkts_pending))
  647. return 1;
  648. return 0;
  649. }
  650. /**
  651. * Utility function to poll for packets. check_hw_for_packets must be
  652. * called before calling this routine.
  653. */
  654. static int
  655. octeon_droq_process_poll_pkts(struct octeon_device *oct,
  656. struct octeon_droq *droq, u32 budget)
  657. {
  658. struct list_head *tmp, *tmp2;
  659. u32 pkts_available = 0, pkts_processed = 0;
  660. u32 total_pkts_processed = 0;
  661. if (budget > droq->max_count)
  662. budget = droq->max_count;
  663. spin_lock(&droq->lock);
  664. while (total_pkts_processed < budget) {
  665. octeon_droq_check_hw_for_pkts(droq);
  666. pkts_available = min((budget - total_pkts_processed),
  667. (u32)(atomic_read(&droq->pkts_pending)));
  668. if (pkts_available == 0)
  669. break;
  670. pkts_processed =
  671. octeon_droq_fast_process_packets(oct, droq,
  672. pkts_available);
  673. atomic_sub(pkts_processed, &droq->pkts_pending);
  674. total_pkts_processed += pkts_processed;
  675. }
  676. spin_unlock(&droq->lock);
  677. list_for_each_safe(tmp, tmp2, &droq->dispatch_list) {
  678. struct __dispatch *rdisp = (struct __dispatch *)tmp;
  679. list_del(tmp);
  680. rdisp->disp_fn(rdisp->rinfo,
  681. octeon_get_dispatch_arg
  682. (oct,
  683. (u16)rdisp->rinfo->recv_pkt->rh.r.opcode,
  684. (u16)rdisp->rinfo->recv_pkt->rh.r.subcode));
  685. }
  686. return total_pkts_processed;
  687. }
  688. int
  689. octeon_process_droq_poll_cmd(struct octeon_device *oct, u32 q_no, int cmd,
  690. u32 arg)
  691. {
  692. struct octeon_droq *droq;
  693. droq = oct->droq[q_no];
  694. if (cmd == POLL_EVENT_PROCESS_PKTS)
  695. return octeon_droq_process_poll_pkts(oct, droq, arg);
  696. if (cmd == POLL_EVENT_PENDING_PKTS) {
  697. u32 pkt_cnt = atomic_read(&droq->pkts_pending);
  698. return octeon_droq_process_packets(oct, droq, pkt_cnt);
  699. }
  700. if (cmd == POLL_EVENT_ENABLE_INTR) {
  701. u32 value;
  702. unsigned long flags;
  703. /* Enable Pkt Interrupt */
  704. switch (oct->chip_id) {
  705. case OCTEON_CN66XX:
  706. case OCTEON_CN68XX: {
  707. struct octeon_cn6xxx *cn6xxx =
  708. (struct octeon_cn6xxx *)oct->chip;
  709. spin_lock_irqsave
  710. (&cn6xxx->lock_for_droq_int_enb_reg, flags);
  711. value =
  712. octeon_read_csr(oct,
  713. CN6XXX_SLI_PKT_TIME_INT_ENB);
  714. value |= (1 << q_no);
  715. octeon_write_csr(oct,
  716. CN6XXX_SLI_PKT_TIME_INT_ENB,
  717. value);
  718. value =
  719. octeon_read_csr(oct,
  720. CN6XXX_SLI_PKT_CNT_INT_ENB);
  721. value |= (1 << q_no);
  722. octeon_write_csr(oct,
  723. CN6XXX_SLI_PKT_CNT_INT_ENB,
  724. value);
  725. /* don't bother flushing the enables */
  726. spin_unlock_irqrestore
  727. (&cn6xxx->lock_for_droq_int_enb_reg, flags);
  728. return 0;
  729. }
  730. break;
  731. case OCTEON_CN23XX_PF_VID: {
  732. lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
  733. }
  734. break;
  735. case OCTEON_CN23XX_VF_VID:
  736. lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
  737. break;
  738. }
  739. return 0;
  740. }
  741. dev_err(&oct->pci_dev->dev, "%s Unknown command: %d\n", __func__, cmd);
  742. return -EINVAL;
  743. }
  744. int octeon_register_droq_ops(struct octeon_device *oct, u32 q_no,
  745. struct octeon_droq_ops *ops)
  746. {
  747. struct octeon_droq *droq;
  748. unsigned long flags;
  749. struct octeon_config *oct_cfg = NULL;
  750. oct_cfg = octeon_get_conf(oct);
  751. if (!oct_cfg)
  752. return -EINVAL;
  753. if (!(ops)) {
  754. dev_err(&oct->pci_dev->dev, "%s: droq_ops pointer is NULL\n",
  755. __func__);
  756. return -EINVAL;
  757. }
  758. if (q_no >= CFG_GET_OQ_MAX_Q(oct_cfg)) {
  759. dev_err(&oct->pci_dev->dev, "%s: droq id (%d) exceeds MAX (%d)\n",
  760. __func__, q_no, (oct->num_oqs - 1));
  761. return -EINVAL;
  762. }
  763. droq = oct->droq[q_no];
  764. spin_lock_irqsave(&droq->lock, flags);
  765. memcpy(&droq->ops, ops, sizeof(struct octeon_droq_ops));
  766. spin_unlock_irqrestore(&droq->lock, flags);
  767. return 0;
  768. }
  769. int octeon_unregister_droq_ops(struct octeon_device *oct, u32 q_no)
  770. {
  771. unsigned long flags;
  772. struct octeon_droq *droq;
  773. struct octeon_config *oct_cfg = NULL;
  774. oct_cfg = octeon_get_conf(oct);
  775. if (!oct_cfg)
  776. return -EINVAL;
  777. if (q_no >= CFG_GET_OQ_MAX_Q(oct_cfg)) {
  778. dev_err(&oct->pci_dev->dev, "%s: droq id (%d) exceeds MAX (%d)\n",
  779. __func__, q_no, oct->num_oqs - 1);
  780. return -EINVAL;
  781. }
  782. droq = oct->droq[q_no];
  783. if (!droq) {
  784. dev_info(&oct->pci_dev->dev,
  785. "Droq id (%d) not available.\n", q_no);
  786. return 0;
  787. }
  788. spin_lock_irqsave(&droq->lock, flags);
  789. droq->ops.fptr = NULL;
  790. droq->ops.farg = NULL;
  791. droq->ops.drop_on_max = 0;
  792. spin_unlock_irqrestore(&droq->lock, flags);
  793. return 0;
  794. }
  795. int octeon_create_droq(struct octeon_device *oct,
  796. u32 q_no, u32 num_descs,
  797. u32 desc_size, void *app_ctx)
  798. {
  799. struct octeon_droq *droq;
  800. int numa_node = cpu_to_node(q_no % num_online_cpus());
  801. if (oct->droq[q_no]) {
  802. dev_dbg(&oct->pci_dev->dev, "Droq already in use. Cannot create droq %d again\n",
  803. q_no);
  804. return 1;
  805. }
  806. /* Allocate the DS for the new droq. */
  807. droq = vmalloc_node(sizeof(*droq), numa_node);
  808. if (!droq)
  809. droq = vmalloc(sizeof(*droq));
  810. if (!droq)
  811. return -1;
  812. memset(droq, 0, sizeof(struct octeon_droq));
  813. /*Disable the pkt o/p for this Q */
  814. octeon_set_droq_pkt_op(oct, q_no, 0);
  815. oct->droq[q_no] = droq;
  816. /* Initialize the Droq */
  817. if (octeon_init_droq(oct, q_no, num_descs, desc_size, app_ctx)) {
  818. vfree(oct->droq[q_no]);
  819. oct->droq[q_no] = NULL;
  820. return -1;
  821. }
  822. oct->num_oqs++;
  823. dev_dbg(&oct->pci_dev->dev, "%s: Total number of OQ: %d\n", __func__,
  824. oct->num_oqs);
  825. /* Global Droq register settings */
  826. /* As of now not required, as setting are done for all 32 Droqs at
  827. * the same time.
  828. */
  829. return 0;
  830. }