pt1.c 25 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/sched/signal.h>
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include <linux/vmalloc.h>
  24. #include <linux/pci.h>
  25. #include <linux/kthread.h>
  26. #include <linux/freezer.h>
  27. #include <linux/ratelimit.h>
  28. #include "dvbdev.h"
  29. #include "dvb_demux.h"
  30. #include "dmxdev.h"
  31. #include "dvb_net.h"
  32. #include "dvb_frontend.h"
  33. #include "va1j5jf8007t.h"
  34. #include "va1j5jf8007s.h"
  35. #define DRIVER_NAME "earth-pt1"
  36. #define PT1_PAGE_SHIFT 12
  37. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  38. #define PT1_NR_UPACKETS 1024
  39. #define PT1_NR_BUFS 511
  40. struct pt1_buffer_page {
  41. __le32 upackets[PT1_NR_UPACKETS];
  42. };
  43. struct pt1_table_page {
  44. __le32 next_pfn;
  45. __le32 buf_pfns[PT1_NR_BUFS];
  46. };
  47. struct pt1_buffer {
  48. struct pt1_buffer_page *page;
  49. dma_addr_t addr;
  50. };
  51. struct pt1_table {
  52. struct pt1_table_page *page;
  53. dma_addr_t addr;
  54. struct pt1_buffer bufs[PT1_NR_BUFS];
  55. };
  56. #define PT1_NR_ADAPS 4
  57. struct pt1_adapter;
  58. struct pt1 {
  59. struct pci_dev *pdev;
  60. void __iomem *regs;
  61. struct i2c_adapter i2c_adap;
  62. int i2c_running;
  63. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  64. struct pt1_table *tables;
  65. struct task_struct *kthread;
  66. int table_index;
  67. int buf_index;
  68. struct mutex lock;
  69. int power;
  70. int reset;
  71. };
  72. struct pt1_adapter {
  73. struct pt1 *pt1;
  74. int index;
  75. u8 *buf;
  76. int upacket_count;
  77. int packet_count;
  78. int st_count;
  79. struct dvb_adapter adap;
  80. struct dvb_demux demux;
  81. int users;
  82. struct dmxdev dmxdev;
  83. struct dvb_frontend *fe;
  84. int (*orig_set_voltage)(struct dvb_frontend *fe,
  85. enum fe_sec_voltage voltage);
  86. int (*orig_sleep)(struct dvb_frontend *fe);
  87. int (*orig_init)(struct dvb_frontend *fe);
  88. enum fe_sec_voltage voltage;
  89. int sleep;
  90. };
  91. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  92. {
  93. writel(data, pt1->regs + reg * 4);
  94. }
  95. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  96. {
  97. return readl(pt1->regs + reg * 4);
  98. }
  99. static int pt1_nr_tables = 8;
  100. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  101. static void pt1_increment_table_count(struct pt1 *pt1)
  102. {
  103. pt1_write_reg(pt1, 0, 0x00000020);
  104. }
  105. static void pt1_init_table_count(struct pt1 *pt1)
  106. {
  107. pt1_write_reg(pt1, 0, 0x00000010);
  108. }
  109. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  110. {
  111. pt1_write_reg(pt1, 5, first_pfn);
  112. pt1_write_reg(pt1, 0, 0x0c000040);
  113. }
  114. static void pt1_unregister_tables(struct pt1 *pt1)
  115. {
  116. pt1_write_reg(pt1, 0, 0x08080000);
  117. }
  118. static int pt1_sync(struct pt1 *pt1)
  119. {
  120. int i;
  121. for (i = 0; i < 57; i++) {
  122. if (pt1_read_reg(pt1, 0) & 0x20000000)
  123. return 0;
  124. pt1_write_reg(pt1, 0, 0x00000008);
  125. }
  126. dev_err(&pt1->pdev->dev, "could not sync\n");
  127. return -EIO;
  128. }
  129. static u64 pt1_identify(struct pt1 *pt1)
  130. {
  131. int i;
  132. u64 id;
  133. id = 0;
  134. for (i = 0; i < 57; i++) {
  135. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  136. pt1_write_reg(pt1, 0, 0x00000008);
  137. }
  138. return id;
  139. }
  140. static int pt1_unlock(struct pt1 *pt1)
  141. {
  142. int i;
  143. pt1_write_reg(pt1, 0, 0x00000008);
  144. for (i = 0; i < 3; i++) {
  145. if (pt1_read_reg(pt1, 0) & 0x80000000)
  146. return 0;
  147. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  148. }
  149. dev_err(&pt1->pdev->dev, "could not unlock\n");
  150. return -EIO;
  151. }
  152. static int pt1_reset_pci(struct pt1 *pt1)
  153. {
  154. int i;
  155. pt1_write_reg(pt1, 0, 0x01010000);
  156. pt1_write_reg(pt1, 0, 0x01000000);
  157. for (i = 0; i < 10; i++) {
  158. if (pt1_read_reg(pt1, 0) & 0x00000001)
  159. return 0;
  160. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  161. }
  162. dev_err(&pt1->pdev->dev, "could not reset PCI\n");
  163. return -EIO;
  164. }
  165. static int pt1_reset_ram(struct pt1 *pt1)
  166. {
  167. int i;
  168. pt1_write_reg(pt1, 0, 0x02020000);
  169. pt1_write_reg(pt1, 0, 0x02000000);
  170. for (i = 0; i < 10; i++) {
  171. if (pt1_read_reg(pt1, 0) & 0x00000002)
  172. return 0;
  173. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  174. }
  175. dev_err(&pt1->pdev->dev, "could not reset RAM\n");
  176. return -EIO;
  177. }
  178. static int pt1_do_enable_ram(struct pt1 *pt1)
  179. {
  180. int i, j;
  181. u32 status;
  182. status = pt1_read_reg(pt1, 0) & 0x00000004;
  183. pt1_write_reg(pt1, 0, 0x00000002);
  184. for (i = 0; i < 10; i++) {
  185. for (j = 0; j < 1024; j++) {
  186. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  187. return 0;
  188. }
  189. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  190. }
  191. dev_err(&pt1->pdev->dev, "could not enable RAM\n");
  192. return -EIO;
  193. }
  194. static int pt1_enable_ram(struct pt1 *pt1)
  195. {
  196. int i, ret;
  197. int phase;
  198. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  199. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  200. for (i = 0; i < phase; i++) {
  201. ret = pt1_do_enable_ram(pt1);
  202. if (ret < 0)
  203. return ret;
  204. }
  205. return 0;
  206. }
  207. static void pt1_disable_ram(struct pt1 *pt1)
  208. {
  209. pt1_write_reg(pt1, 0, 0x0b0b0000);
  210. }
  211. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  212. {
  213. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  214. }
  215. static void pt1_init_streams(struct pt1 *pt1)
  216. {
  217. int i;
  218. for (i = 0; i < PT1_NR_ADAPS; i++)
  219. pt1_set_stream(pt1, i, 0);
  220. }
  221. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  222. {
  223. u32 upacket;
  224. int i;
  225. int index;
  226. struct pt1_adapter *adap;
  227. int offset;
  228. u8 *buf;
  229. int sc;
  230. if (!page->upackets[PT1_NR_UPACKETS - 1])
  231. return 0;
  232. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  233. upacket = le32_to_cpu(page->upackets[i]);
  234. index = (upacket >> 29) - 1;
  235. if (index < 0 || index >= PT1_NR_ADAPS)
  236. continue;
  237. adap = pt1->adaps[index];
  238. if (upacket >> 25 & 1)
  239. adap->upacket_count = 0;
  240. else if (!adap->upacket_count)
  241. continue;
  242. if (upacket >> 24 & 1)
  243. printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
  244. pt1->table_index, pt1->buf_index);
  245. sc = upacket >> 26 & 0x7;
  246. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  247. printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
  248. index);
  249. adap->st_count = sc;
  250. buf = adap->buf;
  251. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  252. buf[offset] = upacket >> 16;
  253. buf[offset + 1] = upacket >> 8;
  254. if (adap->upacket_count != 62)
  255. buf[offset + 2] = upacket;
  256. if (++adap->upacket_count >= 63) {
  257. adap->upacket_count = 0;
  258. if (++adap->packet_count >= 21) {
  259. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  260. adap->packet_count = 0;
  261. }
  262. }
  263. }
  264. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  265. return 1;
  266. }
  267. static int pt1_thread(void *data)
  268. {
  269. struct pt1 *pt1;
  270. struct pt1_buffer_page *page;
  271. pt1 = data;
  272. set_freezable();
  273. while (!kthread_should_stop()) {
  274. try_to_freeze();
  275. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  276. if (!pt1_filter(pt1, page)) {
  277. schedule_timeout_interruptible((HZ + 999) / 1000);
  278. continue;
  279. }
  280. if (++pt1->buf_index >= PT1_NR_BUFS) {
  281. pt1_increment_table_count(pt1);
  282. pt1->buf_index = 0;
  283. if (++pt1->table_index >= pt1_nr_tables)
  284. pt1->table_index = 0;
  285. }
  286. }
  287. return 0;
  288. }
  289. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  290. {
  291. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  292. }
  293. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  294. {
  295. void *page;
  296. dma_addr_t addr;
  297. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  298. GFP_KERNEL);
  299. if (page == NULL)
  300. return NULL;
  301. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  302. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  303. *addrp = addr;
  304. *pfnp = addr >> PT1_PAGE_SHIFT;
  305. return page;
  306. }
  307. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  308. {
  309. pt1_free_page(pt1, buf->page, buf->addr);
  310. }
  311. static int
  312. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  313. {
  314. struct pt1_buffer_page *page;
  315. dma_addr_t addr;
  316. page = pt1_alloc_page(pt1, &addr, pfnp);
  317. if (page == NULL)
  318. return -ENOMEM;
  319. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  320. buf->page = page;
  321. buf->addr = addr;
  322. return 0;
  323. }
  324. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  325. {
  326. int i;
  327. for (i = 0; i < PT1_NR_BUFS; i++)
  328. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  329. pt1_free_page(pt1, table->page, table->addr);
  330. }
  331. static int
  332. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  333. {
  334. struct pt1_table_page *page;
  335. dma_addr_t addr;
  336. int i, ret;
  337. u32 buf_pfn;
  338. page = pt1_alloc_page(pt1, &addr, pfnp);
  339. if (page == NULL)
  340. return -ENOMEM;
  341. for (i = 0; i < PT1_NR_BUFS; i++) {
  342. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  343. if (ret < 0)
  344. goto err;
  345. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  346. }
  347. pt1_increment_table_count(pt1);
  348. table->page = page;
  349. table->addr = addr;
  350. return 0;
  351. err:
  352. while (i--)
  353. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  354. pt1_free_page(pt1, page, addr);
  355. return ret;
  356. }
  357. static void pt1_cleanup_tables(struct pt1 *pt1)
  358. {
  359. struct pt1_table *tables;
  360. int i;
  361. tables = pt1->tables;
  362. pt1_unregister_tables(pt1);
  363. for (i = 0; i < pt1_nr_tables; i++)
  364. pt1_cleanup_table(pt1, &tables[i]);
  365. vfree(tables);
  366. }
  367. static int pt1_init_tables(struct pt1 *pt1)
  368. {
  369. struct pt1_table *tables;
  370. int i, ret;
  371. u32 first_pfn, pfn;
  372. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  373. if (tables == NULL)
  374. return -ENOMEM;
  375. pt1_init_table_count(pt1);
  376. i = 0;
  377. if (pt1_nr_tables) {
  378. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  379. if (ret)
  380. goto err;
  381. i++;
  382. }
  383. while (i < pt1_nr_tables) {
  384. ret = pt1_init_table(pt1, &tables[i], &pfn);
  385. if (ret)
  386. goto err;
  387. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  388. i++;
  389. }
  390. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  391. pt1_register_tables(pt1, first_pfn);
  392. pt1->tables = tables;
  393. return 0;
  394. err:
  395. while (i--)
  396. pt1_cleanup_table(pt1, &tables[i]);
  397. vfree(tables);
  398. return ret;
  399. }
  400. static int pt1_start_polling(struct pt1 *pt1)
  401. {
  402. int ret = 0;
  403. mutex_lock(&pt1->lock);
  404. if (!pt1->kthread) {
  405. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  406. if (IS_ERR(pt1->kthread)) {
  407. ret = PTR_ERR(pt1->kthread);
  408. pt1->kthread = NULL;
  409. }
  410. }
  411. mutex_unlock(&pt1->lock);
  412. return ret;
  413. }
  414. static int pt1_start_feed(struct dvb_demux_feed *feed)
  415. {
  416. struct pt1_adapter *adap;
  417. adap = container_of(feed->demux, struct pt1_adapter, demux);
  418. if (!adap->users++) {
  419. int ret;
  420. ret = pt1_start_polling(adap->pt1);
  421. if (ret)
  422. return ret;
  423. pt1_set_stream(adap->pt1, adap->index, 1);
  424. }
  425. return 0;
  426. }
  427. static void pt1_stop_polling(struct pt1 *pt1)
  428. {
  429. int i, count;
  430. mutex_lock(&pt1->lock);
  431. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  432. count += pt1->adaps[i]->users;
  433. if (count == 0 && pt1->kthread) {
  434. kthread_stop(pt1->kthread);
  435. pt1->kthread = NULL;
  436. }
  437. mutex_unlock(&pt1->lock);
  438. }
  439. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  440. {
  441. struct pt1_adapter *adap;
  442. adap = container_of(feed->demux, struct pt1_adapter, demux);
  443. if (!--adap->users) {
  444. pt1_set_stream(adap->pt1, adap->index, 0);
  445. pt1_stop_polling(adap->pt1);
  446. }
  447. return 0;
  448. }
  449. static void
  450. pt1_update_power(struct pt1 *pt1)
  451. {
  452. int bits;
  453. int i;
  454. struct pt1_adapter *adap;
  455. static const int sleep_bits[] = {
  456. 1 << 4,
  457. 1 << 6 | 1 << 7,
  458. 1 << 5,
  459. 1 << 6 | 1 << 8,
  460. };
  461. bits = pt1->power | !pt1->reset << 3;
  462. mutex_lock(&pt1->lock);
  463. for (i = 0; i < PT1_NR_ADAPS; i++) {
  464. adap = pt1->adaps[i];
  465. switch (adap->voltage) {
  466. case SEC_VOLTAGE_13: /* actually 11V */
  467. bits |= 1 << 1;
  468. break;
  469. case SEC_VOLTAGE_18: /* actually 15V */
  470. bits |= 1 << 1 | 1 << 2;
  471. break;
  472. default:
  473. break;
  474. }
  475. /* XXX: The bits should be changed depending on adap->sleep. */
  476. bits |= sleep_bits[i];
  477. }
  478. pt1_write_reg(pt1, 1, bits);
  479. mutex_unlock(&pt1->lock);
  480. }
  481. static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
  482. {
  483. struct pt1_adapter *adap;
  484. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  485. adap->voltage = voltage;
  486. pt1_update_power(adap->pt1);
  487. if (adap->orig_set_voltage)
  488. return adap->orig_set_voltage(fe, voltage);
  489. else
  490. return 0;
  491. }
  492. static int pt1_sleep(struct dvb_frontend *fe)
  493. {
  494. struct pt1_adapter *adap;
  495. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  496. adap->sleep = 1;
  497. pt1_update_power(adap->pt1);
  498. if (adap->orig_sleep)
  499. return adap->orig_sleep(fe);
  500. else
  501. return 0;
  502. }
  503. static int pt1_wakeup(struct dvb_frontend *fe)
  504. {
  505. struct pt1_adapter *adap;
  506. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  507. adap->sleep = 0;
  508. pt1_update_power(adap->pt1);
  509. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  510. if (adap->orig_init)
  511. return adap->orig_init(fe);
  512. else
  513. return 0;
  514. }
  515. static void pt1_free_adapter(struct pt1_adapter *adap)
  516. {
  517. adap->demux.dmx.close(&adap->demux.dmx);
  518. dvb_dmxdev_release(&adap->dmxdev);
  519. dvb_dmx_release(&adap->demux);
  520. dvb_unregister_adapter(&adap->adap);
  521. free_page((unsigned long)adap->buf);
  522. kfree(adap);
  523. }
  524. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  525. static struct pt1_adapter *
  526. pt1_alloc_adapter(struct pt1 *pt1)
  527. {
  528. struct pt1_adapter *adap;
  529. void *buf;
  530. struct dvb_adapter *dvb_adap;
  531. struct dvb_demux *demux;
  532. struct dmxdev *dmxdev;
  533. int ret;
  534. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  535. if (!adap) {
  536. ret = -ENOMEM;
  537. goto err;
  538. }
  539. adap->pt1 = pt1;
  540. adap->voltage = SEC_VOLTAGE_OFF;
  541. adap->sleep = 1;
  542. buf = (u8 *)__get_free_page(GFP_KERNEL);
  543. if (!buf) {
  544. ret = -ENOMEM;
  545. goto err_kfree;
  546. }
  547. adap->buf = buf;
  548. adap->upacket_count = 0;
  549. adap->packet_count = 0;
  550. adap->st_count = -1;
  551. dvb_adap = &adap->adap;
  552. dvb_adap->priv = adap;
  553. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  554. &pt1->pdev->dev, adapter_nr);
  555. if (ret < 0)
  556. goto err_free_page;
  557. demux = &adap->demux;
  558. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  559. demux->priv = adap;
  560. demux->feednum = 256;
  561. demux->filternum = 256;
  562. demux->start_feed = pt1_start_feed;
  563. demux->stop_feed = pt1_stop_feed;
  564. demux->write_to_decoder = NULL;
  565. ret = dvb_dmx_init(demux);
  566. if (ret < 0)
  567. goto err_unregister_adapter;
  568. dmxdev = &adap->dmxdev;
  569. dmxdev->filternum = 256;
  570. dmxdev->demux = &demux->dmx;
  571. dmxdev->capabilities = 0;
  572. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  573. if (ret < 0)
  574. goto err_dmx_release;
  575. return adap;
  576. err_dmx_release:
  577. dvb_dmx_release(demux);
  578. err_unregister_adapter:
  579. dvb_unregister_adapter(dvb_adap);
  580. err_free_page:
  581. free_page((unsigned long)buf);
  582. err_kfree:
  583. kfree(adap);
  584. err:
  585. return ERR_PTR(ret);
  586. }
  587. static void pt1_cleanup_adapters(struct pt1 *pt1)
  588. {
  589. int i;
  590. for (i = 0; i < PT1_NR_ADAPS; i++)
  591. pt1_free_adapter(pt1->adaps[i]);
  592. }
  593. static int pt1_init_adapters(struct pt1 *pt1)
  594. {
  595. int i;
  596. struct pt1_adapter *adap;
  597. int ret;
  598. for (i = 0; i < PT1_NR_ADAPS; i++) {
  599. adap = pt1_alloc_adapter(pt1);
  600. if (IS_ERR(adap)) {
  601. ret = PTR_ERR(adap);
  602. goto err;
  603. }
  604. adap->index = i;
  605. pt1->adaps[i] = adap;
  606. }
  607. return 0;
  608. err:
  609. while (i--)
  610. pt1_free_adapter(pt1->adaps[i]);
  611. return ret;
  612. }
  613. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  614. {
  615. dvb_unregister_frontend(adap->fe);
  616. }
  617. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  618. {
  619. int ret;
  620. adap->orig_set_voltage = fe->ops.set_voltage;
  621. adap->orig_sleep = fe->ops.sleep;
  622. adap->orig_init = fe->ops.init;
  623. fe->ops.set_voltage = pt1_set_voltage;
  624. fe->ops.sleep = pt1_sleep;
  625. fe->ops.init = pt1_wakeup;
  626. ret = dvb_register_frontend(&adap->adap, fe);
  627. if (ret < 0)
  628. return ret;
  629. adap->fe = fe;
  630. return 0;
  631. }
  632. static void pt1_cleanup_frontends(struct pt1 *pt1)
  633. {
  634. int i;
  635. for (i = 0; i < PT1_NR_ADAPS; i++)
  636. pt1_cleanup_frontend(pt1->adaps[i]);
  637. }
  638. struct pt1_config {
  639. struct va1j5jf8007s_config va1j5jf8007s_config;
  640. struct va1j5jf8007t_config va1j5jf8007t_config;
  641. };
  642. static const struct pt1_config pt1_configs[2] = {
  643. {
  644. {
  645. .demod_address = 0x1b,
  646. .frequency = VA1J5JF8007S_20MHZ,
  647. },
  648. {
  649. .demod_address = 0x1a,
  650. .frequency = VA1J5JF8007T_20MHZ,
  651. },
  652. }, {
  653. {
  654. .demod_address = 0x19,
  655. .frequency = VA1J5JF8007S_20MHZ,
  656. },
  657. {
  658. .demod_address = 0x18,
  659. .frequency = VA1J5JF8007T_20MHZ,
  660. },
  661. },
  662. };
  663. static const struct pt1_config pt2_configs[2] = {
  664. {
  665. {
  666. .demod_address = 0x1b,
  667. .frequency = VA1J5JF8007S_25MHZ,
  668. },
  669. {
  670. .demod_address = 0x1a,
  671. .frequency = VA1J5JF8007T_25MHZ,
  672. },
  673. }, {
  674. {
  675. .demod_address = 0x19,
  676. .frequency = VA1J5JF8007S_25MHZ,
  677. },
  678. {
  679. .demod_address = 0x18,
  680. .frequency = VA1J5JF8007T_25MHZ,
  681. },
  682. },
  683. };
  684. static int pt1_init_frontends(struct pt1 *pt1)
  685. {
  686. int i, j;
  687. struct i2c_adapter *i2c_adap;
  688. const struct pt1_config *configs, *config;
  689. struct dvb_frontend *fe[4];
  690. int ret;
  691. i = 0;
  692. j = 0;
  693. i2c_adap = &pt1->i2c_adap;
  694. configs = pt1->pdev->device == 0x211a ? pt1_configs : pt2_configs;
  695. do {
  696. config = &configs[i / 2];
  697. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  698. i2c_adap);
  699. if (!fe[i]) {
  700. ret = -ENODEV; /* This does not sound nice... */
  701. goto err;
  702. }
  703. i++;
  704. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  705. i2c_adap);
  706. if (!fe[i]) {
  707. ret = -ENODEV;
  708. goto err;
  709. }
  710. i++;
  711. ret = va1j5jf8007s_prepare(fe[i - 2]);
  712. if (ret < 0)
  713. goto err;
  714. ret = va1j5jf8007t_prepare(fe[i - 1]);
  715. if (ret < 0)
  716. goto err;
  717. } while (i < 4);
  718. do {
  719. ret = pt1_init_frontend(pt1->adaps[j], fe[j]);
  720. if (ret < 0)
  721. goto err;
  722. } while (++j < 4);
  723. return 0;
  724. err:
  725. while (i-- > j)
  726. fe[i]->ops.release(fe[i]);
  727. while (j--)
  728. dvb_unregister_frontend(fe[j]);
  729. return ret;
  730. }
  731. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  732. int clock, int data, int next_addr)
  733. {
  734. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  735. !clock << 11 | !data << 10 | next_addr);
  736. }
  737. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  738. {
  739. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  740. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  741. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  742. *addrp = addr + 3;
  743. }
  744. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  745. {
  746. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  747. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  748. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  749. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  750. *addrp = addr + 4;
  751. }
  752. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  753. {
  754. int i;
  755. for (i = 0; i < 8; i++)
  756. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  757. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  758. *addrp = addr;
  759. }
  760. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  761. {
  762. int i;
  763. for (i = 0; i < 8; i++)
  764. pt1_i2c_read_bit(pt1, addr, &addr);
  765. pt1_i2c_write_bit(pt1, addr, &addr, last);
  766. *addrp = addr;
  767. }
  768. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  769. {
  770. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  771. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  772. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  773. *addrp = addr + 3;
  774. }
  775. static void
  776. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  777. {
  778. int i;
  779. pt1_i2c_prepare(pt1, addr, &addr);
  780. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  781. for (i = 0; i < msg->len; i++)
  782. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  783. *addrp = addr;
  784. }
  785. static void
  786. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  787. {
  788. int i;
  789. pt1_i2c_prepare(pt1, addr, &addr);
  790. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  791. for (i = 0; i < msg->len; i++)
  792. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  793. *addrp = addr;
  794. }
  795. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  796. {
  797. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  798. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  799. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  800. pt1_write_reg(pt1, 0, 0x00000004);
  801. do {
  802. if (signal_pending(current))
  803. return -EINTR;
  804. schedule_timeout_interruptible((HZ + 999) / 1000);
  805. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  806. return 0;
  807. }
  808. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  809. {
  810. int addr;
  811. addr = 0;
  812. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  813. addr = addr + 1;
  814. if (!pt1->i2c_running) {
  815. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  816. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  817. addr = addr + 2;
  818. pt1->i2c_running = 1;
  819. }
  820. *addrp = addr;
  821. }
  822. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  823. {
  824. struct pt1 *pt1;
  825. int i;
  826. struct i2c_msg *msg, *next_msg;
  827. int addr, ret;
  828. u16 len;
  829. u32 word;
  830. pt1 = i2c_get_adapdata(adap);
  831. for (i = 0; i < num; i++) {
  832. msg = &msgs[i];
  833. if (msg->flags & I2C_M_RD)
  834. return -ENOTSUPP;
  835. if (i + 1 < num)
  836. next_msg = &msgs[i + 1];
  837. else
  838. next_msg = NULL;
  839. if (next_msg && next_msg->flags & I2C_M_RD) {
  840. i++;
  841. len = next_msg->len;
  842. if (len > 4)
  843. return -ENOTSUPP;
  844. pt1_i2c_begin(pt1, &addr);
  845. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  846. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  847. ret = pt1_i2c_end(pt1, addr);
  848. if (ret < 0)
  849. return ret;
  850. word = pt1_read_reg(pt1, 2);
  851. while (len--) {
  852. next_msg->buf[len] = word;
  853. word >>= 8;
  854. }
  855. } else {
  856. pt1_i2c_begin(pt1, &addr);
  857. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  858. ret = pt1_i2c_end(pt1, addr);
  859. if (ret < 0)
  860. return ret;
  861. }
  862. }
  863. return num;
  864. }
  865. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  866. {
  867. return I2C_FUNC_I2C;
  868. }
  869. static const struct i2c_algorithm pt1_i2c_algo = {
  870. .master_xfer = pt1_i2c_xfer,
  871. .functionality = pt1_i2c_func,
  872. };
  873. static void pt1_i2c_wait(struct pt1 *pt1)
  874. {
  875. int i;
  876. for (i = 0; i < 128; i++)
  877. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  878. }
  879. static void pt1_i2c_init(struct pt1 *pt1)
  880. {
  881. int i;
  882. for (i = 0; i < 1024; i++)
  883. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  884. }
  885. static void pt1_remove(struct pci_dev *pdev)
  886. {
  887. struct pt1 *pt1;
  888. void __iomem *regs;
  889. pt1 = pci_get_drvdata(pdev);
  890. regs = pt1->regs;
  891. if (pt1->kthread)
  892. kthread_stop(pt1->kthread);
  893. pt1_cleanup_tables(pt1);
  894. pt1_cleanup_frontends(pt1);
  895. pt1_disable_ram(pt1);
  896. pt1->power = 0;
  897. pt1->reset = 1;
  898. pt1_update_power(pt1);
  899. pt1_cleanup_adapters(pt1);
  900. i2c_del_adapter(&pt1->i2c_adap);
  901. kfree(pt1);
  902. pci_iounmap(pdev, regs);
  903. pci_release_regions(pdev);
  904. pci_disable_device(pdev);
  905. }
  906. static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  907. {
  908. int ret;
  909. void __iomem *regs;
  910. struct pt1 *pt1;
  911. struct i2c_adapter *i2c_adap;
  912. ret = pci_enable_device(pdev);
  913. if (ret < 0)
  914. goto err;
  915. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  916. if (ret < 0)
  917. goto err_pci_disable_device;
  918. pci_set_master(pdev);
  919. ret = pci_request_regions(pdev, DRIVER_NAME);
  920. if (ret < 0)
  921. goto err_pci_disable_device;
  922. regs = pci_iomap(pdev, 0, 0);
  923. if (!regs) {
  924. ret = -EIO;
  925. goto err_pci_release_regions;
  926. }
  927. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  928. if (!pt1) {
  929. ret = -ENOMEM;
  930. goto err_pci_iounmap;
  931. }
  932. mutex_init(&pt1->lock);
  933. pt1->pdev = pdev;
  934. pt1->regs = regs;
  935. pci_set_drvdata(pdev, pt1);
  936. ret = pt1_init_adapters(pt1);
  937. if (ret < 0)
  938. goto err_kfree;
  939. mutex_init(&pt1->lock);
  940. pt1->power = 0;
  941. pt1->reset = 1;
  942. pt1_update_power(pt1);
  943. i2c_adap = &pt1->i2c_adap;
  944. i2c_adap->algo = &pt1_i2c_algo;
  945. i2c_adap->algo_data = NULL;
  946. i2c_adap->dev.parent = &pdev->dev;
  947. strcpy(i2c_adap->name, DRIVER_NAME);
  948. i2c_set_adapdata(i2c_adap, pt1);
  949. ret = i2c_add_adapter(i2c_adap);
  950. if (ret < 0)
  951. goto err_pt1_cleanup_adapters;
  952. pt1_i2c_init(pt1);
  953. pt1_i2c_wait(pt1);
  954. ret = pt1_sync(pt1);
  955. if (ret < 0)
  956. goto err_i2c_del_adapter;
  957. pt1_identify(pt1);
  958. ret = pt1_unlock(pt1);
  959. if (ret < 0)
  960. goto err_i2c_del_adapter;
  961. ret = pt1_reset_pci(pt1);
  962. if (ret < 0)
  963. goto err_i2c_del_adapter;
  964. ret = pt1_reset_ram(pt1);
  965. if (ret < 0)
  966. goto err_i2c_del_adapter;
  967. ret = pt1_enable_ram(pt1);
  968. if (ret < 0)
  969. goto err_i2c_del_adapter;
  970. pt1_init_streams(pt1);
  971. pt1->power = 1;
  972. pt1_update_power(pt1);
  973. schedule_timeout_uninterruptible((HZ + 49) / 50);
  974. pt1->reset = 0;
  975. pt1_update_power(pt1);
  976. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  977. ret = pt1_init_frontends(pt1);
  978. if (ret < 0)
  979. goto err_pt1_disable_ram;
  980. ret = pt1_init_tables(pt1);
  981. if (ret < 0)
  982. goto err_pt1_cleanup_frontends;
  983. return 0;
  984. err_pt1_cleanup_frontends:
  985. pt1_cleanup_frontends(pt1);
  986. err_pt1_disable_ram:
  987. pt1_disable_ram(pt1);
  988. pt1->power = 0;
  989. pt1->reset = 1;
  990. pt1_update_power(pt1);
  991. err_i2c_del_adapter:
  992. i2c_del_adapter(i2c_adap);
  993. err_pt1_cleanup_adapters:
  994. pt1_cleanup_adapters(pt1);
  995. err_kfree:
  996. kfree(pt1);
  997. err_pci_iounmap:
  998. pci_iounmap(pdev, regs);
  999. err_pci_release_regions:
  1000. pci_release_regions(pdev);
  1001. err_pci_disable_device:
  1002. pci_disable_device(pdev);
  1003. err:
  1004. return ret;
  1005. }
  1006. static struct pci_device_id pt1_id_table[] = {
  1007. { PCI_DEVICE(0x10ee, 0x211a) },
  1008. { PCI_DEVICE(0x10ee, 0x222a) },
  1009. { },
  1010. };
  1011. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1012. static struct pci_driver pt1_driver = {
  1013. .name = DRIVER_NAME,
  1014. .probe = pt1_probe,
  1015. .remove = pt1_remove,
  1016. .id_table = pt1_id_table,
  1017. };
  1018. module_pci_driver(pt1_driver);
  1019. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1020. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1021. MODULE_LICENSE("GPL");