ina2xx-adc.c 18 KB

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  1. /*
  2. * INA2XX Current and Power Monitors
  3. *
  4. * Copyright 2015 Baylibre SAS.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Based on linux/drivers/iio/adc/ad7291.c
  11. * Copyright 2010-2011 Analog Devices Inc.
  12. *
  13. * Based on linux/drivers/hwmon/ina2xx.c
  14. * Copyright 2012 Lothar Felten <l-felten@ti.com>
  15. *
  16. * Licensed under the GPL-2 or later.
  17. *
  18. * IIO driver for INA219-220-226-230-231
  19. *
  20. * Configurable 7-bit I2C slave address from 0x40 to 0x4F
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/kfifo_buf.h>
  27. #include <linux/iio/sysfs.h>
  28. #include <linux/kthread.h>
  29. #include <linux/module.h>
  30. #include <linux/regmap.h>
  31. #include <linux/util_macros.h>
  32. #include <linux/platform_data/ina2xx.h>
  33. /* INA2XX registers definition */
  34. #define INA2XX_CONFIG 0x00
  35. #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */
  36. #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */
  37. #define INA2XX_POWER 0x03 /* readonly */
  38. #define INA2XX_CURRENT 0x04 /* readonly */
  39. #define INA2XX_CALIBRATION 0x05
  40. #define INA226_ALERT_MASK GENMASK(2, 1)
  41. #define INA266_CVRF BIT(3)
  42. #define INA2XX_MAX_REGISTERS 8
  43. /* settings - depend on use case */
  44. #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */
  45. #define INA226_CONFIG_DEFAULT 0x4327
  46. #define INA226_DEFAULT_AVG 4
  47. #define INA226_DEFAULT_IT 1110
  48. #define INA2XX_RSHUNT_DEFAULT 10000
  49. /*
  50. * bit mask for reading the averaging setting in the configuration register
  51. * FIXME: use regmap_fields.
  52. */
  53. #define INA2XX_MODE_MASK GENMASK(3, 0)
  54. #define INA226_AVG_MASK GENMASK(11, 9)
  55. #define INA226_SHIFT_AVG(val) ((val) << 9)
  56. /* Integration time for VBus */
  57. #define INA226_ITB_MASK GENMASK(8, 6)
  58. #define INA226_SHIFT_ITB(val) ((val) << 6)
  59. /* Integration time for VShunt */
  60. #define INA226_ITS_MASK GENMASK(5, 3)
  61. #define INA226_SHIFT_ITS(val) ((val) << 3)
  62. /* Cosmetic macro giving the sampling period for a full P=UxI cycle */
  63. #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \
  64. * c->avg)
  65. static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg)
  66. {
  67. return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT);
  68. }
  69. static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg)
  70. {
  71. return (reg != INA2XX_CONFIG);
  72. }
  73. static inline bool is_signed_reg(unsigned int reg)
  74. {
  75. return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT);
  76. }
  77. static const struct regmap_config ina2xx_regmap_config = {
  78. .reg_bits = 8,
  79. .val_bits = 16,
  80. .max_register = INA2XX_MAX_REGISTERS,
  81. .writeable_reg = ina2xx_is_writeable_reg,
  82. .volatile_reg = ina2xx_is_volatile_reg,
  83. };
  84. enum ina2xx_ids { ina219, ina226 };
  85. struct ina2xx_config {
  86. u16 config_default;
  87. int calibration_factor;
  88. int shunt_div;
  89. int bus_voltage_shift;
  90. int bus_voltage_lsb; /* uV */
  91. int power_lsb; /* uW */
  92. };
  93. struct ina2xx_chip_info {
  94. struct regmap *regmap;
  95. struct task_struct *task;
  96. const struct ina2xx_config *config;
  97. struct mutex state_lock;
  98. unsigned int shunt_resistor;
  99. int avg;
  100. int int_time_vbus; /* Bus voltage integration time uS */
  101. int int_time_vshunt; /* Shunt voltage integration time uS */
  102. bool allow_async_readout;
  103. };
  104. static const struct ina2xx_config ina2xx_config[] = {
  105. [ina219] = {
  106. .config_default = INA219_CONFIG_DEFAULT,
  107. .calibration_factor = 40960000,
  108. .shunt_div = 100,
  109. .bus_voltage_shift = 3,
  110. .bus_voltage_lsb = 4000,
  111. .power_lsb = 20000,
  112. },
  113. [ina226] = {
  114. .config_default = INA226_CONFIG_DEFAULT,
  115. .calibration_factor = 5120000,
  116. .shunt_div = 400,
  117. .bus_voltage_shift = 0,
  118. .bus_voltage_lsb = 1250,
  119. .power_lsb = 25000,
  120. },
  121. };
  122. static int ina2xx_read_raw(struct iio_dev *indio_dev,
  123. struct iio_chan_spec const *chan,
  124. int *val, int *val2, long mask)
  125. {
  126. int ret;
  127. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  128. unsigned int regval;
  129. switch (mask) {
  130. case IIO_CHAN_INFO_RAW:
  131. ret = regmap_read(chip->regmap, chan->address, &regval);
  132. if (ret)
  133. return ret;
  134. if (is_signed_reg(chan->address))
  135. *val = (s16) regval;
  136. else
  137. *val = regval;
  138. return IIO_VAL_INT;
  139. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  140. *val = chip->avg;
  141. return IIO_VAL_INT;
  142. case IIO_CHAN_INFO_INT_TIME:
  143. *val = 0;
  144. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  145. *val2 = chip->int_time_vshunt;
  146. else
  147. *val2 = chip->int_time_vbus;
  148. return IIO_VAL_INT_PLUS_MICRO;
  149. case IIO_CHAN_INFO_SAMP_FREQ:
  150. /*
  151. * Sample freq is read only, it is a consequence of
  152. * 1/AVG*(CT_bus+CT_shunt).
  153. */
  154. *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip));
  155. return IIO_VAL_INT;
  156. case IIO_CHAN_INFO_SCALE:
  157. switch (chan->address) {
  158. case INA2XX_SHUNT_VOLTAGE:
  159. /* processed (mV) = raw/shunt_div */
  160. *val2 = chip->config->shunt_div;
  161. *val = 1;
  162. return IIO_VAL_FRACTIONAL;
  163. case INA2XX_BUS_VOLTAGE:
  164. /* processed (mV) = raw*lsb (uV) / (1000 << shift) */
  165. *val = chip->config->bus_voltage_lsb;
  166. *val2 = 1000 << chip->config->bus_voltage_shift;
  167. return IIO_VAL_FRACTIONAL;
  168. case INA2XX_POWER:
  169. /* processed (mW) = raw*lsb (uW) / 1000 */
  170. *val = chip->config->power_lsb;
  171. *val2 = 1000;
  172. return IIO_VAL_FRACTIONAL;
  173. case INA2XX_CURRENT:
  174. /* processed (mA) = raw (mA) */
  175. *val = 1;
  176. return IIO_VAL_INT;
  177. }
  178. }
  179. return -EINVAL;
  180. }
  181. /*
  182. * Available averaging rates for ina226. The indices correspond with
  183. * the bit values expected by the chip (according to the ina226 datasheet,
  184. * table 3 AVG bit settings, found at
  185. * http://www.ti.com/lit/ds/symlink/ina226.pdf.
  186. */
  187. static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
  188. static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val,
  189. unsigned int *config)
  190. {
  191. int bits;
  192. if (val > 1024 || val < 1)
  193. return -EINVAL;
  194. bits = find_closest(val, ina226_avg_tab,
  195. ARRAY_SIZE(ina226_avg_tab));
  196. chip->avg = ina226_avg_tab[bits];
  197. *config &= ~INA226_AVG_MASK;
  198. *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK;
  199. return 0;
  200. }
  201. /* Conversion times in uS */
  202. static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100,
  203. 2116, 4156, 8244 };
  204. static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip,
  205. unsigned int val_us, unsigned int *config)
  206. {
  207. int bits;
  208. if (val_us > 8244 || val_us < 140)
  209. return -EINVAL;
  210. bits = find_closest(val_us, ina226_conv_time_tab,
  211. ARRAY_SIZE(ina226_conv_time_tab));
  212. chip->int_time_vbus = ina226_conv_time_tab[bits];
  213. *config &= ~INA226_ITB_MASK;
  214. *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK;
  215. return 0;
  216. }
  217. static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip,
  218. unsigned int val_us, unsigned int *config)
  219. {
  220. int bits;
  221. if (val_us > 8244 || val_us < 140)
  222. return -EINVAL;
  223. bits = find_closest(val_us, ina226_conv_time_tab,
  224. ARRAY_SIZE(ina226_conv_time_tab));
  225. chip->int_time_vshunt = ina226_conv_time_tab[bits];
  226. *config &= ~INA226_ITS_MASK;
  227. *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK;
  228. return 0;
  229. }
  230. static int ina2xx_write_raw(struct iio_dev *indio_dev,
  231. struct iio_chan_spec const *chan,
  232. int val, int val2, long mask)
  233. {
  234. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  235. unsigned int config, tmp;
  236. int ret;
  237. if (iio_buffer_enabled(indio_dev))
  238. return -EBUSY;
  239. mutex_lock(&chip->state_lock);
  240. ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config);
  241. if (ret)
  242. goto err;
  243. tmp = config;
  244. switch (mask) {
  245. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  246. ret = ina226_set_average(chip, val, &tmp);
  247. break;
  248. case IIO_CHAN_INFO_INT_TIME:
  249. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  250. ret = ina226_set_int_time_vshunt(chip, val2, &tmp);
  251. else
  252. ret = ina226_set_int_time_vbus(chip, val2, &tmp);
  253. break;
  254. default:
  255. ret = -EINVAL;
  256. }
  257. if (!ret && (tmp != config))
  258. ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp);
  259. err:
  260. mutex_unlock(&chip->state_lock);
  261. return ret;
  262. }
  263. static ssize_t ina2xx_allow_async_readout_show(struct device *dev,
  264. struct device_attribute *attr,
  265. char *buf)
  266. {
  267. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  268. return sprintf(buf, "%d\n", chip->allow_async_readout);
  269. }
  270. static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
  271. struct device_attribute *attr,
  272. const char *buf, size_t len)
  273. {
  274. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  275. bool val;
  276. int ret;
  277. ret = strtobool((const char *) buf, &val);
  278. if (ret)
  279. return ret;
  280. chip->allow_async_readout = val;
  281. return len;
  282. }
  283. /*
  284. * Set current LSB to 1mA, shunt is in uOhms
  285. * (equation 13 in datasheet). We hardcode a Current_LSB
  286. * of 1.0 x10-6. The only remaining parameter is RShunt.
  287. * There is no need to expose the CALIBRATION register
  288. * to the user for now. But we need to reset this register
  289. * if the user updates RShunt after driver init, e.g upon
  290. * reading an EEPROM/Probe-type value.
  291. */
  292. static int ina2xx_set_calibration(struct ina2xx_chip_info *chip)
  293. {
  294. u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor,
  295. chip->shunt_resistor);
  296. return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval);
  297. }
  298. static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
  299. {
  300. if (val <= 0 || val > chip->config->calibration_factor)
  301. return -EINVAL;
  302. chip->shunt_resistor = val;
  303. return 0;
  304. }
  305. static ssize_t ina2xx_shunt_resistor_show(struct device *dev,
  306. struct device_attribute *attr,
  307. char *buf)
  308. {
  309. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  310. return sprintf(buf, "%d\n", chip->shunt_resistor);
  311. }
  312. static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
  313. struct device_attribute *attr,
  314. const char *buf, size_t len)
  315. {
  316. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  317. unsigned long val;
  318. int ret;
  319. ret = kstrtoul((const char *) buf, 10, &val);
  320. if (ret)
  321. return ret;
  322. ret = set_shunt_resistor(chip, val);
  323. if (ret)
  324. return ret;
  325. /* Update the Calibration register */
  326. ret = ina2xx_set_calibration(chip);
  327. if (ret)
  328. return ret;
  329. return len;
  330. }
  331. #define INA2XX_CHAN(_type, _index, _address) { \
  332. .type = (_type), \
  333. .address = (_address), \
  334. .indexed = 1, \
  335. .channel = (_index), \
  336. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
  337. | BIT(IIO_CHAN_INFO_SCALE), \
  338. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  339. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  340. .scan_index = (_index), \
  341. .scan_type = { \
  342. .sign = 'u', \
  343. .realbits = 16, \
  344. .storagebits = 16, \
  345. .endianness = IIO_CPU, \
  346. } \
  347. }
  348. /*
  349. * Sampling Freq is a consequence of the integration times of
  350. * the Voltage channels.
  351. */
  352. #define INA2XX_CHAN_VOLTAGE(_index, _address) { \
  353. .type = IIO_VOLTAGE, \
  354. .address = (_address), \
  355. .indexed = 1, \
  356. .channel = (_index), \
  357. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  358. BIT(IIO_CHAN_INFO_SCALE) | \
  359. BIT(IIO_CHAN_INFO_INT_TIME), \
  360. .scan_index = (_index), \
  361. .scan_type = { \
  362. .sign = 'u', \
  363. .realbits = 16, \
  364. .storagebits = 16, \
  365. .endianness = IIO_LE, \
  366. } \
  367. }
  368. static const struct iio_chan_spec ina2xx_channels[] = {
  369. INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE),
  370. INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE),
  371. INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER),
  372. INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT),
  373. IIO_CHAN_SOFT_TIMESTAMP(4),
  374. };
  375. static int ina2xx_work_buffer(struct iio_dev *indio_dev)
  376. {
  377. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  378. unsigned short data[8];
  379. int bit, ret, i = 0;
  380. s64 time_a, time_b;
  381. unsigned int alert;
  382. time_a = iio_get_time_ns(indio_dev);
  383. /*
  384. * Because the timer thread and the chip conversion clock
  385. * are asynchronous, the period difference will eventually
  386. * result in reading V[k-1] again, or skip V[k] at time Tk.
  387. * In order to resync the timer with the conversion process
  388. * we check the ConVersionReadyFlag.
  389. * On hardware that supports using the ALERT pin to toggle a
  390. * GPIO a triggered buffer could be used instead.
  391. * For now, we pay for that extra read of the ALERT register
  392. */
  393. if (!chip->allow_async_readout)
  394. do {
  395. ret = regmap_read(chip->regmap, INA226_ALERT_MASK,
  396. &alert);
  397. if (ret < 0)
  398. return ret;
  399. alert &= INA266_CVRF;
  400. } while (!alert);
  401. /*
  402. * Single register reads: bulk_read will not work with ina226
  403. * as there is no auto-increment of the address register for
  404. * data length longer than 16bits.
  405. */
  406. for_each_set_bit(bit, indio_dev->active_scan_mask,
  407. indio_dev->masklength) {
  408. unsigned int val;
  409. ret = regmap_read(chip->regmap,
  410. INA2XX_SHUNT_VOLTAGE + bit, &val);
  411. if (ret < 0)
  412. return ret;
  413. data[i++] = val;
  414. }
  415. time_b = iio_get_time_ns(indio_dev);
  416. iio_push_to_buffers_with_timestamp(indio_dev,
  417. (unsigned int *)data, time_a);
  418. return (unsigned long)(time_b - time_a) / 1000;
  419. };
  420. static int ina2xx_capture_thread(void *data)
  421. {
  422. struct iio_dev *indio_dev = data;
  423. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  424. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  425. int buffer_us;
  426. /*
  427. * Poll a bit faster than the chip internal Fs, in case
  428. * we wish to sync with the conversion ready flag.
  429. */
  430. if (!chip->allow_async_readout)
  431. sampling_us -= 200;
  432. do {
  433. buffer_us = ina2xx_work_buffer(indio_dev);
  434. if (buffer_us < 0)
  435. return buffer_us;
  436. if (sampling_us > buffer_us)
  437. udelay(sampling_us - buffer_us);
  438. } while (!kthread_should_stop());
  439. return 0;
  440. }
  441. static int ina2xx_buffer_enable(struct iio_dev *indio_dev)
  442. {
  443. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  444. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  445. dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n",
  446. (unsigned int)(*indio_dev->active_scan_mask),
  447. 1000000 / sampling_us, chip->avg);
  448. dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us);
  449. dev_dbg(&indio_dev->dev, "Async readout mode: %d\n",
  450. chip->allow_async_readout);
  451. chip->task = kthread_run(ina2xx_capture_thread, (void *)indio_dev,
  452. "%s:%d-%uus", indio_dev->name, indio_dev->id,
  453. sampling_us);
  454. return PTR_ERR_OR_ZERO(chip->task);
  455. }
  456. static int ina2xx_buffer_disable(struct iio_dev *indio_dev)
  457. {
  458. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  459. if (chip->task) {
  460. kthread_stop(chip->task);
  461. chip->task = NULL;
  462. }
  463. return 0;
  464. }
  465. static const struct iio_buffer_setup_ops ina2xx_setup_ops = {
  466. .postenable = &ina2xx_buffer_enable,
  467. .predisable = &ina2xx_buffer_disable,
  468. };
  469. static int ina2xx_debug_reg(struct iio_dev *indio_dev,
  470. unsigned reg, unsigned writeval, unsigned *readval)
  471. {
  472. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  473. if (!readval)
  474. return regmap_write(chip->regmap, reg, writeval);
  475. return regmap_read(chip->regmap, reg, readval);
  476. }
  477. /* Possible integration times for vshunt and vbus */
  478. static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244");
  479. static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR,
  480. ina2xx_allow_async_readout_show,
  481. ina2xx_allow_async_readout_store, 0);
  482. static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR,
  483. ina2xx_shunt_resistor_show,
  484. ina2xx_shunt_resistor_store, 0);
  485. static struct attribute *ina2xx_attributes[] = {
  486. &iio_dev_attr_in_allow_async_readout.dev_attr.attr,
  487. &iio_const_attr_integration_time_available.dev_attr.attr,
  488. &iio_dev_attr_in_shunt_resistor.dev_attr.attr,
  489. NULL,
  490. };
  491. static const struct attribute_group ina2xx_attribute_group = {
  492. .attrs = ina2xx_attributes,
  493. };
  494. static const struct iio_info ina2xx_info = {
  495. .driver_module = THIS_MODULE,
  496. .attrs = &ina2xx_attribute_group,
  497. .read_raw = ina2xx_read_raw,
  498. .write_raw = ina2xx_write_raw,
  499. .debugfs_reg_access = ina2xx_debug_reg,
  500. };
  501. /* Initialize the configuration and calibration registers. */
  502. static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config)
  503. {
  504. int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config);
  505. if (ret)
  506. return ret;
  507. return ina2xx_set_calibration(chip);
  508. }
  509. static int ina2xx_probe(struct i2c_client *client,
  510. const struct i2c_device_id *id)
  511. {
  512. struct ina2xx_chip_info *chip;
  513. struct iio_dev *indio_dev;
  514. struct iio_buffer *buffer;
  515. unsigned int val;
  516. int ret;
  517. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
  518. if (!indio_dev)
  519. return -ENOMEM;
  520. chip = iio_priv(indio_dev);
  521. /* This is only used for device removal purposes. */
  522. i2c_set_clientdata(client, indio_dev);
  523. chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
  524. if (IS_ERR(chip->regmap)) {
  525. dev_err(&client->dev, "failed to allocate register map\n");
  526. return PTR_ERR(chip->regmap);
  527. }
  528. chip->config = &ina2xx_config[id->driver_data];
  529. mutex_init(&chip->state_lock);
  530. if (of_property_read_u32(client->dev.of_node,
  531. "shunt-resistor", &val) < 0) {
  532. struct ina2xx_platform_data *pdata =
  533. dev_get_platdata(&client->dev);
  534. if (pdata)
  535. val = pdata->shunt_uohms;
  536. else
  537. val = INA2XX_RSHUNT_DEFAULT;
  538. }
  539. ret = set_shunt_resistor(chip, val);
  540. if (ret)
  541. return ret;
  542. /* Patch the current config register with default. */
  543. val = chip->config->config_default;
  544. if (id->driver_data == ina226) {
  545. ina226_set_average(chip, INA226_DEFAULT_AVG, &val);
  546. ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val);
  547. ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val);
  548. }
  549. ret = ina2xx_init(chip, val);
  550. if (ret) {
  551. dev_err(&client->dev, "error configuring the device\n");
  552. return ret;
  553. }
  554. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  555. indio_dev->dev.parent = &client->dev;
  556. indio_dev->dev.of_node = client->dev.of_node;
  557. indio_dev->channels = ina2xx_channels;
  558. indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels);
  559. indio_dev->name = id->name;
  560. indio_dev->info = &ina2xx_info;
  561. indio_dev->setup_ops = &ina2xx_setup_ops;
  562. buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
  563. if (!buffer)
  564. return -ENOMEM;
  565. iio_device_attach_buffer(indio_dev, buffer);
  566. return iio_device_register(indio_dev);
  567. }
  568. static int ina2xx_remove(struct i2c_client *client)
  569. {
  570. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  571. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  572. iio_device_unregister(indio_dev);
  573. /* Powerdown */
  574. return regmap_update_bits(chip->regmap, INA2XX_CONFIG,
  575. INA2XX_MODE_MASK, 0);
  576. }
  577. static const struct i2c_device_id ina2xx_id[] = {
  578. {"ina219", ina219},
  579. {"ina220", ina219},
  580. {"ina226", ina226},
  581. {"ina230", ina226},
  582. {"ina231", ina226},
  583. {}
  584. };
  585. MODULE_DEVICE_TABLE(i2c, ina2xx_id);
  586. static struct i2c_driver ina2xx_driver = {
  587. .driver = {
  588. .name = KBUILD_MODNAME,
  589. },
  590. .probe = ina2xx_probe,
  591. .remove = ina2xx_remove,
  592. .id_table = ina2xx_id,
  593. };
  594. module_i2c_driver(ina2xx_driver);
  595. MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>");
  596. MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver");
  597. MODULE_LICENSE("GPL v2");