v1.c 6.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266
  1. /*
  2. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20. * DEALINGS IN THE SOFTWARE.
  21. */
  22. #include "priv.h"
  23. #include <core/gpuobj.h>
  24. #include <core/memory.h>
  25. #include <subdev/timer.h>
  26. static void
  27. nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
  28. u32 size, u16 tag, u8 port, bool secure)
  29. {
  30. u8 rem = size % 4;
  31. u32 reg;
  32. int i;
  33. size -= rem;
  34. reg = start | BIT(24) | (secure ? BIT(28) : 0);
  35. nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg);
  36. for (i = 0; i < size / 4; i++) {
  37. /* write new tag every 256B */
  38. if ((i & 0x3f) == 0)
  39. nvkm_falcon_wr32(falcon, 0x188, tag++);
  40. nvkm_falcon_wr32(falcon, 0x184, ((u32 *)data)[i]);
  41. }
  42. /*
  43. * If size is not a multiple of 4, mask the last work to ensure garbage
  44. * does not get written
  45. */
  46. if (rem) {
  47. u32 extra = ((u32 *)data)[i];
  48. /* write new tag every 256B */
  49. if ((i & 0x3f) == 0)
  50. nvkm_falcon_wr32(falcon, 0x188, tag++);
  51. nvkm_falcon_wr32(falcon, 0x184, extra & (BIT(rem * 8) - 1));
  52. ++i;
  53. }
  54. /* code must be padded to 0x40 words */
  55. for (; i & 0x3f; i++)
  56. nvkm_falcon_wr32(falcon, 0x184, 0);
  57. }
  58. static void
  59. nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
  60. u32 size, u8 port)
  61. {
  62. u8 rem = size % 4;
  63. int i;
  64. size -= rem;
  65. nvkm_falcon_wr32(falcon, 0x1c0 + (port * 16), start | (0x1 << 24));
  66. for (i = 0; i < size / 4; i++)
  67. nvkm_falcon_wr32(falcon, 0x1c4, ((u32 *)data)[i]);
  68. /*
  69. * If size is not a multiple of 4, mask the last work to ensure garbage
  70. * does not get read
  71. */
  72. if (rem) {
  73. u32 extra = ((u32 *)data)[i];
  74. nvkm_falcon_wr32(falcon, 0x1c4, extra & (BIT(rem * 8) - 1));
  75. }
  76. }
  77. static void
  78. nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size,
  79. u8 port, void *data)
  80. {
  81. u8 rem = size % 4;
  82. int i;
  83. size -= rem;
  84. nvkm_falcon_wr32(falcon, 0x1c0 + (port * 16), start | (0x1 << 25));
  85. for (i = 0; i < size / 4; i++)
  86. ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0x1c4);
  87. /*
  88. * If size is not a multiple of 4, mask the last work to ensure garbage
  89. * does not get read
  90. */
  91. if (rem) {
  92. u32 extra = nvkm_falcon_rd32(falcon, 0x1c4);
  93. for (i = size; i < size + rem; i++) {
  94. ((u8 *)data)[i] = (u8)(extra & 0xff);
  95. extra >>= 8;
  96. }
  97. }
  98. }
  99. static void
  100. nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *ctx)
  101. {
  102. u32 inst_loc;
  103. /* disable instance block binding */
  104. if (ctx == NULL) {
  105. nvkm_falcon_wr32(falcon, 0x10c, 0x0);
  106. return;
  107. }
  108. nvkm_falcon_wr32(falcon, 0x10c, 0x1);
  109. /* setup apertures - virtual */
  110. nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_UCODE, 0x4);
  111. nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_VIRT, 0x0);
  112. /* setup apertures - physical */
  113. nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_VID, 0x4);
  114. nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5);
  115. nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6);
  116. /* Set context */
  117. switch (nvkm_memory_target(ctx->memory)) {
  118. case NVKM_MEM_TARGET_VRAM: inst_loc = 0; break;
  119. case NVKM_MEM_TARGET_NCOH: inst_loc = 3; break;
  120. default:
  121. WARN_ON(1);
  122. return;
  123. }
  124. /* Enable context */
  125. nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1);
  126. nvkm_falcon_wr32(falcon, 0x480,
  127. ((ctx->addr >> 12) & 0xfffffff) |
  128. (inst_loc << 28) | (1 << 30));
  129. }
  130. static void
  131. nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr)
  132. {
  133. nvkm_falcon_wr32(falcon, 0x104, start_addr);
  134. }
  135. static void
  136. nvkm_falcon_v1_start(struct nvkm_falcon *falcon)
  137. {
  138. u32 reg = nvkm_falcon_rd32(falcon, 0x100);
  139. if (reg & BIT(6))
  140. nvkm_falcon_wr32(falcon, 0x130, 0x2);
  141. else
  142. nvkm_falcon_wr32(falcon, 0x100, 0x2);
  143. }
  144. static int
  145. nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms)
  146. {
  147. struct nvkm_device *device = falcon->owner->device;
  148. int ret;
  149. ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10);
  150. if (ret < 0)
  151. return ret;
  152. return 0;
  153. }
  154. static int
  155. nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask)
  156. {
  157. struct nvkm_device *device = falcon->owner->device;
  158. int ret;
  159. /* clear interrupt(s) */
  160. nvkm_falcon_mask(falcon, 0x004, mask, mask);
  161. /* wait until interrupts are cleared */
  162. ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0);
  163. if (ret < 0)
  164. return ret;
  165. return 0;
  166. }
  167. static int
  168. falcon_v1_wait_idle(struct nvkm_falcon *falcon)
  169. {
  170. struct nvkm_device *device = falcon->owner->device;
  171. int ret;
  172. ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0);
  173. if (ret < 0)
  174. return ret;
  175. return 0;
  176. }
  177. static int
  178. nvkm_falcon_v1_enable(struct nvkm_falcon *falcon)
  179. {
  180. struct nvkm_device *device = falcon->owner->device;
  181. int ret;
  182. ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0);
  183. if (ret < 0) {
  184. nvkm_error(falcon->user, "Falcon mem scrubbing timeout\n");
  185. return ret;
  186. }
  187. ret = falcon_v1_wait_idle(falcon);
  188. if (ret)
  189. return ret;
  190. /* enable IRQs */
  191. nvkm_falcon_wr32(falcon, 0x010, 0xff);
  192. return 0;
  193. }
  194. static void
  195. nvkm_falcon_v1_disable(struct nvkm_falcon *falcon)
  196. {
  197. /* disable IRQs and wait for any previous code to complete */
  198. nvkm_falcon_wr32(falcon, 0x014, 0xff);
  199. falcon_v1_wait_idle(falcon);
  200. }
  201. static const struct nvkm_falcon_func
  202. nvkm_falcon_v1 = {
  203. .load_imem = nvkm_falcon_v1_load_imem,
  204. .load_dmem = nvkm_falcon_v1_load_dmem,
  205. .read_dmem = nvkm_falcon_v1_read_dmem,
  206. .bind_context = nvkm_falcon_v1_bind_context,
  207. .start = nvkm_falcon_v1_start,
  208. .wait_for_halt = nvkm_falcon_v1_wait_for_halt,
  209. .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
  210. .enable = nvkm_falcon_v1_enable,
  211. .disable = nvkm_falcon_v1_disable,
  212. .set_start_addr = nvkm_falcon_v1_set_start_addr,
  213. };
  214. int
  215. nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr,
  216. struct nvkm_falcon **pfalcon)
  217. {
  218. struct nvkm_falcon *falcon;
  219. if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
  220. return -ENOMEM;
  221. nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon);
  222. return 0;
  223. }