vgpu.c 13 KB

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  1. /*
  2. * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21. * SOFTWARE.
  22. *
  23. * Authors:
  24. * Eddie Dong <eddie.dong@intel.com>
  25. * Kevin Tian <kevin.tian@intel.com>
  26. *
  27. * Contributors:
  28. * Ping Gao <ping.a.gao@intel.com>
  29. * Zhi Wang <zhi.a.wang@intel.com>
  30. * Bing Niu <bing.niu@intel.com>
  31. *
  32. */
  33. #include "i915_drv.h"
  34. #include "gvt.h"
  35. #include "i915_pvinfo.h"
  36. void populate_pvinfo_page(struct intel_vgpu *vgpu)
  37. {
  38. /* setup the ballooning information */
  39. vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
  40. vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
  41. vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
  42. vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
  43. vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
  44. vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
  45. vgpu_aperture_gmadr_base(vgpu);
  46. vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
  47. vgpu_aperture_sz(vgpu);
  48. vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
  49. vgpu_hidden_gmadr_base(vgpu);
  50. vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
  51. vgpu_hidden_sz(vgpu);
  52. vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
  53. gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
  54. gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
  55. vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
  56. gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
  57. vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
  58. gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
  59. WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
  60. }
  61. static struct {
  62. unsigned int low_mm;
  63. unsigned int high_mm;
  64. unsigned int fence;
  65. enum intel_vgpu_edid edid;
  66. char *name;
  67. } vgpu_types[] = {
  68. /* Fixed vGPU type table */
  69. { MB_TO_BYTES(64), MB_TO_BYTES(512), 4, GVT_EDID_1024_768, "8" },
  70. { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, GVT_EDID_1920_1200, "4" },
  71. { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, GVT_EDID_1920_1200, "2" },
  72. { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, GVT_EDID_1920_1200, "1" },
  73. };
  74. /**
  75. * intel_gvt_init_vgpu_types - initialize vGPU type list
  76. * @gvt : GVT device
  77. *
  78. * Initialize vGPU type list based on available resource.
  79. *
  80. */
  81. int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
  82. {
  83. unsigned int num_types;
  84. unsigned int i, low_avail, high_avail;
  85. unsigned int min_low;
  86. /* vGPU type name is defined as GVTg_Vx_y which contains
  87. * physical GPU generation type (e.g V4 as BDW server, V5 as
  88. * SKL server).
  89. *
  90. * Depend on physical SKU resource, might see vGPU types like
  91. * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
  92. * different types of vGPU on same physical GPU depending on
  93. * available resource. Each vGPU type will have "avail_instance"
  94. * to indicate how many vGPU instance can be created for this
  95. * type.
  96. *
  97. */
  98. low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
  99. high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
  100. num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
  101. gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
  102. GFP_KERNEL);
  103. if (!gvt->types)
  104. return -ENOMEM;
  105. min_low = MB_TO_BYTES(32);
  106. for (i = 0; i < num_types; ++i) {
  107. if (low_avail / vgpu_types[i].low_mm == 0)
  108. break;
  109. gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
  110. gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
  111. gvt->types[i].fence = vgpu_types[i].fence;
  112. gvt->types[i].resolution = vgpu_types[i].edid;
  113. gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
  114. high_avail / vgpu_types[i].high_mm);
  115. if (IS_GEN8(gvt->dev_priv))
  116. sprintf(gvt->types[i].name, "GVTg_V4_%s",
  117. vgpu_types[i].name);
  118. else if (IS_GEN9(gvt->dev_priv))
  119. sprintf(gvt->types[i].name, "GVTg_V5_%s",
  120. vgpu_types[i].name);
  121. gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u res %s\n",
  122. i, gvt->types[i].name,
  123. gvt->types[i].avail_instance,
  124. gvt->types[i].low_gm_size,
  125. gvt->types[i].high_gm_size, gvt->types[i].fence,
  126. vgpu_edid_str(gvt->types[i].resolution));
  127. }
  128. gvt->num_types = i;
  129. return 0;
  130. }
  131. void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
  132. {
  133. kfree(gvt->types);
  134. }
  135. static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
  136. {
  137. int i;
  138. unsigned int low_gm_avail, high_gm_avail, fence_avail;
  139. unsigned int low_gm_min, high_gm_min, fence_min;
  140. /* Need to depend on maxium hw resource size but keep on
  141. * static config for now.
  142. */
  143. low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
  144. gvt->gm.vgpu_allocated_low_gm_size;
  145. high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
  146. gvt->gm.vgpu_allocated_high_gm_size;
  147. fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
  148. gvt->fence.vgpu_allocated_fence_num;
  149. for (i = 0; i < gvt->num_types; i++) {
  150. low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
  151. high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
  152. fence_min = fence_avail / gvt->types[i].fence;
  153. gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
  154. fence_min);
  155. gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
  156. i, gvt->types[i].name,
  157. gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
  158. gvt->types[i].high_gm_size, gvt->types[i].fence);
  159. }
  160. }
  161. /**
  162. * intel_gvt_destroy_vgpu - destroy a virtual GPU
  163. * @vgpu: virtual GPU
  164. *
  165. * This function is called when user wants to destroy a virtual GPU.
  166. *
  167. */
  168. void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
  169. {
  170. struct intel_gvt *gvt = vgpu->gvt;
  171. mutex_lock(&gvt->lock);
  172. vgpu->active = false;
  173. idr_remove(&gvt->vgpu_idr, vgpu->id);
  174. if (atomic_read(&vgpu->running_workload_num)) {
  175. mutex_unlock(&gvt->lock);
  176. intel_gvt_wait_vgpu_idle(vgpu);
  177. mutex_lock(&gvt->lock);
  178. }
  179. intel_vgpu_stop_schedule(vgpu);
  180. intel_vgpu_clean_sched_policy(vgpu);
  181. intel_vgpu_clean_gvt_context(vgpu);
  182. intel_vgpu_clean_execlist(vgpu);
  183. intel_vgpu_clean_display(vgpu);
  184. intel_vgpu_clean_opregion(vgpu);
  185. intel_vgpu_clean_gtt(vgpu);
  186. intel_gvt_hypervisor_detach_vgpu(vgpu);
  187. intel_vgpu_free_resource(vgpu);
  188. intel_vgpu_clean_mmio(vgpu);
  189. vfree(vgpu);
  190. intel_gvt_update_vgpu_types(gvt);
  191. mutex_unlock(&gvt->lock);
  192. }
  193. static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
  194. struct intel_vgpu_creation_params *param)
  195. {
  196. struct intel_vgpu *vgpu;
  197. int ret;
  198. gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
  199. param->handle, param->low_gm_sz, param->high_gm_sz,
  200. param->fence_sz);
  201. vgpu = vzalloc(sizeof(*vgpu));
  202. if (!vgpu)
  203. return ERR_PTR(-ENOMEM);
  204. mutex_lock(&gvt->lock);
  205. ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL);
  206. if (ret < 0)
  207. goto out_free_vgpu;
  208. vgpu->id = ret;
  209. vgpu->handle = param->handle;
  210. vgpu->gvt = gvt;
  211. bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
  212. intel_vgpu_init_cfg_space(vgpu, param->primary);
  213. ret = intel_vgpu_init_mmio(vgpu);
  214. if (ret)
  215. goto out_clean_idr;
  216. ret = intel_vgpu_alloc_resource(vgpu, param);
  217. if (ret)
  218. goto out_clean_vgpu_mmio;
  219. populate_pvinfo_page(vgpu);
  220. ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
  221. if (ret)
  222. goto out_clean_vgpu_resource;
  223. ret = intel_vgpu_init_gtt(vgpu);
  224. if (ret)
  225. goto out_detach_hypervisor_vgpu;
  226. ret = intel_vgpu_init_display(vgpu, param->resolution);
  227. if (ret)
  228. goto out_clean_gtt;
  229. ret = intel_vgpu_init_execlist(vgpu);
  230. if (ret)
  231. goto out_clean_display;
  232. ret = intel_vgpu_init_gvt_context(vgpu);
  233. if (ret)
  234. goto out_clean_execlist;
  235. ret = intel_vgpu_init_sched_policy(vgpu);
  236. if (ret)
  237. goto out_clean_shadow_ctx;
  238. vgpu->active = true;
  239. mutex_unlock(&gvt->lock);
  240. return vgpu;
  241. out_clean_shadow_ctx:
  242. intel_vgpu_clean_gvt_context(vgpu);
  243. out_clean_execlist:
  244. intel_vgpu_clean_execlist(vgpu);
  245. out_clean_display:
  246. intel_vgpu_clean_display(vgpu);
  247. out_clean_gtt:
  248. intel_vgpu_clean_gtt(vgpu);
  249. out_detach_hypervisor_vgpu:
  250. intel_gvt_hypervisor_detach_vgpu(vgpu);
  251. out_clean_vgpu_resource:
  252. intel_vgpu_free_resource(vgpu);
  253. out_clean_vgpu_mmio:
  254. intel_vgpu_clean_mmio(vgpu);
  255. out_clean_idr:
  256. idr_remove(&gvt->vgpu_idr, vgpu->id);
  257. out_free_vgpu:
  258. vfree(vgpu);
  259. mutex_unlock(&gvt->lock);
  260. return ERR_PTR(ret);
  261. }
  262. /**
  263. * intel_gvt_create_vgpu - create a virtual GPU
  264. * @gvt: GVT device
  265. * @type: type of the vGPU to create
  266. *
  267. * This function is called when user wants to create a virtual GPU.
  268. *
  269. * Returns:
  270. * pointer to intel_vgpu, error pointer if failed.
  271. */
  272. struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
  273. struct intel_vgpu_type *type)
  274. {
  275. struct intel_vgpu_creation_params param;
  276. struct intel_vgpu *vgpu;
  277. param.handle = 0;
  278. param.primary = 1;
  279. param.low_gm_sz = type->low_gm_size;
  280. param.high_gm_sz = type->high_gm_size;
  281. param.fence_sz = type->fence;
  282. param.resolution = type->resolution;
  283. /* XXX current param based on MB */
  284. param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
  285. param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
  286. vgpu = __intel_gvt_create_vgpu(gvt, &param);
  287. if (IS_ERR(vgpu))
  288. return vgpu;
  289. /* calculate left instance change for types */
  290. intel_gvt_update_vgpu_types(gvt);
  291. return vgpu;
  292. }
  293. /**
  294. * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
  295. * @vgpu: virtual GPU
  296. * @dmlr: vGPU Device Model Level Reset or GT Reset
  297. * @engine_mask: engines to reset for GT reset
  298. *
  299. * This function is called when user wants to reset a virtual GPU through
  300. * device model reset or GT reset. The caller should hold the gvt lock.
  301. *
  302. * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
  303. * the whole vGPU to default state as when it is created. This vGPU function
  304. * is required both for functionary and security concerns.The ultimate goal
  305. * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
  306. * assign a vGPU to a virtual machine we must isse such reset first.
  307. *
  308. * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
  309. * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
  310. * Unlike the FLR, GT reset only reset particular resource of a vGPU per
  311. * the reset request. Guest driver can issue a GT reset by programming the
  312. * virtual GDRST register to reset specific virtual GPU engine or all
  313. * engines.
  314. *
  315. * The parameter dev_level is to identify if we will do DMLR or GT reset.
  316. * The parameter engine_mask is to specific the engines that need to be
  317. * resetted. If value ALL_ENGINES is given for engine_mask, it means
  318. * the caller requests a full GT reset that we will reset all virtual
  319. * GPU engines. For FLR, engine_mask is ignored.
  320. */
  321. void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
  322. unsigned int engine_mask)
  323. {
  324. struct intel_gvt *gvt = vgpu->gvt;
  325. struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
  326. gvt_dbg_core("------------------------------------------\n");
  327. gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
  328. vgpu->id, dmlr, engine_mask);
  329. vgpu->resetting = true;
  330. intel_vgpu_stop_schedule(vgpu);
  331. /*
  332. * The current_vgpu will set to NULL after stopping the
  333. * scheduler when the reset is triggered by current vgpu.
  334. */
  335. if (scheduler->current_vgpu == NULL) {
  336. mutex_unlock(&gvt->lock);
  337. intel_gvt_wait_vgpu_idle(vgpu);
  338. mutex_lock(&gvt->lock);
  339. }
  340. intel_vgpu_reset_execlist(vgpu, dmlr ? ALL_ENGINES : engine_mask);
  341. /* full GPU reset or device model level reset */
  342. if (engine_mask == ALL_ENGINES || dmlr) {
  343. intel_vgpu_reset_gtt(vgpu, dmlr);
  344. intel_vgpu_reset_resource(vgpu);
  345. intel_vgpu_reset_mmio(vgpu);
  346. populate_pvinfo_page(vgpu);
  347. intel_vgpu_reset_display(vgpu);
  348. if (dmlr) {
  349. intel_vgpu_reset_cfg_space(vgpu);
  350. /* only reset the failsafe mode when dmlr reset */
  351. vgpu->failsafe = false;
  352. vgpu->pv_notified = false;
  353. }
  354. }
  355. vgpu->resetting = false;
  356. gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
  357. gvt_dbg_core("------------------------------------------\n");
  358. }
  359. /**
  360. * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
  361. * @vgpu: virtual GPU
  362. *
  363. * This function is called when user wants to reset a virtual GPU.
  364. *
  365. */
  366. void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
  367. {
  368. mutex_lock(&vgpu->gvt->lock);
  369. intel_gvt_reset_vgpu_locked(vgpu, true, 0);
  370. mutex_unlock(&vgpu->gvt->lock);
  371. }