malidp_drv.c 15 KB

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  1. /*
  2. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  3. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4. *
  5. * This program is free software and is provided to you under the terms of the
  6. * GNU General Public License version 2 as published by the Free Software
  7. * Foundation, and any use by you of this program is subject to the terms
  8. * of such GNU licence.
  9. *
  10. * ARM Mali DP500/DP550/DP650 KMS/DRM driver
  11. */
  12. #include <linux/module.h>
  13. #include <linux/clk.h>
  14. #include <linux/component.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/of_reserved_mem.h>
  18. #include <drm/drmP.h>
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_cma_helper.h>
  24. #include <drm/drm_gem_cma_helper.h>
  25. #include <drm/drm_of.h>
  26. #include "malidp_drv.h"
  27. #include "malidp_regs.h"
  28. #include "malidp_hw.h"
  29. #define MALIDP_CONF_VALID_TIMEOUT 250
  30. /*
  31. * set the "config valid" bit and wait until the hardware acts on it
  32. */
  33. static int malidp_set_and_wait_config_valid(struct drm_device *drm)
  34. {
  35. struct malidp_drm *malidp = drm->dev_private;
  36. struct malidp_hw_device *hwdev = malidp->dev;
  37. int ret;
  38. atomic_set(&malidp->config_valid, 0);
  39. hwdev->set_config_valid(hwdev);
  40. /* don't wait for config_valid flag if we are in config mode */
  41. if (hwdev->in_config_mode(hwdev))
  42. return 0;
  43. ret = wait_event_interruptible_timeout(malidp->wq,
  44. atomic_read(&malidp->config_valid) == 1,
  45. msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
  46. return (ret > 0) ? 0 : -ETIMEDOUT;
  47. }
  48. static void malidp_output_poll_changed(struct drm_device *drm)
  49. {
  50. struct malidp_drm *malidp = drm->dev_private;
  51. drm_fbdev_cma_hotplug_event(malidp->fbdev);
  52. }
  53. static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
  54. {
  55. struct drm_pending_vblank_event *event;
  56. struct drm_device *drm = state->dev;
  57. struct malidp_drm *malidp = drm->dev_private;
  58. int ret = malidp_set_and_wait_config_valid(drm);
  59. if (ret)
  60. DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
  61. event = malidp->crtc.state->event;
  62. if (event) {
  63. malidp->crtc.state->event = NULL;
  64. spin_lock_irq(&drm->event_lock);
  65. if (drm_crtc_vblank_get(&malidp->crtc) == 0)
  66. drm_crtc_arm_vblank_event(&malidp->crtc, event);
  67. else
  68. drm_crtc_send_vblank_event(&malidp->crtc, event);
  69. spin_unlock_irq(&drm->event_lock);
  70. }
  71. drm_atomic_helper_commit_hw_done(state);
  72. }
  73. static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
  74. {
  75. struct drm_device *drm = state->dev;
  76. drm_atomic_helper_commit_modeset_disables(drm, state);
  77. drm_atomic_helper_commit_modeset_enables(drm, state);
  78. drm_atomic_helper_commit_planes(drm, state, 0);
  79. malidp_atomic_commit_hw_done(state);
  80. drm_atomic_helper_wait_for_vblanks(drm, state);
  81. drm_atomic_helper_cleanup_planes(drm, state);
  82. }
  83. static struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
  84. .atomic_commit_tail = malidp_atomic_commit_tail,
  85. };
  86. static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
  87. .fb_create = drm_fb_cma_create,
  88. .output_poll_changed = malidp_output_poll_changed,
  89. .atomic_check = drm_atomic_helper_check,
  90. .atomic_commit = drm_atomic_helper_commit,
  91. };
  92. static int malidp_enable_vblank(struct drm_device *drm, unsigned int crtc)
  93. {
  94. struct malidp_drm *malidp = drm->dev_private;
  95. struct malidp_hw_device *hwdev = malidp->dev;
  96. malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
  97. hwdev->map.de_irq_map.vsync_irq);
  98. return 0;
  99. }
  100. static void malidp_disable_vblank(struct drm_device *drm, unsigned int pipe)
  101. {
  102. struct malidp_drm *malidp = drm->dev_private;
  103. struct malidp_hw_device *hwdev = malidp->dev;
  104. malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
  105. hwdev->map.de_irq_map.vsync_irq);
  106. }
  107. static int malidp_init(struct drm_device *drm)
  108. {
  109. int ret;
  110. struct malidp_drm *malidp = drm->dev_private;
  111. struct malidp_hw_device *hwdev = malidp->dev;
  112. drm_mode_config_init(drm);
  113. drm->mode_config.min_width = hwdev->min_line_size;
  114. drm->mode_config.min_height = hwdev->min_line_size;
  115. drm->mode_config.max_width = hwdev->max_line_size;
  116. drm->mode_config.max_height = hwdev->max_line_size;
  117. drm->mode_config.funcs = &malidp_mode_config_funcs;
  118. drm->mode_config.helper_private = &malidp_mode_config_helpers;
  119. ret = malidp_crtc_init(drm);
  120. if (ret) {
  121. drm_mode_config_cleanup(drm);
  122. return ret;
  123. }
  124. return 0;
  125. }
  126. static void malidp_fini(struct drm_device *drm)
  127. {
  128. malidp_de_planes_destroy(drm);
  129. drm_mode_config_cleanup(drm);
  130. }
  131. static int malidp_irq_init(struct platform_device *pdev)
  132. {
  133. int irq_de, irq_se, ret = 0;
  134. struct drm_device *drm = dev_get_drvdata(&pdev->dev);
  135. /* fetch the interrupts from DT */
  136. irq_de = platform_get_irq_byname(pdev, "DE");
  137. if (irq_de < 0) {
  138. DRM_ERROR("no 'DE' IRQ specified!\n");
  139. return irq_de;
  140. }
  141. irq_se = platform_get_irq_byname(pdev, "SE");
  142. if (irq_se < 0) {
  143. DRM_ERROR("no 'SE' IRQ specified!\n");
  144. return irq_se;
  145. }
  146. ret = malidp_de_irq_init(drm, irq_de);
  147. if (ret)
  148. return ret;
  149. ret = malidp_se_irq_init(drm, irq_se);
  150. if (ret) {
  151. malidp_de_irq_fini(drm);
  152. return ret;
  153. }
  154. return 0;
  155. }
  156. static void malidp_lastclose(struct drm_device *drm)
  157. {
  158. struct malidp_drm *malidp = drm->dev_private;
  159. drm_fbdev_cma_restore_mode(malidp->fbdev);
  160. }
  161. static const struct file_operations fops = {
  162. .owner = THIS_MODULE,
  163. .open = drm_open,
  164. .release = drm_release,
  165. .unlocked_ioctl = drm_ioctl,
  166. .compat_ioctl = drm_compat_ioctl,
  167. .poll = drm_poll,
  168. .read = drm_read,
  169. .llseek = noop_llseek,
  170. .mmap = drm_gem_cma_mmap,
  171. };
  172. static struct drm_driver malidp_driver = {
  173. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
  174. DRIVER_PRIME,
  175. .lastclose = malidp_lastclose,
  176. .get_vblank_counter = drm_vblank_no_hw_counter,
  177. .enable_vblank = malidp_enable_vblank,
  178. .disable_vblank = malidp_disable_vblank,
  179. .gem_free_object_unlocked = drm_gem_cma_free_object,
  180. .gem_vm_ops = &drm_gem_cma_vm_ops,
  181. .dumb_create = drm_gem_cma_dumb_create,
  182. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  183. .dumb_destroy = drm_gem_dumb_destroy,
  184. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  185. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  186. .gem_prime_export = drm_gem_prime_export,
  187. .gem_prime_import = drm_gem_prime_import,
  188. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  189. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  190. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  191. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  192. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  193. .fops = &fops,
  194. .name = "mali-dp",
  195. .desc = "ARM Mali Display Processor driver",
  196. .date = "20160106",
  197. .major = 1,
  198. .minor = 0,
  199. };
  200. static const struct of_device_id malidp_drm_of_match[] = {
  201. {
  202. .compatible = "arm,mali-dp500",
  203. .data = &malidp_device[MALIDP_500]
  204. },
  205. {
  206. .compatible = "arm,mali-dp550",
  207. .data = &malidp_device[MALIDP_550]
  208. },
  209. {
  210. .compatible = "arm,mali-dp650",
  211. .data = &malidp_device[MALIDP_650]
  212. },
  213. {},
  214. };
  215. MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
  216. static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
  217. const struct of_device_id *dev_id)
  218. {
  219. u32 core_id;
  220. const char *compatstr_dp500 = "arm,mali-dp500";
  221. bool is_dp500;
  222. bool dt_is_dp500;
  223. /*
  224. * The DP500 CORE_ID register is in a different location, so check it
  225. * first. If the product id field matches, then this is DP500, otherwise
  226. * check the DP550/650 CORE_ID register.
  227. */
  228. core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
  229. /* Offset 0x18 will never read 0x500 on products other than DP500. */
  230. is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
  231. dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
  232. sizeof(dev_id->compatible)) != NULL;
  233. if (is_dp500 != dt_is_dp500) {
  234. DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
  235. dev_id->compatible, is_dp500 ? "is" : "is not");
  236. return false;
  237. } else if (!dt_is_dp500) {
  238. u16 product_id;
  239. char buf[32];
  240. core_id = malidp_hw_read(hwdev,
  241. MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
  242. product_id = MALIDP_PRODUCT_ID(core_id);
  243. snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
  244. if (!strnstr(dev_id->compatible, buf,
  245. sizeof(dev_id->compatible))) {
  246. DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
  247. dev_id->compatible, product_id);
  248. return false;
  249. }
  250. }
  251. return true;
  252. }
  253. static bool malidp_has_sufficient_address_space(const struct resource *res,
  254. const struct of_device_id *dev_id)
  255. {
  256. resource_size_t res_size = resource_size(res);
  257. const char *compatstr_dp500 = "arm,mali-dp500";
  258. if (!strnstr(dev_id->compatible, compatstr_dp500,
  259. sizeof(dev_id->compatible)))
  260. return res_size >= MALIDP550_ADDR_SPACE_SIZE;
  261. else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
  262. return false;
  263. return true;
  264. }
  265. #define MAX_OUTPUT_CHANNELS 3
  266. static int malidp_bind(struct device *dev)
  267. {
  268. struct resource *res;
  269. struct drm_device *drm;
  270. struct device_node *ep;
  271. struct malidp_drm *malidp;
  272. struct malidp_hw_device *hwdev;
  273. struct platform_device *pdev = to_platform_device(dev);
  274. struct of_device_id const *dev_id;
  275. /* number of lines for the R, G and B output */
  276. u8 output_width[MAX_OUTPUT_CHANNELS];
  277. int ret = 0, i;
  278. u32 version, out_depth = 0;
  279. malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
  280. if (!malidp)
  281. return -ENOMEM;
  282. hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
  283. if (!hwdev)
  284. return -ENOMEM;
  285. /*
  286. * copy the associated data from malidp_drm_of_match to avoid
  287. * having to keep a reference to the OF node after binding
  288. */
  289. memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
  290. malidp->dev = hwdev;
  291. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  292. hwdev->regs = devm_ioremap_resource(dev, res);
  293. if (IS_ERR(hwdev->regs))
  294. return PTR_ERR(hwdev->regs);
  295. hwdev->pclk = devm_clk_get(dev, "pclk");
  296. if (IS_ERR(hwdev->pclk))
  297. return PTR_ERR(hwdev->pclk);
  298. hwdev->aclk = devm_clk_get(dev, "aclk");
  299. if (IS_ERR(hwdev->aclk))
  300. return PTR_ERR(hwdev->aclk);
  301. hwdev->mclk = devm_clk_get(dev, "mclk");
  302. if (IS_ERR(hwdev->mclk))
  303. return PTR_ERR(hwdev->mclk);
  304. hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
  305. if (IS_ERR(hwdev->pxlclk))
  306. return PTR_ERR(hwdev->pxlclk);
  307. /* Get the optional framebuffer memory resource */
  308. ret = of_reserved_mem_device_init(dev);
  309. if (ret && ret != -ENODEV)
  310. return ret;
  311. drm = drm_dev_alloc(&malidp_driver, dev);
  312. if (IS_ERR(drm)) {
  313. ret = PTR_ERR(drm);
  314. goto alloc_fail;
  315. }
  316. /* Enable APB clock in order to get access to the registers */
  317. clk_prepare_enable(hwdev->pclk);
  318. /*
  319. * Enable AXI clock and main clock so that prefetch can start once
  320. * the registers are set
  321. */
  322. clk_prepare_enable(hwdev->aclk);
  323. clk_prepare_enable(hwdev->mclk);
  324. dev_id = of_match_device(malidp_drm_of_match, dev);
  325. if (!dev_id) {
  326. ret = -EINVAL;
  327. goto query_hw_fail;
  328. }
  329. if (!malidp_has_sufficient_address_space(res, dev_id)) {
  330. DRM_ERROR("Insufficient address space in device-tree.\n");
  331. ret = -EINVAL;
  332. goto query_hw_fail;
  333. }
  334. if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
  335. ret = -EINVAL;
  336. goto query_hw_fail;
  337. }
  338. ret = hwdev->query_hw(hwdev);
  339. if (ret) {
  340. DRM_ERROR("Invalid HW configuration\n");
  341. goto query_hw_fail;
  342. }
  343. version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
  344. DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
  345. (version >> 12) & 0xf, (version >> 8) & 0xf);
  346. /* set the number of lines used for output of RGB data */
  347. ret = of_property_read_u8_array(dev->of_node,
  348. "arm,malidp-output-port-lines",
  349. output_width, MAX_OUTPUT_CHANNELS);
  350. if (ret)
  351. goto query_hw_fail;
  352. for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
  353. out_depth = (out_depth << 8) | (output_width[i] & 0xf);
  354. malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
  355. drm->dev_private = malidp;
  356. dev_set_drvdata(dev, drm);
  357. atomic_set(&malidp->config_valid, 0);
  358. init_waitqueue_head(&malidp->wq);
  359. ret = malidp_init(drm);
  360. if (ret < 0)
  361. goto init_fail;
  362. /* Set the CRTC's port so that the encoder component can find it */
  363. ep = of_graph_get_next_endpoint(dev->of_node, NULL);
  364. if (!ep) {
  365. ret = -EINVAL;
  366. goto port_fail;
  367. }
  368. malidp->crtc.port = of_get_next_parent(ep);
  369. ret = component_bind_all(dev, drm);
  370. if (ret) {
  371. DRM_ERROR("Failed to bind all components\n");
  372. goto bind_fail;
  373. }
  374. ret = malidp_irq_init(pdev);
  375. if (ret < 0)
  376. goto irq_init_fail;
  377. drm->irq_enabled = true;
  378. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  379. if (ret < 0) {
  380. DRM_ERROR("failed to initialise vblank\n");
  381. goto vblank_fail;
  382. }
  383. drm_mode_config_reset(drm);
  384. malidp->fbdev = drm_fbdev_cma_init(drm, 32,
  385. drm->mode_config.num_connector);
  386. if (IS_ERR(malidp->fbdev)) {
  387. ret = PTR_ERR(malidp->fbdev);
  388. malidp->fbdev = NULL;
  389. goto fbdev_fail;
  390. }
  391. drm_kms_helper_poll_init(drm);
  392. ret = drm_dev_register(drm, 0);
  393. if (ret)
  394. goto register_fail;
  395. return 0;
  396. register_fail:
  397. if (malidp->fbdev) {
  398. drm_fbdev_cma_fini(malidp->fbdev);
  399. malidp->fbdev = NULL;
  400. }
  401. fbdev_fail:
  402. drm_vblank_cleanup(drm);
  403. vblank_fail:
  404. malidp_se_irq_fini(drm);
  405. malidp_de_irq_fini(drm);
  406. drm->irq_enabled = false;
  407. irq_init_fail:
  408. component_unbind_all(dev, drm);
  409. bind_fail:
  410. of_node_put(malidp->crtc.port);
  411. malidp->crtc.port = NULL;
  412. port_fail:
  413. malidp_fini(drm);
  414. init_fail:
  415. drm->dev_private = NULL;
  416. dev_set_drvdata(dev, NULL);
  417. query_hw_fail:
  418. clk_disable_unprepare(hwdev->mclk);
  419. clk_disable_unprepare(hwdev->aclk);
  420. clk_disable_unprepare(hwdev->pclk);
  421. drm_dev_unref(drm);
  422. alloc_fail:
  423. of_reserved_mem_device_release(dev);
  424. return ret;
  425. }
  426. static void malidp_unbind(struct device *dev)
  427. {
  428. struct drm_device *drm = dev_get_drvdata(dev);
  429. struct malidp_drm *malidp = drm->dev_private;
  430. struct malidp_hw_device *hwdev = malidp->dev;
  431. drm_dev_unregister(drm);
  432. if (malidp->fbdev) {
  433. drm_fbdev_cma_fini(malidp->fbdev);
  434. malidp->fbdev = NULL;
  435. }
  436. drm_kms_helper_poll_fini(drm);
  437. malidp_se_irq_fini(drm);
  438. malidp_de_irq_fini(drm);
  439. drm_vblank_cleanup(drm);
  440. component_unbind_all(dev, drm);
  441. of_node_put(malidp->crtc.port);
  442. malidp->crtc.port = NULL;
  443. malidp_fini(drm);
  444. drm->dev_private = NULL;
  445. dev_set_drvdata(dev, NULL);
  446. clk_disable_unprepare(hwdev->mclk);
  447. clk_disable_unprepare(hwdev->aclk);
  448. clk_disable_unprepare(hwdev->pclk);
  449. drm_dev_unref(drm);
  450. of_reserved_mem_device_release(dev);
  451. }
  452. static const struct component_master_ops malidp_master_ops = {
  453. .bind = malidp_bind,
  454. .unbind = malidp_unbind,
  455. };
  456. static int malidp_compare_dev(struct device *dev, void *data)
  457. {
  458. struct device_node *np = data;
  459. return dev->of_node == np;
  460. }
  461. static int malidp_platform_probe(struct platform_device *pdev)
  462. {
  463. struct device_node *port, *ep;
  464. struct component_match *match = NULL;
  465. if (!pdev->dev.of_node)
  466. return -ENODEV;
  467. /* there is only one output port inside each device, find it */
  468. ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
  469. if (!ep)
  470. return -ENODEV;
  471. if (!of_device_is_available(ep)) {
  472. of_node_put(ep);
  473. return -ENODEV;
  474. }
  475. /* add the remote encoder port as component */
  476. port = of_graph_get_remote_port_parent(ep);
  477. of_node_put(ep);
  478. if (!port || !of_device_is_available(port)) {
  479. of_node_put(port);
  480. return -EAGAIN;
  481. }
  482. drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
  483. port);
  484. of_node_put(port);
  485. return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
  486. match);
  487. }
  488. static int malidp_platform_remove(struct platform_device *pdev)
  489. {
  490. component_master_del(&pdev->dev, &malidp_master_ops);
  491. return 0;
  492. }
  493. static struct platform_driver malidp_platform_driver = {
  494. .probe = malidp_platform_probe,
  495. .remove = malidp_platform_remove,
  496. .driver = {
  497. .name = "mali-dp",
  498. .of_match_table = malidp_drm_of_match,
  499. },
  500. };
  501. module_platform_driver(malidp_platform_driver);
  502. MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
  503. MODULE_DESCRIPTION("ARM Mali DP DRM driver");
  504. MODULE_LICENSE("GPL v2");