gpio-pca953x.c 24 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/gpio/consumer.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_data/pca953x.h>
  20. #include <linux/slab.h>
  21. #include <asm/unaligned.h>
  22. #include <linux/of_platform.h>
  23. #include <linux/acpi.h>
  24. #include <linux/regulator/consumer.h>
  25. #define PCA953X_INPUT 0
  26. #define PCA953X_OUTPUT 1
  27. #define PCA953X_INVERT 2
  28. #define PCA953X_DIRECTION 3
  29. #define REG_ADDR_AI 0x80
  30. #define PCA957X_IN 0
  31. #define PCA957X_INVRT 1
  32. #define PCA957X_BKEN 2
  33. #define PCA957X_PUPD 3
  34. #define PCA957X_CFG 4
  35. #define PCA957X_OUT 5
  36. #define PCA957X_MSK 6
  37. #define PCA957X_INTS 7
  38. #define PCAL953X_IN_LATCH 34
  39. #define PCAL953X_INT_MASK 37
  40. #define PCAL953X_INT_STAT 38
  41. #define PCA_GPIO_MASK 0x00FF
  42. #define PCA_INT 0x0100
  43. #define PCA_PCAL 0x0200
  44. #define PCA953X_TYPE 0x1000
  45. #define PCA957X_TYPE 0x2000
  46. #define PCA_TYPE_MASK 0xF000
  47. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  48. static const struct i2c_device_id pca953x_id[] = {
  49. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9536", 4 | PCA953X_TYPE, },
  53. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  57. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "pca9556", 8 | PCA953X_TYPE, },
  59. { "pca9557", 8 | PCA953X_TYPE, },
  60. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  61. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  62. { "pca9698", 40 | PCA953X_TYPE, },
  63. { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  64. { "max7310", 8 | PCA953X_TYPE, },
  65. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  66. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  67. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  68. { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
  69. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  70. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  71. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  72. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  73. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  74. { "xra1202", 8 | PCA953X_TYPE },
  75. { }
  76. };
  77. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  78. static const struct acpi_device_id pca953x_acpi_ids[] = {
  79. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  80. { }
  81. };
  82. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  83. #define MAX_BANK 5
  84. #define BANK_SZ 8
  85. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  86. struct pca953x_reg_config {
  87. int direction;
  88. int output;
  89. int input;
  90. };
  91. static const struct pca953x_reg_config pca953x_regs = {
  92. .direction = PCA953X_DIRECTION,
  93. .output = PCA953X_OUTPUT,
  94. .input = PCA953X_INPUT,
  95. };
  96. static const struct pca953x_reg_config pca957x_regs = {
  97. .direction = PCA957X_CFG,
  98. .output = PCA957X_OUT,
  99. .input = PCA957X_IN,
  100. };
  101. struct pca953x_chip {
  102. unsigned gpio_start;
  103. u8 reg_output[MAX_BANK];
  104. u8 reg_direction[MAX_BANK];
  105. struct mutex i2c_lock;
  106. #ifdef CONFIG_GPIO_PCA953X_IRQ
  107. struct mutex irq_lock;
  108. u8 irq_mask[MAX_BANK];
  109. u8 irq_stat[MAX_BANK];
  110. u8 irq_trig_raise[MAX_BANK];
  111. u8 irq_trig_fall[MAX_BANK];
  112. #endif
  113. struct i2c_client *client;
  114. struct gpio_chip gpio_chip;
  115. const char *const *names;
  116. unsigned long driver_data;
  117. struct regulator *regulator;
  118. const struct pca953x_reg_config *regs;
  119. int (*write_regs)(struct pca953x_chip *, int, u8 *);
  120. int (*read_regs)(struct pca953x_chip *, int, u8 *);
  121. };
  122. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  123. int off)
  124. {
  125. int ret;
  126. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  127. int offset = off / BANK_SZ;
  128. ret = i2c_smbus_read_byte_data(chip->client,
  129. (reg << bank_shift) + offset);
  130. *val = ret;
  131. if (ret < 0) {
  132. dev_err(&chip->client->dev, "failed reading register\n");
  133. return ret;
  134. }
  135. return 0;
  136. }
  137. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  138. int off)
  139. {
  140. int ret;
  141. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  142. int offset = off / BANK_SZ;
  143. ret = i2c_smbus_write_byte_data(chip->client,
  144. (reg << bank_shift) + offset, val);
  145. if (ret < 0) {
  146. dev_err(&chip->client->dev, "failed writing register\n");
  147. return ret;
  148. }
  149. return 0;
  150. }
  151. static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  152. {
  153. return i2c_smbus_write_byte_data(chip->client, reg, *val);
  154. }
  155. static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  156. {
  157. __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
  158. return i2c_smbus_write_word_data(chip->client,
  159. reg << 1, (__force u16)word);
  160. }
  161. static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  162. {
  163. int ret;
  164. ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
  165. if (ret < 0)
  166. return ret;
  167. return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
  168. }
  169. static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  170. {
  171. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  172. return i2c_smbus_write_i2c_block_data(chip->client,
  173. (reg << bank_shift) | REG_ADDR_AI,
  174. NBANK(chip), val);
  175. }
  176. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  177. {
  178. int ret = 0;
  179. ret = chip->write_regs(chip, reg, val);
  180. if (ret < 0) {
  181. dev_err(&chip->client->dev, "failed writing register\n");
  182. return ret;
  183. }
  184. return 0;
  185. }
  186. static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  187. {
  188. int ret;
  189. ret = i2c_smbus_read_byte_data(chip->client, reg);
  190. *val = ret;
  191. return ret;
  192. }
  193. static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  194. {
  195. int ret;
  196. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  197. val[0] = (u16)ret & 0xFF;
  198. val[1] = (u16)ret >> 8;
  199. return ret;
  200. }
  201. static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  202. {
  203. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  204. return i2c_smbus_read_i2c_block_data(chip->client,
  205. (reg << bank_shift) | REG_ADDR_AI,
  206. NBANK(chip), val);
  207. }
  208. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  209. {
  210. int ret;
  211. ret = chip->read_regs(chip, reg, val);
  212. if (ret < 0) {
  213. dev_err(&chip->client->dev, "failed reading register\n");
  214. return ret;
  215. }
  216. return 0;
  217. }
  218. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  219. {
  220. struct pca953x_chip *chip = gpiochip_get_data(gc);
  221. u8 reg_val;
  222. int ret;
  223. mutex_lock(&chip->i2c_lock);
  224. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  225. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  226. if (ret)
  227. goto exit;
  228. chip->reg_direction[off / BANK_SZ] = reg_val;
  229. exit:
  230. mutex_unlock(&chip->i2c_lock);
  231. return ret;
  232. }
  233. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  234. unsigned off, int val)
  235. {
  236. struct pca953x_chip *chip = gpiochip_get_data(gc);
  237. u8 reg_val;
  238. int ret;
  239. mutex_lock(&chip->i2c_lock);
  240. /* set output level */
  241. if (val)
  242. reg_val = chip->reg_output[off / BANK_SZ]
  243. | (1u << (off % BANK_SZ));
  244. else
  245. reg_val = chip->reg_output[off / BANK_SZ]
  246. & ~(1u << (off % BANK_SZ));
  247. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  248. if (ret)
  249. goto exit;
  250. chip->reg_output[off / BANK_SZ] = reg_val;
  251. /* then direction */
  252. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  253. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  254. if (ret)
  255. goto exit;
  256. chip->reg_direction[off / BANK_SZ] = reg_val;
  257. exit:
  258. mutex_unlock(&chip->i2c_lock);
  259. return ret;
  260. }
  261. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  262. {
  263. struct pca953x_chip *chip = gpiochip_get_data(gc);
  264. u32 reg_val;
  265. int ret;
  266. mutex_lock(&chip->i2c_lock);
  267. ret = pca953x_read_single(chip, chip->regs->input, &reg_val, off);
  268. mutex_unlock(&chip->i2c_lock);
  269. if (ret < 0) {
  270. /* NOTE: diagnostic already emitted; that's all we should
  271. * do unless gpio_*_value_cansleep() calls become different
  272. * from their nonsleeping siblings (and report faults).
  273. */
  274. return 0;
  275. }
  276. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  277. }
  278. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  279. {
  280. struct pca953x_chip *chip = gpiochip_get_data(gc);
  281. u8 reg_val;
  282. int ret;
  283. mutex_lock(&chip->i2c_lock);
  284. if (val)
  285. reg_val = chip->reg_output[off / BANK_SZ]
  286. | (1u << (off % BANK_SZ));
  287. else
  288. reg_val = chip->reg_output[off / BANK_SZ]
  289. & ~(1u << (off % BANK_SZ));
  290. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  291. if (ret)
  292. goto exit;
  293. chip->reg_output[off / BANK_SZ] = reg_val;
  294. exit:
  295. mutex_unlock(&chip->i2c_lock);
  296. }
  297. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  298. unsigned long *mask, unsigned long *bits)
  299. {
  300. struct pca953x_chip *chip = gpiochip_get_data(gc);
  301. unsigned int bank_mask, bank_val;
  302. int bank_shift, bank;
  303. u8 reg_val[MAX_BANK];
  304. int ret;
  305. bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  306. mutex_lock(&chip->i2c_lock);
  307. memcpy(reg_val, chip->reg_output, NBANK(chip));
  308. for (bank = 0; bank < NBANK(chip); bank++) {
  309. bank_mask = mask[bank / sizeof(*mask)] >>
  310. ((bank % sizeof(*mask)) * 8);
  311. if (bank_mask) {
  312. bank_val = bits[bank / sizeof(*bits)] >>
  313. ((bank % sizeof(*bits)) * 8);
  314. bank_val &= bank_mask;
  315. reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
  316. }
  317. }
  318. ret = i2c_smbus_write_i2c_block_data(chip->client,
  319. chip->regs->output << bank_shift,
  320. NBANK(chip), reg_val);
  321. if (ret)
  322. goto exit;
  323. memcpy(chip->reg_output, reg_val, NBANK(chip));
  324. exit:
  325. mutex_unlock(&chip->i2c_lock);
  326. }
  327. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  328. {
  329. struct gpio_chip *gc;
  330. gc = &chip->gpio_chip;
  331. gc->direction_input = pca953x_gpio_direction_input;
  332. gc->direction_output = pca953x_gpio_direction_output;
  333. gc->get = pca953x_gpio_get_value;
  334. gc->set = pca953x_gpio_set_value;
  335. gc->set_multiple = pca953x_gpio_set_multiple;
  336. gc->can_sleep = true;
  337. gc->base = chip->gpio_start;
  338. gc->ngpio = gpios;
  339. gc->label = chip->client->name;
  340. gc->parent = &chip->client->dev;
  341. gc->owner = THIS_MODULE;
  342. gc->names = chip->names;
  343. }
  344. #ifdef CONFIG_GPIO_PCA953X_IRQ
  345. static void pca953x_irq_mask(struct irq_data *d)
  346. {
  347. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  348. struct pca953x_chip *chip = gpiochip_get_data(gc);
  349. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  350. }
  351. static void pca953x_irq_unmask(struct irq_data *d)
  352. {
  353. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  354. struct pca953x_chip *chip = gpiochip_get_data(gc);
  355. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  356. }
  357. static void pca953x_irq_bus_lock(struct irq_data *d)
  358. {
  359. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  360. struct pca953x_chip *chip = gpiochip_get_data(gc);
  361. mutex_lock(&chip->irq_lock);
  362. }
  363. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  364. {
  365. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  366. struct pca953x_chip *chip = gpiochip_get_data(gc);
  367. u8 new_irqs;
  368. int level, i;
  369. u8 invert_irq_mask[MAX_BANK];
  370. if (chip->driver_data & PCA_PCAL) {
  371. /* Enable latch on interrupt-enabled inputs */
  372. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  373. for (i = 0; i < NBANK(chip); i++)
  374. invert_irq_mask[i] = ~chip->irq_mask[i];
  375. /* Unmask enabled interrupts */
  376. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  377. }
  378. /* Look for any newly setup interrupt */
  379. for (i = 0; i < NBANK(chip); i++) {
  380. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  381. new_irqs &= ~chip->reg_direction[i];
  382. while (new_irqs) {
  383. level = __ffs(new_irqs);
  384. pca953x_gpio_direction_input(&chip->gpio_chip,
  385. level + (BANK_SZ * i));
  386. new_irqs &= ~(1 << level);
  387. }
  388. }
  389. mutex_unlock(&chip->irq_lock);
  390. }
  391. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  392. {
  393. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  394. struct pca953x_chip *chip = gpiochip_get_data(gc);
  395. int bank_nb = d->hwirq / BANK_SZ;
  396. u8 mask = 1 << (d->hwirq % BANK_SZ);
  397. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  398. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  399. d->irq, type);
  400. return -EINVAL;
  401. }
  402. if (type & IRQ_TYPE_EDGE_FALLING)
  403. chip->irq_trig_fall[bank_nb] |= mask;
  404. else
  405. chip->irq_trig_fall[bank_nb] &= ~mask;
  406. if (type & IRQ_TYPE_EDGE_RISING)
  407. chip->irq_trig_raise[bank_nb] |= mask;
  408. else
  409. chip->irq_trig_raise[bank_nb] &= ~mask;
  410. return 0;
  411. }
  412. static struct irq_chip pca953x_irq_chip = {
  413. .name = "pca953x",
  414. .irq_mask = pca953x_irq_mask,
  415. .irq_unmask = pca953x_irq_unmask,
  416. .irq_bus_lock = pca953x_irq_bus_lock,
  417. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  418. .irq_set_type = pca953x_irq_set_type,
  419. };
  420. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  421. {
  422. u8 cur_stat[MAX_BANK];
  423. u8 old_stat[MAX_BANK];
  424. bool pending_seen = false;
  425. bool trigger_seen = false;
  426. u8 trigger[MAX_BANK];
  427. int ret, i;
  428. if (chip->driver_data & PCA_PCAL) {
  429. /* Read the current interrupt status from the device */
  430. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  431. if (ret)
  432. return false;
  433. /* Check latched inputs and clear interrupt status */
  434. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  435. if (ret)
  436. return false;
  437. for (i = 0; i < NBANK(chip); i++) {
  438. /* Apply filter for rising/falling edge selection */
  439. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  440. (cur_stat[i] & chip->irq_trig_raise[i]);
  441. pending[i] &= trigger[i];
  442. if (pending[i])
  443. pending_seen = true;
  444. }
  445. return pending_seen;
  446. }
  447. ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
  448. if (ret)
  449. return false;
  450. /* Remove output pins from the equation */
  451. for (i = 0; i < NBANK(chip); i++)
  452. cur_stat[i] &= chip->reg_direction[i];
  453. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  454. for (i = 0; i < NBANK(chip); i++) {
  455. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  456. if (trigger[i])
  457. trigger_seen = true;
  458. }
  459. if (!trigger_seen)
  460. return false;
  461. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  462. for (i = 0; i < NBANK(chip); i++) {
  463. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  464. (cur_stat[i] & chip->irq_trig_raise[i]);
  465. pending[i] &= trigger[i];
  466. if (pending[i])
  467. pending_seen = true;
  468. }
  469. return pending_seen;
  470. }
  471. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  472. {
  473. struct pca953x_chip *chip = devid;
  474. u8 pending[MAX_BANK];
  475. u8 level;
  476. unsigned nhandled = 0;
  477. int i;
  478. if (!pca953x_irq_pending(chip, pending))
  479. return IRQ_NONE;
  480. for (i = 0; i < NBANK(chip); i++) {
  481. while (pending[i]) {
  482. level = __ffs(pending[i]);
  483. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  484. level + (BANK_SZ * i)));
  485. pending[i] &= ~(1 << level);
  486. nhandled++;
  487. }
  488. }
  489. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  490. }
  491. static int pca953x_irq_setup(struct pca953x_chip *chip,
  492. int irq_base)
  493. {
  494. struct i2c_client *client = chip->client;
  495. int ret, i;
  496. if (client->irq && irq_base != -1
  497. && (chip->driver_data & PCA_INT)) {
  498. ret = pca953x_read_regs(chip,
  499. chip->regs->input, chip->irq_stat);
  500. if (ret)
  501. return ret;
  502. /*
  503. * There is no way to know which GPIO line generated the
  504. * interrupt. We have to rely on the previous read for
  505. * this purpose.
  506. */
  507. for (i = 0; i < NBANK(chip); i++)
  508. chip->irq_stat[i] &= chip->reg_direction[i];
  509. mutex_init(&chip->irq_lock);
  510. ret = devm_request_threaded_irq(&client->dev,
  511. client->irq,
  512. NULL,
  513. pca953x_irq_handler,
  514. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  515. IRQF_SHARED,
  516. dev_name(&client->dev), chip);
  517. if (ret) {
  518. dev_err(&client->dev, "failed to request irq %d\n",
  519. client->irq);
  520. return ret;
  521. }
  522. ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
  523. &pca953x_irq_chip,
  524. irq_base,
  525. handle_simple_irq,
  526. IRQ_TYPE_NONE);
  527. if (ret) {
  528. dev_err(&client->dev,
  529. "could not connect irqchip to gpiochip\n");
  530. return ret;
  531. }
  532. gpiochip_set_nested_irqchip(&chip->gpio_chip,
  533. &pca953x_irq_chip,
  534. client->irq);
  535. }
  536. return 0;
  537. }
  538. #else /* CONFIG_GPIO_PCA953X_IRQ */
  539. static int pca953x_irq_setup(struct pca953x_chip *chip,
  540. int irq_base)
  541. {
  542. struct i2c_client *client = chip->client;
  543. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  544. dev_warn(&client->dev, "interrupt support not compiled in\n");
  545. return 0;
  546. }
  547. #endif
  548. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  549. {
  550. int ret;
  551. u8 val[MAX_BANK];
  552. chip->regs = &pca953x_regs;
  553. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  554. if (ret)
  555. goto out;
  556. ret = pca953x_read_regs(chip, chip->regs->direction,
  557. chip->reg_direction);
  558. if (ret)
  559. goto out;
  560. /* set platform specific polarity inversion */
  561. if (invert)
  562. memset(val, 0xFF, NBANK(chip));
  563. else
  564. memset(val, 0, NBANK(chip));
  565. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  566. out:
  567. return ret;
  568. }
  569. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  570. {
  571. int ret;
  572. u8 val[MAX_BANK];
  573. chip->regs = &pca957x_regs;
  574. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  575. if (ret)
  576. goto out;
  577. ret = pca953x_read_regs(chip, chip->regs->direction,
  578. chip->reg_direction);
  579. if (ret)
  580. goto out;
  581. /* set platform specific polarity inversion */
  582. if (invert)
  583. memset(val, 0xFF, NBANK(chip));
  584. else
  585. memset(val, 0, NBANK(chip));
  586. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  587. if (ret)
  588. goto out;
  589. /* To enable register 6, 7 to control pull up and pull down */
  590. memset(val, 0x02, NBANK(chip));
  591. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  592. if (ret)
  593. goto out;
  594. return 0;
  595. out:
  596. return ret;
  597. }
  598. static const struct of_device_id pca953x_dt_ids[];
  599. static int pca953x_probe(struct i2c_client *client,
  600. const struct i2c_device_id *i2c_id)
  601. {
  602. struct pca953x_platform_data *pdata;
  603. struct pca953x_chip *chip;
  604. int irq_base = 0;
  605. int ret;
  606. u32 invert = 0;
  607. struct regulator *reg;
  608. chip = devm_kzalloc(&client->dev,
  609. sizeof(struct pca953x_chip), GFP_KERNEL);
  610. if (chip == NULL)
  611. return -ENOMEM;
  612. pdata = dev_get_platdata(&client->dev);
  613. if (pdata) {
  614. irq_base = pdata->irq_base;
  615. chip->gpio_start = pdata->gpio_base;
  616. invert = pdata->invert;
  617. chip->names = pdata->names;
  618. } else {
  619. struct gpio_desc *reset_gpio;
  620. chip->gpio_start = -1;
  621. irq_base = 0;
  622. /* See if we need to de-assert a reset pin */
  623. reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
  624. GPIOD_OUT_LOW);
  625. if (IS_ERR(reset_gpio))
  626. return PTR_ERR(reset_gpio);
  627. }
  628. chip->client = client;
  629. reg = devm_regulator_get(&client->dev, "vcc");
  630. if (IS_ERR(reg)) {
  631. ret = PTR_ERR(reg);
  632. if (ret != -EPROBE_DEFER)
  633. dev_err(&client->dev, "reg get err: %d\n", ret);
  634. return ret;
  635. }
  636. ret = regulator_enable(reg);
  637. if (ret) {
  638. dev_err(&client->dev, "reg en err: %d\n", ret);
  639. return ret;
  640. }
  641. chip->regulator = reg;
  642. if (i2c_id) {
  643. chip->driver_data = i2c_id->driver_data;
  644. } else {
  645. const struct acpi_device_id *acpi_id;
  646. const struct of_device_id *match;
  647. match = of_match_device(pca953x_dt_ids, &client->dev);
  648. if (match) {
  649. chip->driver_data = (int)(uintptr_t)match->data;
  650. } else {
  651. acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  652. if (!acpi_id) {
  653. ret = -ENODEV;
  654. goto err_exit;
  655. }
  656. chip->driver_data = acpi_id->driver_data;
  657. }
  658. }
  659. mutex_init(&chip->i2c_lock);
  660. /*
  661. * In case we have an i2c-mux controlled by a GPIO provided by an
  662. * expander using the same driver higher on the device tree, read the
  663. * i2c adapter nesting depth and use the retrieved value as lockdep
  664. * subclass for chip->i2c_lock.
  665. *
  666. * REVISIT: This solution is not complete. It protects us from lockdep
  667. * false positives when the expander controlling the i2c-mux is on
  668. * a different level on the device tree, but not when it's on the same
  669. * level on a different branch (in which case the subclass number
  670. * would be the same).
  671. *
  672. * TODO: Once a correct solution is developed, a similar fix should be
  673. * applied to all other i2c-controlled GPIO expanders (and potentially
  674. * regmap-i2c).
  675. */
  676. lockdep_set_subclass(&chip->i2c_lock,
  677. i2c_adapter_depth(client->adapter));
  678. /* initialize cached registers from their original values.
  679. * we can't share this chip with another i2c master.
  680. */
  681. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  682. if (chip->gpio_chip.ngpio <= 8) {
  683. chip->write_regs = pca953x_write_regs_8;
  684. chip->read_regs = pca953x_read_regs_8;
  685. } else if (chip->gpio_chip.ngpio >= 24) {
  686. chip->write_regs = pca953x_write_regs_24;
  687. chip->read_regs = pca953x_read_regs_24;
  688. } else {
  689. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  690. chip->write_regs = pca953x_write_regs_16;
  691. else
  692. chip->write_regs = pca957x_write_regs_16;
  693. chip->read_regs = pca953x_read_regs_16;
  694. }
  695. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  696. ret = device_pca953x_init(chip, invert);
  697. else
  698. ret = device_pca957x_init(chip, invert);
  699. if (ret)
  700. goto err_exit;
  701. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  702. if (ret)
  703. goto err_exit;
  704. ret = pca953x_irq_setup(chip, irq_base);
  705. if (ret)
  706. goto err_exit;
  707. if (pdata && pdata->setup) {
  708. ret = pdata->setup(client, chip->gpio_chip.base,
  709. chip->gpio_chip.ngpio, pdata->context);
  710. if (ret < 0)
  711. dev_warn(&client->dev, "setup failed, %d\n", ret);
  712. }
  713. i2c_set_clientdata(client, chip);
  714. return 0;
  715. err_exit:
  716. regulator_disable(chip->regulator);
  717. return ret;
  718. }
  719. static int pca953x_remove(struct i2c_client *client)
  720. {
  721. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  722. struct pca953x_chip *chip = i2c_get_clientdata(client);
  723. int ret;
  724. if (pdata && pdata->teardown) {
  725. ret = pdata->teardown(client, chip->gpio_chip.base,
  726. chip->gpio_chip.ngpio, pdata->context);
  727. if (ret < 0)
  728. dev_err(&client->dev, "%s failed, %d\n",
  729. "teardown", ret);
  730. } else {
  731. ret = 0;
  732. }
  733. regulator_disable(chip->regulator);
  734. return ret;
  735. }
  736. /* convenience to stop overlong match-table lines */
  737. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  738. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  739. static const struct of_device_id pca953x_dt_ids[] = {
  740. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  741. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  742. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  743. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  744. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  745. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  746. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  747. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  748. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  749. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  750. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  751. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  752. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  753. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  754. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  755. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  756. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  757. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  758. { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
  759. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  760. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  761. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  762. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  763. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  764. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  765. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  766. { }
  767. };
  768. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  769. static struct i2c_driver pca953x_driver = {
  770. .driver = {
  771. .name = "pca953x",
  772. .of_match_table = pca953x_dt_ids,
  773. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  774. },
  775. .probe = pca953x_probe,
  776. .remove = pca953x_remove,
  777. .id_table = pca953x_id,
  778. };
  779. static int __init pca953x_init(void)
  780. {
  781. return i2c_add_driver(&pca953x_driver);
  782. }
  783. /* register after i2c postcore initcall and before
  784. * subsys initcalls that may rely on these GPIOs
  785. */
  786. subsys_initcall(pca953x_init);
  787. static void __exit pca953x_exit(void)
  788. {
  789. i2c_del_driver(&pca953x_driver);
  790. }
  791. module_exit(pca953x_exit);
  792. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  793. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  794. MODULE_LICENSE("GPL");