gpio-f7188x.c 13 KB

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  1. /*
  2. * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
  3. *
  4. * Copyright (C) 2010-2013 LaCie
  5. *
  6. * Author: Simon Guinot <simon.guinot@sequanux.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/gpio/driver.h>
  18. #include <linux/bitops.h>
  19. #define DRVNAME "gpio-f7188x"
  20. /*
  21. * Super-I/O registers
  22. */
  23. #define SIO_LDSEL 0x07 /* Logical device select */
  24. #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
  25. #define SIO_DEVREV 0x22 /* Device revision */
  26. #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
  27. #define SIO_LD_GPIO 0x06 /* GPIO logical device */
  28. #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
  29. #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
  30. #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
  31. #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
  32. #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
  33. #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
  34. #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
  35. #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
  36. enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };
  37. static const char * const f7188x_names[] = {
  38. "f71869",
  39. "f71869a",
  40. "f71882fg",
  41. "f71889f",
  42. "f81866",
  43. };
  44. struct f7188x_sio {
  45. int addr;
  46. enum chips type;
  47. };
  48. struct f7188x_gpio_bank {
  49. struct gpio_chip chip;
  50. unsigned int regbase;
  51. struct f7188x_gpio_data *data;
  52. };
  53. struct f7188x_gpio_data {
  54. struct f7188x_sio *sio;
  55. int nr_bank;
  56. struct f7188x_gpio_bank *bank;
  57. };
  58. /*
  59. * Super-I/O functions.
  60. */
  61. static inline int superio_inb(int base, int reg)
  62. {
  63. outb(reg, base);
  64. return inb(base + 1);
  65. }
  66. static int superio_inw(int base, int reg)
  67. {
  68. int val;
  69. outb(reg++, base);
  70. val = inb(base + 1) << 8;
  71. outb(reg, base);
  72. val |= inb(base + 1);
  73. return val;
  74. }
  75. static inline void superio_outb(int base, int reg, int val)
  76. {
  77. outb(reg, base);
  78. outb(val, base + 1);
  79. }
  80. static inline int superio_enter(int base)
  81. {
  82. /* Don't step on other drivers' I/O space by accident. */
  83. if (!request_muxed_region(base, 2, DRVNAME)) {
  84. pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
  85. return -EBUSY;
  86. }
  87. /* According to the datasheet the key must be send twice. */
  88. outb(SIO_UNLOCK_KEY, base);
  89. outb(SIO_UNLOCK_KEY, base);
  90. return 0;
  91. }
  92. static inline void superio_select(int base, int ld)
  93. {
  94. outb(SIO_LDSEL, base);
  95. outb(ld, base + 1);
  96. }
  97. static inline void superio_exit(int base)
  98. {
  99. outb(SIO_LOCK_KEY, base);
  100. release_region(base, 2);
  101. }
  102. /*
  103. * GPIO chip.
  104. */
  105. static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
  106. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
  107. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
  108. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  109. unsigned offset, int value);
  110. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
  111. static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  112. unsigned long config);
  113. #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
  114. { \
  115. .chip = { \
  116. .label = DRVNAME, \
  117. .owner = THIS_MODULE, \
  118. .get_direction = f7188x_gpio_get_direction, \
  119. .direction_input = f7188x_gpio_direction_in, \
  120. .get = f7188x_gpio_get, \
  121. .direction_output = f7188x_gpio_direction_out, \
  122. .set = f7188x_gpio_set, \
  123. .set_config = f7188x_gpio_set_config, \
  124. .base = _base, \
  125. .ngpio = _ngpio, \
  126. .can_sleep = true, \
  127. }, \
  128. .regbase = _regbase, \
  129. }
  130. #define gpio_dir(base) (base + 0)
  131. #define gpio_data_out(base) (base + 1)
  132. #define gpio_data_in(base) (base + 2)
  133. /* Output mode register (0:open drain 1:push-pull). */
  134. #define gpio_out_mode(base) (base + 3)
  135. static struct f7188x_gpio_bank f71869_gpio_bank[] = {
  136. F7188X_GPIO_BANK(0, 6, 0xF0),
  137. F7188X_GPIO_BANK(10, 8, 0xE0),
  138. F7188X_GPIO_BANK(20, 8, 0xD0),
  139. F7188X_GPIO_BANK(30, 8, 0xC0),
  140. F7188X_GPIO_BANK(40, 8, 0xB0),
  141. F7188X_GPIO_BANK(50, 5, 0xA0),
  142. F7188X_GPIO_BANK(60, 6, 0x90),
  143. };
  144. static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
  145. F7188X_GPIO_BANK(0, 6, 0xF0),
  146. F7188X_GPIO_BANK(10, 8, 0xE0),
  147. F7188X_GPIO_BANK(20, 8, 0xD0),
  148. F7188X_GPIO_BANK(30, 8, 0xC0),
  149. F7188X_GPIO_BANK(40, 8, 0xB0),
  150. F7188X_GPIO_BANK(50, 5, 0xA0),
  151. F7188X_GPIO_BANK(60, 8, 0x90),
  152. F7188X_GPIO_BANK(70, 8, 0x80),
  153. };
  154. static struct f7188x_gpio_bank f71882_gpio_bank[] = {
  155. F7188X_GPIO_BANK(0, 8, 0xF0),
  156. F7188X_GPIO_BANK(10, 8, 0xE0),
  157. F7188X_GPIO_BANK(20, 8, 0xD0),
  158. F7188X_GPIO_BANK(30, 4, 0xC0),
  159. F7188X_GPIO_BANK(40, 4, 0xB0),
  160. };
  161. static struct f7188x_gpio_bank f71889_gpio_bank[] = {
  162. F7188X_GPIO_BANK(0, 7, 0xF0),
  163. F7188X_GPIO_BANK(10, 7, 0xE0),
  164. F7188X_GPIO_BANK(20, 8, 0xD0),
  165. F7188X_GPIO_BANK(30, 8, 0xC0),
  166. F7188X_GPIO_BANK(40, 8, 0xB0),
  167. F7188X_GPIO_BANK(50, 5, 0xA0),
  168. F7188X_GPIO_BANK(60, 8, 0x90),
  169. F7188X_GPIO_BANK(70, 8, 0x80),
  170. };
  171. static struct f7188x_gpio_bank f81866_gpio_bank[] = {
  172. F7188X_GPIO_BANK(0, 8, 0xF0),
  173. F7188X_GPIO_BANK(10, 8, 0xE0),
  174. F7188X_GPIO_BANK(20, 8, 0xD0),
  175. F7188X_GPIO_BANK(30, 8, 0xC0),
  176. F7188X_GPIO_BANK(40, 8, 0xB0),
  177. F7188X_GPIO_BANK(50, 8, 0xA0),
  178. F7188X_GPIO_BANK(60, 8, 0x90),
  179. F7188X_GPIO_BANK(70, 8, 0x80),
  180. F7188X_GPIO_BANK(80, 8, 0x88),
  181. };
  182. static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  183. {
  184. int err;
  185. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  186. struct f7188x_sio *sio = bank->data->sio;
  187. u8 dir;
  188. err = superio_enter(sio->addr);
  189. if (err)
  190. return err;
  191. superio_select(sio->addr, SIO_LD_GPIO);
  192. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  193. superio_exit(sio->addr);
  194. return !(dir & 1 << offset);
  195. }
  196. static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  197. {
  198. int err;
  199. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  200. struct f7188x_sio *sio = bank->data->sio;
  201. u8 dir;
  202. err = superio_enter(sio->addr);
  203. if (err)
  204. return err;
  205. superio_select(sio->addr, SIO_LD_GPIO);
  206. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  207. dir &= ~BIT(offset);
  208. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  209. superio_exit(sio->addr);
  210. return 0;
  211. }
  212. static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
  213. {
  214. int err;
  215. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  216. struct f7188x_sio *sio = bank->data->sio;
  217. u8 dir, data;
  218. err = superio_enter(sio->addr);
  219. if (err)
  220. return err;
  221. superio_select(sio->addr, SIO_LD_GPIO);
  222. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  223. dir = !!(dir & BIT(offset));
  224. if (dir)
  225. data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  226. else
  227. data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
  228. superio_exit(sio->addr);
  229. return !!(data & BIT(offset));
  230. }
  231. static int f7188x_gpio_direction_out(struct gpio_chip *chip,
  232. unsigned offset, int value)
  233. {
  234. int err;
  235. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  236. struct f7188x_sio *sio = bank->data->sio;
  237. u8 dir, data_out;
  238. err = superio_enter(sio->addr);
  239. if (err)
  240. return err;
  241. superio_select(sio->addr, SIO_LD_GPIO);
  242. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  243. if (value)
  244. data_out |= BIT(offset);
  245. else
  246. data_out &= ~BIT(offset);
  247. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  248. dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
  249. dir |= BIT(offset);
  250. superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
  251. superio_exit(sio->addr);
  252. return 0;
  253. }
  254. static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  255. {
  256. int err;
  257. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  258. struct f7188x_sio *sio = bank->data->sio;
  259. u8 data_out;
  260. err = superio_enter(sio->addr);
  261. if (err)
  262. return;
  263. superio_select(sio->addr, SIO_LD_GPIO);
  264. data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
  265. if (value)
  266. data_out |= BIT(offset);
  267. else
  268. data_out &= ~BIT(offset);
  269. superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
  270. superio_exit(sio->addr);
  271. }
  272. static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
  273. unsigned long config)
  274. {
  275. int err;
  276. enum pin_config_param param = pinconf_to_config_param(config);
  277. struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
  278. struct f7188x_sio *sio = bank->data->sio;
  279. u8 data;
  280. if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
  281. param != PIN_CONFIG_DRIVE_PUSH_PULL)
  282. return -ENOTSUPP;
  283. err = superio_enter(sio->addr);
  284. if (err)
  285. return err;
  286. superio_select(sio->addr, SIO_LD_GPIO);
  287. data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
  288. if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
  289. data &= ~BIT(offset);
  290. else
  291. data |= BIT(offset);
  292. superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
  293. superio_exit(sio->addr);
  294. return 0;
  295. }
  296. /*
  297. * Platform device and driver.
  298. */
  299. static int f7188x_gpio_probe(struct platform_device *pdev)
  300. {
  301. int err;
  302. int i;
  303. struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
  304. struct f7188x_gpio_data *data;
  305. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  306. if (!data)
  307. return -ENOMEM;
  308. switch (sio->type) {
  309. case f71869:
  310. data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
  311. data->bank = f71869_gpio_bank;
  312. break;
  313. case f71869a:
  314. data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
  315. data->bank = f71869a_gpio_bank;
  316. break;
  317. case f71882fg:
  318. data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
  319. data->bank = f71882_gpio_bank;
  320. break;
  321. case f71889f:
  322. data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
  323. data->bank = f71889_gpio_bank;
  324. break;
  325. case f81866:
  326. data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
  327. data->bank = f81866_gpio_bank;
  328. break;
  329. default:
  330. return -ENODEV;
  331. }
  332. data->sio = sio;
  333. platform_set_drvdata(pdev, data);
  334. /* For each GPIO bank, register a GPIO chip. */
  335. for (i = 0; i < data->nr_bank; i++) {
  336. struct f7188x_gpio_bank *bank = &data->bank[i];
  337. bank->chip.parent = &pdev->dev;
  338. bank->data = data;
  339. err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
  340. if (err) {
  341. dev_err(&pdev->dev,
  342. "Failed to register gpiochip %d: %d\n",
  343. i, err);
  344. return err;
  345. }
  346. }
  347. return 0;
  348. }
  349. static int __init f7188x_find(int addr, struct f7188x_sio *sio)
  350. {
  351. int err;
  352. u16 devid;
  353. err = superio_enter(addr);
  354. if (err)
  355. return err;
  356. err = -ENODEV;
  357. devid = superio_inw(addr, SIO_MANID);
  358. if (devid != SIO_FINTEK_ID) {
  359. pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
  360. goto err;
  361. }
  362. devid = superio_inw(addr, SIO_DEVID);
  363. switch (devid) {
  364. case SIO_F71869_ID:
  365. sio->type = f71869;
  366. break;
  367. case SIO_F71869A_ID:
  368. sio->type = f71869a;
  369. break;
  370. case SIO_F71882_ID:
  371. sio->type = f71882fg;
  372. break;
  373. case SIO_F71889_ID:
  374. sio->type = f71889f;
  375. break;
  376. case SIO_F81866_ID:
  377. sio->type = f81866;
  378. break;
  379. default:
  380. pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
  381. goto err;
  382. }
  383. sio->addr = addr;
  384. err = 0;
  385. pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
  386. f7188x_names[sio->type],
  387. (unsigned int) addr,
  388. (int) superio_inb(addr, SIO_DEVREV));
  389. err:
  390. superio_exit(addr);
  391. return err;
  392. }
  393. static struct platform_device *f7188x_gpio_pdev;
  394. static int __init
  395. f7188x_gpio_device_add(const struct f7188x_sio *sio)
  396. {
  397. int err;
  398. f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
  399. if (!f7188x_gpio_pdev)
  400. return -ENOMEM;
  401. err = platform_device_add_data(f7188x_gpio_pdev,
  402. sio, sizeof(*sio));
  403. if (err) {
  404. pr_err(DRVNAME "Platform data allocation failed\n");
  405. goto err;
  406. }
  407. err = platform_device_add(f7188x_gpio_pdev);
  408. if (err) {
  409. pr_err(DRVNAME "Device addition failed\n");
  410. goto err;
  411. }
  412. return 0;
  413. err:
  414. platform_device_put(f7188x_gpio_pdev);
  415. return err;
  416. }
  417. /*
  418. * Try to match a supported Fintek device by reading the (hard-wired)
  419. * configuration I/O ports. If available, then register both the platform
  420. * device and driver to support the GPIOs.
  421. */
  422. static struct platform_driver f7188x_gpio_driver = {
  423. .driver = {
  424. .name = DRVNAME,
  425. },
  426. .probe = f7188x_gpio_probe,
  427. };
  428. static int __init f7188x_gpio_init(void)
  429. {
  430. int err;
  431. struct f7188x_sio sio;
  432. if (f7188x_find(0x2e, &sio) &&
  433. f7188x_find(0x4e, &sio))
  434. return -ENODEV;
  435. err = platform_driver_register(&f7188x_gpio_driver);
  436. if (!err) {
  437. err = f7188x_gpio_device_add(&sio);
  438. if (err)
  439. platform_driver_unregister(&f7188x_gpio_driver);
  440. }
  441. return err;
  442. }
  443. subsys_initcall(f7188x_gpio_init);
  444. static void __exit f7188x_gpio_exit(void)
  445. {
  446. platform_device_unregister(f7188x_gpio_pdev);
  447. platform_driver_unregister(&f7188x_gpio_driver);
  448. }
  449. module_exit(f7188x_gpio_exit);
  450. MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
  451. MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
  452. MODULE_LICENSE("GPL");