clk-pmc-atom.c 8.4 KB

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  1. /*
  2. * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
  3. *
  4. * Copyright (C) 2016, Intel Corporation
  5. * Author: Irina Tirdea <irina.tirdea@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. */
  16. #include <linux/clk-provider.h>
  17. #include <linux/clkdev.h>
  18. #include <linux/err.h>
  19. #include <linux/platform_data/x86/clk-pmc-atom.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #define PLT_CLK_NAME_BASE "pmc_plt_clk"
  23. #define PMC_CLK_CTL_OFFSET 0x60
  24. #define PMC_CLK_CTL_SIZE 4
  25. #define PMC_CLK_NUM 6
  26. #define PMC_CLK_CTL_GATED_ON_D3 0x0
  27. #define PMC_CLK_CTL_FORCE_ON 0x1
  28. #define PMC_CLK_CTL_FORCE_OFF 0x2
  29. #define PMC_CLK_CTL_RESERVED 0x3
  30. #define PMC_MASK_CLK_CTL GENMASK(1, 0)
  31. #define PMC_MASK_CLK_FREQ BIT(2)
  32. #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
  33. #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
  34. struct clk_plt_fixed {
  35. struct clk_hw *clk;
  36. struct clk_lookup *lookup;
  37. };
  38. struct clk_plt {
  39. struct clk_hw hw;
  40. void __iomem *reg;
  41. struct clk_lookup *lookup;
  42. /* protect access to PMC registers */
  43. spinlock_t lock;
  44. };
  45. #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
  46. struct clk_plt_data {
  47. struct clk_plt_fixed **parents;
  48. u8 nparents;
  49. struct clk_plt *clks[PMC_CLK_NUM];
  50. };
  51. /* Return an index in parent table */
  52. static inline int plt_reg_to_parent(int reg)
  53. {
  54. switch (reg & PMC_MASK_CLK_FREQ) {
  55. default:
  56. case PMC_CLK_FREQ_XTAL:
  57. return 0;
  58. case PMC_CLK_FREQ_PLL:
  59. return 1;
  60. }
  61. }
  62. /* Return clk index of parent */
  63. static inline int plt_parent_to_reg(int index)
  64. {
  65. switch (index) {
  66. default:
  67. case 0:
  68. return PMC_CLK_FREQ_XTAL;
  69. case 1:
  70. return PMC_CLK_FREQ_PLL;
  71. }
  72. }
  73. /* Abstract status in simpler enabled/disabled value */
  74. static inline int plt_reg_to_enabled(int reg)
  75. {
  76. switch (reg & PMC_MASK_CLK_CTL) {
  77. case PMC_CLK_CTL_GATED_ON_D3:
  78. case PMC_CLK_CTL_FORCE_ON:
  79. return 1; /* enabled */
  80. case PMC_CLK_CTL_FORCE_OFF:
  81. case PMC_CLK_CTL_RESERVED:
  82. default:
  83. return 0; /* disabled */
  84. }
  85. }
  86. static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
  87. {
  88. u32 tmp;
  89. unsigned long flags;
  90. spin_lock_irqsave(&clk->lock, flags);
  91. tmp = readl(clk->reg);
  92. tmp = (tmp & ~mask) | (val & mask);
  93. writel(tmp, clk->reg);
  94. spin_unlock_irqrestore(&clk->lock, flags);
  95. }
  96. static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
  97. {
  98. struct clk_plt *clk = to_clk_plt(hw);
  99. plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
  100. return 0;
  101. }
  102. static u8 plt_clk_get_parent(struct clk_hw *hw)
  103. {
  104. struct clk_plt *clk = to_clk_plt(hw);
  105. u32 value;
  106. value = readl(clk->reg);
  107. return plt_reg_to_parent(value);
  108. }
  109. static int plt_clk_enable(struct clk_hw *hw)
  110. {
  111. struct clk_plt *clk = to_clk_plt(hw);
  112. plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
  113. return 0;
  114. }
  115. static void plt_clk_disable(struct clk_hw *hw)
  116. {
  117. struct clk_plt *clk = to_clk_plt(hw);
  118. plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
  119. }
  120. static int plt_clk_is_enabled(struct clk_hw *hw)
  121. {
  122. struct clk_plt *clk = to_clk_plt(hw);
  123. u32 value;
  124. value = readl(clk->reg);
  125. return plt_reg_to_enabled(value);
  126. }
  127. static const struct clk_ops plt_clk_ops = {
  128. .enable = plt_clk_enable,
  129. .disable = plt_clk_disable,
  130. .is_enabled = plt_clk_is_enabled,
  131. .get_parent = plt_clk_get_parent,
  132. .set_parent = plt_clk_set_parent,
  133. .determine_rate = __clk_mux_determine_rate,
  134. };
  135. static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
  136. void __iomem *base,
  137. const char **parent_names,
  138. int num_parents)
  139. {
  140. struct clk_plt *pclk;
  141. struct clk_init_data init;
  142. int ret;
  143. pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
  144. if (!pclk)
  145. return ERR_PTR(-ENOMEM);
  146. init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
  147. init.ops = &plt_clk_ops;
  148. init.flags = 0;
  149. init.parent_names = parent_names;
  150. init.num_parents = num_parents;
  151. pclk->hw.init = &init;
  152. pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
  153. spin_lock_init(&pclk->lock);
  154. ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
  155. if (ret) {
  156. pclk = ERR_PTR(ret);
  157. goto err_free_init;
  158. }
  159. pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
  160. if (!pclk->lookup) {
  161. pclk = ERR_PTR(-ENOMEM);
  162. goto err_free_init;
  163. }
  164. err_free_init:
  165. kfree(init.name);
  166. return pclk;
  167. }
  168. static void plt_clk_unregister(struct clk_plt *pclk)
  169. {
  170. clkdev_drop(pclk->lookup);
  171. }
  172. static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
  173. const char *name,
  174. const char *parent_name,
  175. unsigned long fixed_rate)
  176. {
  177. struct clk_plt_fixed *pclk;
  178. pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
  179. if (!pclk)
  180. return ERR_PTR(-ENOMEM);
  181. pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
  182. 0, fixed_rate);
  183. if (IS_ERR(pclk->clk))
  184. return ERR_CAST(pclk->clk);
  185. pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
  186. if (!pclk->lookup) {
  187. clk_hw_unregister_fixed_rate(pclk->clk);
  188. return ERR_PTR(-ENOMEM);
  189. }
  190. return pclk;
  191. }
  192. static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
  193. {
  194. clkdev_drop(pclk->lookup);
  195. clk_hw_unregister_fixed_rate(pclk->clk);
  196. }
  197. static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
  198. unsigned int i)
  199. {
  200. while (i--)
  201. plt_clk_unregister_fixed_rate(data->parents[i]);
  202. }
  203. static void plt_clk_free_parent_names_loop(const char **parent_names,
  204. unsigned int i)
  205. {
  206. while (i--)
  207. kfree_const(parent_names[i]);
  208. kfree(parent_names);
  209. }
  210. static void plt_clk_unregister_loop(struct clk_plt_data *data,
  211. unsigned int i)
  212. {
  213. while (i--)
  214. plt_clk_unregister(data->clks[i]);
  215. }
  216. static const char **plt_clk_register_parents(struct platform_device *pdev,
  217. struct clk_plt_data *data,
  218. const struct pmc_clk *clks)
  219. {
  220. const char **parent_names;
  221. unsigned int i;
  222. int err;
  223. int nparents = 0;
  224. data->nparents = 0;
  225. while (clks[nparents].name)
  226. nparents++;
  227. data->parents = devm_kcalloc(&pdev->dev, nparents,
  228. sizeof(*data->parents), GFP_KERNEL);
  229. if (!data->parents)
  230. return ERR_PTR(-ENOMEM);
  231. parent_names = kcalloc(nparents, sizeof(*parent_names),
  232. GFP_KERNEL);
  233. if (!parent_names)
  234. return ERR_PTR(-ENOMEM);
  235. for (i = 0; i < nparents; i++) {
  236. data->parents[i] =
  237. plt_clk_register_fixed_rate(pdev, clks[i].name,
  238. clks[i].parent_name,
  239. clks[i].freq);
  240. if (IS_ERR(data->parents[i])) {
  241. err = PTR_ERR(data->parents[i]);
  242. goto err_unreg;
  243. }
  244. parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
  245. }
  246. data->nparents = nparents;
  247. return parent_names;
  248. err_unreg:
  249. plt_clk_unregister_fixed_rate_loop(data, i);
  250. plt_clk_free_parent_names_loop(parent_names, i);
  251. return ERR_PTR(err);
  252. }
  253. static void plt_clk_unregister_parents(struct clk_plt_data *data)
  254. {
  255. plt_clk_unregister_fixed_rate_loop(data, data->nparents);
  256. }
  257. static int plt_clk_probe(struct platform_device *pdev)
  258. {
  259. const struct pmc_clk_data *pmc_data;
  260. const char **parent_names;
  261. struct clk_plt_data *data;
  262. unsigned int i;
  263. int err;
  264. pmc_data = dev_get_platdata(&pdev->dev);
  265. if (!pmc_data || !pmc_data->clks)
  266. return -EINVAL;
  267. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  268. if (!data)
  269. return -ENOMEM;
  270. parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
  271. if (IS_ERR(parent_names))
  272. return PTR_ERR(parent_names);
  273. for (i = 0; i < PMC_CLK_NUM; i++) {
  274. data->clks[i] = plt_clk_register(pdev, i, pmc_data->base,
  275. parent_names, data->nparents);
  276. if (IS_ERR(data->clks[i])) {
  277. err = PTR_ERR(data->clks[i]);
  278. goto err_unreg_clk_plt;
  279. }
  280. }
  281. plt_clk_free_parent_names_loop(parent_names, data->nparents);
  282. platform_set_drvdata(pdev, data);
  283. return 0;
  284. err_unreg_clk_plt:
  285. plt_clk_unregister_loop(data, i);
  286. plt_clk_unregister_parents(data);
  287. plt_clk_free_parent_names_loop(parent_names, data->nparents);
  288. return err;
  289. }
  290. static int plt_clk_remove(struct platform_device *pdev)
  291. {
  292. struct clk_plt_data *data;
  293. data = platform_get_drvdata(pdev);
  294. plt_clk_unregister_loop(data, PMC_CLK_NUM);
  295. plt_clk_unregister_parents(data);
  296. return 0;
  297. }
  298. static struct platform_driver plt_clk_driver = {
  299. .driver = {
  300. .name = "clk-pmc-atom",
  301. },
  302. .probe = plt_clk_probe,
  303. .remove = plt_clk_remove,
  304. };
  305. builtin_platform_driver(plt_clk_driver);