ccu_mux.c 6.5 KB

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  1. /*
  2. * Copyright (C) 2016 Maxime Ripard
  3. * Maxime Ripard <maxime.ripard@free-electrons.com>
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/delay.h>
  13. #include "ccu_gate.h"
  14. #include "ccu_mux.h"
  15. void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
  16. struct ccu_mux_internal *cm,
  17. int parent_index,
  18. unsigned long *parent_rate)
  19. {
  20. u16 prediv = 1;
  21. u32 reg;
  22. int i;
  23. if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
  24. (common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
  25. (common->features & CCU_FEATURE_ALL_PREDIV)))
  26. return;
  27. if (common->features & CCU_FEATURE_ALL_PREDIV) {
  28. *parent_rate = *parent_rate / common->prediv;
  29. return;
  30. }
  31. reg = readl(common->base + common->reg);
  32. if (parent_index < 0) {
  33. parent_index = reg >> cm->shift;
  34. parent_index &= (1 << cm->width) - 1;
  35. }
  36. if (common->features & CCU_FEATURE_FIXED_PREDIV)
  37. for (i = 0; i < cm->n_predivs; i++)
  38. if (parent_index == cm->fixed_predivs[i].index)
  39. prediv = cm->fixed_predivs[i].div;
  40. if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
  41. if (parent_index == cm->variable_prediv.index) {
  42. u8 div;
  43. div = reg >> cm->variable_prediv.shift;
  44. div &= (1 << cm->variable_prediv.width) - 1;
  45. prediv = div + 1;
  46. }
  47. *parent_rate = *parent_rate / prediv;
  48. }
  49. int ccu_mux_helper_determine_rate(struct ccu_common *common,
  50. struct ccu_mux_internal *cm,
  51. struct clk_rate_request *req,
  52. unsigned long (*round)(struct ccu_mux_internal *,
  53. unsigned long,
  54. unsigned long,
  55. void *),
  56. void *data)
  57. {
  58. unsigned long best_parent_rate = 0, best_rate = 0;
  59. struct clk_hw *best_parent, *hw = &common->hw;
  60. unsigned int i;
  61. if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
  62. unsigned long adj_parent_rate;
  63. best_parent = clk_hw_get_parent(hw);
  64. best_parent_rate = clk_hw_get_rate(best_parent);
  65. adj_parent_rate = best_parent_rate;
  66. ccu_mux_helper_adjust_parent_for_prediv(common, cm, -1,
  67. &adj_parent_rate);
  68. best_rate = round(cm, adj_parent_rate, req->rate, data);
  69. goto out;
  70. }
  71. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  72. unsigned long tmp_rate, parent_rate, adj_parent_rate;
  73. struct clk_hw *parent;
  74. parent = clk_hw_get_parent_by_index(hw, i);
  75. if (!parent)
  76. continue;
  77. if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
  78. struct clk_rate_request parent_req = *req;
  79. int ret = __clk_determine_rate(parent, &parent_req);
  80. if (ret)
  81. continue;
  82. parent_rate = parent_req.rate;
  83. } else {
  84. parent_rate = clk_hw_get_rate(parent);
  85. }
  86. adj_parent_rate = parent_rate;
  87. ccu_mux_helper_adjust_parent_for_prediv(common, cm, i,
  88. &adj_parent_rate);
  89. tmp_rate = round(cm, adj_parent_rate, req->rate, data);
  90. if (tmp_rate == req->rate) {
  91. best_parent = parent;
  92. best_parent_rate = parent_rate;
  93. best_rate = tmp_rate;
  94. goto out;
  95. }
  96. if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
  97. best_rate = tmp_rate;
  98. best_parent_rate = parent_rate;
  99. best_parent = parent;
  100. }
  101. }
  102. if (best_rate == 0)
  103. return -EINVAL;
  104. out:
  105. req->best_parent_hw = best_parent;
  106. req->best_parent_rate = best_parent_rate;
  107. req->rate = best_rate;
  108. return 0;
  109. }
  110. u8 ccu_mux_helper_get_parent(struct ccu_common *common,
  111. struct ccu_mux_internal *cm)
  112. {
  113. u32 reg;
  114. u8 parent;
  115. reg = readl(common->base + common->reg);
  116. parent = reg >> cm->shift;
  117. parent &= (1 << cm->width) - 1;
  118. if (cm->table) {
  119. int num_parents = clk_hw_get_num_parents(&common->hw);
  120. int i;
  121. for (i = 0; i < num_parents; i++)
  122. if (cm->table[i] == parent)
  123. return i;
  124. }
  125. return parent;
  126. }
  127. int ccu_mux_helper_set_parent(struct ccu_common *common,
  128. struct ccu_mux_internal *cm,
  129. u8 index)
  130. {
  131. unsigned long flags;
  132. u32 reg;
  133. if (cm->table)
  134. index = cm->table[index];
  135. spin_lock_irqsave(common->lock, flags);
  136. reg = readl(common->base + common->reg);
  137. reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
  138. writel(reg | (index << cm->shift), common->base + common->reg);
  139. spin_unlock_irqrestore(common->lock, flags);
  140. return 0;
  141. }
  142. static void ccu_mux_disable(struct clk_hw *hw)
  143. {
  144. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  145. return ccu_gate_helper_disable(&cm->common, cm->enable);
  146. }
  147. static int ccu_mux_enable(struct clk_hw *hw)
  148. {
  149. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  150. return ccu_gate_helper_enable(&cm->common, cm->enable);
  151. }
  152. static int ccu_mux_is_enabled(struct clk_hw *hw)
  153. {
  154. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  155. return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
  156. }
  157. static u8 ccu_mux_get_parent(struct clk_hw *hw)
  158. {
  159. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  160. return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
  161. }
  162. static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
  163. {
  164. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  165. return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
  166. }
  167. static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
  168. unsigned long parent_rate)
  169. {
  170. struct ccu_mux *cm = hw_to_ccu_mux(hw);
  171. ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
  172. &parent_rate);
  173. return parent_rate;
  174. }
  175. const struct clk_ops ccu_mux_ops = {
  176. .disable = ccu_mux_disable,
  177. .enable = ccu_mux_enable,
  178. .is_enabled = ccu_mux_is_enabled,
  179. .get_parent = ccu_mux_get_parent,
  180. .set_parent = ccu_mux_set_parent,
  181. .determine_rate = __clk_mux_determine_rate,
  182. .recalc_rate = ccu_mux_recalc_rate,
  183. };
  184. /*
  185. * This clock notifier is called when the frequency of the of the parent
  186. * PLL clock is to be changed. The idea is to switch the parent to a
  187. * stable clock, such as the main oscillator, while the PLL frequency
  188. * stabilizes.
  189. */
  190. static int ccu_mux_notifier_cb(struct notifier_block *nb,
  191. unsigned long event, void *data)
  192. {
  193. struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
  194. int ret = 0;
  195. if (event == PRE_RATE_CHANGE) {
  196. mux->original_index = ccu_mux_helper_get_parent(mux->common,
  197. mux->cm);
  198. ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
  199. mux->bypass_index);
  200. } else if (event == POST_RATE_CHANGE) {
  201. ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
  202. mux->original_index);
  203. }
  204. udelay(mux->delay_us);
  205. return notifier_from_errno(ret);
  206. }
  207. int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
  208. {
  209. mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
  210. return clk_notifier_register(clk, &mux_nb->clk_nb);
  211. }