Kconfig 4.2 KB

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  1. #
  2. # Memory devices
  3. #
  4. menuconfig MEMORY
  5. bool "Memory Controller drivers"
  6. if MEMORY
  7. config ARM_PL172_MPMC
  8. tristate "ARM PL172 MPMC driver"
  9. depends on ARM_AMBA && OF
  10. help
  11. This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
  12. If you have an embedded system with an AMBA bus and a PL172
  13. controller, say Y or M here.
  14. config ATMEL_SDRAMC
  15. bool "Atmel (Multi-port DDR-)SDRAM Controller"
  16. default y
  17. depends on ARCH_AT91 && OF
  18. help
  19. This driver is for Atmel SDRAM Controller or Atmel Multi-port
  20. DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
  21. Starting with the at91sam9g45, this controller supports SDR, DDR and
  22. LP-DDR memories.
  23. config TI_AEMIF
  24. tristate "Texas Instruments AEMIF driver"
  25. depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
  26. help
  27. This driver is for the AEMIF module available in Texas Instruments
  28. SoCs. AEMIF stands for Asynchronous External Memory Interface and
  29. is intended to provide a glue-less interface to a variety of
  30. asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
  31. of 256M bytes of any of these memories can be accessed at a given
  32. time via four chip selects with 64M byte access per chip select.
  33. config TI_EMIF
  34. tristate "Texas Instruments EMIF driver"
  35. depends on ARCH_OMAP2PLUS
  36. select DDR
  37. help
  38. This driver is for the EMIF module available in Texas Instruments
  39. SoCs. EMIF is an SDRAM controller that, based on its revision,
  40. supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
  41. This driver takes care of only LPDDR2 memories presently. The
  42. functions of the driver includes re-configuring AC timing
  43. parameters and other settings during frequency, voltage and
  44. temperature changes
  45. config OMAP_GPMC
  46. bool
  47. select GPIOLIB
  48. help
  49. This driver is for the General Purpose Memory Controller (GPMC)
  50. present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
  51. interfacing to a variety of asynchronous as well as synchronous
  52. memory drives like NOR, NAND, OneNAND, SRAM.
  53. config OMAP_GPMC_DEBUG
  54. bool "Enable GPMC debug output and skip reset of GPMC during init"
  55. depends on OMAP_GPMC
  56. help
  57. Enables verbose debugging mostly to decode the bootloader provided
  58. timings. To preserve the bootloader provided timings, the reset
  59. of GPMC is skipped during init. Enable this during development to
  60. configure devices connected to the GPMC bus.
  61. NOTE: In addition to matching the register setup with the bootloader
  62. you also need to match the GPMC FCLK frequency used by the
  63. bootloader or else the GPMC timings won't be identical with the
  64. bootloader timings.
  65. config MVEBU_DEVBUS
  66. bool "Marvell EBU Device Bus Controller"
  67. default y
  68. depends on PLAT_ORION && OF
  69. help
  70. This driver is for the Device Bus controller available in some
  71. Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
  72. Armada 370 and Armada XP. This controller allows to handle flash
  73. devices such as NOR, NAND, SRAM, and FPGA.
  74. config TEGRA20_MC
  75. bool "Tegra20 Memory Controller(MC) driver"
  76. default y
  77. depends on ARCH_TEGRA_2x_SOC
  78. help
  79. This driver is for the Memory Controller(MC) module available
  80. in Tegra20 SoCs, mainly for a address translation fault
  81. analysis, especially for IOMMU/GART(Graphics Address
  82. Relocation Table) module.
  83. config FSL_CORENET_CF
  84. tristate "Freescale CoreNet Error Reporting"
  85. depends on FSL_SOC_BOOKE
  86. help
  87. Say Y for reporting of errors from the Freescale CoreNet
  88. Coherency Fabric. Errors reported include accesses to
  89. physical addresses that mapped by no local access window
  90. (LAW) or an invalid LAW, as well as bad cache state that
  91. represents a coherency violation.
  92. config FSL_IFC
  93. bool
  94. depends on FSL_SOC
  95. config JZ4780_NEMC
  96. bool "Ingenic JZ4780 SoC NEMC driver"
  97. default y
  98. depends on MACH_JZ4780
  99. help
  100. This driver is for the NAND/External Memory Controller (NEMC) in
  101. the Ingenic JZ4780. This controller is used to handle external
  102. memory devices such as NAND and SRAM.
  103. config MTK_SMI
  104. bool
  105. depends on ARCH_MEDIATEK || COMPILE_TEST
  106. help
  107. This driver is for the Memory Controller module in MediaTek SoCs,
  108. mainly help enable/disable iommu and control the power domain and
  109. clocks for each local arbiter.
  110. source "drivers/memory/samsung/Kconfig"
  111. source "drivers/memory/tegra/Kconfig"
  112. endif