amdgpu_dm.c 141 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: AMD
  23. *
  24. */
  25. #include "dm_services_types.h"
  26. #include "dc.h"
  27. #include "dc/inc/core_types.h"
  28. #include "vid.h"
  29. #include "amdgpu.h"
  30. #include "amdgpu_display.h"
  31. #include "atom.h"
  32. #include "amdgpu_dm.h"
  33. #include "amdgpu_pm.h"
  34. #include "amd_shared.h"
  35. #include "amdgpu_dm_irq.h"
  36. #include "dm_helpers.h"
  37. #include "dm_services_types.h"
  38. #include "amdgpu_dm_mst_types.h"
  39. #include "ivsrcid/ivsrcid_vislands30.h"
  40. #include <linux/module.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/version.h>
  43. #include <linux/types.h>
  44. #include <linux/pm_runtime.h>
  45. #include <drm/drmP.h>
  46. #include <drm/drm_atomic.h>
  47. #include <drm/drm_atomic_helper.h>
  48. #include <drm/drm_dp_mst_helper.h>
  49. #include <drm/drm_fb_helper.h>
  50. #include <drm/drm_edid.h>
  51. #include "modules/inc/mod_freesync.h"
  52. #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  53. #include "ivsrcid/irqsrcs_dcn_1_0.h"
  54. #include "dcn/dcn_1_0_offset.h"
  55. #include "dcn/dcn_1_0_sh_mask.h"
  56. #include "soc15_hw_ip.h"
  57. #include "vega10_ip_offset.h"
  58. #include "soc15_common.h"
  59. #endif
  60. #include "modules/inc/mod_freesync.h"
  61. #include "i2caux_interface.h"
  62. /* basic init/fini API */
  63. static int amdgpu_dm_init(struct amdgpu_device *adev);
  64. static void amdgpu_dm_fini(struct amdgpu_device *adev);
  65. /* initializes drm_device display related structures, based on the information
  66. * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
  67. * drm_encoder, drm_mode_config
  68. *
  69. * Returns 0 on success
  70. */
  71. static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
  72. /* removes and deallocates the drm structures, created by the above function */
  73. static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
  74. static void
  75. amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
  76. static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  77. struct amdgpu_plane *aplane,
  78. unsigned long possible_crtcs);
  79. static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
  80. struct drm_plane *plane,
  81. uint32_t link_index);
  82. static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
  83. struct amdgpu_dm_connector *amdgpu_dm_connector,
  84. uint32_t link_index,
  85. struct amdgpu_encoder *amdgpu_encoder);
  86. static int amdgpu_dm_encoder_init(struct drm_device *dev,
  87. struct amdgpu_encoder *aencoder,
  88. uint32_t link_index);
  89. static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
  90. static int amdgpu_dm_atomic_commit(struct drm_device *dev,
  91. struct drm_atomic_state *state,
  92. bool nonblock);
  93. static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
  94. static int amdgpu_dm_atomic_check(struct drm_device *dev,
  95. struct drm_atomic_state *state);
  96. static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
  97. DRM_PLANE_TYPE_PRIMARY,
  98. DRM_PLANE_TYPE_PRIMARY,
  99. DRM_PLANE_TYPE_PRIMARY,
  100. DRM_PLANE_TYPE_PRIMARY,
  101. DRM_PLANE_TYPE_PRIMARY,
  102. DRM_PLANE_TYPE_PRIMARY,
  103. };
  104. static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
  105. DRM_PLANE_TYPE_PRIMARY,
  106. DRM_PLANE_TYPE_PRIMARY,
  107. DRM_PLANE_TYPE_PRIMARY,
  108. DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
  109. };
  110. static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
  111. DRM_PLANE_TYPE_PRIMARY,
  112. DRM_PLANE_TYPE_PRIMARY,
  113. DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
  114. };
  115. /*
  116. * dm_vblank_get_counter
  117. *
  118. * @brief
  119. * Get counter for number of vertical blanks
  120. *
  121. * @param
  122. * struct amdgpu_device *adev - [in] desired amdgpu device
  123. * int disp_idx - [in] which CRTC to get the counter from
  124. *
  125. * @return
  126. * Counter for vertical blanks
  127. */
  128. static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  129. {
  130. if (crtc >= adev->mode_info.num_crtc)
  131. return 0;
  132. else {
  133. struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
  134. struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
  135. acrtc->base.state);
  136. if (acrtc_state->stream == NULL) {
  137. DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
  138. crtc);
  139. return 0;
  140. }
  141. return dc_stream_get_vblank_counter(acrtc_state->stream);
  142. }
  143. }
  144. static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  145. u32 *vbl, u32 *position)
  146. {
  147. uint32_t v_blank_start, v_blank_end, h_position, v_position;
  148. if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
  149. return -EINVAL;
  150. else {
  151. struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
  152. struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
  153. acrtc->base.state);
  154. if (acrtc_state->stream == NULL) {
  155. DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
  156. crtc);
  157. return 0;
  158. }
  159. /*
  160. * TODO rework base driver to use values directly.
  161. * for now parse it back into reg-format
  162. */
  163. dc_stream_get_scanoutpos(acrtc_state->stream,
  164. &v_blank_start,
  165. &v_blank_end,
  166. &h_position,
  167. &v_position);
  168. *position = v_position | (h_position << 16);
  169. *vbl = v_blank_start | (v_blank_end << 16);
  170. }
  171. return 0;
  172. }
  173. static bool dm_is_idle(void *handle)
  174. {
  175. /* XXX todo */
  176. return true;
  177. }
  178. static int dm_wait_for_idle(void *handle)
  179. {
  180. /* XXX todo */
  181. return 0;
  182. }
  183. static bool dm_check_soft_reset(void *handle)
  184. {
  185. return false;
  186. }
  187. static int dm_soft_reset(void *handle)
  188. {
  189. /* XXX todo */
  190. return 0;
  191. }
  192. static struct amdgpu_crtc *
  193. get_crtc_by_otg_inst(struct amdgpu_device *adev,
  194. int otg_inst)
  195. {
  196. struct drm_device *dev = adev->ddev;
  197. struct drm_crtc *crtc;
  198. struct amdgpu_crtc *amdgpu_crtc;
  199. /*
  200. * following if is check inherited from both functions where this one is
  201. * used now. Need to be checked why it could happen.
  202. */
  203. if (otg_inst == -1) {
  204. WARN_ON(1);
  205. return adev->mode_info.crtcs[0];
  206. }
  207. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  208. amdgpu_crtc = to_amdgpu_crtc(crtc);
  209. if (amdgpu_crtc->otg_inst == otg_inst)
  210. return amdgpu_crtc;
  211. }
  212. return NULL;
  213. }
  214. static void dm_pflip_high_irq(void *interrupt_params)
  215. {
  216. struct amdgpu_crtc *amdgpu_crtc;
  217. struct common_irq_params *irq_params = interrupt_params;
  218. struct amdgpu_device *adev = irq_params->adev;
  219. unsigned long flags;
  220. amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
  221. /* IRQ could occur when in initial stage */
  222. /*TODO work and BO cleanup */
  223. if (amdgpu_crtc == NULL) {
  224. DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
  225. return;
  226. }
  227. spin_lock_irqsave(&adev->ddev->event_lock, flags);
  228. if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
  229. DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
  230. amdgpu_crtc->pflip_status,
  231. AMDGPU_FLIP_SUBMITTED,
  232. amdgpu_crtc->crtc_id,
  233. amdgpu_crtc);
  234. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  235. return;
  236. }
  237. /* wakeup usersapce */
  238. if (amdgpu_crtc->event) {
  239. /* Update to correct count/ts if racing with vblank irq */
  240. drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
  241. drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
  242. /* page flip completed. clean up */
  243. amdgpu_crtc->event = NULL;
  244. } else
  245. WARN_ON(1);
  246. amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
  247. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  248. DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
  249. __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
  250. drm_crtc_vblank_put(&amdgpu_crtc->base);
  251. }
  252. static void dm_crtc_high_irq(void *interrupt_params)
  253. {
  254. struct common_irq_params *irq_params = interrupt_params;
  255. struct amdgpu_device *adev = irq_params->adev;
  256. uint8_t crtc_index = 0;
  257. struct amdgpu_crtc *acrtc;
  258. acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
  259. if (acrtc)
  260. crtc_index = acrtc->crtc_id;
  261. drm_handle_vblank(adev->ddev, crtc_index);
  262. amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
  263. }
  264. static int dm_set_clockgating_state(void *handle,
  265. enum amd_clockgating_state state)
  266. {
  267. return 0;
  268. }
  269. static int dm_set_powergating_state(void *handle,
  270. enum amd_powergating_state state)
  271. {
  272. return 0;
  273. }
  274. /* Prototypes of private functions */
  275. static int dm_early_init(void* handle);
  276. static void hotplug_notify_work_func(struct work_struct *work)
  277. {
  278. struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
  279. struct drm_device *dev = dm->ddev;
  280. drm_kms_helper_hotplug_event(dev);
  281. }
  282. #if defined(CONFIG_DRM_AMD_DC_FBC)
  283. /* Allocate memory for FBC compressed data */
  284. static void amdgpu_dm_fbc_init(struct drm_connector *connector)
  285. {
  286. struct drm_device *dev = connector->dev;
  287. struct amdgpu_device *adev = dev->dev_private;
  288. struct dm_comressor_info *compressor = &adev->dm.compressor;
  289. struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
  290. struct drm_display_mode *mode;
  291. unsigned long max_size = 0;
  292. if (adev->dm.dc->fbc_compressor == NULL)
  293. return;
  294. if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
  295. return;
  296. if (compressor->bo_ptr)
  297. return;
  298. list_for_each_entry(mode, &connector->modes, head) {
  299. if (max_size < mode->htotal * mode->vtotal)
  300. max_size = mode->htotal * mode->vtotal;
  301. }
  302. if (max_size) {
  303. int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
  304. AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
  305. &compressor->gpu_addr, &compressor->cpu_addr);
  306. if (r)
  307. DRM_ERROR("DM: Failed to initialize FBC\n");
  308. else {
  309. adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
  310. DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
  311. }
  312. }
  313. }
  314. #endif
  315. /* Init display KMS
  316. *
  317. * Returns 0 on success
  318. */
  319. static int amdgpu_dm_init(struct amdgpu_device *adev)
  320. {
  321. struct dc_init_data init_data;
  322. adev->dm.ddev = adev->ddev;
  323. adev->dm.adev = adev;
  324. /* Zero all the fields */
  325. memset(&init_data, 0, sizeof(init_data));
  326. if(amdgpu_dm_irq_init(adev)) {
  327. DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
  328. goto error;
  329. }
  330. init_data.asic_id.chip_family = adev->family;
  331. init_data.asic_id.pci_revision_id = adev->rev_id;
  332. init_data.asic_id.hw_internal_rev = adev->external_rev_id;
  333. init_data.asic_id.vram_width = adev->gmc.vram_width;
  334. /* TODO: initialize init_data.asic_id.vram_type here!!!! */
  335. init_data.asic_id.atombios_base_address =
  336. adev->mode_info.atom_context->bios;
  337. init_data.driver = adev;
  338. adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
  339. if (!adev->dm.cgs_device) {
  340. DRM_ERROR("amdgpu: failed to create cgs device.\n");
  341. goto error;
  342. }
  343. init_data.cgs_device = adev->dm.cgs_device;
  344. adev->dm.dal = NULL;
  345. init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
  346. /*
  347. * TODO debug why this doesn't work on Raven
  348. */
  349. if (adev->flags & AMD_IS_APU &&
  350. adev->asic_type >= CHIP_CARRIZO &&
  351. adev->asic_type < CHIP_RAVEN)
  352. init_data.flags.gpu_vm_support = true;
  353. /* Display Core create. */
  354. adev->dm.dc = dc_create(&init_data);
  355. if (adev->dm.dc) {
  356. DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
  357. } else {
  358. DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
  359. goto error;
  360. }
  361. INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
  362. adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
  363. if (!adev->dm.freesync_module) {
  364. DRM_ERROR(
  365. "amdgpu: failed to initialize freesync_module.\n");
  366. } else
  367. DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
  368. adev->dm.freesync_module);
  369. amdgpu_dm_init_color_mod();
  370. if (amdgpu_dm_initialize_drm_device(adev)) {
  371. DRM_ERROR(
  372. "amdgpu: failed to initialize sw for display support.\n");
  373. goto error;
  374. }
  375. /* Update the actual used number of crtc */
  376. adev->mode_info.num_crtc = adev->dm.display_indexes_num;
  377. /* TODO: Add_display_info? */
  378. /* TODO use dynamic cursor width */
  379. adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
  380. adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
  381. if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
  382. DRM_ERROR(
  383. "amdgpu: failed to initialize sw for display support.\n");
  384. goto error;
  385. }
  386. DRM_DEBUG_DRIVER("KMS initialized.\n");
  387. return 0;
  388. error:
  389. amdgpu_dm_fini(adev);
  390. return -1;
  391. }
  392. static void amdgpu_dm_fini(struct amdgpu_device *adev)
  393. {
  394. amdgpu_dm_destroy_drm_device(&adev->dm);
  395. /*
  396. * TODO: pageflip, vlank interrupt
  397. *
  398. * amdgpu_dm_irq_fini(adev);
  399. */
  400. if (adev->dm.cgs_device) {
  401. amdgpu_cgs_destroy_device(adev->dm.cgs_device);
  402. adev->dm.cgs_device = NULL;
  403. }
  404. if (adev->dm.freesync_module) {
  405. mod_freesync_destroy(adev->dm.freesync_module);
  406. adev->dm.freesync_module = NULL;
  407. }
  408. /* DC Destroy TODO: Replace destroy DAL */
  409. if (adev->dm.dc)
  410. dc_destroy(&adev->dm.dc);
  411. return;
  412. }
  413. static int dm_sw_init(void *handle)
  414. {
  415. return 0;
  416. }
  417. static int dm_sw_fini(void *handle)
  418. {
  419. return 0;
  420. }
  421. static int detect_mst_link_for_all_connectors(struct drm_device *dev)
  422. {
  423. struct amdgpu_dm_connector *aconnector;
  424. struct drm_connector *connector;
  425. int ret = 0;
  426. drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
  427. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  428. aconnector = to_amdgpu_dm_connector(connector);
  429. if (aconnector->dc_link->type == dc_connection_mst_branch &&
  430. aconnector->mst_mgr.aux) {
  431. DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
  432. aconnector, aconnector->base.base.id);
  433. ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
  434. if (ret < 0) {
  435. DRM_ERROR("DM_MST: Failed to start MST\n");
  436. ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
  437. return ret;
  438. }
  439. }
  440. }
  441. drm_modeset_unlock(&dev->mode_config.connection_mutex);
  442. return ret;
  443. }
  444. static int dm_late_init(void *handle)
  445. {
  446. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  447. return detect_mst_link_for_all_connectors(adev->ddev);
  448. }
  449. static void s3_handle_mst(struct drm_device *dev, bool suspend)
  450. {
  451. struct amdgpu_dm_connector *aconnector;
  452. struct drm_connector *connector;
  453. drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
  454. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  455. aconnector = to_amdgpu_dm_connector(connector);
  456. if (aconnector->dc_link->type == dc_connection_mst_branch &&
  457. !aconnector->mst_port) {
  458. if (suspend)
  459. drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
  460. else
  461. drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
  462. }
  463. }
  464. drm_modeset_unlock(&dev->mode_config.connection_mutex);
  465. }
  466. static int dm_hw_init(void *handle)
  467. {
  468. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  469. /* Create DAL display manager */
  470. amdgpu_dm_init(adev);
  471. amdgpu_dm_hpd_init(adev);
  472. return 0;
  473. }
  474. static int dm_hw_fini(void *handle)
  475. {
  476. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  477. amdgpu_dm_hpd_fini(adev);
  478. amdgpu_dm_irq_fini(adev);
  479. amdgpu_dm_fini(adev);
  480. return 0;
  481. }
  482. static int dm_suspend(void *handle)
  483. {
  484. struct amdgpu_device *adev = handle;
  485. struct amdgpu_display_manager *dm = &adev->dm;
  486. int ret = 0;
  487. s3_handle_mst(adev->ddev, true);
  488. amdgpu_dm_irq_suspend(adev);
  489. WARN_ON(adev->dm.cached_state);
  490. adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
  491. dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
  492. return ret;
  493. }
  494. static struct amdgpu_dm_connector *
  495. amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
  496. struct drm_crtc *crtc)
  497. {
  498. uint32_t i;
  499. struct drm_connector_state *new_con_state;
  500. struct drm_connector *connector;
  501. struct drm_crtc *crtc_from_state;
  502. for_each_new_connector_in_state(state, connector, new_con_state, i) {
  503. crtc_from_state = new_con_state->crtc;
  504. if (crtc_from_state == crtc)
  505. return to_amdgpu_dm_connector(connector);
  506. }
  507. return NULL;
  508. }
  509. static int dm_resume(void *handle)
  510. {
  511. struct amdgpu_device *adev = handle;
  512. struct drm_device *ddev = adev->ddev;
  513. struct amdgpu_display_manager *dm = &adev->dm;
  514. struct amdgpu_dm_connector *aconnector;
  515. struct drm_connector *connector;
  516. struct drm_crtc *crtc;
  517. struct drm_crtc_state *new_crtc_state;
  518. struct dm_crtc_state *dm_new_crtc_state;
  519. struct drm_plane *plane;
  520. struct drm_plane_state *new_plane_state;
  521. struct dm_plane_state *dm_new_plane_state;
  522. int ret;
  523. int i;
  524. /* power on hardware */
  525. dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
  526. /* program HPD filter */
  527. dc_resume(dm->dc);
  528. /* On resume we need to rewrite the MSTM control bits to enamble MST*/
  529. s3_handle_mst(ddev, false);
  530. /*
  531. * early enable HPD Rx IRQ, should be done before set mode as short
  532. * pulse interrupts are used for MST
  533. */
  534. amdgpu_dm_irq_resume_early(adev);
  535. /* Do detection*/
  536. list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
  537. aconnector = to_amdgpu_dm_connector(connector);
  538. /*
  539. * this is the case when traversing through already created
  540. * MST connectors, should be skipped
  541. */
  542. if (aconnector->mst_port)
  543. continue;
  544. mutex_lock(&aconnector->hpd_lock);
  545. dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
  546. if (aconnector->fake_enable && aconnector->dc_link->local_sink)
  547. aconnector->fake_enable = false;
  548. aconnector->dc_sink = NULL;
  549. amdgpu_dm_update_connector_after_detect(aconnector);
  550. mutex_unlock(&aconnector->hpd_lock);
  551. }
  552. /* Force mode set in atomic comit */
  553. for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
  554. new_crtc_state->active_changed = true;
  555. /*
  556. * atomic_check is expected to create the dc states. We need to release
  557. * them here, since they were duplicated as part of the suspend
  558. * procedure.
  559. */
  560. for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
  561. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  562. if (dm_new_crtc_state->stream) {
  563. WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
  564. dc_stream_release(dm_new_crtc_state->stream);
  565. dm_new_crtc_state->stream = NULL;
  566. }
  567. }
  568. for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
  569. dm_new_plane_state = to_dm_plane_state(new_plane_state);
  570. if (dm_new_plane_state->dc_state) {
  571. WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
  572. dc_plane_state_release(dm_new_plane_state->dc_state);
  573. dm_new_plane_state->dc_state = NULL;
  574. }
  575. }
  576. ret = drm_atomic_helper_resume(ddev, dm->cached_state);
  577. dm->cached_state = NULL;
  578. amdgpu_dm_irq_resume_late(adev);
  579. return ret;
  580. }
  581. static const struct amd_ip_funcs amdgpu_dm_funcs = {
  582. .name = "dm",
  583. .early_init = dm_early_init,
  584. .late_init = dm_late_init,
  585. .sw_init = dm_sw_init,
  586. .sw_fini = dm_sw_fini,
  587. .hw_init = dm_hw_init,
  588. .hw_fini = dm_hw_fini,
  589. .suspend = dm_suspend,
  590. .resume = dm_resume,
  591. .is_idle = dm_is_idle,
  592. .wait_for_idle = dm_wait_for_idle,
  593. .check_soft_reset = dm_check_soft_reset,
  594. .soft_reset = dm_soft_reset,
  595. .set_clockgating_state = dm_set_clockgating_state,
  596. .set_powergating_state = dm_set_powergating_state,
  597. };
  598. const struct amdgpu_ip_block_version dm_ip_block =
  599. {
  600. .type = AMD_IP_BLOCK_TYPE_DCE,
  601. .major = 1,
  602. .minor = 0,
  603. .rev = 0,
  604. .funcs = &amdgpu_dm_funcs,
  605. };
  606. static struct drm_atomic_state *
  607. dm_atomic_state_alloc(struct drm_device *dev)
  608. {
  609. struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
  610. if (!state)
  611. return NULL;
  612. if (drm_atomic_state_init(dev, &state->base) < 0)
  613. goto fail;
  614. return &state->base;
  615. fail:
  616. kfree(state);
  617. return NULL;
  618. }
  619. static void
  620. dm_atomic_state_clear(struct drm_atomic_state *state)
  621. {
  622. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  623. if (dm_state->context) {
  624. dc_release_state(dm_state->context);
  625. dm_state->context = NULL;
  626. }
  627. drm_atomic_state_default_clear(state);
  628. }
  629. static void
  630. dm_atomic_state_alloc_free(struct drm_atomic_state *state)
  631. {
  632. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  633. drm_atomic_state_default_release(state);
  634. kfree(dm_state);
  635. }
  636. static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
  637. .fb_create = amdgpu_display_user_framebuffer_create,
  638. .output_poll_changed = drm_fb_helper_output_poll_changed,
  639. .atomic_check = amdgpu_dm_atomic_check,
  640. .atomic_commit = amdgpu_dm_atomic_commit,
  641. .atomic_state_alloc = dm_atomic_state_alloc,
  642. .atomic_state_clear = dm_atomic_state_clear,
  643. .atomic_state_free = dm_atomic_state_alloc_free
  644. };
  645. static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
  646. .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
  647. };
  648. static void
  649. amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
  650. {
  651. struct drm_connector *connector = &aconnector->base;
  652. struct drm_device *dev = connector->dev;
  653. struct dc_sink *sink;
  654. /* MST handled by drm_mst framework */
  655. if (aconnector->mst_mgr.mst_state == true)
  656. return;
  657. sink = aconnector->dc_link->local_sink;
  658. /* Edid mgmt connector gets first update only in mode_valid hook and then
  659. * the connector sink is set to either fake or physical sink depends on link status.
  660. * don't do it here if u are during boot
  661. */
  662. if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
  663. && aconnector->dc_em_sink) {
  664. /* For S3 resume with headless use eml_sink to fake stream
  665. * because on resume connecotr->sink is set ti NULL
  666. */
  667. mutex_lock(&dev->mode_config.mutex);
  668. if (sink) {
  669. if (aconnector->dc_sink) {
  670. amdgpu_dm_remove_sink_from_freesync_module(
  671. connector);
  672. /* retain and release bellow are used for
  673. * bump up refcount for sink because the link don't point
  674. * to it anymore after disconnect so on next crtc to connector
  675. * reshuffle by UMD we will get into unwanted dc_sink release
  676. */
  677. if (aconnector->dc_sink != aconnector->dc_em_sink)
  678. dc_sink_release(aconnector->dc_sink);
  679. }
  680. aconnector->dc_sink = sink;
  681. amdgpu_dm_add_sink_to_freesync_module(
  682. connector, aconnector->edid);
  683. } else {
  684. amdgpu_dm_remove_sink_from_freesync_module(connector);
  685. if (!aconnector->dc_sink)
  686. aconnector->dc_sink = aconnector->dc_em_sink;
  687. else if (aconnector->dc_sink != aconnector->dc_em_sink)
  688. dc_sink_retain(aconnector->dc_sink);
  689. }
  690. mutex_unlock(&dev->mode_config.mutex);
  691. return;
  692. }
  693. /*
  694. * TODO: temporary guard to look for proper fix
  695. * if this sink is MST sink, we should not do anything
  696. */
  697. if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
  698. return;
  699. if (aconnector->dc_sink == sink) {
  700. /* We got a DP short pulse (Link Loss, DP CTS, etc...).
  701. * Do nothing!! */
  702. DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
  703. aconnector->connector_id);
  704. return;
  705. }
  706. DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
  707. aconnector->connector_id, aconnector->dc_sink, sink);
  708. mutex_lock(&dev->mode_config.mutex);
  709. /* 1. Update status of the drm connector
  710. * 2. Send an event and let userspace tell us what to do */
  711. if (sink) {
  712. /* TODO: check if we still need the S3 mode update workaround.
  713. * If yes, put it here. */
  714. if (aconnector->dc_sink)
  715. amdgpu_dm_remove_sink_from_freesync_module(
  716. connector);
  717. aconnector->dc_sink = sink;
  718. if (sink->dc_edid.length == 0) {
  719. aconnector->edid = NULL;
  720. } else {
  721. aconnector->edid =
  722. (struct edid *) sink->dc_edid.raw_edid;
  723. drm_mode_connector_update_edid_property(connector,
  724. aconnector->edid);
  725. }
  726. amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
  727. } else {
  728. amdgpu_dm_remove_sink_from_freesync_module(connector);
  729. drm_mode_connector_update_edid_property(connector, NULL);
  730. aconnector->num_modes = 0;
  731. aconnector->dc_sink = NULL;
  732. aconnector->edid = NULL;
  733. }
  734. mutex_unlock(&dev->mode_config.mutex);
  735. }
  736. static void handle_hpd_irq(void *param)
  737. {
  738. struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
  739. struct drm_connector *connector = &aconnector->base;
  740. struct drm_device *dev = connector->dev;
  741. /* In case of failure or MST no need to update connector status or notify the OS
  742. * since (for MST case) MST does this in it's own context.
  743. */
  744. mutex_lock(&aconnector->hpd_lock);
  745. if (aconnector->fake_enable)
  746. aconnector->fake_enable = false;
  747. if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
  748. amdgpu_dm_update_connector_after_detect(aconnector);
  749. drm_modeset_lock_all(dev);
  750. dm_restore_drm_connector_state(dev, connector);
  751. drm_modeset_unlock_all(dev);
  752. if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
  753. drm_kms_helper_hotplug_event(dev);
  754. }
  755. mutex_unlock(&aconnector->hpd_lock);
  756. }
  757. static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
  758. {
  759. uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
  760. uint8_t dret;
  761. bool new_irq_handled = false;
  762. int dpcd_addr;
  763. int dpcd_bytes_to_read;
  764. const int max_process_count = 30;
  765. int process_count = 0;
  766. const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
  767. if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
  768. dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
  769. /* DPCD 0x200 - 0x201 for downstream IRQ */
  770. dpcd_addr = DP_SINK_COUNT;
  771. } else {
  772. dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
  773. /* DPCD 0x2002 - 0x2005 for downstream IRQ */
  774. dpcd_addr = DP_SINK_COUNT_ESI;
  775. }
  776. dret = drm_dp_dpcd_read(
  777. &aconnector->dm_dp_aux.aux,
  778. dpcd_addr,
  779. esi,
  780. dpcd_bytes_to_read);
  781. while (dret == dpcd_bytes_to_read &&
  782. process_count < max_process_count) {
  783. uint8_t retry;
  784. dret = 0;
  785. process_count++;
  786. DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
  787. /* handle HPD short pulse irq */
  788. if (aconnector->mst_mgr.mst_state)
  789. drm_dp_mst_hpd_irq(
  790. &aconnector->mst_mgr,
  791. esi,
  792. &new_irq_handled);
  793. if (new_irq_handled) {
  794. /* ACK at DPCD to notify down stream */
  795. const int ack_dpcd_bytes_to_write =
  796. dpcd_bytes_to_read - 1;
  797. for (retry = 0; retry < 3; retry++) {
  798. uint8_t wret;
  799. wret = drm_dp_dpcd_write(
  800. &aconnector->dm_dp_aux.aux,
  801. dpcd_addr + 1,
  802. &esi[1],
  803. ack_dpcd_bytes_to_write);
  804. if (wret == ack_dpcd_bytes_to_write)
  805. break;
  806. }
  807. /* check if there is new irq to be handle */
  808. dret = drm_dp_dpcd_read(
  809. &aconnector->dm_dp_aux.aux,
  810. dpcd_addr,
  811. esi,
  812. dpcd_bytes_to_read);
  813. new_irq_handled = false;
  814. } else {
  815. break;
  816. }
  817. }
  818. if (process_count == max_process_count)
  819. DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
  820. }
  821. static void handle_hpd_rx_irq(void *param)
  822. {
  823. struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
  824. struct drm_connector *connector = &aconnector->base;
  825. struct drm_device *dev = connector->dev;
  826. struct dc_link *dc_link = aconnector->dc_link;
  827. bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
  828. /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
  829. * conflict, after implement i2c helper, this mutex should be
  830. * retired.
  831. */
  832. if (dc_link->type != dc_connection_mst_branch)
  833. mutex_lock(&aconnector->hpd_lock);
  834. if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
  835. !is_mst_root_connector) {
  836. /* Downstream Port status changed. */
  837. if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
  838. if (aconnector->fake_enable)
  839. aconnector->fake_enable = false;
  840. amdgpu_dm_update_connector_after_detect(aconnector);
  841. drm_modeset_lock_all(dev);
  842. dm_restore_drm_connector_state(dev, connector);
  843. drm_modeset_unlock_all(dev);
  844. drm_kms_helper_hotplug_event(dev);
  845. }
  846. }
  847. if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
  848. (dc_link->type == dc_connection_mst_branch))
  849. dm_handle_hpd_rx_irq(aconnector);
  850. if (dc_link->type != dc_connection_mst_branch)
  851. mutex_unlock(&aconnector->hpd_lock);
  852. }
  853. static void register_hpd_handlers(struct amdgpu_device *adev)
  854. {
  855. struct drm_device *dev = adev->ddev;
  856. struct drm_connector *connector;
  857. struct amdgpu_dm_connector *aconnector;
  858. const struct dc_link *dc_link;
  859. struct dc_interrupt_params int_params = {0};
  860. int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
  861. int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
  862. list_for_each_entry(connector,
  863. &dev->mode_config.connector_list, head) {
  864. aconnector = to_amdgpu_dm_connector(connector);
  865. dc_link = aconnector->dc_link;
  866. if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
  867. int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
  868. int_params.irq_source = dc_link->irq_source_hpd;
  869. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  870. handle_hpd_irq,
  871. (void *) aconnector);
  872. }
  873. if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
  874. /* Also register for DP short pulse (hpd_rx). */
  875. int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
  876. int_params.irq_source = dc_link->irq_source_hpd_rx;
  877. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  878. handle_hpd_rx_irq,
  879. (void *) aconnector);
  880. }
  881. }
  882. }
  883. /* Register IRQ sources and initialize IRQ callbacks */
  884. static int dce110_register_irq_handlers(struct amdgpu_device *adev)
  885. {
  886. struct dc *dc = adev->dm.dc;
  887. struct common_irq_params *c_irq_params;
  888. struct dc_interrupt_params int_params = {0};
  889. int r;
  890. int i;
  891. unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
  892. if (adev->asic_type == CHIP_VEGA10 ||
  893. adev->asic_type == CHIP_VEGA12 ||
  894. adev->asic_type == CHIP_VEGA20 ||
  895. adev->asic_type == CHIP_RAVEN)
  896. client_id = SOC15_IH_CLIENTID_DCE;
  897. int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
  898. int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
  899. /* Actions of amdgpu_irq_add_id():
  900. * 1. Register a set() function with base driver.
  901. * Base driver will call set() function to enable/disable an
  902. * interrupt in DC hardware.
  903. * 2. Register amdgpu_dm_irq_handler().
  904. * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
  905. * coming from DC hardware.
  906. * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
  907. * for acknowledging and handling. */
  908. /* Use VBLANK interrupt */
  909. for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
  910. r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
  911. if (r) {
  912. DRM_ERROR("Failed to add crtc irq id!\n");
  913. return r;
  914. }
  915. int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
  916. int_params.irq_source =
  917. dc_interrupt_to_irq_source(dc, i, 0);
  918. c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
  919. c_irq_params->adev = adev;
  920. c_irq_params->irq_src = int_params.irq_source;
  921. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  922. dm_crtc_high_irq, c_irq_params);
  923. }
  924. /* Use GRPH_PFLIP interrupt */
  925. for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
  926. i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
  927. r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
  928. if (r) {
  929. DRM_ERROR("Failed to add page flip irq id!\n");
  930. return r;
  931. }
  932. int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
  933. int_params.irq_source =
  934. dc_interrupt_to_irq_source(dc, i, 0);
  935. c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
  936. c_irq_params->adev = adev;
  937. c_irq_params->irq_src = int_params.irq_source;
  938. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  939. dm_pflip_high_irq, c_irq_params);
  940. }
  941. /* HPD */
  942. r = amdgpu_irq_add_id(adev, client_id,
  943. VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
  944. if (r) {
  945. DRM_ERROR("Failed to add hpd irq id!\n");
  946. return r;
  947. }
  948. register_hpd_handlers(adev);
  949. return 0;
  950. }
  951. #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  952. /* Register IRQ sources and initialize IRQ callbacks */
  953. static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
  954. {
  955. struct dc *dc = adev->dm.dc;
  956. struct common_irq_params *c_irq_params;
  957. struct dc_interrupt_params int_params = {0};
  958. int r;
  959. int i;
  960. int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
  961. int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
  962. /* Actions of amdgpu_irq_add_id():
  963. * 1. Register a set() function with base driver.
  964. * Base driver will call set() function to enable/disable an
  965. * interrupt in DC hardware.
  966. * 2. Register amdgpu_dm_irq_handler().
  967. * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
  968. * coming from DC hardware.
  969. * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
  970. * for acknowledging and handling.
  971. * */
  972. /* Use VSTARTUP interrupt */
  973. for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
  974. i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
  975. i++) {
  976. r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
  977. if (r) {
  978. DRM_ERROR("Failed to add crtc irq id!\n");
  979. return r;
  980. }
  981. int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
  982. int_params.irq_source =
  983. dc_interrupt_to_irq_source(dc, i, 0);
  984. c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
  985. c_irq_params->adev = adev;
  986. c_irq_params->irq_src = int_params.irq_source;
  987. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  988. dm_crtc_high_irq, c_irq_params);
  989. }
  990. /* Use GRPH_PFLIP interrupt */
  991. for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
  992. i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
  993. i++) {
  994. r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
  995. if (r) {
  996. DRM_ERROR("Failed to add page flip irq id!\n");
  997. return r;
  998. }
  999. int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
  1000. int_params.irq_source =
  1001. dc_interrupt_to_irq_source(dc, i, 0);
  1002. c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
  1003. c_irq_params->adev = adev;
  1004. c_irq_params->irq_src = int_params.irq_source;
  1005. amdgpu_dm_irq_register_interrupt(adev, &int_params,
  1006. dm_pflip_high_irq, c_irq_params);
  1007. }
  1008. /* HPD */
  1009. r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
  1010. &adev->hpd_irq);
  1011. if (r) {
  1012. DRM_ERROR("Failed to add hpd irq id!\n");
  1013. return r;
  1014. }
  1015. register_hpd_handlers(adev);
  1016. return 0;
  1017. }
  1018. #endif
  1019. static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
  1020. {
  1021. int r;
  1022. adev->mode_info.mode_config_initialized = true;
  1023. adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
  1024. adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
  1025. adev->ddev->mode_config.max_width = 16384;
  1026. adev->ddev->mode_config.max_height = 16384;
  1027. adev->ddev->mode_config.preferred_depth = 24;
  1028. adev->ddev->mode_config.prefer_shadow = 1;
  1029. /* indicate support of immediate flip */
  1030. adev->ddev->mode_config.async_page_flip = true;
  1031. adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
  1032. r = amdgpu_display_modeset_create_props(adev);
  1033. if (r)
  1034. return r;
  1035. return 0;
  1036. }
  1037. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
  1038. defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  1039. static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
  1040. {
  1041. struct amdgpu_display_manager *dm = bl_get_data(bd);
  1042. if (dc_link_set_backlight_level(dm->backlight_link,
  1043. bd->props.brightness, 0, 0))
  1044. return 0;
  1045. else
  1046. return 1;
  1047. }
  1048. static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
  1049. {
  1050. return bd->props.brightness;
  1051. }
  1052. static const struct backlight_ops amdgpu_dm_backlight_ops = {
  1053. .get_brightness = amdgpu_dm_backlight_get_brightness,
  1054. .update_status = amdgpu_dm_backlight_update_status,
  1055. };
  1056. static void
  1057. amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
  1058. {
  1059. char bl_name[16];
  1060. struct backlight_properties props = { 0 };
  1061. props.max_brightness = AMDGPU_MAX_BL_LEVEL;
  1062. props.type = BACKLIGHT_RAW;
  1063. snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
  1064. dm->adev->ddev->primary->index);
  1065. dm->backlight_dev = backlight_device_register(bl_name,
  1066. dm->adev->ddev->dev,
  1067. dm,
  1068. &amdgpu_dm_backlight_ops,
  1069. &props);
  1070. if (IS_ERR(dm->backlight_dev))
  1071. DRM_ERROR("DM: Backlight registration failed!\n");
  1072. else
  1073. DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
  1074. }
  1075. #endif
  1076. static int initialize_plane(struct amdgpu_display_manager *dm,
  1077. struct amdgpu_mode_info *mode_info,
  1078. int plane_id)
  1079. {
  1080. struct amdgpu_plane *plane;
  1081. unsigned long possible_crtcs;
  1082. int ret = 0;
  1083. plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
  1084. mode_info->planes[plane_id] = plane;
  1085. if (!plane) {
  1086. DRM_ERROR("KMS: Failed to allocate plane\n");
  1087. return -ENOMEM;
  1088. }
  1089. plane->base.type = mode_info->plane_type[plane_id];
  1090. /*
  1091. * HACK: IGT tests expect that each plane can only have one
  1092. * one possible CRTC. For now, set one CRTC for each
  1093. * plane that is not an underlay, but still allow multiple
  1094. * CRTCs for underlay planes.
  1095. */
  1096. possible_crtcs = 1 << plane_id;
  1097. if (plane_id >= dm->dc->caps.max_streams)
  1098. possible_crtcs = 0xff;
  1099. ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
  1100. if (ret) {
  1101. DRM_ERROR("KMS: Failed to initialize plane\n");
  1102. return ret;
  1103. }
  1104. return ret;
  1105. }
  1106. static void register_backlight_device(struct amdgpu_display_manager *dm,
  1107. struct dc_link *link)
  1108. {
  1109. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
  1110. defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  1111. if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
  1112. link->type != dc_connection_none) {
  1113. /* Event if registration failed, we should continue with
  1114. * DM initialization because not having a backlight control
  1115. * is better then a black screen.
  1116. */
  1117. amdgpu_dm_register_backlight_device(dm);
  1118. if (dm->backlight_dev)
  1119. dm->backlight_link = link;
  1120. }
  1121. #endif
  1122. }
  1123. /* In this architecture, the association
  1124. * connector -> encoder -> crtc
  1125. * id not really requried. The crtc and connector will hold the
  1126. * display_index as an abstraction to use with DAL component
  1127. *
  1128. * Returns 0 on success
  1129. */
  1130. static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
  1131. {
  1132. struct amdgpu_display_manager *dm = &adev->dm;
  1133. int32_t i;
  1134. struct amdgpu_dm_connector *aconnector = NULL;
  1135. struct amdgpu_encoder *aencoder = NULL;
  1136. struct amdgpu_mode_info *mode_info = &adev->mode_info;
  1137. uint32_t link_cnt;
  1138. int32_t total_overlay_planes, total_primary_planes;
  1139. link_cnt = dm->dc->caps.max_links;
  1140. if (amdgpu_dm_mode_config_init(dm->adev)) {
  1141. DRM_ERROR("DM: Failed to initialize mode config\n");
  1142. return -1;
  1143. }
  1144. /* Identify the number of planes to be initialized */
  1145. total_overlay_planes = dm->dc->caps.max_slave_planes;
  1146. total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
  1147. /* First initialize overlay planes, index starting after primary planes */
  1148. for (i = (total_overlay_planes - 1); i >= 0; i--) {
  1149. if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
  1150. DRM_ERROR("KMS: Failed to initialize overlay plane\n");
  1151. goto fail;
  1152. }
  1153. }
  1154. /* Initialize primary planes */
  1155. for (i = (total_primary_planes - 1); i >= 0; i--) {
  1156. if (initialize_plane(dm, mode_info, i)) {
  1157. DRM_ERROR("KMS: Failed to initialize primary plane\n");
  1158. goto fail;
  1159. }
  1160. }
  1161. for (i = 0; i < dm->dc->caps.max_streams; i++)
  1162. if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
  1163. DRM_ERROR("KMS: Failed to initialize crtc\n");
  1164. goto fail;
  1165. }
  1166. dm->display_indexes_num = dm->dc->caps.max_streams;
  1167. /* loops over all connectors on the board */
  1168. for (i = 0; i < link_cnt; i++) {
  1169. struct dc_link *link = NULL;
  1170. if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
  1171. DRM_ERROR(
  1172. "KMS: Cannot support more than %d display indexes\n",
  1173. AMDGPU_DM_MAX_DISPLAY_INDEX);
  1174. continue;
  1175. }
  1176. aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
  1177. if (!aconnector)
  1178. goto fail;
  1179. aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
  1180. if (!aencoder)
  1181. goto fail;
  1182. if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
  1183. DRM_ERROR("KMS: Failed to initialize encoder\n");
  1184. goto fail;
  1185. }
  1186. if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
  1187. DRM_ERROR("KMS: Failed to initialize connector\n");
  1188. goto fail;
  1189. }
  1190. link = dc_get_link_at_index(dm->dc, i);
  1191. if (dc_link_detect(link, DETECT_REASON_BOOT)) {
  1192. amdgpu_dm_update_connector_after_detect(aconnector);
  1193. register_backlight_device(dm, link);
  1194. }
  1195. }
  1196. /* Software is initialized. Now we can register interrupt handlers. */
  1197. switch (adev->asic_type) {
  1198. case CHIP_BONAIRE:
  1199. case CHIP_HAWAII:
  1200. case CHIP_KAVERI:
  1201. case CHIP_KABINI:
  1202. case CHIP_MULLINS:
  1203. case CHIP_TONGA:
  1204. case CHIP_FIJI:
  1205. case CHIP_CARRIZO:
  1206. case CHIP_STONEY:
  1207. case CHIP_POLARIS11:
  1208. case CHIP_POLARIS10:
  1209. case CHIP_POLARIS12:
  1210. case CHIP_VEGAM:
  1211. case CHIP_VEGA10:
  1212. case CHIP_VEGA12:
  1213. case CHIP_VEGA20:
  1214. if (dce110_register_irq_handlers(dm->adev)) {
  1215. DRM_ERROR("DM: Failed to initialize IRQ\n");
  1216. goto fail;
  1217. }
  1218. break;
  1219. #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  1220. case CHIP_RAVEN:
  1221. if (dcn10_register_irq_handlers(dm->adev)) {
  1222. DRM_ERROR("DM: Failed to initialize IRQ\n");
  1223. goto fail;
  1224. }
  1225. /*
  1226. * Temporary disable until pplib/smu interaction is implemented
  1227. */
  1228. dm->dc->debug.disable_stutter = true;
  1229. break;
  1230. #endif
  1231. default:
  1232. DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
  1233. goto fail;
  1234. }
  1235. return 0;
  1236. fail:
  1237. kfree(aencoder);
  1238. kfree(aconnector);
  1239. for (i = 0; i < dm->dc->caps.max_planes; i++)
  1240. kfree(mode_info->planes[i]);
  1241. return -1;
  1242. }
  1243. static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
  1244. {
  1245. drm_mode_config_cleanup(dm->ddev);
  1246. return;
  1247. }
  1248. /******************************************************************************
  1249. * amdgpu_display_funcs functions
  1250. *****************************************************************************/
  1251. /**
  1252. * dm_bandwidth_update - program display watermarks
  1253. *
  1254. * @adev: amdgpu_device pointer
  1255. *
  1256. * Calculate and program the display watermarks and line buffer allocation.
  1257. */
  1258. static void dm_bandwidth_update(struct amdgpu_device *adev)
  1259. {
  1260. /* TODO: implement later */
  1261. }
  1262. static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
  1263. u8 level)
  1264. {
  1265. /* TODO: translate amdgpu_encoder to display_index and call DAL */
  1266. }
  1267. static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
  1268. {
  1269. /* TODO: translate amdgpu_encoder to display_index and call DAL */
  1270. return 0;
  1271. }
  1272. static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
  1273. struct drm_file *filp)
  1274. {
  1275. struct mod_freesync_params freesync_params;
  1276. uint8_t num_streams;
  1277. uint8_t i;
  1278. struct amdgpu_device *adev = dev->dev_private;
  1279. int r = 0;
  1280. /* Get freesync enable flag from DRM */
  1281. num_streams = dc_get_current_stream_count(adev->dm.dc);
  1282. for (i = 0; i < num_streams; i++) {
  1283. struct dc_stream_state *stream;
  1284. stream = dc_get_stream_at_index(adev->dm.dc, i);
  1285. mod_freesync_update_state(adev->dm.freesync_module,
  1286. &stream, 1, &freesync_params);
  1287. }
  1288. return r;
  1289. }
  1290. static const struct amdgpu_display_funcs dm_display_funcs = {
  1291. .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
  1292. .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
  1293. .backlight_set_level =
  1294. dm_set_backlight_level,/* called unconditionally */
  1295. .backlight_get_level =
  1296. dm_get_backlight_level,/* called unconditionally */
  1297. .hpd_sense = NULL,/* called unconditionally */
  1298. .hpd_set_polarity = NULL, /* called unconditionally */
  1299. .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
  1300. .page_flip_get_scanoutpos =
  1301. dm_crtc_get_scanoutpos,/* called unconditionally */
  1302. .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
  1303. .add_connector = NULL, /* VBIOS parsing. DAL does it. */
  1304. .notify_freesync = amdgpu_notify_freesync,
  1305. };
  1306. #if defined(CONFIG_DEBUG_KERNEL_DC)
  1307. static ssize_t s3_debug_store(struct device *device,
  1308. struct device_attribute *attr,
  1309. const char *buf,
  1310. size_t count)
  1311. {
  1312. int ret;
  1313. int s3_state;
  1314. struct pci_dev *pdev = to_pci_dev(device);
  1315. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  1316. struct amdgpu_device *adev = drm_dev->dev_private;
  1317. ret = kstrtoint(buf, 0, &s3_state);
  1318. if (ret == 0) {
  1319. if (s3_state) {
  1320. dm_resume(adev);
  1321. drm_kms_helper_hotplug_event(adev->ddev);
  1322. } else
  1323. dm_suspend(adev);
  1324. }
  1325. return ret == 0 ? count : 0;
  1326. }
  1327. DEVICE_ATTR_WO(s3_debug);
  1328. #endif
  1329. static int dm_early_init(void *handle)
  1330. {
  1331. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1332. switch (adev->asic_type) {
  1333. case CHIP_BONAIRE:
  1334. case CHIP_HAWAII:
  1335. adev->mode_info.num_crtc = 6;
  1336. adev->mode_info.num_hpd = 6;
  1337. adev->mode_info.num_dig = 6;
  1338. adev->mode_info.plane_type = dm_plane_type_default;
  1339. break;
  1340. case CHIP_KAVERI:
  1341. adev->mode_info.num_crtc = 4;
  1342. adev->mode_info.num_hpd = 6;
  1343. adev->mode_info.num_dig = 7;
  1344. adev->mode_info.plane_type = dm_plane_type_default;
  1345. break;
  1346. case CHIP_KABINI:
  1347. case CHIP_MULLINS:
  1348. adev->mode_info.num_crtc = 2;
  1349. adev->mode_info.num_hpd = 6;
  1350. adev->mode_info.num_dig = 6;
  1351. adev->mode_info.plane_type = dm_plane_type_default;
  1352. break;
  1353. case CHIP_FIJI:
  1354. case CHIP_TONGA:
  1355. adev->mode_info.num_crtc = 6;
  1356. adev->mode_info.num_hpd = 6;
  1357. adev->mode_info.num_dig = 7;
  1358. adev->mode_info.plane_type = dm_plane_type_default;
  1359. break;
  1360. case CHIP_CARRIZO:
  1361. adev->mode_info.num_crtc = 3;
  1362. adev->mode_info.num_hpd = 6;
  1363. adev->mode_info.num_dig = 9;
  1364. adev->mode_info.plane_type = dm_plane_type_carizzo;
  1365. break;
  1366. case CHIP_STONEY:
  1367. adev->mode_info.num_crtc = 2;
  1368. adev->mode_info.num_hpd = 6;
  1369. adev->mode_info.num_dig = 9;
  1370. adev->mode_info.plane_type = dm_plane_type_stoney;
  1371. break;
  1372. case CHIP_POLARIS11:
  1373. case CHIP_POLARIS12:
  1374. adev->mode_info.num_crtc = 5;
  1375. adev->mode_info.num_hpd = 5;
  1376. adev->mode_info.num_dig = 5;
  1377. adev->mode_info.plane_type = dm_plane_type_default;
  1378. break;
  1379. case CHIP_POLARIS10:
  1380. case CHIP_VEGAM:
  1381. adev->mode_info.num_crtc = 6;
  1382. adev->mode_info.num_hpd = 6;
  1383. adev->mode_info.num_dig = 6;
  1384. adev->mode_info.plane_type = dm_plane_type_default;
  1385. break;
  1386. case CHIP_VEGA10:
  1387. case CHIP_VEGA12:
  1388. case CHIP_VEGA20:
  1389. adev->mode_info.num_crtc = 6;
  1390. adev->mode_info.num_hpd = 6;
  1391. adev->mode_info.num_dig = 6;
  1392. adev->mode_info.plane_type = dm_plane_type_default;
  1393. break;
  1394. #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  1395. case CHIP_RAVEN:
  1396. adev->mode_info.num_crtc = 4;
  1397. adev->mode_info.num_hpd = 4;
  1398. adev->mode_info.num_dig = 4;
  1399. adev->mode_info.plane_type = dm_plane_type_default;
  1400. break;
  1401. #endif
  1402. default:
  1403. DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
  1404. return -EINVAL;
  1405. }
  1406. amdgpu_dm_set_irq_funcs(adev);
  1407. if (adev->mode_info.funcs == NULL)
  1408. adev->mode_info.funcs = &dm_display_funcs;
  1409. /* Note: Do NOT change adev->audio_endpt_rreg and
  1410. * adev->audio_endpt_wreg because they are initialised in
  1411. * amdgpu_device_init() */
  1412. #if defined(CONFIG_DEBUG_KERNEL_DC)
  1413. device_create_file(
  1414. adev->ddev->dev,
  1415. &dev_attr_s3_debug);
  1416. #endif
  1417. return 0;
  1418. }
  1419. static bool modeset_required(struct drm_crtc_state *crtc_state,
  1420. struct dc_stream_state *new_stream,
  1421. struct dc_stream_state *old_stream)
  1422. {
  1423. if (!drm_atomic_crtc_needs_modeset(crtc_state))
  1424. return false;
  1425. if (!crtc_state->enable)
  1426. return false;
  1427. return crtc_state->active;
  1428. }
  1429. static bool modereset_required(struct drm_crtc_state *crtc_state)
  1430. {
  1431. if (!drm_atomic_crtc_needs_modeset(crtc_state))
  1432. return false;
  1433. return !crtc_state->enable || !crtc_state->active;
  1434. }
  1435. static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
  1436. {
  1437. drm_encoder_cleanup(encoder);
  1438. kfree(encoder);
  1439. }
  1440. static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
  1441. .destroy = amdgpu_dm_encoder_destroy,
  1442. };
  1443. static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
  1444. struct dc_plane_state *plane_state)
  1445. {
  1446. plane_state->src_rect.x = state->src_x >> 16;
  1447. plane_state->src_rect.y = state->src_y >> 16;
  1448. /*we ignore for now mantissa and do not to deal with floating pixels :(*/
  1449. plane_state->src_rect.width = state->src_w >> 16;
  1450. if (plane_state->src_rect.width == 0)
  1451. return false;
  1452. plane_state->src_rect.height = state->src_h >> 16;
  1453. if (plane_state->src_rect.height == 0)
  1454. return false;
  1455. plane_state->dst_rect.x = state->crtc_x;
  1456. plane_state->dst_rect.y = state->crtc_y;
  1457. if (state->crtc_w == 0)
  1458. return false;
  1459. plane_state->dst_rect.width = state->crtc_w;
  1460. if (state->crtc_h == 0)
  1461. return false;
  1462. plane_state->dst_rect.height = state->crtc_h;
  1463. plane_state->clip_rect = plane_state->dst_rect;
  1464. switch (state->rotation & DRM_MODE_ROTATE_MASK) {
  1465. case DRM_MODE_ROTATE_0:
  1466. plane_state->rotation = ROTATION_ANGLE_0;
  1467. break;
  1468. case DRM_MODE_ROTATE_90:
  1469. plane_state->rotation = ROTATION_ANGLE_90;
  1470. break;
  1471. case DRM_MODE_ROTATE_180:
  1472. plane_state->rotation = ROTATION_ANGLE_180;
  1473. break;
  1474. case DRM_MODE_ROTATE_270:
  1475. plane_state->rotation = ROTATION_ANGLE_270;
  1476. break;
  1477. default:
  1478. plane_state->rotation = ROTATION_ANGLE_0;
  1479. break;
  1480. }
  1481. return true;
  1482. }
  1483. static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
  1484. uint64_t *tiling_flags)
  1485. {
  1486. struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
  1487. int r = amdgpu_bo_reserve(rbo, false);
  1488. if (unlikely(r)) {
  1489. // Don't show error msg. when return -ERESTARTSYS
  1490. if (r != -ERESTARTSYS)
  1491. DRM_ERROR("Unable to reserve buffer: %d\n", r);
  1492. return r;
  1493. }
  1494. if (tiling_flags)
  1495. amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
  1496. amdgpu_bo_unreserve(rbo);
  1497. return r;
  1498. }
  1499. static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
  1500. struct dc_plane_state *plane_state,
  1501. const struct amdgpu_framebuffer *amdgpu_fb)
  1502. {
  1503. uint64_t tiling_flags;
  1504. unsigned int awidth;
  1505. const struct drm_framebuffer *fb = &amdgpu_fb->base;
  1506. int ret = 0;
  1507. struct drm_format_name_buf format_name;
  1508. ret = get_fb_info(
  1509. amdgpu_fb,
  1510. &tiling_flags);
  1511. if (ret)
  1512. return ret;
  1513. switch (fb->format->format) {
  1514. case DRM_FORMAT_C8:
  1515. plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
  1516. break;
  1517. case DRM_FORMAT_RGB565:
  1518. plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
  1519. break;
  1520. case DRM_FORMAT_XRGB8888:
  1521. case DRM_FORMAT_ARGB8888:
  1522. plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
  1523. break;
  1524. case DRM_FORMAT_XRGB2101010:
  1525. case DRM_FORMAT_ARGB2101010:
  1526. plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
  1527. break;
  1528. case DRM_FORMAT_XBGR2101010:
  1529. case DRM_FORMAT_ABGR2101010:
  1530. plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
  1531. break;
  1532. case DRM_FORMAT_NV21:
  1533. plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
  1534. break;
  1535. case DRM_FORMAT_NV12:
  1536. plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
  1537. break;
  1538. default:
  1539. DRM_ERROR("Unsupported screen format %s\n",
  1540. drm_get_format_name(fb->format->format, &format_name));
  1541. return -EINVAL;
  1542. }
  1543. if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
  1544. plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
  1545. plane_state->plane_size.grph.surface_size.x = 0;
  1546. plane_state->plane_size.grph.surface_size.y = 0;
  1547. plane_state->plane_size.grph.surface_size.width = fb->width;
  1548. plane_state->plane_size.grph.surface_size.height = fb->height;
  1549. plane_state->plane_size.grph.surface_pitch =
  1550. fb->pitches[0] / fb->format->cpp[0];
  1551. /* TODO: unhardcode */
  1552. plane_state->color_space = COLOR_SPACE_SRGB;
  1553. } else {
  1554. awidth = ALIGN(fb->width, 64);
  1555. plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
  1556. plane_state->plane_size.video.luma_size.x = 0;
  1557. plane_state->plane_size.video.luma_size.y = 0;
  1558. plane_state->plane_size.video.luma_size.width = awidth;
  1559. plane_state->plane_size.video.luma_size.height = fb->height;
  1560. /* TODO: unhardcode */
  1561. plane_state->plane_size.video.luma_pitch = awidth;
  1562. plane_state->plane_size.video.chroma_size.x = 0;
  1563. plane_state->plane_size.video.chroma_size.y = 0;
  1564. plane_state->plane_size.video.chroma_size.width = awidth;
  1565. plane_state->plane_size.video.chroma_size.height = fb->height;
  1566. plane_state->plane_size.video.chroma_pitch = awidth / 2;
  1567. /* TODO: unhardcode */
  1568. plane_state->color_space = COLOR_SPACE_YCBCR709;
  1569. }
  1570. memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
  1571. /* Fill GFX8 params */
  1572. if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
  1573. unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
  1574. bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
  1575. bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
  1576. mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
  1577. tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
  1578. num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
  1579. /* XXX fix me for VI */
  1580. plane_state->tiling_info.gfx8.num_banks = num_banks;
  1581. plane_state->tiling_info.gfx8.array_mode =
  1582. DC_ARRAY_2D_TILED_THIN1;
  1583. plane_state->tiling_info.gfx8.tile_split = tile_split;
  1584. plane_state->tiling_info.gfx8.bank_width = bankw;
  1585. plane_state->tiling_info.gfx8.bank_height = bankh;
  1586. plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
  1587. plane_state->tiling_info.gfx8.tile_mode =
  1588. DC_ADDR_SURF_MICRO_TILING_DISPLAY;
  1589. } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
  1590. == DC_ARRAY_1D_TILED_THIN1) {
  1591. plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
  1592. }
  1593. plane_state->tiling_info.gfx8.pipe_config =
  1594. AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
  1595. if (adev->asic_type == CHIP_VEGA10 ||
  1596. adev->asic_type == CHIP_VEGA12 ||
  1597. adev->asic_type == CHIP_VEGA20 ||
  1598. adev->asic_type == CHIP_RAVEN) {
  1599. /* Fill GFX9 params */
  1600. plane_state->tiling_info.gfx9.num_pipes =
  1601. adev->gfx.config.gb_addr_config_fields.num_pipes;
  1602. plane_state->tiling_info.gfx9.num_banks =
  1603. adev->gfx.config.gb_addr_config_fields.num_banks;
  1604. plane_state->tiling_info.gfx9.pipe_interleave =
  1605. adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
  1606. plane_state->tiling_info.gfx9.num_shader_engines =
  1607. adev->gfx.config.gb_addr_config_fields.num_se;
  1608. plane_state->tiling_info.gfx9.max_compressed_frags =
  1609. adev->gfx.config.gb_addr_config_fields.max_compress_frags;
  1610. plane_state->tiling_info.gfx9.num_rb_per_se =
  1611. adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
  1612. plane_state->tiling_info.gfx9.swizzle =
  1613. AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
  1614. plane_state->tiling_info.gfx9.shaderEnable = 1;
  1615. }
  1616. plane_state->visible = true;
  1617. plane_state->scaling_quality.h_taps_c = 0;
  1618. plane_state->scaling_quality.v_taps_c = 0;
  1619. /* is this needed? is plane_state zeroed at allocation? */
  1620. plane_state->scaling_quality.h_taps = 0;
  1621. plane_state->scaling_quality.v_taps = 0;
  1622. plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
  1623. return ret;
  1624. }
  1625. static int fill_plane_attributes(struct amdgpu_device *adev,
  1626. struct dc_plane_state *dc_plane_state,
  1627. struct drm_plane_state *plane_state,
  1628. struct drm_crtc_state *crtc_state)
  1629. {
  1630. const struct amdgpu_framebuffer *amdgpu_fb =
  1631. to_amdgpu_framebuffer(plane_state->fb);
  1632. const struct drm_crtc *crtc = plane_state->crtc;
  1633. int ret = 0;
  1634. if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
  1635. return -EINVAL;
  1636. ret = fill_plane_attributes_from_fb(
  1637. crtc->dev->dev_private,
  1638. dc_plane_state,
  1639. amdgpu_fb);
  1640. if (ret)
  1641. return ret;
  1642. /*
  1643. * Always set input transfer function, since plane state is refreshed
  1644. * every time.
  1645. */
  1646. ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
  1647. if (ret) {
  1648. dc_transfer_func_release(dc_plane_state->in_transfer_func);
  1649. dc_plane_state->in_transfer_func = NULL;
  1650. }
  1651. return ret;
  1652. }
  1653. /*****************************************************************************/
  1654. static void update_stream_scaling_settings(const struct drm_display_mode *mode,
  1655. const struct dm_connector_state *dm_state,
  1656. struct dc_stream_state *stream)
  1657. {
  1658. enum amdgpu_rmx_type rmx_type;
  1659. struct rect src = { 0 }; /* viewport in composition space*/
  1660. struct rect dst = { 0 }; /* stream addressable area */
  1661. /* no mode. nothing to be done */
  1662. if (!mode)
  1663. return;
  1664. /* Full screen scaling by default */
  1665. src.width = mode->hdisplay;
  1666. src.height = mode->vdisplay;
  1667. dst.width = stream->timing.h_addressable;
  1668. dst.height = stream->timing.v_addressable;
  1669. if (dm_state) {
  1670. rmx_type = dm_state->scaling;
  1671. if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
  1672. if (src.width * dst.height <
  1673. src.height * dst.width) {
  1674. /* height needs less upscaling/more downscaling */
  1675. dst.width = src.width *
  1676. dst.height / src.height;
  1677. } else {
  1678. /* width needs less upscaling/more downscaling */
  1679. dst.height = src.height *
  1680. dst.width / src.width;
  1681. }
  1682. } else if (rmx_type == RMX_CENTER) {
  1683. dst = src;
  1684. }
  1685. dst.x = (stream->timing.h_addressable - dst.width) / 2;
  1686. dst.y = (stream->timing.v_addressable - dst.height) / 2;
  1687. if (dm_state->underscan_enable) {
  1688. dst.x += dm_state->underscan_hborder / 2;
  1689. dst.y += dm_state->underscan_vborder / 2;
  1690. dst.width -= dm_state->underscan_hborder;
  1691. dst.height -= dm_state->underscan_vborder;
  1692. }
  1693. }
  1694. stream->src = src;
  1695. stream->dst = dst;
  1696. DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
  1697. dst.x, dst.y, dst.width, dst.height);
  1698. }
  1699. static enum dc_color_depth
  1700. convert_color_depth_from_display_info(const struct drm_connector *connector)
  1701. {
  1702. uint32_t bpc = connector->display_info.bpc;
  1703. switch (bpc) {
  1704. case 0:
  1705. /* Temporary Work around, DRM don't parse color depth for
  1706. * EDID revision before 1.4
  1707. * TODO: Fix edid parsing
  1708. */
  1709. return COLOR_DEPTH_888;
  1710. case 6:
  1711. return COLOR_DEPTH_666;
  1712. case 8:
  1713. return COLOR_DEPTH_888;
  1714. case 10:
  1715. return COLOR_DEPTH_101010;
  1716. case 12:
  1717. return COLOR_DEPTH_121212;
  1718. case 14:
  1719. return COLOR_DEPTH_141414;
  1720. case 16:
  1721. return COLOR_DEPTH_161616;
  1722. default:
  1723. return COLOR_DEPTH_UNDEFINED;
  1724. }
  1725. }
  1726. static enum dc_aspect_ratio
  1727. get_aspect_ratio(const struct drm_display_mode *mode_in)
  1728. {
  1729. int32_t width = mode_in->crtc_hdisplay * 9;
  1730. int32_t height = mode_in->crtc_vdisplay * 16;
  1731. if ((width - height) < 10 && (width - height) > -10)
  1732. return ASPECT_RATIO_16_9;
  1733. else
  1734. return ASPECT_RATIO_4_3;
  1735. }
  1736. static enum dc_color_space
  1737. get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
  1738. {
  1739. enum dc_color_space color_space = COLOR_SPACE_SRGB;
  1740. switch (dc_crtc_timing->pixel_encoding) {
  1741. case PIXEL_ENCODING_YCBCR422:
  1742. case PIXEL_ENCODING_YCBCR444:
  1743. case PIXEL_ENCODING_YCBCR420:
  1744. {
  1745. /*
  1746. * 27030khz is the separation point between HDTV and SDTV
  1747. * according to HDMI spec, we use YCbCr709 and YCbCr601
  1748. * respectively
  1749. */
  1750. if (dc_crtc_timing->pix_clk_khz > 27030) {
  1751. if (dc_crtc_timing->flags.Y_ONLY)
  1752. color_space =
  1753. COLOR_SPACE_YCBCR709_LIMITED;
  1754. else
  1755. color_space = COLOR_SPACE_YCBCR709;
  1756. } else {
  1757. if (dc_crtc_timing->flags.Y_ONLY)
  1758. color_space =
  1759. COLOR_SPACE_YCBCR601_LIMITED;
  1760. else
  1761. color_space = COLOR_SPACE_YCBCR601;
  1762. }
  1763. }
  1764. break;
  1765. case PIXEL_ENCODING_RGB:
  1766. color_space = COLOR_SPACE_SRGB;
  1767. break;
  1768. default:
  1769. WARN_ON(1);
  1770. break;
  1771. }
  1772. return color_space;
  1773. }
  1774. /*****************************************************************************/
  1775. static void
  1776. fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
  1777. const struct drm_display_mode *mode_in,
  1778. const struct drm_connector *connector)
  1779. {
  1780. struct dc_crtc_timing *timing_out = &stream->timing;
  1781. memset(timing_out, 0, sizeof(struct dc_crtc_timing));
  1782. timing_out->h_border_left = 0;
  1783. timing_out->h_border_right = 0;
  1784. timing_out->v_border_top = 0;
  1785. timing_out->v_border_bottom = 0;
  1786. /* TODO: un-hardcode */
  1787. if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
  1788. && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
  1789. timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
  1790. else
  1791. timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
  1792. timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
  1793. timing_out->display_color_depth = convert_color_depth_from_display_info(
  1794. connector);
  1795. timing_out->scan_type = SCANNING_TYPE_NODATA;
  1796. timing_out->hdmi_vic = 0;
  1797. timing_out->vic = drm_match_cea_mode(mode_in);
  1798. timing_out->h_addressable = mode_in->crtc_hdisplay;
  1799. timing_out->h_total = mode_in->crtc_htotal;
  1800. timing_out->h_sync_width =
  1801. mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
  1802. timing_out->h_front_porch =
  1803. mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
  1804. timing_out->v_total = mode_in->crtc_vtotal;
  1805. timing_out->v_addressable = mode_in->crtc_vdisplay;
  1806. timing_out->v_front_porch =
  1807. mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
  1808. timing_out->v_sync_width =
  1809. mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
  1810. timing_out->pix_clk_khz = mode_in->crtc_clock;
  1811. timing_out->aspect_ratio = get_aspect_ratio(mode_in);
  1812. if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
  1813. timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
  1814. if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
  1815. timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
  1816. stream->output_color_space = get_output_color_space(timing_out);
  1817. stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
  1818. stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
  1819. }
  1820. static void fill_audio_info(struct audio_info *audio_info,
  1821. const struct drm_connector *drm_connector,
  1822. const struct dc_sink *dc_sink)
  1823. {
  1824. int i = 0;
  1825. int cea_revision = 0;
  1826. const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
  1827. audio_info->manufacture_id = edid_caps->manufacturer_id;
  1828. audio_info->product_id = edid_caps->product_id;
  1829. cea_revision = drm_connector->display_info.cea_rev;
  1830. strncpy(audio_info->display_name,
  1831. edid_caps->display_name,
  1832. AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
  1833. if (cea_revision >= 3) {
  1834. audio_info->mode_count = edid_caps->audio_mode_count;
  1835. for (i = 0; i < audio_info->mode_count; ++i) {
  1836. audio_info->modes[i].format_code =
  1837. (enum audio_format_code)
  1838. (edid_caps->audio_modes[i].format_code);
  1839. audio_info->modes[i].channel_count =
  1840. edid_caps->audio_modes[i].channel_count;
  1841. audio_info->modes[i].sample_rates.all =
  1842. edid_caps->audio_modes[i].sample_rate;
  1843. audio_info->modes[i].sample_size =
  1844. edid_caps->audio_modes[i].sample_size;
  1845. }
  1846. }
  1847. audio_info->flags.all = edid_caps->speaker_flags;
  1848. /* TODO: We only check for the progressive mode, check for interlace mode too */
  1849. if (drm_connector->latency_present[0]) {
  1850. audio_info->video_latency = drm_connector->video_latency[0];
  1851. audio_info->audio_latency = drm_connector->audio_latency[0];
  1852. }
  1853. /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
  1854. }
  1855. static void
  1856. copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
  1857. struct drm_display_mode *dst_mode)
  1858. {
  1859. dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
  1860. dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
  1861. dst_mode->crtc_clock = src_mode->crtc_clock;
  1862. dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
  1863. dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
  1864. dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
  1865. dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
  1866. dst_mode->crtc_htotal = src_mode->crtc_htotal;
  1867. dst_mode->crtc_hskew = src_mode->crtc_hskew;
  1868. dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
  1869. dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
  1870. dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
  1871. dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
  1872. dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
  1873. }
  1874. static void
  1875. decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
  1876. const struct drm_display_mode *native_mode,
  1877. bool scale_enabled)
  1878. {
  1879. if (scale_enabled) {
  1880. copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
  1881. } else if (native_mode->clock == drm_mode->clock &&
  1882. native_mode->htotal == drm_mode->htotal &&
  1883. native_mode->vtotal == drm_mode->vtotal) {
  1884. copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
  1885. } else {
  1886. /* no scaling nor amdgpu inserted, no need to patch */
  1887. }
  1888. }
  1889. static struct dc_sink *
  1890. create_fake_sink(struct amdgpu_dm_connector *aconnector)
  1891. {
  1892. struct dc_sink_init_data sink_init_data = { 0 };
  1893. struct dc_sink *sink = NULL;
  1894. sink_init_data.link = aconnector->dc_link;
  1895. sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
  1896. sink = dc_sink_create(&sink_init_data);
  1897. if (!sink) {
  1898. DRM_ERROR("Failed to create sink!\n");
  1899. return NULL;
  1900. }
  1901. sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
  1902. return sink;
  1903. }
  1904. static void set_multisync_trigger_params(
  1905. struct dc_stream_state *stream)
  1906. {
  1907. if (stream->triggered_crtc_reset.enabled) {
  1908. stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
  1909. stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
  1910. }
  1911. }
  1912. static void set_master_stream(struct dc_stream_state *stream_set[],
  1913. int stream_count)
  1914. {
  1915. int j, highest_rfr = 0, master_stream = 0;
  1916. for (j = 0; j < stream_count; j++) {
  1917. if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
  1918. int refresh_rate = 0;
  1919. refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
  1920. (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
  1921. if (refresh_rate > highest_rfr) {
  1922. highest_rfr = refresh_rate;
  1923. master_stream = j;
  1924. }
  1925. }
  1926. }
  1927. for (j = 0; j < stream_count; j++) {
  1928. if (stream_set[j])
  1929. stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
  1930. }
  1931. }
  1932. static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
  1933. {
  1934. int i = 0;
  1935. if (context->stream_count < 2)
  1936. return;
  1937. for (i = 0; i < context->stream_count ; i++) {
  1938. if (!context->streams[i])
  1939. continue;
  1940. /* TODO: add a function to read AMD VSDB bits and will set
  1941. * crtc_sync_master.multi_sync_enabled flag
  1942. * For now its set to false
  1943. */
  1944. set_multisync_trigger_params(context->streams[i]);
  1945. }
  1946. set_master_stream(context->streams, context->stream_count);
  1947. }
  1948. static struct dc_stream_state *
  1949. create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
  1950. const struct drm_display_mode *drm_mode,
  1951. const struct dm_connector_state *dm_state)
  1952. {
  1953. struct drm_display_mode *preferred_mode = NULL;
  1954. struct drm_connector *drm_connector;
  1955. struct dc_stream_state *stream = NULL;
  1956. struct drm_display_mode mode = *drm_mode;
  1957. bool native_mode_found = false;
  1958. struct dc_sink *sink = NULL;
  1959. if (aconnector == NULL) {
  1960. DRM_ERROR("aconnector is NULL!\n");
  1961. return stream;
  1962. }
  1963. drm_connector = &aconnector->base;
  1964. if (!aconnector->dc_sink) {
  1965. /*
  1966. * Create dc_sink when necessary to MST
  1967. * Don't apply fake_sink to MST
  1968. */
  1969. if (aconnector->mst_port) {
  1970. dm_dp_mst_dc_sink_create(drm_connector);
  1971. return stream;
  1972. }
  1973. sink = create_fake_sink(aconnector);
  1974. if (!sink)
  1975. return stream;
  1976. } else {
  1977. sink = aconnector->dc_sink;
  1978. }
  1979. stream = dc_create_stream_for_sink(sink);
  1980. if (stream == NULL) {
  1981. DRM_ERROR("Failed to create stream for sink!\n");
  1982. goto finish;
  1983. }
  1984. list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
  1985. /* Search for preferred mode */
  1986. if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
  1987. native_mode_found = true;
  1988. break;
  1989. }
  1990. }
  1991. if (!native_mode_found)
  1992. preferred_mode = list_first_entry_or_null(
  1993. &aconnector->base.modes,
  1994. struct drm_display_mode,
  1995. head);
  1996. if (preferred_mode == NULL) {
  1997. /* This may not be an error, the use case is when we we have no
  1998. * usermode calls to reset and set mode upon hotplug. In this
  1999. * case, we call set mode ourselves to restore the previous mode
  2000. * and the modelist may not be filled in in time.
  2001. */
  2002. DRM_DEBUG_DRIVER("No preferred mode found\n");
  2003. } else {
  2004. decide_crtc_timing_for_drm_display_mode(
  2005. &mode, preferred_mode,
  2006. dm_state ? (dm_state->scaling != RMX_OFF) : false);
  2007. }
  2008. if (!dm_state)
  2009. drm_mode_set_crtcinfo(&mode, 0);
  2010. fill_stream_properties_from_drm_display_mode(stream,
  2011. &mode, &aconnector->base);
  2012. update_stream_scaling_settings(&mode, dm_state, stream);
  2013. fill_audio_info(
  2014. &stream->audio_info,
  2015. drm_connector,
  2016. sink);
  2017. update_stream_signal(stream);
  2018. if (dm_state && dm_state->freesync_capable)
  2019. stream->ignore_msa_timing_param = true;
  2020. finish:
  2021. if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
  2022. dc_sink_release(sink);
  2023. return stream;
  2024. }
  2025. static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
  2026. {
  2027. drm_crtc_cleanup(crtc);
  2028. kfree(crtc);
  2029. }
  2030. static void dm_crtc_destroy_state(struct drm_crtc *crtc,
  2031. struct drm_crtc_state *state)
  2032. {
  2033. struct dm_crtc_state *cur = to_dm_crtc_state(state);
  2034. /* TODO Destroy dc_stream objects are stream object is flattened */
  2035. if (cur->stream)
  2036. dc_stream_release(cur->stream);
  2037. __drm_atomic_helper_crtc_destroy_state(state);
  2038. kfree(state);
  2039. }
  2040. static void dm_crtc_reset_state(struct drm_crtc *crtc)
  2041. {
  2042. struct dm_crtc_state *state;
  2043. if (crtc->state)
  2044. dm_crtc_destroy_state(crtc, crtc->state);
  2045. state = kzalloc(sizeof(*state), GFP_KERNEL);
  2046. if (WARN_ON(!state))
  2047. return;
  2048. crtc->state = &state->base;
  2049. crtc->state->crtc = crtc;
  2050. }
  2051. static struct drm_crtc_state *
  2052. dm_crtc_duplicate_state(struct drm_crtc *crtc)
  2053. {
  2054. struct dm_crtc_state *state, *cur;
  2055. cur = to_dm_crtc_state(crtc->state);
  2056. if (WARN_ON(!crtc->state))
  2057. return NULL;
  2058. state = kzalloc(sizeof(*state), GFP_KERNEL);
  2059. if (!state)
  2060. return NULL;
  2061. __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
  2062. if (cur->stream) {
  2063. state->stream = cur->stream;
  2064. dc_stream_retain(state->stream);
  2065. }
  2066. /* TODO Duplicate dc_stream after objects are stream object is flattened */
  2067. return &state->base;
  2068. }
  2069. static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
  2070. {
  2071. enum dc_irq_source irq_source;
  2072. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  2073. struct amdgpu_device *adev = crtc->dev->dev_private;
  2074. irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
  2075. return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
  2076. }
  2077. static int dm_enable_vblank(struct drm_crtc *crtc)
  2078. {
  2079. return dm_set_vblank(crtc, true);
  2080. }
  2081. static void dm_disable_vblank(struct drm_crtc *crtc)
  2082. {
  2083. dm_set_vblank(crtc, false);
  2084. }
  2085. /* Implemented only the options currently availible for the driver */
  2086. static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
  2087. .reset = dm_crtc_reset_state,
  2088. .destroy = amdgpu_dm_crtc_destroy,
  2089. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  2090. .set_config = drm_atomic_helper_set_config,
  2091. .page_flip = drm_atomic_helper_page_flip,
  2092. .atomic_duplicate_state = dm_crtc_duplicate_state,
  2093. .atomic_destroy_state = dm_crtc_destroy_state,
  2094. .set_crc_source = amdgpu_dm_crtc_set_crc_source,
  2095. .enable_vblank = dm_enable_vblank,
  2096. .disable_vblank = dm_disable_vblank,
  2097. };
  2098. static enum drm_connector_status
  2099. amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
  2100. {
  2101. bool connected;
  2102. struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  2103. /* Notes:
  2104. * 1. This interface is NOT called in context of HPD irq.
  2105. * 2. This interface *is called* in context of user-mode ioctl. Which
  2106. * makes it a bad place for *any* MST-related activit. */
  2107. if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
  2108. !aconnector->fake_enable)
  2109. connected = (aconnector->dc_sink != NULL);
  2110. else
  2111. connected = (aconnector->base.force == DRM_FORCE_ON);
  2112. return (connected ? connector_status_connected :
  2113. connector_status_disconnected);
  2114. }
  2115. int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
  2116. struct drm_connector_state *connector_state,
  2117. struct drm_property *property,
  2118. uint64_t val)
  2119. {
  2120. struct drm_device *dev = connector->dev;
  2121. struct amdgpu_device *adev = dev->dev_private;
  2122. struct dm_connector_state *dm_old_state =
  2123. to_dm_connector_state(connector->state);
  2124. struct dm_connector_state *dm_new_state =
  2125. to_dm_connector_state(connector_state);
  2126. int ret = -EINVAL;
  2127. if (property == dev->mode_config.scaling_mode_property) {
  2128. enum amdgpu_rmx_type rmx_type;
  2129. switch (val) {
  2130. case DRM_MODE_SCALE_CENTER:
  2131. rmx_type = RMX_CENTER;
  2132. break;
  2133. case DRM_MODE_SCALE_ASPECT:
  2134. rmx_type = RMX_ASPECT;
  2135. break;
  2136. case DRM_MODE_SCALE_FULLSCREEN:
  2137. rmx_type = RMX_FULL;
  2138. break;
  2139. case DRM_MODE_SCALE_NONE:
  2140. default:
  2141. rmx_type = RMX_OFF;
  2142. break;
  2143. }
  2144. if (dm_old_state->scaling == rmx_type)
  2145. return 0;
  2146. dm_new_state->scaling = rmx_type;
  2147. ret = 0;
  2148. } else if (property == adev->mode_info.underscan_hborder_property) {
  2149. dm_new_state->underscan_hborder = val;
  2150. ret = 0;
  2151. } else if (property == adev->mode_info.underscan_vborder_property) {
  2152. dm_new_state->underscan_vborder = val;
  2153. ret = 0;
  2154. } else if (property == adev->mode_info.underscan_property) {
  2155. dm_new_state->underscan_enable = val;
  2156. ret = 0;
  2157. }
  2158. return ret;
  2159. }
  2160. int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
  2161. const struct drm_connector_state *state,
  2162. struct drm_property *property,
  2163. uint64_t *val)
  2164. {
  2165. struct drm_device *dev = connector->dev;
  2166. struct amdgpu_device *adev = dev->dev_private;
  2167. struct dm_connector_state *dm_state =
  2168. to_dm_connector_state(state);
  2169. int ret = -EINVAL;
  2170. if (property == dev->mode_config.scaling_mode_property) {
  2171. switch (dm_state->scaling) {
  2172. case RMX_CENTER:
  2173. *val = DRM_MODE_SCALE_CENTER;
  2174. break;
  2175. case RMX_ASPECT:
  2176. *val = DRM_MODE_SCALE_ASPECT;
  2177. break;
  2178. case RMX_FULL:
  2179. *val = DRM_MODE_SCALE_FULLSCREEN;
  2180. break;
  2181. case RMX_OFF:
  2182. default:
  2183. *val = DRM_MODE_SCALE_NONE;
  2184. break;
  2185. }
  2186. ret = 0;
  2187. } else if (property == adev->mode_info.underscan_hborder_property) {
  2188. *val = dm_state->underscan_hborder;
  2189. ret = 0;
  2190. } else if (property == adev->mode_info.underscan_vborder_property) {
  2191. *val = dm_state->underscan_vborder;
  2192. ret = 0;
  2193. } else if (property == adev->mode_info.underscan_property) {
  2194. *val = dm_state->underscan_enable;
  2195. ret = 0;
  2196. }
  2197. return ret;
  2198. }
  2199. static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
  2200. {
  2201. struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  2202. const struct dc_link *link = aconnector->dc_link;
  2203. struct amdgpu_device *adev = connector->dev->dev_private;
  2204. struct amdgpu_display_manager *dm = &adev->dm;
  2205. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
  2206. defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  2207. if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
  2208. link->type != dc_connection_none &&
  2209. dm->backlight_dev) {
  2210. backlight_device_unregister(dm->backlight_dev);
  2211. dm->backlight_dev = NULL;
  2212. }
  2213. #endif
  2214. drm_connector_unregister(connector);
  2215. drm_connector_cleanup(connector);
  2216. kfree(connector);
  2217. }
  2218. void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
  2219. {
  2220. struct dm_connector_state *state =
  2221. to_dm_connector_state(connector->state);
  2222. if (connector->state)
  2223. __drm_atomic_helper_connector_destroy_state(connector->state);
  2224. kfree(state);
  2225. state = kzalloc(sizeof(*state), GFP_KERNEL);
  2226. if (state) {
  2227. state->scaling = RMX_OFF;
  2228. state->underscan_enable = false;
  2229. state->underscan_hborder = 0;
  2230. state->underscan_vborder = 0;
  2231. __drm_atomic_helper_connector_reset(connector, &state->base);
  2232. }
  2233. }
  2234. struct drm_connector_state *
  2235. amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
  2236. {
  2237. struct dm_connector_state *state =
  2238. to_dm_connector_state(connector->state);
  2239. struct dm_connector_state *new_state =
  2240. kmemdup(state, sizeof(*state), GFP_KERNEL);
  2241. if (new_state) {
  2242. __drm_atomic_helper_connector_duplicate_state(connector,
  2243. &new_state->base);
  2244. return &new_state->base;
  2245. }
  2246. return NULL;
  2247. }
  2248. static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
  2249. .reset = amdgpu_dm_connector_funcs_reset,
  2250. .detect = amdgpu_dm_connector_detect,
  2251. .fill_modes = drm_helper_probe_single_connector_modes,
  2252. .destroy = amdgpu_dm_connector_destroy,
  2253. .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
  2254. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  2255. .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
  2256. .atomic_get_property = amdgpu_dm_connector_atomic_get_property
  2257. };
  2258. static struct drm_encoder *best_encoder(struct drm_connector *connector)
  2259. {
  2260. int enc_id = connector->encoder_ids[0];
  2261. struct drm_mode_object *obj;
  2262. struct drm_encoder *encoder;
  2263. DRM_DEBUG_DRIVER("Finding the best encoder\n");
  2264. /* pick the encoder ids */
  2265. if (enc_id) {
  2266. obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
  2267. if (!obj) {
  2268. DRM_ERROR("Couldn't find a matching encoder for our connector\n");
  2269. return NULL;
  2270. }
  2271. encoder = obj_to_encoder(obj);
  2272. return encoder;
  2273. }
  2274. DRM_ERROR("No encoder id\n");
  2275. return NULL;
  2276. }
  2277. static int get_modes(struct drm_connector *connector)
  2278. {
  2279. return amdgpu_dm_connector_get_modes(connector);
  2280. }
  2281. static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
  2282. {
  2283. struct dc_sink_init_data init_params = {
  2284. .link = aconnector->dc_link,
  2285. .sink_signal = SIGNAL_TYPE_VIRTUAL
  2286. };
  2287. struct edid *edid;
  2288. if (!aconnector->base.edid_blob_ptr) {
  2289. DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
  2290. aconnector->base.name);
  2291. aconnector->base.force = DRM_FORCE_OFF;
  2292. aconnector->base.override_edid = false;
  2293. return;
  2294. }
  2295. edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
  2296. aconnector->edid = edid;
  2297. aconnector->dc_em_sink = dc_link_add_remote_sink(
  2298. aconnector->dc_link,
  2299. (uint8_t *)edid,
  2300. (edid->extensions + 1) * EDID_LENGTH,
  2301. &init_params);
  2302. if (aconnector->base.force == DRM_FORCE_ON)
  2303. aconnector->dc_sink = aconnector->dc_link->local_sink ?
  2304. aconnector->dc_link->local_sink :
  2305. aconnector->dc_em_sink;
  2306. }
  2307. static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
  2308. {
  2309. struct dc_link *link = (struct dc_link *)aconnector->dc_link;
  2310. /* In case of headless boot with force on for DP managed connector
  2311. * Those settings have to be != 0 to get initial modeset
  2312. */
  2313. if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
  2314. link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
  2315. link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
  2316. }
  2317. aconnector->base.override_edid = true;
  2318. create_eml_sink(aconnector);
  2319. }
  2320. enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
  2321. struct drm_display_mode *mode)
  2322. {
  2323. int result = MODE_ERROR;
  2324. struct dc_sink *dc_sink;
  2325. struct amdgpu_device *adev = connector->dev->dev_private;
  2326. /* TODO: Unhardcode stream count */
  2327. struct dc_stream_state *stream;
  2328. struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  2329. enum dc_status dc_result = DC_OK;
  2330. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  2331. (mode->flags & DRM_MODE_FLAG_DBLSCAN))
  2332. return result;
  2333. /* Only run this the first time mode_valid is called to initilialize
  2334. * EDID mgmt
  2335. */
  2336. if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
  2337. !aconnector->dc_em_sink)
  2338. handle_edid_mgmt(aconnector);
  2339. dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
  2340. if (dc_sink == NULL) {
  2341. DRM_ERROR("dc_sink is NULL!\n");
  2342. goto fail;
  2343. }
  2344. stream = create_stream_for_sink(aconnector, mode, NULL);
  2345. if (stream == NULL) {
  2346. DRM_ERROR("Failed to create stream for sink!\n");
  2347. goto fail;
  2348. }
  2349. dc_result = dc_validate_stream(adev->dm.dc, stream);
  2350. if (dc_result == DC_OK)
  2351. result = MODE_OK;
  2352. else
  2353. DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
  2354. mode->vdisplay,
  2355. mode->hdisplay,
  2356. mode->clock,
  2357. dc_result);
  2358. dc_stream_release(stream);
  2359. fail:
  2360. /* TODO: error handling*/
  2361. return result;
  2362. }
  2363. static const struct drm_connector_helper_funcs
  2364. amdgpu_dm_connector_helper_funcs = {
  2365. /*
  2366. * If hotplug a second bigger display in FB Con mode, bigger resolution
  2367. * modes will be filtered by drm_mode_validate_size(), and those modes
  2368. * is missing after user start lightdm. So we need to renew modes list.
  2369. * in get_modes call back, not just return the modes count
  2370. */
  2371. .get_modes = get_modes,
  2372. .mode_valid = amdgpu_dm_connector_mode_valid,
  2373. .best_encoder = best_encoder
  2374. };
  2375. static void dm_crtc_helper_disable(struct drm_crtc *crtc)
  2376. {
  2377. }
  2378. static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
  2379. struct drm_crtc_state *state)
  2380. {
  2381. struct amdgpu_device *adev = crtc->dev->dev_private;
  2382. struct dc *dc = adev->dm.dc;
  2383. struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
  2384. int ret = -EINVAL;
  2385. if (unlikely(!dm_crtc_state->stream &&
  2386. modeset_required(state, NULL, dm_crtc_state->stream))) {
  2387. WARN_ON(1);
  2388. return ret;
  2389. }
  2390. /* In some use cases, like reset, no stream is attached */
  2391. if (!dm_crtc_state->stream)
  2392. return 0;
  2393. if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
  2394. return 0;
  2395. return ret;
  2396. }
  2397. static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
  2398. const struct drm_display_mode *mode,
  2399. struct drm_display_mode *adjusted_mode)
  2400. {
  2401. return true;
  2402. }
  2403. static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
  2404. .disable = dm_crtc_helper_disable,
  2405. .atomic_check = dm_crtc_helper_atomic_check,
  2406. .mode_fixup = dm_crtc_helper_mode_fixup
  2407. };
  2408. static void dm_encoder_helper_disable(struct drm_encoder *encoder)
  2409. {
  2410. }
  2411. static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
  2412. struct drm_crtc_state *crtc_state,
  2413. struct drm_connector_state *conn_state)
  2414. {
  2415. return 0;
  2416. }
  2417. const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
  2418. .disable = dm_encoder_helper_disable,
  2419. .atomic_check = dm_encoder_helper_atomic_check
  2420. };
  2421. static void dm_drm_plane_reset(struct drm_plane *plane)
  2422. {
  2423. struct dm_plane_state *amdgpu_state = NULL;
  2424. if (plane->state)
  2425. plane->funcs->atomic_destroy_state(plane, plane->state);
  2426. amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
  2427. WARN_ON(amdgpu_state == NULL);
  2428. if (amdgpu_state) {
  2429. plane->state = &amdgpu_state->base;
  2430. plane->state->plane = plane;
  2431. plane->state->rotation = DRM_MODE_ROTATE_0;
  2432. }
  2433. }
  2434. static struct drm_plane_state *
  2435. dm_drm_plane_duplicate_state(struct drm_plane *plane)
  2436. {
  2437. struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
  2438. old_dm_plane_state = to_dm_plane_state(plane->state);
  2439. dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
  2440. if (!dm_plane_state)
  2441. return NULL;
  2442. __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
  2443. if (old_dm_plane_state->dc_state) {
  2444. dm_plane_state->dc_state = old_dm_plane_state->dc_state;
  2445. dc_plane_state_retain(dm_plane_state->dc_state);
  2446. }
  2447. return &dm_plane_state->base;
  2448. }
  2449. void dm_drm_plane_destroy_state(struct drm_plane *plane,
  2450. struct drm_plane_state *state)
  2451. {
  2452. struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
  2453. if (dm_plane_state->dc_state)
  2454. dc_plane_state_release(dm_plane_state->dc_state);
  2455. drm_atomic_helper_plane_destroy_state(plane, state);
  2456. }
  2457. static const struct drm_plane_funcs dm_plane_funcs = {
  2458. .update_plane = drm_atomic_helper_update_plane,
  2459. .disable_plane = drm_atomic_helper_disable_plane,
  2460. .destroy = drm_plane_cleanup,
  2461. .reset = dm_drm_plane_reset,
  2462. .atomic_duplicate_state = dm_drm_plane_duplicate_state,
  2463. .atomic_destroy_state = dm_drm_plane_destroy_state,
  2464. };
  2465. static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
  2466. struct drm_plane_state *new_state)
  2467. {
  2468. struct amdgpu_framebuffer *afb;
  2469. struct drm_gem_object *obj;
  2470. struct amdgpu_device *adev;
  2471. struct amdgpu_bo *rbo;
  2472. uint64_t chroma_addr = 0;
  2473. struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
  2474. unsigned int awidth;
  2475. uint32_t domain;
  2476. int r;
  2477. dm_plane_state_old = to_dm_plane_state(plane->state);
  2478. dm_plane_state_new = to_dm_plane_state(new_state);
  2479. if (!new_state->fb) {
  2480. DRM_DEBUG_DRIVER("No FB bound\n");
  2481. return 0;
  2482. }
  2483. afb = to_amdgpu_framebuffer(new_state->fb);
  2484. obj = new_state->fb->obj[0];
  2485. rbo = gem_to_amdgpu_bo(obj);
  2486. adev = amdgpu_ttm_adev(rbo->tbo.bdev);
  2487. r = amdgpu_bo_reserve(rbo, false);
  2488. if (unlikely(r != 0))
  2489. return r;
  2490. if (plane->type != DRM_PLANE_TYPE_CURSOR)
  2491. domain = amdgpu_display_supported_domains(adev);
  2492. else
  2493. domain = AMDGPU_GEM_DOMAIN_VRAM;
  2494. r = amdgpu_bo_pin(rbo, domain, &afb->address);
  2495. amdgpu_bo_unreserve(rbo);
  2496. if (unlikely(r != 0)) {
  2497. if (r != -ERESTARTSYS)
  2498. DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
  2499. return r;
  2500. }
  2501. amdgpu_bo_ref(rbo);
  2502. if (dm_plane_state_new->dc_state &&
  2503. dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
  2504. struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
  2505. if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
  2506. plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
  2507. plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
  2508. } else {
  2509. awidth = ALIGN(new_state->fb->width, 64);
  2510. plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
  2511. plane_state->address.video_progressive.luma_addr.low_part
  2512. = lower_32_bits(afb->address);
  2513. plane_state->address.video_progressive.luma_addr.high_part
  2514. = upper_32_bits(afb->address);
  2515. chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
  2516. plane_state->address.video_progressive.chroma_addr.low_part
  2517. = lower_32_bits(chroma_addr);
  2518. plane_state->address.video_progressive.chroma_addr.high_part
  2519. = upper_32_bits(chroma_addr);
  2520. }
  2521. }
  2522. return 0;
  2523. }
  2524. static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
  2525. struct drm_plane_state *old_state)
  2526. {
  2527. struct amdgpu_bo *rbo;
  2528. int r;
  2529. if (!old_state->fb)
  2530. return;
  2531. rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
  2532. r = amdgpu_bo_reserve(rbo, false);
  2533. if (unlikely(r)) {
  2534. DRM_ERROR("failed to reserve rbo before unpin\n");
  2535. return;
  2536. }
  2537. amdgpu_bo_unpin(rbo);
  2538. amdgpu_bo_unreserve(rbo);
  2539. amdgpu_bo_unref(&rbo);
  2540. }
  2541. static int dm_plane_atomic_check(struct drm_plane *plane,
  2542. struct drm_plane_state *state)
  2543. {
  2544. struct amdgpu_device *adev = plane->dev->dev_private;
  2545. struct dc *dc = adev->dm.dc;
  2546. struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
  2547. if (!dm_plane_state->dc_state)
  2548. return 0;
  2549. if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
  2550. return -EINVAL;
  2551. if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
  2552. return 0;
  2553. return -EINVAL;
  2554. }
  2555. static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
  2556. .prepare_fb = dm_plane_helper_prepare_fb,
  2557. .cleanup_fb = dm_plane_helper_cleanup_fb,
  2558. .atomic_check = dm_plane_atomic_check,
  2559. };
  2560. /*
  2561. * TODO: these are currently initialized to rgb formats only.
  2562. * For future use cases we should either initialize them dynamically based on
  2563. * plane capabilities, or initialize this array to all formats, so internal drm
  2564. * check will succeed, and let DC to implement proper check
  2565. */
  2566. static const uint32_t rgb_formats[] = {
  2567. DRM_FORMAT_RGB888,
  2568. DRM_FORMAT_XRGB8888,
  2569. DRM_FORMAT_ARGB8888,
  2570. DRM_FORMAT_RGBA8888,
  2571. DRM_FORMAT_XRGB2101010,
  2572. DRM_FORMAT_XBGR2101010,
  2573. DRM_FORMAT_ARGB2101010,
  2574. DRM_FORMAT_ABGR2101010,
  2575. };
  2576. static const uint32_t yuv_formats[] = {
  2577. DRM_FORMAT_NV12,
  2578. DRM_FORMAT_NV21,
  2579. };
  2580. static const u32 cursor_formats[] = {
  2581. DRM_FORMAT_ARGB8888
  2582. };
  2583. static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  2584. struct amdgpu_plane *aplane,
  2585. unsigned long possible_crtcs)
  2586. {
  2587. int res = -EPERM;
  2588. switch (aplane->base.type) {
  2589. case DRM_PLANE_TYPE_PRIMARY:
  2590. res = drm_universal_plane_init(
  2591. dm->adev->ddev,
  2592. &aplane->base,
  2593. possible_crtcs,
  2594. &dm_plane_funcs,
  2595. rgb_formats,
  2596. ARRAY_SIZE(rgb_formats),
  2597. NULL, aplane->base.type, NULL);
  2598. break;
  2599. case DRM_PLANE_TYPE_OVERLAY:
  2600. res = drm_universal_plane_init(
  2601. dm->adev->ddev,
  2602. &aplane->base,
  2603. possible_crtcs,
  2604. &dm_plane_funcs,
  2605. yuv_formats,
  2606. ARRAY_SIZE(yuv_formats),
  2607. NULL, aplane->base.type, NULL);
  2608. break;
  2609. case DRM_PLANE_TYPE_CURSOR:
  2610. res = drm_universal_plane_init(
  2611. dm->adev->ddev,
  2612. &aplane->base,
  2613. possible_crtcs,
  2614. &dm_plane_funcs,
  2615. cursor_formats,
  2616. ARRAY_SIZE(cursor_formats),
  2617. NULL, aplane->base.type, NULL);
  2618. break;
  2619. }
  2620. drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
  2621. /* Create (reset) the plane state */
  2622. if (aplane->base.funcs->reset)
  2623. aplane->base.funcs->reset(&aplane->base);
  2624. return res;
  2625. }
  2626. static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
  2627. struct drm_plane *plane,
  2628. uint32_t crtc_index)
  2629. {
  2630. struct amdgpu_crtc *acrtc = NULL;
  2631. struct amdgpu_plane *cursor_plane;
  2632. int res = -ENOMEM;
  2633. cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
  2634. if (!cursor_plane)
  2635. goto fail;
  2636. cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
  2637. res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
  2638. acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
  2639. if (!acrtc)
  2640. goto fail;
  2641. res = drm_crtc_init_with_planes(
  2642. dm->ddev,
  2643. &acrtc->base,
  2644. plane,
  2645. &cursor_plane->base,
  2646. &amdgpu_dm_crtc_funcs, NULL);
  2647. if (res)
  2648. goto fail;
  2649. drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
  2650. /* Create (reset) the plane state */
  2651. if (acrtc->base.funcs->reset)
  2652. acrtc->base.funcs->reset(&acrtc->base);
  2653. acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
  2654. acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
  2655. acrtc->crtc_id = crtc_index;
  2656. acrtc->base.enabled = false;
  2657. dm->adev->mode_info.crtcs[crtc_index] = acrtc;
  2658. drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
  2659. true, MAX_COLOR_LUT_ENTRIES);
  2660. drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
  2661. return 0;
  2662. fail:
  2663. kfree(acrtc);
  2664. kfree(cursor_plane);
  2665. return res;
  2666. }
  2667. static int to_drm_connector_type(enum signal_type st)
  2668. {
  2669. switch (st) {
  2670. case SIGNAL_TYPE_HDMI_TYPE_A:
  2671. return DRM_MODE_CONNECTOR_HDMIA;
  2672. case SIGNAL_TYPE_EDP:
  2673. return DRM_MODE_CONNECTOR_eDP;
  2674. case SIGNAL_TYPE_RGB:
  2675. return DRM_MODE_CONNECTOR_VGA;
  2676. case SIGNAL_TYPE_DISPLAY_PORT:
  2677. case SIGNAL_TYPE_DISPLAY_PORT_MST:
  2678. return DRM_MODE_CONNECTOR_DisplayPort;
  2679. case SIGNAL_TYPE_DVI_DUAL_LINK:
  2680. case SIGNAL_TYPE_DVI_SINGLE_LINK:
  2681. return DRM_MODE_CONNECTOR_DVID;
  2682. case SIGNAL_TYPE_VIRTUAL:
  2683. return DRM_MODE_CONNECTOR_VIRTUAL;
  2684. default:
  2685. return DRM_MODE_CONNECTOR_Unknown;
  2686. }
  2687. }
  2688. static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
  2689. {
  2690. const struct drm_connector_helper_funcs *helper =
  2691. connector->helper_private;
  2692. struct drm_encoder *encoder;
  2693. struct amdgpu_encoder *amdgpu_encoder;
  2694. encoder = helper->best_encoder(connector);
  2695. if (encoder == NULL)
  2696. return;
  2697. amdgpu_encoder = to_amdgpu_encoder(encoder);
  2698. amdgpu_encoder->native_mode.clock = 0;
  2699. if (!list_empty(&connector->probed_modes)) {
  2700. struct drm_display_mode *preferred_mode = NULL;
  2701. list_for_each_entry(preferred_mode,
  2702. &connector->probed_modes,
  2703. head) {
  2704. if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
  2705. amdgpu_encoder->native_mode = *preferred_mode;
  2706. break;
  2707. }
  2708. }
  2709. }
  2710. static struct drm_display_mode *
  2711. amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
  2712. char *name,
  2713. int hdisplay, int vdisplay)
  2714. {
  2715. struct drm_device *dev = encoder->dev;
  2716. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  2717. struct drm_display_mode *mode = NULL;
  2718. struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
  2719. mode = drm_mode_duplicate(dev, native_mode);
  2720. if (mode == NULL)
  2721. return NULL;
  2722. mode->hdisplay = hdisplay;
  2723. mode->vdisplay = vdisplay;
  2724. mode->type &= ~DRM_MODE_TYPE_PREFERRED;
  2725. strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
  2726. return mode;
  2727. }
  2728. static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
  2729. struct drm_connector *connector)
  2730. {
  2731. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  2732. struct drm_display_mode *mode = NULL;
  2733. struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
  2734. struct amdgpu_dm_connector *amdgpu_dm_connector =
  2735. to_amdgpu_dm_connector(connector);
  2736. int i;
  2737. int n;
  2738. struct mode_size {
  2739. char name[DRM_DISPLAY_MODE_LEN];
  2740. int w;
  2741. int h;
  2742. } common_modes[] = {
  2743. { "640x480", 640, 480},
  2744. { "800x600", 800, 600},
  2745. { "1024x768", 1024, 768},
  2746. { "1280x720", 1280, 720},
  2747. { "1280x800", 1280, 800},
  2748. {"1280x1024", 1280, 1024},
  2749. { "1440x900", 1440, 900},
  2750. {"1680x1050", 1680, 1050},
  2751. {"1600x1200", 1600, 1200},
  2752. {"1920x1080", 1920, 1080},
  2753. {"1920x1200", 1920, 1200}
  2754. };
  2755. n = ARRAY_SIZE(common_modes);
  2756. for (i = 0; i < n; i++) {
  2757. struct drm_display_mode *curmode = NULL;
  2758. bool mode_existed = false;
  2759. if (common_modes[i].w > native_mode->hdisplay ||
  2760. common_modes[i].h > native_mode->vdisplay ||
  2761. (common_modes[i].w == native_mode->hdisplay &&
  2762. common_modes[i].h == native_mode->vdisplay))
  2763. continue;
  2764. list_for_each_entry(curmode, &connector->probed_modes, head) {
  2765. if (common_modes[i].w == curmode->hdisplay &&
  2766. common_modes[i].h == curmode->vdisplay) {
  2767. mode_existed = true;
  2768. break;
  2769. }
  2770. }
  2771. if (mode_existed)
  2772. continue;
  2773. mode = amdgpu_dm_create_common_mode(encoder,
  2774. common_modes[i].name, common_modes[i].w,
  2775. common_modes[i].h);
  2776. drm_mode_probed_add(connector, mode);
  2777. amdgpu_dm_connector->num_modes++;
  2778. }
  2779. }
  2780. static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
  2781. struct edid *edid)
  2782. {
  2783. struct amdgpu_dm_connector *amdgpu_dm_connector =
  2784. to_amdgpu_dm_connector(connector);
  2785. if (edid) {
  2786. /* empty probed_modes */
  2787. INIT_LIST_HEAD(&connector->probed_modes);
  2788. amdgpu_dm_connector->num_modes =
  2789. drm_add_edid_modes(connector, edid);
  2790. amdgpu_dm_get_native_mode(connector);
  2791. } else {
  2792. amdgpu_dm_connector->num_modes = 0;
  2793. }
  2794. }
  2795. static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
  2796. {
  2797. const struct drm_connector_helper_funcs *helper =
  2798. connector->helper_private;
  2799. struct amdgpu_dm_connector *amdgpu_dm_connector =
  2800. to_amdgpu_dm_connector(connector);
  2801. struct drm_encoder *encoder;
  2802. struct edid *edid = amdgpu_dm_connector->edid;
  2803. encoder = helper->best_encoder(connector);
  2804. amdgpu_dm_connector_ddc_get_modes(connector, edid);
  2805. amdgpu_dm_connector_add_common_modes(encoder, connector);
  2806. #if defined(CONFIG_DRM_AMD_DC_FBC)
  2807. amdgpu_dm_fbc_init(connector);
  2808. #endif
  2809. return amdgpu_dm_connector->num_modes;
  2810. }
  2811. void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
  2812. struct amdgpu_dm_connector *aconnector,
  2813. int connector_type,
  2814. struct dc_link *link,
  2815. int link_index)
  2816. {
  2817. struct amdgpu_device *adev = dm->ddev->dev_private;
  2818. aconnector->connector_id = link_index;
  2819. aconnector->dc_link = link;
  2820. aconnector->base.interlace_allowed = false;
  2821. aconnector->base.doublescan_allowed = false;
  2822. aconnector->base.stereo_allowed = false;
  2823. aconnector->base.dpms = DRM_MODE_DPMS_OFF;
  2824. aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
  2825. mutex_init(&aconnector->hpd_lock);
  2826. /* configure support HPD hot plug connector_>polled default value is 0
  2827. * which means HPD hot plug not supported
  2828. */
  2829. switch (connector_type) {
  2830. case DRM_MODE_CONNECTOR_HDMIA:
  2831. aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
  2832. break;
  2833. case DRM_MODE_CONNECTOR_DisplayPort:
  2834. aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
  2835. break;
  2836. case DRM_MODE_CONNECTOR_DVID:
  2837. aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
  2838. break;
  2839. default:
  2840. break;
  2841. }
  2842. drm_object_attach_property(&aconnector->base.base,
  2843. dm->ddev->mode_config.scaling_mode_property,
  2844. DRM_MODE_SCALE_NONE);
  2845. drm_object_attach_property(&aconnector->base.base,
  2846. adev->mode_info.underscan_property,
  2847. UNDERSCAN_OFF);
  2848. drm_object_attach_property(&aconnector->base.base,
  2849. adev->mode_info.underscan_hborder_property,
  2850. 0);
  2851. drm_object_attach_property(&aconnector->base.base,
  2852. adev->mode_info.underscan_vborder_property,
  2853. 0);
  2854. }
  2855. static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
  2856. struct i2c_msg *msgs, int num)
  2857. {
  2858. struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
  2859. struct ddc_service *ddc_service = i2c->ddc_service;
  2860. struct i2c_command cmd;
  2861. int i;
  2862. int result = -EIO;
  2863. cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
  2864. if (!cmd.payloads)
  2865. return result;
  2866. cmd.number_of_payloads = num;
  2867. cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
  2868. cmd.speed = 100;
  2869. for (i = 0; i < num; i++) {
  2870. cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
  2871. cmd.payloads[i].address = msgs[i].addr;
  2872. cmd.payloads[i].length = msgs[i].len;
  2873. cmd.payloads[i].data = msgs[i].buf;
  2874. }
  2875. if (dal_i2caux_submit_i2c_command(
  2876. ddc_service->ctx->i2caux,
  2877. ddc_service->ddc_pin,
  2878. &cmd))
  2879. result = num;
  2880. kfree(cmd.payloads);
  2881. return result;
  2882. }
  2883. static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
  2884. {
  2885. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  2886. }
  2887. static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
  2888. .master_xfer = amdgpu_dm_i2c_xfer,
  2889. .functionality = amdgpu_dm_i2c_func,
  2890. };
  2891. static struct amdgpu_i2c_adapter *
  2892. create_i2c(struct ddc_service *ddc_service,
  2893. int link_index,
  2894. int *res)
  2895. {
  2896. struct amdgpu_device *adev = ddc_service->ctx->driver_context;
  2897. struct amdgpu_i2c_adapter *i2c;
  2898. i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
  2899. if (!i2c)
  2900. return NULL;
  2901. i2c->base.owner = THIS_MODULE;
  2902. i2c->base.class = I2C_CLASS_DDC;
  2903. i2c->base.dev.parent = &adev->pdev->dev;
  2904. i2c->base.algo = &amdgpu_dm_i2c_algo;
  2905. snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
  2906. i2c_set_adapdata(&i2c->base, i2c);
  2907. i2c->ddc_service = ddc_service;
  2908. return i2c;
  2909. }
  2910. /* Note: this function assumes that dc_link_detect() was called for the
  2911. * dc_link which will be represented by this aconnector.
  2912. */
  2913. static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
  2914. struct amdgpu_dm_connector *aconnector,
  2915. uint32_t link_index,
  2916. struct amdgpu_encoder *aencoder)
  2917. {
  2918. int res = 0;
  2919. int connector_type;
  2920. struct dc *dc = dm->dc;
  2921. struct dc_link *link = dc_get_link_at_index(dc, link_index);
  2922. struct amdgpu_i2c_adapter *i2c;
  2923. link->priv = aconnector;
  2924. DRM_DEBUG_DRIVER("%s()\n", __func__);
  2925. i2c = create_i2c(link->ddc, link->link_index, &res);
  2926. if (!i2c) {
  2927. DRM_ERROR("Failed to create i2c adapter data\n");
  2928. return -ENOMEM;
  2929. }
  2930. aconnector->i2c = i2c;
  2931. res = i2c_add_adapter(&i2c->base);
  2932. if (res) {
  2933. DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
  2934. goto out_free;
  2935. }
  2936. connector_type = to_drm_connector_type(link->connector_signal);
  2937. res = drm_connector_init(
  2938. dm->ddev,
  2939. &aconnector->base,
  2940. &amdgpu_dm_connector_funcs,
  2941. connector_type);
  2942. if (res) {
  2943. DRM_ERROR("connector_init failed\n");
  2944. aconnector->connector_id = -1;
  2945. goto out_free;
  2946. }
  2947. drm_connector_helper_add(
  2948. &aconnector->base,
  2949. &amdgpu_dm_connector_helper_funcs);
  2950. if (aconnector->base.funcs->reset)
  2951. aconnector->base.funcs->reset(&aconnector->base);
  2952. amdgpu_dm_connector_init_helper(
  2953. dm,
  2954. aconnector,
  2955. connector_type,
  2956. link,
  2957. link_index);
  2958. drm_mode_connector_attach_encoder(
  2959. &aconnector->base, &aencoder->base);
  2960. drm_connector_register(&aconnector->base);
  2961. if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
  2962. || connector_type == DRM_MODE_CONNECTOR_eDP)
  2963. amdgpu_dm_initialize_dp_connector(dm, aconnector);
  2964. out_free:
  2965. if (res) {
  2966. kfree(i2c);
  2967. aconnector->i2c = NULL;
  2968. }
  2969. return res;
  2970. }
  2971. int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
  2972. {
  2973. switch (adev->mode_info.num_crtc) {
  2974. case 1:
  2975. return 0x1;
  2976. case 2:
  2977. return 0x3;
  2978. case 3:
  2979. return 0x7;
  2980. case 4:
  2981. return 0xf;
  2982. case 5:
  2983. return 0x1f;
  2984. case 6:
  2985. default:
  2986. return 0x3f;
  2987. }
  2988. }
  2989. static int amdgpu_dm_encoder_init(struct drm_device *dev,
  2990. struct amdgpu_encoder *aencoder,
  2991. uint32_t link_index)
  2992. {
  2993. struct amdgpu_device *adev = dev->dev_private;
  2994. int res = drm_encoder_init(dev,
  2995. &aencoder->base,
  2996. &amdgpu_dm_encoder_funcs,
  2997. DRM_MODE_ENCODER_TMDS,
  2998. NULL);
  2999. aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
  3000. if (!res)
  3001. aencoder->encoder_id = link_index;
  3002. else
  3003. aencoder->encoder_id = -1;
  3004. drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
  3005. return res;
  3006. }
  3007. static void manage_dm_interrupts(struct amdgpu_device *adev,
  3008. struct amdgpu_crtc *acrtc,
  3009. bool enable)
  3010. {
  3011. /*
  3012. * this is not correct translation but will work as soon as VBLANK
  3013. * constant is the same as PFLIP
  3014. */
  3015. int irq_type =
  3016. amdgpu_display_crtc_idx_to_irq_type(
  3017. adev,
  3018. acrtc->crtc_id);
  3019. if (enable) {
  3020. drm_crtc_vblank_on(&acrtc->base);
  3021. amdgpu_irq_get(
  3022. adev,
  3023. &adev->pageflip_irq,
  3024. irq_type);
  3025. } else {
  3026. amdgpu_irq_put(
  3027. adev,
  3028. &adev->pageflip_irq,
  3029. irq_type);
  3030. drm_crtc_vblank_off(&acrtc->base);
  3031. }
  3032. }
  3033. static bool
  3034. is_scaling_state_different(const struct dm_connector_state *dm_state,
  3035. const struct dm_connector_state *old_dm_state)
  3036. {
  3037. if (dm_state->scaling != old_dm_state->scaling)
  3038. return true;
  3039. if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
  3040. if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
  3041. return true;
  3042. } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
  3043. if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
  3044. return true;
  3045. } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
  3046. dm_state->underscan_vborder != old_dm_state->underscan_vborder)
  3047. return true;
  3048. return false;
  3049. }
  3050. static void remove_stream(struct amdgpu_device *adev,
  3051. struct amdgpu_crtc *acrtc,
  3052. struct dc_stream_state *stream)
  3053. {
  3054. /* this is the update mode case */
  3055. if (adev->dm.freesync_module)
  3056. mod_freesync_remove_stream(adev->dm.freesync_module, stream);
  3057. acrtc->otg_inst = -1;
  3058. acrtc->enabled = false;
  3059. }
  3060. static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
  3061. struct dc_cursor_position *position)
  3062. {
  3063. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  3064. int x, y;
  3065. int xorigin = 0, yorigin = 0;
  3066. if (!crtc || !plane->state->fb) {
  3067. position->enable = false;
  3068. position->x = 0;
  3069. position->y = 0;
  3070. return 0;
  3071. }
  3072. if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
  3073. (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
  3074. DRM_ERROR("%s: bad cursor width or height %d x %d\n",
  3075. __func__,
  3076. plane->state->crtc_w,
  3077. plane->state->crtc_h);
  3078. return -EINVAL;
  3079. }
  3080. x = plane->state->crtc_x;
  3081. y = plane->state->crtc_y;
  3082. /* avivo cursor are offset into the total surface */
  3083. x += crtc->primary->state->src_x >> 16;
  3084. y += crtc->primary->state->src_y >> 16;
  3085. if (x < 0) {
  3086. xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
  3087. x = 0;
  3088. }
  3089. if (y < 0) {
  3090. yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
  3091. y = 0;
  3092. }
  3093. position->enable = true;
  3094. position->x = x;
  3095. position->y = y;
  3096. position->x_hotspot = xorigin;
  3097. position->y_hotspot = yorigin;
  3098. return 0;
  3099. }
  3100. static void handle_cursor_update(struct drm_plane *plane,
  3101. struct drm_plane_state *old_plane_state)
  3102. {
  3103. struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
  3104. struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
  3105. struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
  3106. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  3107. uint64_t address = afb ? afb->address : 0;
  3108. struct dc_cursor_position position;
  3109. struct dc_cursor_attributes attributes;
  3110. int ret;
  3111. if (!plane->state->fb && !old_plane_state->fb)
  3112. return;
  3113. DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
  3114. __func__,
  3115. amdgpu_crtc->crtc_id,
  3116. plane->state->crtc_w,
  3117. plane->state->crtc_h);
  3118. ret = get_cursor_position(plane, crtc, &position);
  3119. if (ret)
  3120. return;
  3121. if (!position.enable) {
  3122. /* turn off cursor */
  3123. if (crtc_state && crtc_state->stream)
  3124. dc_stream_set_cursor_position(crtc_state->stream,
  3125. &position);
  3126. return;
  3127. }
  3128. amdgpu_crtc->cursor_width = plane->state->crtc_w;
  3129. amdgpu_crtc->cursor_height = plane->state->crtc_h;
  3130. attributes.address.high_part = upper_32_bits(address);
  3131. attributes.address.low_part = lower_32_bits(address);
  3132. attributes.width = plane->state->crtc_w;
  3133. attributes.height = plane->state->crtc_h;
  3134. attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
  3135. attributes.rotation_angle = 0;
  3136. attributes.attribute_flags.value = 0;
  3137. attributes.pitch = attributes.width;
  3138. if (crtc_state->stream) {
  3139. if (!dc_stream_set_cursor_attributes(crtc_state->stream,
  3140. &attributes))
  3141. DRM_ERROR("DC failed to set cursor attributes\n");
  3142. if (!dc_stream_set_cursor_position(crtc_state->stream,
  3143. &position))
  3144. DRM_ERROR("DC failed to set cursor position\n");
  3145. }
  3146. }
  3147. static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
  3148. {
  3149. assert_spin_locked(&acrtc->base.dev->event_lock);
  3150. WARN_ON(acrtc->event);
  3151. acrtc->event = acrtc->base.state->event;
  3152. /* Set the flip status */
  3153. acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
  3154. /* Mark this event as consumed */
  3155. acrtc->base.state->event = NULL;
  3156. DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
  3157. acrtc->crtc_id);
  3158. }
  3159. /*
  3160. * Executes flip
  3161. *
  3162. * Waits on all BO's fences and for proper vblank count
  3163. */
  3164. static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
  3165. struct drm_framebuffer *fb,
  3166. uint32_t target,
  3167. struct dc_state *state)
  3168. {
  3169. unsigned long flags;
  3170. uint32_t target_vblank;
  3171. int r, vpos, hpos;
  3172. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  3173. struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
  3174. struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
  3175. struct amdgpu_device *adev = crtc->dev->dev_private;
  3176. bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
  3177. struct dc_flip_addrs addr = { {0} };
  3178. /* TODO eliminate or rename surface_update */
  3179. struct dc_surface_update surface_updates[1] = { {0} };
  3180. struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
  3181. /* Prepare wait for target vblank early - before the fence-waits */
  3182. target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
  3183. amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
  3184. /* TODO This might fail and hence better not used, wait
  3185. * explicitly on fences instead
  3186. * and in general should be called for
  3187. * blocking commit to as per framework helpers
  3188. */
  3189. r = amdgpu_bo_reserve(abo, true);
  3190. if (unlikely(r != 0)) {
  3191. DRM_ERROR("failed to reserve buffer before flip\n");
  3192. WARN_ON(1);
  3193. }
  3194. /* Wait for all fences on this FB */
  3195. WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
  3196. MAX_SCHEDULE_TIMEOUT) < 0);
  3197. amdgpu_bo_unreserve(abo);
  3198. /* Wait until we're out of the vertical blank period before the one
  3199. * targeted by the flip
  3200. */
  3201. while ((acrtc->enabled &&
  3202. (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
  3203. 0, &vpos, &hpos, NULL,
  3204. NULL, &crtc->hwmode)
  3205. & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
  3206. (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
  3207. (int)(target_vblank -
  3208. amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
  3209. usleep_range(1000, 1100);
  3210. }
  3211. /* Flip */
  3212. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  3213. /* update crtc fb */
  3214. crtc->primary->fb = fb;
  3215. WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
  3216. WARN_ON(!acrtc_state->stream);
  3217. addr.address.grph.addr.low_part = lower_32_bits(afb->address);
  3218. addr.address.grph.addr.high_part = upper_32_bits(afb->address);
  3219. addr.flip_immediate = async_flip;
  3220. if (acrtc->base.state->event)
  3221. prepare_flip_isr(acrtc);
  3222. surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
  3223. surface_updates->flip_addr = &addr;
  3224. dc_commit_updates_for_stream(adev->dm.dc,
  3225. surface_updates,
  3226. 1,
  3227. acrtc_state->stream,
  3228. NULL,
  3229. &surface_updates->surface,
  3230. state);
  3231. DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
  3232. __func__,
  3233. addr.address.grph.addr.high_part,
  3234. addr.address.grph.addr.low_part);
  3235. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  3236. }
  3237. /*
  3238. * TODO this whole function needs to go
  3239. *
  3240. * dc_surface_update is needlessly complex. See if we can just replace this
  3241. * with a dc_plane_state and follow the atomic model a bit more closely here.
  3242. */
  3243. static bool commit_planes_to_stream(
  3244. struct dc *dc,
  3245. struct dc_plane_state **plane_states,
  3246. uint8_t new_plane_count,
  3247. struct dm_crtc_state *dm_new_crtc_state,
  3248. struct dm_crtc_state *dm_old_crtc_state,
  3249. struct dc_state *state)
  3250. {
  3251. /* no need to dynamically allocate this. it's pretty small */
  3252. struct dc_surface_update updates[MAX_SURFACES];
  3253. struct dc_flip_addrs *flip_addr;
  3254. struct dc_plane_info *plane_info;
  3255. struct dc_scaling_info *scaling_info;
  3256. int i;
  3257. struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
  3258. struct dc_stream_update *stream_update =
  3259. kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
  3260. if (!stream_update) {
  3261. BREAK_TO_DEBUGGER();
  3262. return false;
  3263. }
  3264. flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
  3265. GFP_KERNEL);
  3266. plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
  3267. GFP_KERNEL);
  3268. scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
  3269. GFP_KERNEL);
  3270. if (!flip_addr || !plane_info || !scaling_info) {
  3271. kfree(flip_addr);
  3272. kfree(plane_info);
  3273. kfree(scaling_info);
  3274. kfree(stream_update);
  3275. return false;
  3276. }
  3277. memset(updates, 0, sizeof(updates));
  3278. stream_update->src = dc_stream->src;
  3279. stream_update->dst = dc_stream->dst;
  3280. stream_update->out_transfer_func = dc_stream->out_transfer_func;
  3281. for (i = 0; i < new_plane_count; i++) {
  3282. updates[i].surface = plane_states[i];
  3283. updates[i].gamma =
  3284. (struct dc_gamma *)plane_states[i]->gamma_correction;
  3285. updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
  3286. flip_addr[i].address = plane_states[i]->address;
  3287. flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
  3288. plane_info[i].color_space = plane_states[i]->color_space;
  3289. plane_info[i].format = plane_states[i]->format;
  3290. plane_info[i].plane_size = plane_states[i]->plane_size;
  3291. plane_info[i].rotation = plane_states[i]->rotation;
  3292. plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
  3293. plane_info[i].stereo_format = plane_states[i]->stereo_format;
  3294. plane_info[i].tiling_info = plane_states[i]->tiling_info;
  3295. plane_info[i].visible = plane_states[i]->visible;
  3296. plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
  3297. plane_info[i].dcc = plane_states[i]->dcc;
  3298. scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
  3299. scaling_info[i].src_rect = plane_states[i]->src_rect;
  3300. scaling_info[i].dst_rect = plane_states[i]->dst_rect;
  3301. scaling_info[i].clip_rect = plane_states[i]->clip_rect;
  3302. updates[i].flip_addr = &flip_addr[i];
  3303. updates[i].plane_info = &plane_info[i];
  3304. updates[i].scaling_info = &scaling_info[i];
  3305. }
  3306. dc_commit_updates_for_stream(
  3307. dc,
  3308. updates,
  3309. new_plane_count,
  3310. dc_stream, stream_update, plane_states, state);
  3311. kfree(flip_addr);
  3312. kfree(plane_info);
  3313. kfree(scaling_info);
  3314. kfree(stream_update);
  3315. return true;
  3316. }
  3317. static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
  3318. struct drm_device *dev,
  3319. struct amdgpu_display_manager *dm,
  3320. struct drm_crtc *pcrtc,
  3321. bool *wait_for_vblank)
  3322. {
  3323. uint32_t i;
  3324. struct drm_plane *plane;
  3325. struct drm_plane_state *old_plane_state, *new_plane_state;
  3326. struct dc_stream_state *dc_stream_attach;
  3327. struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
  3328. struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
  3329. struct drm_crtc_state *new_pcrtc_state =
  3330. drm_atomic_get_new_crtc_state(state, pcrtc);
  3331. struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
  3332. struct dm_crtc_state *dm_old_crtc_state =
  3333. to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
  3334. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  3335. int planes_count = 0;
  3336. unsigned long flags;
  3337. /* update planes when needed */
  3338. for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
  3339. struct drm_crtc *crtc = new_plane_state->crtc;
  3340. struct drm_crtc_state *new_crtc_state;
  3341. struct drm_framebuffer *fb = new_plane_state->fb;
  3342. bool pflip_needed;
  3343. struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
  3344. if (plane->type == DRM_PLANE_TYPE_CURSOR) {
  3345. handle_cursor_update(plane, old_plane_state);
  3346. continue;
  3347. }
  3348. if (!fb || !crtc || pcrtc != crtc)
  3349. continue;
  3350. new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  3351. if (!new_crtc_state->active)
  3352. continue;
  3353. pflip_needed = !state->allow_modeset;
  3354. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  3355. if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
  3356. DRM_ERROR("%s: acrtc %d, already busy\n",
  3357. __func__,
  3358. acrtc_attach->crtc_id);
  3359. /* In commit tail framework this cannot happen */
  3360. WARN_ON(1);
  3361. }
  3362. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  3363. if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
  3364. WARN_ON(!dm_new_plane_state->dc_state);
  3365. plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
  3366. dc_stream_attach = acrtc_state->stream;
  3367. planes_count++;
  3368. } else if (new_crtc_state->planes_changed) {
  3369. /* Assume even ONE crtc with immediate flip means
  3370. * entire can't wait for VBLANK
  3371. * TODO Check if it's correct
  3372. */
  3373. *wait_for_vblank =
  3374. new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
  3375. false : true;
  3376. /* TODO: Needs rework for multiplane flip */
  3377. if (plane->type == DRM_PLANE_TYPE_PRIMARY)
  3378. drm_crtc_vblank_get(crtc);
  3379. amdgpu_dm_do_flip(
  3380. crtc,
  3381. fb,
  3382. (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
  3383. dm_state->context);
  3384. }
  3385. }
  3386. if (planes_count) {
  3387. unsigned long flags;
  3388. if (new_pcrtc_state->event) {
  3389. drm_crtc_vblank_get(pcrtc);
  3390. spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
  3391. prepare_flip_isr(acrtc_attach);
  3392. spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
  3393. }
  3394. if (false == commit_planes_to_stream(dm->dc,
  3395. plane_states_constructed,
  3396. planes_count,
  3397. acrtc_state,
  3398. dm_old_crtc_state,
  3399. dm_state->context))
  3400. dm_error("%s: Failed to attach plane!\n", __func__);
  3401. } else {
  3402. /*TODO BUG Here should go disable planes on CRTC. */
  3403. }
  3404. }
  3405. /**
  3406. * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
  3407. * @crtc_state: the DRM CRTC state
  3408. * @stream_state: the DC stream state.
  3409. *
  3410. * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
  3411. * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
  3412. */
  3413. static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
  3414. struct dc_stream_state *stream_state)
  3415. {
  3416. stream_state->mode_changed = crtc_state->mode_changed;
  3417. }
  3418. static int amdgpu_dm_atomic_commit(struct drm_device *dev,
  3419. struct drm_atomic_state *state,
  3420. bool nonblock)
  3421. {
  3422. struct drm_crtc *crtc;
  3423. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  3424. struct amdgpu_device *adev = dev->dev_private;
  3425. int i;
  3426. /*
  3427. * We evade vblanks and pflips on crtc that
  3428. * should be changed. We do it here to flush & disable
  3429. * interrupts before drm_swap_state is called in drm_atomic_helper_commit
  3430. * it will update crtc->dm_crtc_state->stream pointer which is used in
  3431. * the ISRs.
  3432. */
  3433. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  3434. struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3435. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  3436. if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
  3437. manage_dm_interrupts(adev, acrtc, false);
  3438. }
  3439. /* Add check here for SoC's that support hardware cursor plane, to
  3440. * unset legacy_cursor_update */
  3441. return drm_atomic_helper_commit(dev, state, nonblock);
  3442. /*TODO Handle EINTR, reenable IRQ*/
  3443. }
  3444. static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
  3445. {
  3446. struct drm_device *dev = state->dev;
  3447. struct amdgpu_device *adev = dev->dev_private;
  3448. struct amdgpu_display_manager *dm = &adev->dm;
  3449. struct dm_atomic_state *dm_state;
  3450. uint32_t i, j;
  3451. struct drm_crtc *crtc;
  3452. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  3453. unsigned long flags;
  3454. bool wait_for_vblank = true;
  3455. struct drm_connector *connector;
  3456. struct drm_connector_state *old_con_state, *new_con_state;
  3457. struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
  3458. drm_atomic_helper_update_legacy_modeset_state(dev, state);
  3459. dm_state = to_dm_atomic_state(state);
  3460. /* update changed items */
  3461. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  3462. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  3463. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3464. dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3465. DRM_DEBUG_DRIVER(
  3466. "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
  3467. "planes_changed:%d, mode_changed:%d,active_changed:%d,"
  3468. "connectors_changed:%d\n",
  3469. acrtc->crtc_id,
  3470. new_crtc_state->enable,
  3471. new_crtc_state->active,
  3472. new_crtc_state->planes_changed,
  3473. new_crtc_state->mode_changed,
  3474. new_crtc_state->active_changed,
  3475. new_crtc_state->connectors_changed);
  3476. /* Copy all transient state flags into dc state */
  3477. if (dm_new_crtc_state->stream) {
  3478. amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
  3479. dm_new_crtc_state->stream);
  3480. }
  3481. /* handles headless hotplug case, updating new_state and
  3482. * aconnector as needed
  3483. */
  3484. if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
  3485. DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
  3486. if (!dm_new_crtc_state->stream) {
  3487. /*
  3488. * this could happen because of issues with
  3489. * userspace notifications delivery.
  3490. * In this case userspace tries to set mode on
  3491. * display which is disconnect in fact.
  3492. * dc_sink in NULL in this case on aconnector.
  3493. * We expect reset mode will come soon.
  3494. *
  3495. * This can also happen when unplug is done
  3496. * during resume sequence ended
  3497. *
  3498. * In this case, we want to pretend we still
  3499. * have a sink to keep the pipe running so that
  3500. * hw state is consistent with the sw state
  3501. */
  3502. DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
  3503. __func__, acrtc->base.base.id);
  3504. continue;
  3505. }
  3506. if (dm_old_crtc_state->stream)
  3507. remove_stream(adev, acrtc, dm_old_crtc_state->stream);
  3508. pm_runtime_get_noresume(dev->dev);
  3509. acrtc->enabled = true;
  3510. acrtc->hw_mode = new_crtc_state->mode;
  3511. crtc->hwmode = new_crtc_state->mode;
  3512. } else if (modereset_required(new_crtc_state)) {
  3513. DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
  3514. /* i.e. reset mode */
  3515. if (dm_old_crtc_state->stream)
  3516. remove_stream(adev, acrtc, dm_old_crtc_state->stream);
  3517. }
  3518. } /* for_each_crtc_in_state() */
  3519. /*
  3520. * Add streams after required streams from new and replaced streams
  3521. * are removed from freesync module
  3522. */
  3523. if (adev->dm.freesync_module) {
  3524. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
  3525. new_crtc_state, i) {
  3526. struct amdgpu_dm_connector *aconnector = NULL;
  3527. struct dm_connector_state *dm_new_con_state = NULL;
  3528. struct amdgpu_crtc *acrtc = NULL;
  3529. bool modeset_needed;
  3530. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3531. dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3532. modeset_needed = modeset_required(
  3533. new_crtc_state,
  3534. dm_new_crtc_state->stream,
  3535. dm_old_crtc_state->stream);
  3536. /* We add stream to freesync if:
  3537. * 1. Said stream is not null, and
  3538. * 2. A modeset is requested. This means that the
  3539. * stream was removed previously, and needs to be
  3540. * replaced.
  3541. */
  3542. if (dm_new_crtc_state->stream == NULL ||
  3543. !modeset_needed)
  3544. continue;
  3545. acrtc = to_amdgpu_crtc(crtc);
  3546. aconnector =
  3547. amdgpu_dm_find_first_crtc_matching_connector(
  3548. state, crtc);
  3549. if (!aconnector) {
  3550. DRM_DEBUG_DRIVER("Atomic commit: Failed to "
  3551. "find connector for acrtc "
  3552. "id:%d skipping freesync "
  3553. "init\n",
  3554. acrtc->crtc_id);
  3555. continue;
  3556. }
  3557. mod_freesync_add_stream(adev->dm.freesync_module,
  3558. dm_new_crtc_state->stream,
  3559. &aconnector->caps);
  3560. new_con_state = drm_atomic_get_new_connector_state(
  3561. state, &aconnector->base);
  3562. dm_new_con_state = to_dm_connector_state(new_con_state);
  3563. mod_freesync_set_user_enable(adev->dm.freesync_module,
  3564. &dm_new_crtc_state->stream,
  3565. 1,
  3566. &dm_new_con_state->user_enable);
  3567. }
  3568. }
  3569. if (dm_state->context) {
  3570. dm_enable_per_frame_crtc_master_sync(dm_state->context);
  3571. WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
  3572. }
  3573. for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
  3574. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  3575. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3576. if (dm_new_crtc_state->stream != NULL) {
  3577. const struct dc_stream_status *status =
  3578. dc_stream_get_status(dm_new_crtc_state->stream);
  3579. if (!status)
  3580. DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
  3581. else
  3582. acrtc->otg_inst = status->primary_otg_inst;
  3583. }
  3584. }
  3585. /* Handle scaling and underscan changes*/
  3586. for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
  3587. struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
  3588. struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
  3589. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
  3590. struct dc_stream_status *status = NULL;
  3591. if (acrtc) {
  3592. new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
  3593. old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
  3594. }
  3595. /* Skip any modesets/resets */
  3596. if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
  3597. continue;
  3598. /* Skip any thing not scale or underscan changes */
  3599. if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
  3600. continue;
  3601. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3602. update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
  3603. dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
  3604. if (!dm_new_crtc_state->stream)
  3605. continue;
  3606. status = dc_stream_get_status(dm_new_crtc_state->stream);
  3607. WARN_ON(!status);
  3608. WARN_ON(!status->plane_count);
  3609. /*TODO How it works with MPO ?*/
  3610. if (!commit_planes_to_stream(
  3611. dm->dc,
  3612. status->plane_states,
  3613. status->plane_count,
  3614. dm_new_crtc_state,
  3615. to_dm_crtc_state(old_crtc_state),
  3616. dm_state->context))
  3617. dm_error("%s: Failed to update stream scaling!\n", __func__);
  3618. }
  3619. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
  3620. new_crtc_state, i) {
  3621. /*
  3622. * loop to enable interrupts on newly arrived crtc
  3623. */
  3624. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  3625. bool modeset_needed;
  3626. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3627. dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3628. modeset_needed = modeset_required(
  3629. new_crtc_state,
  3630. dm_new_crtc_state->stream,
  3631. dm_old_crtc_state->stream);
  3632. if (dm_new_crtc_state->stream == NULL || !modeset_needed)
  3633. continue;
  3634. if (adev->dm.freesync_module)
  3635. mod_freesync_notify_mode_change(
  3636. adev->dm.freesync_module,
  3637. &dm_new_crtc_state->stream, 1);
  3638. manage_dm_interrupts(adev, acrtc, true);
  3639. }
  3640. /* update planes when needed per crtc*/
  3641. for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
  3642. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3643. if (dm_new_crtc_state->stream)
  3644. amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
  3645. }
  3646. /*
  3647. * send vblank event on all events not handled in flip and
  3648. * mark consumed event for drm_atomic_helper_commit_hw_done
  3649. */
  3650. spin_lock_irqsave(&adev->ddev->event_lock, flags);
  3651. for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
  3652. if (new_crtc_state->event)
  3653. drm_send_event_locked(dev, &new_crtc_state->event->base);
  3654. new_crtc_state->event = NULL;
  3655. }
  3656. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  3657. /* Signal HW programming completion */
  3658. drm_atomic_helper_commit_hw_done(state);
  3659. if (wait_for_vblank)
  3660. drm_atomic_helper_wait_for_flip_done(dev, state);
  3661. drm_atomic_helper_cleanup_planes(dev, state);
  3662. /* Finally, drop a runtime PM reference for each newly disabled CRTC,
  3663. * so we can put the GPU into runtime suspend if we're not driving any
  3664. * displays anymore
  3665. */
  3666. pm_runtime_mark_last_busy(dev->dev);
  3667. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  3668. if (old_crtc_state->active && !new_crtc_state->active)
  3669. pm_runtime_put_autosuspend(dev->dev);
  3670. }
  3671. }
  3672. static int dm_force_atomic_commit(struct drm_connector *connector)
  3673. {
  3674. int ret = 0;
  3675. struct drm_device *ddev = connector->dev;
  3676. struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
  3677. struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
  3678. struct drm_plane *plane = disconnected_acrtc->base.primary;
  3679. struct drm_connector_state *conn_state;
  3680. struct drm_crtc_state *crtc_state;
  3681. struct drm_plane_state *plane_state;
  3682. if (!state)
  3683. return -ENOMEM;
  3684. state->acquire_ctx = ddev->mode_config.acquire_ctx;
  3685. /* Construct an atomic state to restore previous display setting */
  3686. /*
  3687. * Attach connectors to drm_atomic_state
  3688. */
  3689. conn_state = drm_atomic_get_connector_state(state, connector);
  3690. ret = PTR_ERR_OR_ZERO(conn_state);
  3691. if (ret)
  3692. goto err;
  3693. /* Attach crtc to drm_atomic_state*/
  3694. crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
  3695. ret = PTR_ERR_OR_ZERO(crtc_state);
  3696. if (ret)
  3697. goto err;
  3698. /* force a restore */
  3699. crtc_state->mode_changed = true;
  3700. /* Attach plane to drm_atomic_state */
  3701. plane_state = drm_atomic_get_plane_state(state, plane);
  3702. ret = PTR_ERR_OR_ZERO(plane_state);
  3703. if (ret)
  3704. goto err;
  3705. /* Call commit internally with the state we just constructed */
  3706. ret = drm_atomic_commit(state);
  3707. if (!ret)
  3708. return 0;
  3709. err:
  3710. DRM_ERROR("Restoring old state failed with %i\n", ret);
  3711. drm_atomic_state_put(state);
  3712. return ret;
  3713. }
  3714. /*
  3715. * This functions handle all cases when set mode does not come upon hotplug.
  3716. * This include when the same display is unplugged then plugged back into the
  3717. * same port and when we are running without usermode desktop manager supprot
  3718. */
  3719. void dm_restore_drm_connector_state(struct drm_device *dev,
  3720. struct drm_connector *connector)
  3721. {
  3722. struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  3723. struct amdgpu_crtc *disconnected_acrtc;
  3724. struct dm_crtc_state *acrtc_state;
  3725. if (!aconnector->dc_sink || !connector->state || !connector->encoder)
  3726. return;
  3727. disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
  3728. if (!disconnected_acrtc)
  3729. return;
  3730. acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
  3731. if (!acrtc_state->stream)
  3732. return;
  3733. /*
  3734. * If the previous sink is not released and different from the current,
  3735. * we deduce we are in a state where we can not rely on usermode call
  3736. * to turn on the display, so we do it here
  3737. */
  3738. if (acrtc_state->stream->sink != aconnector->dc_sink)
  3739. dm_force_atomic_commit(&aconnector->base);
  3740. }
  3741. /*`
  3742. * Grabs all modesetting locks to serialize against any blocking commits,
  3743. * Waits for completion of all non blocking commits.
  3744. */
  3745. static int do_aquire_global_lock(struct drm_device *dev,
  3746. struct drm_atomic_state *state)
  3747. {
  3748. struct drm_crtc *crtc;
  3749. struct drm_crtc_commit *commit;
  3750. long ret;
  3751. /* Adding all modeset locks to aquire_ctx will
  3752. * ensure that when the framework release it the
  3753. * extra locks we are locking here will get released to
  3754. */
  3755. ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
  3756. if (ret)
  3757. return ret;
  3758. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3759. spin_lock(&crtc->commit_lock);
  3760. commit = list_first_entry_or_null(&crtc->commit_list,
  3761. struct drm_crtc_commit, commit_entry);
  3762. if (commit)
  3763. drm_crtc_commit_get(commit);
  3764. spin_unlock(&crtc->commit_lock);
  3765. if (!commit)
  3766. continue;
  3767. /* Make sure all pending HW programming completed and
  3768. * page flips done
  3769. */
  3770. ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
  3771. if (ret > 0)
  3772. ret = wait_for_completion_interruptible_timeout(
  3773. &commit->flip_done, 10*HZ);
  3774. if (ret == 0)
  3775. DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
  3776. "timed out\n", crtc->base.id, crtc->name);
  3777. drm_crtc_commit_put(commit);
  3778. }
  3779. return ret < 0 ? ret : 0;
  3780. }
  3781. static int dm_update_crtcs_state(struct dc *dc,
  3782. struct drm_atomic_state *state,
  3783. bool enable,
  3784. bool *lock_and_validation_needed)
  3785. {
  3786. struct drm_crtc *crtc;
  3787. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  3788. int i;
  3789. struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
  3790. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  3791. struct dc_stream_state *new_stream;
  3792. int ret = 0;
  3793. /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
  3794. /* update changed items */
  3795. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  3796. struct amdgpu_crtc *acrtc = NULL;
  3797. struct amdgpu_dm_connector *aconnector = NULL;
  3798. struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
  3799. struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
  3800. struct drm_plane_state *new_plane_state = NULL;
  3801. new_stream = NULL;
  3802. dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3803. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  3804. acrtc = to_amdgpu_crtc(crtc);
  3805. new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
  3806. if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
  3807. ret = -EINVAL;
  3808. goto fail;
  3809. }
  3810. aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
  3811. /* TODO This hack should go away */
  3812. if (aconnector && enable) {
  3813. // Make sure fake sink is created in plug-in scenario
  3814. drm_new_conn_state = drm_atomic_get_new_connector_state(state,
  3815. &aconnector->base);
  3816. drm_old_conn_state = drm_atomic_get_old_connector_state(state,
  3817. &aconnector->base);
  3818. if (IS_ERR(drm_new_conn_state)) {
  3819. ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
  3820. break;
  3821. }
  3822. dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
  3823. dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
  3824. new_stream = create_stream_for_sink(aconnector,
  3825. &new_crtc_state->mode,
  3826. dm_new_conn_state);
  3827. /*
  3828. * we can have no stream on ACTION_SET if a display
  3829. * was disconnected during S3, in this case it not and
  3830. * error, the OS will be updated after detection, and
  3831. * do the right thing on next atomic commit
  3832. */
  3833. if (!new_stream) {
  3834. DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
  3835. __func__, acrtc->base.base.id);
  3836. break;
  3837. }
  3838. if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
  3839. dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
  3840. new_crtc_state->mode_changed = false;
  3841. DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
  3842. new_crtc_state->mode_changed);
  3843. }
  3844. }
  3845. if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
  3846. goto next_crtc;
  3847. DRM_DEBUG_DRIVER(
  3848. "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
  3849. "planes_changed:%d, mode_changed:%d,active_changed:%d,"
  3850. "connectors_changed:%d\n",
  3851. acrtc->crtc_id,
  3852. new_crtc_state->enable,
  3853. new_crtc_state->active,
  3854. new_crtc_state->planes_changed,
  3855. new_crtc_state->mode_changed,
  3856. new_crtc_state->active_changed,
  3857. new_crtc_state->connectors_changed);
  3858. /* Remove stream for any changed/disabled CRTC */
  3859. if (!enable) {
  3860. if (!dm_old_crtc_state->stream)
  3861. goto next_crtc;
  3862. DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
  3863. crtc->base.id);
  3864. /* i.e. reset mode */
  3865. if (dc_remove_stream_from_ctx(
  3866. dc,
  3867. dm_state->context,
  3868. dm_old_crtc_state->stream) != DC_OK) {
  3869. ret = -EINVAL;
  3870. goto fail;
  3871. }
  3872. dc_stream_release(dm_old_crtc_state->stream);
  3873. dm_new_crtc_state->stream = NULL;
  3874. *lock_and_validation_needed = true;
  3875. } else {/* Add stream for any updated/enabled CRTC */
  3876. /*
  3877. * Quick fix to prevent NULL pointer on new_stream when
  3878. * added MST connectors not found in existing crtc_state in the chained mode
  3879. * TODO: need to dig out the root cause of that
  3880. */
  3881. if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
  3882. goto next_crtc;
  3883. if (modereset_required(new_crtc_state))
  3884. goto next_crtc;
  3885. if (modeset_required(new_crtc_state, new_stream,
  3886. dm_old_crtc_state->stream)) {
  3887. WARN_ON(dm_new_crtc_state->stream);
  3888. dm_new_crtc_state->stream = new_stream;
  3889. dc_stream_retain(new_stream);
  3890. DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
  3891. crtc->base.id);
  3892. if (dc_add_stream_to_ctx(
  3893. dc,
  3894. dm_state->context,
  3895. dm_new_crtc_state->stream) != DC_OK) {
  3896. ret = -EINVAL;
  3897. goto fail;
  3898. }
  3899. *lock_and_validation_needed = true;
  3900. }
  3901. }
  3902. next_crtc:
  3903. /* Release extra reference */
  3904. if (new_stream)
  3905. dc_stream_release(new_stream);
  3906. /*
  3907. * We want to do dc stream updates that do not require a
  3908. * full modeset below.
  3909. */
  3910. if (!(enable && aconnector && new_crtc_state->enable &&
  3911. new_crtc_state->active))
  3912. continue;
  3913. /*
  3914. * Given above conditions, the dc state cannot be NULL because:
  3915. * 1. We're in the process of enabling CRTCs (just been added
  3916. * to the dc context, or already is on the context)
  3917. * 2. Has a valid connector attached, and
  3918. * 3. Is currently active and enabled.
  3919. * => The dc stream state currently exists.
  3920. */
  3921. BUG_ON(dm_new_crtc_state->stream == NULL);
  3922. /* Scaling or underscan settings */
  3923. if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
  3924. update_stream_scaling_settings(
  3925. &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
  3926. /*
  3927. * Color management settings. We also update color properties
  3928. * when a modeset is needed, to ensure it gets reprogrammed.
  3929. */
  3930. if (dm_new_crtc_state->base.color_mgmt_changed ||
  3931. drm_atomic_crtc_needs_modeset(new_crtc_state)) {
  3932. ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
  3933. if (ret)
  3934. goto fail;
  3935. amdgpu_dm_set_ctm(dm_new_crtc_state);
  3936. }
  3937. }
  3938. return ret;
  3939. fail:
  3940. if (new_stream)
  3941. dc_stream_release(new_stream);
  3942. return ret;
  3943. }
  3944. static int dm_update_planes_state(struct dc *dc,
  3945. struct drm_atomic_state *state,
  3946. bool enable,
  3947. bool *lock_and_validation_needed)
  3948. {
  3949. struct drm_crtc *new_plane_crtc, *old_plane_crtc;
  3950. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  3951. struct drm_plane *plane;
  3952. struct drm_plane_state *old_plane_state, *new_plane_state;
  3953. struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
  3954. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  3955. struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
  3956. int i ;
  3957. /* TODO return page_flip_needed() function */
  3958. bool pflip_needed = !state->allow_modeset;
  3959. int ret = 0;
  3960. /* Add new planes, in reverse order as DC expectation */
  3961. for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
  3962. new_plane_crtc = new_plane_state->crtc;
  3963. old_plane_crtc = old_plane_state->crtc;
  3964. dm_new_plane_state = to_dm_plane_state(new_plane_state);
  3965. dm_old_plane_state = to_dm_plane_state(old_plane_state);
  3966. /*TODO Implement atomic check for cursor plane */
  3967. if (plane->type == DRM_PLANE_TYPE_CURSOR)
  3968. continue;
  3969. /* Remove any changed/removed planes */
  3970. if (!enable) {
  3971. if (pflip_needed &&
  3972. plane->type != DRM_PLANE_TYPE_OVERLAY)
  3973. continue;
  3974. if (!old_plane_crtc)
  3975. continue;
  3976. old_crtc_state = drm_atomic_get_old_crtc_state(
  3977. state, old_plane_crtc);
  3978. dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  3979. if (!dm_old_crtc_state->stream)
  3980. continue;
  3981. DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
  3982. plane->base.id, old_plane_crtc->base.id);
  3983. if (!dc_remove_plane_from_context(
  3984. dc,
  3985. dm_old_crtc_state->stream,
  3986. dm_old_plane_state->dc_state,
  3987. dm_state->context)) {
  3988. ret = EINVAL;
  3989. return ret;
  3990. }
  3991. dc_plane_state_release(dm_old_plane_state->dc_state);
  3992. dm_new_plane_state->dc_state = NULL;
  3993. *lock_and_validation_needed = true;
  3994. } else { /* Add new planes */
  3995. struct dc_plane_state *dc_new_plane_state;
  3996. if (drm_atomic_plane_disabling(plane->state, new_plane_state))
  3997. continue;
  3998. if (!new_plane_crtc)
  3999. continue;
  4000. new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
  4001. dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
  4002. if (!dm_new_crtc_state->stream)
  4003. continue;
  4004. if (pflip_needed &&
  4005. plane->type != DRM_PLANE_TYPE_OVERLAY)
  4006. continue;
  4007. WARN_ON(dm_new_plane_state->dc_state);
  4008. dc_new_plane_state = dc_create_plane_state(dc);
  4009. if (!dc_new_plane_state)
  4010. return -ENOMEM;
  4011. DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
  4012. plane->base.id, new_plane_crtc->base.id);
  4013. ret = fill_plane_attributes(
  4014. new_plane_crtc->dev->dev_private,
  4015. dc_new_plane_state,
  4016. new_plane_state,
  4017. new_crtc_state);
  4018. if (ret) {
  4019. dc_plane_state_release(dc_new_plane_state);
  4020. return ret;
  4021. }
  4022. /*
  4023. * Any atomic check errors that occur after this will
  4024. * not need a release. The plane state will be attached
  4025. * to the stream, and therefore part of the atomic
  4026. * state. It'll be released when the atomic state is
  4027. * cleaned.
  4028. */
  4029. if (!dc_add_plane_to_context(
  4030. dc,
  4031. dm_new_crtc_state->stream,
  4032. dc_new_plane_state,
  4033. dm_state->context)) {
  4034. dc_plane_state_release(dc_new_plane_state);
  4035. return -EINVAL;
  4036. }
  4037. dm_new_plane_state->dc_state = dc_new_plane_state;
  4038. /* Tell DC to do a full surface update every time there
  4039. * is a plane change. Inefficient, but works for now.
  4040. */
  4041. dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
  4042. *lock_and_validation_needed = true;
  4043. }
  4044. }
  4045. return ret;
  4046. }
  4047. static int amdgpu_dm_atomic_check(struct drm_device *dev,
  4048. struct drm_atomic_state *state)
  4049. {
  4050. struct amdgpu_device *adev = dev->dev_private;
  4051. struct dc *dc = adev->dm.dc;
  4052. struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
  4053. struct drm_connector *connector;
  4054. struct drm_connector_state *old_con_state, *new_con_state;
  4055. struct drm_crtc *crtc;
  4056. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  4057. int ret, i;
  4058. /*
  4059. * This bool will be set for true for any modeset/reset
  4060. * or plane update which implies non fast surface update.
  4061. */
  4062. bool lock_and_validation_needed = false;
  4063. ret = drm_atomic_helper_check_modeset(dev, state);
  4064. if (ret)
  4065. goto fail;
  4066. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  4067. if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
  4068. !new_crtc_state->color_mgmt_changed)
  4069. continue;
  4070. if (!new_crtc_state->enable)
  4071. continue;
  4072. ret = drm_atomic_add_affected_connectors(state, crtc);
  4073. if (ret)
  4074. return ret;
  4075. ret = drm_atomic_add_affected_planes(state, crtc);
  4076. if (ret)
  4077. goto fail;
  4078. }
  4079. dm_state->context = dc_create_state();
  4080. ASSERT(dm_state->context);
  4081. dc_resource_state_copy_construct_current(dc, dm_state->context);
  4082. /* Remove exiting planes if they are modified */
  4083. ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
  4084. if (ret) {
  4085. goto fail;
  4086. }
  4087. /* Disable all crtcs which require disable */
  4088. ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
  4089. if (ret) {
  4090. goto fail;
  4091. }
  4092. /* Enable all crtcs which require enable */
  4093. ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
  4094. if (ret) {
  4095. goto fail;
  4096. }
  4097. /* Add new/modified planes */
  4098. ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
  4099. if (ret) {
  4100. goto fail;
  4101. }
  4102. /* Run this here since we want to validate the streams we created */
  4103. ret = drm_atomic_helper_check_planes(dev, state);
  4104. if (ret)
  4105. goto fail;
  4106. /* Check scaling and underscan changes*/
  4107. /*TODO Removed scaling changes validation due to inability to commit
  4108. * new stream into context w\o causing full reset. Need to
  4109. * decide how to handle.
  4110. */
  4111. for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
  4112. struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
  4113. struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
  4114. struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
  4115. /* Skip any modesets/resets */
  4116. if (!acrtc || drm_atomic_crtc_needs_modeset(
  4117. drm_atomic_get_new_crtc_state(state, &acrtc->base)))
  4118. continue;
  4119. /* Skip any thing not scale or underscan changes */
  4120. if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
  4121. continue;
  4122. lock_and_validation_needed = true;
  4123. }
  4124. /*
  4125. * For full updates case when
  4126. * removing/adding/updating streams on once CRTC while flipping
  4127. * on another CRTC,
  4128. * acquiring global lock will guarantee that any such full
  4129. * update commit
  4130. * will wait for completion of any outstanding flip using DRMs
  4131. * synchronization events.
  4132. */
  4133. if (lock_and_validation_needed) {
  4134. ret = do_aquire_global_lock(dev, state);
  4135. if (ret)
  4136. goto fail;
  4137. if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
  4138. ret = -EINVAL;
  4139. goto fail;
  4140. }
  4141. }
  4142. /* Must be success */
  4143. WARN_ON(ret);
  4144. return ret;
  4145. fail:
  4146. if (ret == -EDEADLK)
  4147. DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
  4148. else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
  4149. DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
  4150. else
  4151. DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
  4152. return ret;
  4153. }
  4154. static bool is_dp_capable_without_timing_msa(struct dc *dc,
  4155. struct amdgpu_dm_connector *amdgpu_dm_connector)
  4156. {
  4157. uint8_t dpcd_data;
  4158. bool capable = false;
  4159. if (amdgpu_dm_connector->dc_link &&
  4160. dm_helpers_dp_read_dpcd(
  4161. NULL,
  4162. amdgpu_dm_connector->dc_link,
  4163. DP_DOWN_STREAM_PORT_COUNT,
  4164. &dpcd_data,
  4165. sizeof(dpcd_data))) {
  4166. capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
  4167. }
  4168. return capable;
  4169. }
  4170. void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
  4171. struct edid *edid)
  4172. {
  4173. int i;
  4174. bool edid_check_required;
  4175. struct detailed_timing *timing;
  4176. struct detailed_non_pixel *data;
  4177. struct detailed_data_monitor_range *range;
  4178. struct amdgpu_dm_connector *amdgpu_dm_connector =
  4179. to_amdgpu_dm_connector(connector);
  4180. struct dm_connector_state *dm_con_state;
  4181. struct drm_device *dev = connector->dev;
  4182. struct amdgpu_device *adev = dev->dev_private;
  4183. if (!connector->state) {
  4184. DRM_ERROR("%s - Connector has no state", __func__);
  4185. return;
  4186. }
  4187. dm_con_state = to_dm_connector_state(connector->state);
  4188. edid_check_required = false;
  4189. if (!amdgpu_dm_connector->dc_sink) {
  4190. DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
  4191. return;
  4192. }
  4193. if (!adev->dm.freesync_module)
  4194. return;
  4195. /*
  4196. * if edid non zero restrict freesync only for dp and edp
  4197. */
  4198. if (edid) {
  4199. if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
  4200. || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
  4201. edid_check_required = is_dp_capable_without_timing_msa(
  4202. adev->dm.dc,
  4203. amdgpu_dm_connector);
  4204. }
  4205. }
  4206. dm_con_state->freesync_capable = false;
  4207. if (edid_check_required == true && (edid->version > 1 ||
  4208. (edid->version == 1 && edid->revision > 1))) {
  4209. for (i = 0; i < 4; i++) {
  4210. timing = &edid->detailed_timings[i];
  4211. data = &timing->data.other_data;
  4212. range = &data->data.range;
  4213. /*
  4214. * Check if monitor has continuous frequency mode
  4215. */
  4216. if (data->type != EDID_DETAIL_MONITOR_RANGE)
  4217. continue;
  4218. /*
  4219. * Check for flag range limits only. If flag == 1 then
  4220. * no additional timing information provided.
  4221. * Default GTF, GTF Secondary curve and CVT are not
  4222. * supported
  4223. */
  4224. if (range->flags != 1)
  4225. continue;
  4226. amdgpu_dm_connector->min_vfreq = range->min_vfreq;
  4227. amdgpu_dm_connector->max_vfreq = range->max_vfreq;
  4228. amdgpu_dm_connector->pixel_clock_mhz =
  4229. range->pixel_clock_mhz * 10;
  4230. break;
  4231. }
  4232. if (amdgpu_dm_connector->max_vfreq -
  4233. amdgpu_dm_connector->min_vfreq > 10) {
  4234. amdgpu_dm_connector->caps.supported = true;
  4235. amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
  4236. amdgpu_dm_connector->min_vfreq * 1000000;
  4237. amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
  4238. amdgpu_dm_connector->max_vfreq * 1000000;
  4239. dm_con_state->freesync_capable = true;
  4240. }
  4241. }
  4242. /*
  4243. * TODO figure out how to notify user-mode or DRM of freesync caps
  4244. * once we figure out how to deal with freesync in an upstreamable
  4245. * fashion
  4246. */
  4247. }
  4248. void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
  4249. {
  4250. /*
  4251. * TODO fill in once we figure out how to deal with freesync in
  4252. * an upstreamable fashion
  4253. */
  4254. }