lpd270.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/gpio.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/syscore_ops.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/sched.h>
  21. #include <linux/bitops.h>
  22. #include <linux/fb.h>
  23. #include <linux/ioport.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/pwm_backlight.h>
  27. #include <linux/smc91x.h>
  28. #include <asm/types.h>
  29. #include <asm/setup.h>
  30. #include <asm/memory.h>
  31. #include <asm/mach-types.h>
  32. #include <mach/hardware.h>
  33. #include <asm/irq.h>
  34. #include <asm/sizes.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <asm/mach/flash.h>
  39. #include <mach/pxa27x.h>
  40. #include <mach/lpd270.h>
  41. #include <mach/audio.h>
  42. #include <linux/platform_data/video-pxafb.h>
  43. #include <linux/platform_data/mmc-pxamci.h>
  44. #include <linux/platform_data/irda-pxaficp.h>
  45. #include <linux/platform_data/usb-ohci-pxa27x.h>
  46. #include <mach/smemc.h>
  47. #include "generic.h"
  48. #include "devices.h"
  49. static unsigned long lpd270_pin_config[] __initdata = {
  50. /* Chip Selects */
  51. GPIO15_nCS_1, /* Mainboard Flash */
  52. GPIO78_nCS_2, /* CPLD + Ethernet */
  53. /* LCD - 16bpp Active TFT */
  54. GPIO58_LCD_LDD_0,
  55. GPIO59_LCD_LDD_1,
  56. GPIO60_LCD_LDD_2,
  57. GPIO61_LCD_LDD_3,
  58. GPIO62_LCD_LDD_4,
  59. GPIO63_LCD_LDD_5,
  60. GPIO64_LCD_LDD_6,
  61. GPIO65_LCD_LDD_7,
  62. GPIO66_LCD_LDD_8,
  63. GPIO67_LCD_LDD_9,
  64. GPIO68_LCD_LDD_10,
  65. GPIO69_LCD_LDD_11,
  66. GPIO70_LCD_LDD_12,
  67. GPIO71_LCD_LDD_13,
  68. GPIO72_LCD_LDD_14,
  69. GPIO73_LCD_LDD_15,
  70. GPIO74_LCD_FCLK,
  71. GPIO75_LCD_LCLK,
  72. GPIO76_LCD_PCLK,
  73. GPIO77_LCD_BIAS,
  74. GPIO16_PWM0_OUT, /* Backlight */
  75. /* USB Host */
  76. GPIO88_USBH1_PWR,
  77. GPIO89_USBH1_PEN,
  78. /* AC97 */
  79. GPIO28_AC97_BITCLK,
  80. GPIO29_AC97_SDATA_IN_0,
  81. GPIO30_AC97_SDATA_OUT,
  82. GPIO31_AC97_SYNC,
  83. GPIO45_AC97_SYSCLK,
  84. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  85. };
  86. static unsigned int lpd270_irq_enabled;
  87. static void lpd270_mask_irq(struct irq_data *d)
  88. {
  89. int lpd270_irq = d->irq - LPD270_IRQ(0);
  90. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  91. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  92. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  93. }
  94. static void lpd270_unmask_irq(struct irq_data *d)
  95. {
  96. int lpd270_irq = d->irq - LPD270_IRQ(0);
  97. lpd270_irq_enabled |= 1 << lpd270_irq;
  98. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  99. }
  100. static struct irq_chip lpd270_irq_chip = {
  101. .name = "CPLD",
  102. .irq_ack = lpd270_mask_irq,
  103. .irq_mask = lpd270_mask_irq,
  104. .irq_unmask = lpd270_unmask_irq,
  105. };
  106. static void lpd270_irq_handler(struct irq_desc *desc)
  107. {
  108. unsigned int irq;
  109. unsigned long pending;
  110. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  111. do {
  112. /* clear useless edge notification */
  113. desc->irq_data.chip->irq_ack(&desc->irq_data);
  114. if (likely(pending)) {
  115. irq = LPD270_IRQ(0) + __ffs(pending);
  116. generic_handle_irq(irq);
  117. pending = __raw_readw(LPD270_INT_STATUS) &
  118. lpd270_irq_enabled;
  119. }
  120. } while (pending);
  121. }
  122. static void __init lpd270_init_irq(void)
  123. {
  124. int irq;
  125. pxa27x_init_irq();
  126. __raw_writew(0, LPD270_INT_MASK);
  127. __raw_writew(0, LPD270_INT_STATUS);
  128. /* setup extra LogicPD PXA270 irqs */
  129. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  130. irq_set_chip_and_handler(irq, &lpd270_irq_chip,
  131. handle_level_irq);
  132. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  133. }
  134. irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
  135. irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
  136. }
  137. #ifdef CONFIG_PM
  138. static void lpd270_irq_resume(void)
  139. {
  140. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  141. }
  142. static struct syscore_ops lpd270_irq_syscore_ops = {
  143. .resume = lpd270_irq_resume,
  144. };
  145. static int __init lpd270_irq_device_init(void)
  146. {
  147. if (machine_is_logicpd_pxa270()) {
  148. register_syscore_ops(&lpd270_irq_syscore_ops);
  149. return 0;
  150. }
  151. return -ENODEV;
  152. }
  153. device_initcall(lpd270_irq_device_init);
  154. #endif
  155. static struct resource smc91x_resources[] = {
  156. [0] = {
  157. .start = LPD270_ETH_PHYS,
  158. .end = (LPD270_ETH_PHYS + 0xfffff),
  159. .flags = IORESOURCE_MEM,
  160. },
  161. [1] = {
  162. .start = LPD270_ETHERNET_IRQ,
  163. .end = LPD270_ETHERNET_IRQ,
  164. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  165. },
  166. };
  167. struct smc91x_platdata smc91x_platdata = {
  168. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  169. };
  170. static struct platform_device smc91x_device = {
  171. .name = "smc91x",
  172. .id = 0,
  173. .num_resources = ARRAY_SIZE(smc91x_resources),
  174. .resource = smc91x_resources,
  175. .dev.platform_data = &smc91x_platdata,
  176. };
  177. static struct resource lpd270_flash_resources[] = {
  178. [0] = {
  179. .start = PXA_CS0_PHYS,
  180. .end = PXA_CS0_PHYS + SZ_64M - 1,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. [1] = {
  184. .start = PXA_CS1_PHYS,
  185. .end = PXA_CS1_PHYS + SZ_64M - 1,
  186. .flags = IORESOURCE_MEM,
  187. },
  188. };
  189. static struct mtd_partition lpd270_flash0_partitions[] = {
  190. {
  191. .name = "Bootloader",
  192. .size = 0x00040000,
  193. .offset = 0,
  194. .mask_flags = MTD_WRITEABLE /* force read-only */
  195. }, {
  196. .name = "Kernel",
  197. .size = 0x00400000,
  198. .offset = 0x00040000,
  199. }, {
  200. .name = "Filesystem",
  201. .size = MTDPART_SIZ_FULL,
  202. .offset = 0x00440000
  203. },
  204. };
  205. static struct flash_platform_data lpd270_flash_data[2] = {
  206. {
  207. .name = "processor-flash",
  208. .map_name = "cfi_probe",
  209. .parts = lpd270_flash0_partitions,
  210. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  211. }, {
  212. .name = "mainboard-flash",
  213. .map_name = "cfi_probe",
  214. .parts = NULL,
  215. .nr_parts = 0,
  216. }
  217. };
  218. static struct platform_device lpd270_flash_device[2] = {
  219. {
  220. .name = "pxa2xx-flash",
  221. .id = 0,
  222. .dev = {
  223. .platform_data = &lpd270_flash_data[0],
  224. },
  225. .resource = &lpd270_flash_resources[0],
  226. .num_resources = 1,
  227. }, {
  228. .name = "pxa2xx-flash",
  229. .id = 1,
  230. .dev = {
  231. .platform_data = &lpd270_flash_data[1],
  232. },
  233. .resource = &lpd270_flash_resources[1],
  234. .num_resources = 1,
  235. },
  236. };
  237. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  238. .pwm_id = 0,
  239. .max_brightness = 1,
  240. .dft_brightness = 1,
  241. .pwm_period_ns = 78770,
  242. .enable_gpio = -1,
  243. };
  244. static struct platform_device lpd270_backlight_device = {
  245. .name = "pwm-backlight",
  246. .dev = {
  247. .parent = &pxa27x_device_pwm0.dev,
  248. .platform_data = &lpd270_backlight_data,
  249. },
  250. };
  251. /* 5.7" TFT QVGA (LoLo display number 1) */
  252. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  253. .pixclock = 150000,
  254. .xres = 320,
  255. .yres = 240,
  256. .bpp = 16,
  257. .hsync_len = 0x14,
  258. .left_margin = 0x28,
  259. .right_margin = 0x0a,
  260. .vsync_len = 0x02,
  261. .upper_margin = 0x08,
  262. .lower_margin = 0x14,
  263. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  264. };
  265. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  266. .modes = &sharp_lq057q3dc02_mode,
  267. .num_modes = 1,
  268. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  269. LCD_ALTERNATE_MAPPING,
  270. };
  271. /* 12.1" TFT SVGA (LoLo display number 2) */
  272. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  273. .pixclock = 50000,
  274. .xres = 800,
  275. .yres = 600,
  276. .bpp = 16,
  277. .hsync_len = 0x05,
  278. .left_margin = 0x52,
  279. .right_margin = 0x05,
  280. .vsync_len = 0x04,
  281. .upper_margin = 0x14,
  282. .lower_margin = 0x0a,
  283. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  284. };
  285. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  286. .modes = &sharp_lq121s1dg31_mode,
  287. .num_modes = 1,
  288. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  289. LCD_ALTERNATE_MAPPING,
  290. };
  291. /* 3.6" TFT QVGA (LoLo display number 3) */
  292. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  293. .pixclock = 150000,
  294. .xres = 320,
  295. .yres = 240,
  296. .bpp = 16,
  297. .hsync_len = 0x0e,
  298. .left_margin = 0x04,
  299. .right_margin = 0x0a,
  300. .vsync_len = 0x03,
  301. .upper_margin = 0x03,
  302. .lower_margin = 0x03,
  303. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  304. };
  305. static struct pxafb_mach_info sharp_lq036q1da01 = {
  306. .modes = &sharp_lq036q1da01_mode,
  307. .num_modes = 1,
  308. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  309. LCD_ALTERNATE_MAPPING,
  310. };
  311. /* 6.4" TFT VGA (LoLo display number 5) */
  312. static struct pxafb_mode_info sharp_lq64d343_mode = {
  313. .pixclock = 25000,
  314. .xres = 640,
  315. .yres = 480,
  316. .bpp = 16,
  317. .hsync_len = 0x31,
  318. .left_margin = 0x89,
  319. .right_margin = 0x19,
  320. .vsync_len = 0x12,
  321. .upper_margin = 0x22,
  322. .lower_margin = 0x00,
  323. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  324. };
  325. static struct pxafb_mach_info sharp_lq64d343 = {
  326. .modes = &sharp_lq64d343_mode,
  327. .num_modes = 1,
  328. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  329. LCD_ALTERNATE_MAPPING,
  330. };
  331. /* 10.4" TFT VGA (LoLo display number 7) */
  332. static struct pxafb_mode_info sharp_lq10d368_mode = {
  333. .pixclock = 25000,
  334. .xres = 640,
  335. .yres = 480,
  336. .bpp = 16,
  337. .hsync_len = 0x31,
  338. .left_margin = 0x89,
  339. .right_margin = 0x19,
  340. .vsync_len = 0x12,
  341. .upper_margin = 0x22,
  342. .lower_margin = 0x00,
  343. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  344. };
  345. static struct pxafb_mach_info sharp_lq10d368 = {
  346. .modes = &sharp_lq10d368_mode,
  347. .num_modes = 1,
  348. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  349. LCD_ALTERNATE_MAPPING,
  350. };
  351. /* 3.5" TFT QVGA (LoLo display number 8) */
  352. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  353. .pixclock = 150000,
  354. .xres = 240,
  355. .yres = 320,
  356. .bpp = 16,
  357. .hsync_len = 0x0e,
  358. .left_margin = 0x0a,
  359. .right_margin = 0x0a,
  360. .vsync_len = 0x03,
  361. .upper_margin = 0x05,
  362. .lower_margin = 0x14,
  363. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  364. };
  365. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  366. .modes = &sharp_lq035q7db02_20_mode,
  367. .num_modes = 1,
  368. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  369. LCD_ALTERNATE_MAPPING,
  370. };
  371. static struct pxafb_mach_info *lpd270_lcd_to_use;
  372. static int __init lpd270_set_lcd(char *str)
  373. {
  374. if (!strncasecmp(str, "lq057q3dc02", 11)) {
  375. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  376. } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
  377. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  378. } else if (!strncasecmp(str, "lq036q1da01", 11)) {
  379. lpd270_lcd_to_use = &sharp_lq036q1da01;
  380. } else if (!strncasecmp(str, "lq64d343", 8)) {
  381. lpd270_lcd_to_use = &sharp_lq64d343;
  382. } else if (!strncasecmp(str, "lq10d368", 8)) {
  383. lpd270_lcd_to_use = &sharp_lq10d368;
  384. } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
  385. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  386. } else {
  387. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  388. }
  389. return 1;
  390. }
  391. __setup("lcd=", lpd270_set_lcd);
  392. static struct platform_device *platform_devices[] __initdata = {
  393. &smc91x_device,
  394. &lpd270_backlight_device,
  395. &lpd270_flash_device[0],
  396. &lpd270_flash_device[1],
  397. };
  398. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  399. .port_mode = PMM_PERPORT_MODE,
  400. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  401. };
  402. static void __init lpd270_init(void)
  403. {
  404. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  405. pxa_set_ffuart_info(NULL);
  406. pxa_set_btuart_info(NULL);
  407. pxa_set_stuart_info(NULL);
  408. lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
  409. lpd270_flash_data[1].width = 4;
  410. /*
  411. * System bus arbiter setting:
  412. * - Core_Park
  413. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  414. */
  415. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  416. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  417. pxa_set_ac97_info(NULL);
  418. if (lpd270_lcd_to_use != NULL)
  419. pxa_set_fb_info(NULL, lpd270_lcd_to_use);
  420. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  421. }
  422. static struct map_desc lpd270_io_desc[] __initdata = {
  423. {
  424. .virtual = (unsigned long)LPD270_CPLD_VIRT,
  425. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  426. .length = LPD270_CPLD_SIZE,
  427. .type = MT_DEVICE,
  428. },
  429. };
  430. static void __init lpd270_map_io(void)
  431. {
  432. pxa27x_map_io();
  433. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  434. /* for use I SRAM as framebuffer. */
  435. PSLR |= 0x00000F04;
  436. PCFR = 0x00000066;
  437. }
  438. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  439. /* Maintainer: Peter Barada */
  440. .atag_offset = 0x100,
  441. .map_io = lpd270_map_io,
  442. .nr_irqs = LPD270_NR_IRQS,
  443. .init_irq = lpd270_init_irq,
  444. .handle_irq = pxa27x_handle_irq,
  445. .init_time = pxa_timer_init,
  446. .init_machine = lpd270_init,
  447. .restart = pxa_restart,
  448. MACHINE_END