amdgpu_gtt_mgr.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258
  1. /*
  2. * Copyright 2016 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Christian König
  23. */
  24. #include <drm/drmP.h>
  25. #include "amdgpu.h"
  26. struct amdgpu_gtt_mgr {
  27. struct drm_mm mm;
  28. spinlock_t lock;
  29. uint64_t available;
  30. };
  31. /**
  32. * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
  33. *
  34. * @man: TTM memory type manager
  35. * @p_size: maximum size of GTT
  36. *
  37. * Allocate and initialize the GTT manager.
  38. */
  39. static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
  40. unsigned long p_size)
  41. {
  42. struct amdgpu_gtt_mgr *mgr;
  43. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  44. if (!mgr)
  45. return -ENOMEM;
  46. drm_mm_init(&mgr->mm, 0, p_size);
  47. spin_lock_init(&mgr->lock);
  48. mgr->available = p_size;
  49. man->priv = mgr;
  50. return 0;
  51. }
  52. /**
  53. * amdgpu_gtt_mgr_fini - free and destroy GTT manager
  54. *
  55. * @man: TTM memory type manager
  56. *
  57. * Destroy and free the GTT manager, returns -EBUSY if ranges are still
  58. * allocated inside it.
  59. */
  60. static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
  61. {
  62. struct amdgpu_gtt_mgr *mgr = man->priv;
  63. spin_lock(&mgr->lock);
  64. if (!drm_mm_clean(&mgr->mm)) {
  65. spin_unlock(&mgr->lock);
  66. return -EBUSY;
  67. }
  68. drm_mm_takedown(&mgr->mm);
  69. spin_unlock(&mgr->lock);
  70. kfree(mgr);
  71. man->priv = NULL;
  72. return 0;
  73. }
  74. /**
  75. * amdgpu_gtt_mgr_alloc - allocate new ranges
  76. *
  77. * @man: TTM memory type manager
  78. * @tbo: TTM BO we need this range for
  79. * @place: placement flags and restrictions
  80. * @mem: the resulting mem object
  81. *
  82. * Allocate the address space for a node.
  83. */
  84. int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
  85. struct ttm_buffer_object *tbo,
  86. const struct ttm_place *place,
  87. struct ttm_mem_reg *mem)
  88. {
  89. struct amdgpu_gtt_mgr *mgr = man->priv;
  90. struct drm_mm_node *node = mem->mm_node;
  91. enum drm_mm_insert_mode mode;
  92. unsigned long fpfn, lpfn;
  93. int r;
  94. if (node->start != AMDGPU_BO_INVALID_OFFSET)
  95. return 0;
  96. if (place)
  97. fpfn = place->fpfn;
  98. else
  99. fpfn = 0;
  100. if (place && place->lpfn)
  101. lpfn = place->lpfn;
  102. else
  103. lpfn = man->size;
  104. mode = DRM_MM_INSERT_BEST;
  105. if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
  106. mode = DRM_MM_INSERT_HIGH;
  107. spin_lock(&mgr->lock);
  108. r = drm_mm_insert_node_in_range(&mgr->mm, node,
  109. mem->num_pages, mem->page_alignment, 0,
  110. fpfn, lpfn, mode);
  111. spin_unlock(&mgr->lock);
  112. if (!r) {
  113. mem->start = node->start;
  114. if (&tbo->mem == mem)
  115. tbo->offset = (tbo->mem.start << PAGE_SHIFT) +
  116. tbo->bdev->man[tbo->mem.mem_type].gpu_offset;
  117. }
  118. return r;
  119. }
  120. void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager *man)
  121. {
  122. struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
  123. struct amdgpu_gtt_mgr *mgr = man->priv;
  124. seq_printf(m, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n",
  125. man->size, mgr->available, (u64)atomic64_read(&adev->gtt_usage) >> 20);
  126. }
  127. /**
  128. * amdgpu_gtt_mgr_new - allocate a new node
  129. *
  130. * @man: TTM memory type manager
  131. * @tbo: TTM BO we need this range for
  132. * @place: placement flags and restrictions
  133. * @mem: the resulting mem object
  134. *
  135. * Dummy, allocate the node but no space for it yet.
  136. */
  137. static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
  138. struct ttm_buffer_object *tbo,
  139. const struct ttm_place *place,
  140. struct ttm_mem_reg *mem)
  141. {
  142. struct amdgpu_gtt_mgr *mgr = man->priv;
  143. struct drm_mm_node *node;
  144. int r;
  145. spin_lock(&mgr->lock);
  146. if (mgr->available < mem->num_pages) {
  147. spin_unlock(&mgr->lock);
  148. return 0;
  149. }
  150. mgr->available -= mem->num_pages;
  151. spin_unlock(&mgr->lock);
  152. node = kzalloc(sizeof(*node), GFP_KERNEL);
  153. if (!node) {
  154. r = -ENOMEM;
  155. goto err_out;
  156. }
  157. node->start = AMDGPU_BO_INVALID_OFFSET;
  158. node->size = mem->num_pages;
  159. mem->mm_node = node;
  160. if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
  161. r = amdgpu_gtt_mgr_alloc(man, tbo, place, mem);
  162. if (unlikely(r)) {
  163. kfree(node);
  164. mem->mm_node = NULL;
  165. r = 0;
  166. goto err_out;
  167. }
  168. } else {
  169. mem->start = node->start;
  170. }
  171. return 0;
  172. err_out:
  173. spin_lock(&mgr->lock);
  174. mgr->available += mem->num_pages;
  175. spin_unlock(&mgr->lock);
  176. return r;
  177. }
  178. /**
  179. * amdgpu_gtt_mgr_del - free ranges
  180. *
  181. * @man: TTM memory type manager
  182. * @tbo: TTM BO we need this range for
  183. * @place: placement flags and restrictions
  184. * @mem: TTM memory object
  185. *
  186. * Free the allocated GTT again.
  187. */
  188. static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man,
  189. struct ttm_mem_reg *mem)
  190. {
  191. struct amdgpu_gtt_mgr *mgr = man->priv;
  192. struct drm_mm_node *node = mem->mm_node;
  193. if (!node)
  194. return;
  195. spin_lock(&mgr->lock);
  196. if (node->start != AMDGPU_BO_INVALID_OFFSET)
  197. drm_mm_remove_node(node);
  198. mgr->available += mem->num_pages;
  199. spin_unlock(&mgr->lock);
  200. kfree(node);
  201. mem->mm_node = NULL;
  202. }
  203. /**
  204. * amdgpu_gtt_mgr_debug - dump VRAM table
  205. *
  206. * @man: TTM memory type manager
  207. * @prefix: text prefix
  208. *
  209. * Dump the table content using printk.
  210. */
  211. static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man,
  212. const char *prefix)
  213. {
  214. struct amdgpu_gtt_mgr *mgr = man->priv;
  215. struct drm_printer p = drm_debug_printer(prefix);
  216. spin_lock(&mgr->lock);
  217. drm_mm_print(&mgr->mm, &p);
  218. spin_unlock(&mgr->lock);
  219. }
  220. const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = {
  221. .init = amdgpu_gtt_mgr_init,
  222. .takedown = amdgpu_gtt_mgr_fini,
  223. .get_node = amdgpu_gtt_mgr_new,
  224. .put_node = amdgpu_gtt_mgr_del,
  225. .debug = amdgpu_gtt_mgr_debug
  226. };