ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/err.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/fsl_devices.h>
  32. #include "ehci-fsl.h"
  33. /* configure so an HC device and id are always provided */
  34. /* always called with process context; sleeping is OK */
  35. /**
  36. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  37. * @drvier: Driver to be used for this HCD
  38. * @pdev: USB Host Controller being probed
  39. * Context: !in_interrupt()
  40. *
  41. * Allocates basic resources for this USB host controller.
  42. *
  43. */
  44. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  45. struct platform_device *pdev)
  46. {
  47. struct fsl_usb2_platform_data *pdata;
  48. struct usb_hcd *hcd;
  49. struct resource *res;
  50. int irq;
  51. int retval;
  52. pr_debug("initializing FSL-SOC USB Controller\n");
  53. /* Need platform data for setup */
  54. pdata = dev_get_platdata(&pdev->dev);
  55. if (!pdata) {
  56. dev_err(&pdev->dev,
  57. "No platform data for %s.\n", dev_name(&pdev->dev));
  58. return -ENODEV;
  59. }
  60. /*
  61. * This is a host mode driver, verify that we're supposed to be
  62. * in host mode.
  63. */
  64. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  66. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  67. dev_err(&pdev->dev,
  68. "Non Host Mode configured for %s. Wrong driver linked.\n",
  69. dev_name(&pdev->dev));
  70. return -ENODEV;
  71. }
  72. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  73. if (!res) {
  74. dev_err(&pdev->dev,
  75. "Found HC with no IRQ. Check %s setup!\n",
  76. dev_name(&pdev->dev));
  77. return -ENODEV;
  78. }
  79. irq = res->start;
  80. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  81. if (!hcd) {
  82. retval = -ENOMEM;
  83. goto err1;
  84. }
  85. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. hcd->regs = devm_ioremap_resource(&pdev->dev, res);
  87. if (IS_ERR(hcd->regs)) {
  88. retval = PTR_ERR(hcd->regs);
  89. goto err2;
  90. }
  91. hcd->rsrc_start = res->start;
  92. hcd->rsrc_len = resource_size(res);
  93. pdata->regs = hcd->regs;
  94. if (pdata->power_budget)
  95. hcd->power_budget = pdata->power_budget;
  96. /*
  97. * do platform specific init: check the clock, grab/config pins, etc.
  98. */
  99. if (pdata->init && pdata->init(pdev)) {
  100. retval = -ENODEV;
  101. goto err2;
  102. }
  103. /* Enable USB controller, 83xx or 8536 */
  104. if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
  105. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  106. /* Don't need to set host mode here. It will be done by tdi_reset() */
  107. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  108. if (retval != 0)
  109. goto err2;
  110. device_wakeup_enable(hcd->self.controller);
  111. #ifdef CONFIG_USB_OTG
  112. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  113. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  114. hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
  115. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
  116. hcd, ehci, hcd->usb_phy);
  117. if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
  118. retval = otg_set_host(hcd->usb_phy->otg,
  119. &ehci_to_hcd(ehci)->self);
  120. if (retval) {
  121. usb_put_phy(hcd->usb_phy);
  122. goto err2;
  123. }
  124. } else {
  125. dev_err(&pdev->dev, "can't find phy\n");
  126. retval = -ENODEV;
  127. goto err2;
  128. }
  129. }
  130. #endif
  131. return retval;
  132. err2:
  133. usb_put_hcd(hcd);
  134. err1:
  135. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  136. if (pdata->exit)
  137. pdata->exit(pdev);
  138. return retval;
  139. }
  140. /* may be called without controller electrically present */
  141. /* may be called with controller, bus, and devices active */
  142. /**
  143. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  144. * @dev: USB Host Controller being removed
  145. * Context: !in_interrupt()
  146. *
  147. * Reverses the effect of usb_hcd_fsl_probe().
  148. *
  149. */
  150. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  151. struct platform_device *pdev)
  152. {
  153. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  154. if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
  155. otg_set_host(hcd->usb_phy->otg, NULL);
  156. usb_put_phy(hcd->usb_phy);
  157. }
  158. usb_remove_hcd(hcd);
  159. /*
  160. * do platform specific un-initialization:
  161. * release iomux pins, disable clock, etc.
  162. */
  163. if (pdata->exit)
  164. pdata->exit(pdev);
  165. usb_put_hcd(hcd);
  166. }
  167. static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
  168. enum fsl_usb2_phy_modes phy_mode,
  169. unsigned int port_offset)
  170. {
  171. u32 portsc;
  172. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  173. void __iomem *non_ehci = hcd->regs;
  174. struct device *dev = hcd->self.controller;
  175. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  176. if (pdata->controller_ver < 0) {
  177. dev_warn(hcd->self.controller, "Could not get controller version\n");
  178. return -ENODEV;
  179. }
  180. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  181. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  182. switch (phy_mode) {
  183. case FSL_USB2_PHY_ULPI:
  184. if (pdata->have_sysif_regs && pdata->controller_ver) {
  185. /* controller version 1.6 or above */
  186. clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  187. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  188. ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
  189. }
  190. portsc |= PORT_PTS_ULPI;
  191. break;
  192. case FSL_USB2_PHY_SERIAL:
  193. portsc |= PORT_PTS_SERIAL;
  194. break;
  195. case FSL_USB2_PHY_UTMI_WIDE:
  196. portsc |= PORT_PTS_PTW;
  197. /* fall through */
  198. case FSL_USB2_PHY_UTMI:
  199. if (pdata->have_sysif_regs && pdata->controller_ver) {
  200. /* controller version 1.6 or above */
  201. setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  202. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  203. become stable - 10ms*/
  204. }
  205. /* enable UTMI PHY */
  206. if (pdata->have_sysif_regs)
  207. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  208. CTRL_UTMI_PHY_EN);
  209. portsc |= PORT_PTS_UTMI;
  210. break;
  211. case FSL_USB2_PHY_NONE:
  212. break;
  213. }
  214. if (pdata->have_sysif_regs &&
  215. pdata->controller_ver > FSL_USB_VER_1_6 &&
  216. (phy_mode == FSL_USB2_PHY_ULPI)) {
  217. /* check PHY_CLK_VALID to get phy clk valid */
  218. if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
  219. PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
  220. in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
  221. dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
  222. return -EINVAL;
  223. }
  224. }
  225. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  226. if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
  227. setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
  228. return 0;
  229. }
  230. static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  231. {
  232. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  233. struct fsl_usb2_platform_data *pdata;
  234. void __iomem *non_ehci = hcd->regs;
  235. pdata = dev_get_platdata(hcd->self.controller);
  236. if (pdata->have_sysif_regs) {
  237. /*
  238. * Turn on cache snooping hardware, since some PowerPC platforms
  239. * wholly rely on hardware to deal with cache coherent
  240. */
  241. /* Setup Snooping for all the 4GB space */
  242. /* SNOOP1 starts from 0x0, size 2G */
  243. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  244. /* SNOOP2 starts from 0x80000000, size 2G */
  245. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  246. }
  247. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  248. (pdata->operating_mode == FSL_USB2_DR_OTG))
  249. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  250. return -EINVAL;
  251. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  252. unsigned int chip, rev, svr;
  253. svr = mfspr(SPRN_SVR);
  254. chip = svr >> 16;
  255. rev = (svr >> 4) & 0xf;
  256. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  257. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  258. ehci->has_fsl_port_bug = 1;
  259. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  260. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  261. return -EINVAL;
  262. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  263. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
  264. return -EINVAL;
  265. }
  266. if (pdata->have_sysif_regs) {
  267. #ifdef CONFIG_FSL_SOC_BOOKE
  268. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  269. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  270. #else
  271. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  272. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  273. #endif
  274. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  275. }
  276. return 0;
  277. }
  278. /* called after powerup, by probe or system-pm "wakeup" */
  279. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  280. {
  281. if (ehci_fsl_usb_setup(ehci))
  282. return -EINVAL;
  283. return 0;
  284. }
  285. /* called during probe() after chip reset completes */
  286. static int ehci_fsl_setup(struct usb_hcd *hcd)
  287. {
  288. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  289. int retval;
  290. struct fsl_usb2_platform_data *pdata;
  291. struct device *dev;
  292. dev = hcd->self.controller;
  293. pdata = dev_get_platdata(hcd->self.controller);
  294. ehci->big_endian_desc = pdata->big_endian_desc;
  295. ehci->big_endian_mmio = pdata->big_endian_mmio;
  296. /* EHCI registers start at offset 0x100 */
  297. ehci->caps = hcd->regs + 0x100;
  298. #ifdef CONFIG_PPC_83xx
  299. /*
  300. * Deal with MPC834X that need port power to be cycled after the power
  301. * fault condition is removed. Otherwise the state machine does not
  302. * reflect PORTSC[CSC] correctly.
  303. */
  304. ehci->need_oc_pp_cycle = 1;
  305. #endif
  306. hcd->has_tt = 1;
  307. retval = ehci_setup(hcd);
  308. if (retval)
  309. return retval;
  310. if (of_device_is_compatible(dev->parent->of_node,
  311. "fsl,mpc5121-usb2-dr")) {
  312. /*
  313. * set SBUSCFG:AHBBRST so that control msgs don't
  314. * fail when doing heavy PATA writes.
  315. */
  316. ehci_writel(ehci, SBUSCFG_INCR8,
  317. hcd->regs + FSL_SOC_USB_SBUSCFG);
  318. }
  319. retval = ehci_fsl_reinit(ehci);
  320. return retval;
  321. }
  322. struct ehci_fsl {
  323. struct ehci_hcd ehci;
  324. #ifdef CONFIG_PM
  325. /* Saved USB PHY settings, need to restore after deep sleep. */
  326. u32 usb_ctrl;
  327. #endif
  328. };
  329. #ifdef CONFIG_PM
  330. #ifdef CONFIG_PPC_MPC512x
  331. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  332. {
  333. struct usb_hcd *hcd = dev_get_drvdata(dev);
  334. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  335. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  336. u32 tmp;
  337. #ifdef CONFIG_DYNAMIC_DEBUG
  338. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  339. mode &= USBMODE_CM_MASK;
  340. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  341. dev_dbg(dev, "suspend=%d already_suspended=%d "
  342. "mode=%d usbcmd %08x\n", pdata->suspended,
  343. pdata->already_suspended, mode, tmp);
  344. #endif
  345. /*
  346. * If the controller is already suspended, then this must be a
  347. * PM suspend. Remember this fact, so that we will leave the
  348. * controller suspended at PM resume time.
  349. */
  350. if (pdata->suspended) {
  351. dev_dbg(dev, "already suspended, leaving early\n");
  352. pdata->already_suspended = 1;
  353. return 0;
  354. }
  355. dev_dbg(dev, "suspending...\n");
  356. ehci->rh_state = EHCI_RH_SUSPENDED;
  357. dev->power.power_state = PMSG_SUSPEND;
  358. /* ignore non-host interrupts */
  359. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  360. /* stop the controller */
  361. tmp = ehci_readl(ehci, &ehci->regs->command);
  362. tmp &= ~CMD_RUN;
  363. ehci_writel(ehci, tmp, &ehci->regs->command);
  364. /* save EHCI registers */
  365. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  366. pdata->pm_command &= ~CMD_RUN;
  367. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  368. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  369. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  370. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  371. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  372. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  373. pdata->pm_configured_flag =
  374. ehci_readl(ehci, &ehci->regs->configured_flag);
  375. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  376. pdata->pm_usbgenctrl = ehci_readl(ehci,
  377. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  378. /* clear the W1C bits */
  379. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  380. pdata->suspended = 1;
  381. /* clear PP to cut power to the port */
  382. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  383. tmp &= ~PORT_POWER;
  384. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  385. return 0;
  386. }
  387. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  388. {
  389. struct usb_hcd *hcd = dev_get_drvdata(dev);
  390. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  391. struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
  392. u32 tmp;
  393. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  394. pdata->suspended, pdata->already_suspended);
  395. /*
  396. * If the controller was already suspended at suspend time,
  397. * then don't resume it now.
  398. */
  399. if (pdata->already_suspended) {
  400. dev_dbg(dev, "already suspended, leaving early\n");
  401. pdata->already_suspended = 0;
  402. return 0;
  403. }
  404. if (!pdata->suspended) {
  405. dev_dbg(dev, "not suspended, leaving early\n");
  406. return 0;
  407. }
  408. pdata->suspended = 0;
  409. dev_dbg(dev, "resuming...\n");
  410. /* set host mode */
  411. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  412. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  413. ehci_writel(ehci, pdata->pm_usbgenctrl,
  414. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  415. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  416. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  417. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  418. /* restore EHCI registers */
  419. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  420. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  421. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  422. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  423. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  424. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  425. ehci_writel(ehci, pdata->pm_configured_flag,
  426. &ehci->regs->configured_flag);
  427. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  428. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  429. ehci->rh_state = EHCI_RH_RUNNING;
  430. dev->power.power_state = PMSG_ON;
  431. tmp = ehci_readl(ehci, &ehci->regs->command);
  432. tmp |= CMD_RUN;
  433. ehci_writel(ehci, tmp, &ehci->regs->command);
  434. usb_hcd_resume_root_hub(hcd);
  435. return 0;
  436. }
  437. #else
  438. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  439. {
  440. return 0;
  441. }
  442. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  443. {
  444. return 0;
  445. }
  446. #endif /* CONFIG_PPC_MPC512x */
  447. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  448. {
  449. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  450. return container_of(ehci, struct ehci_fsl, ehci);
  451. }
  452. static int ehci_fsl_drv_suspend(struct device *dev)
  453. {
  454. struct usb_hcd *hcd = dev_get_drvdata(dev);
  455. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  456. void __iomem *non_ehci = hcd->regs;
  457. if (of_device_is_compatible(dev->parent->of_node,
  458. "fsl,mpc5121-usb2-dr")) {
  459. return ehci_fsl_mpc512x_drv_suspend(dev);
  460. }
  461. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  462. device_may_wakeup(dev));
  463. if (!fsl_deep_sleep())
  464. return 0;
  465. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  466. return 0;
  467. }
  468. static int ehci_fsl_drv_resume(struct device *dev)
  469. {
  470. struct usb_hcd *hcd = dev_get_drvdata(dev);
  471. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  472. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  473. void __iomem *non_ehci = hcd->regs;
  474. if (of_device_is_compatible(dev->parent->of_node,
  475. "fsl,mpc5121-usb2-dr")) {
  476. return ehci_fsl_mpc512x_drv_resume(dev);
  477. }
  478. ehci_prepare_ports_for_controller_resume(ehci);
  479. if (!fsl_deep_sleep())
  480. return 0;
  481. usb_root_hub_lost_power(hcd->self.root_hub);
  482. /* Restore USB PHY settings and enable the controller. */
  483. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  484. ehci_reset(ehci);
  485. ehci_fsl_reinit(ehci);
  486. return 0;
  487. }
  488. static int ehci_fsl_drv_restore(struct device *dev)
  489. {
  490. struct usb_hcd *hcd = dev_get_drvdata(dev);
  491. usb_root_hub_lost_power(hcd->self.root_hub);
  492. return 0;
  493. }
  494. static struct dev_pm_ops ehci_fsl_pm_ops = {
  495. .suspend = ehci_fsl_drv_suspend,
  496. .resume = ehci_fsl_drv_resume,
  497. .restore = ehci_fsl_drv_restore,
  498. };
  499. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  500. #else
  501. #define EHCI_FSL_PM_OPS NULL
  502. #endif /* CONFIG_PM */
  503. #ifdef CONFIG_USB_OTG
  504. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  505. {
  506. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  507. u32 status;
  508. if (!port)
  509. return -EINVAL;
  510. port--;
  511. /* start port reset before HNP protocol time out */
  512. status = readl(&ehci->regs->port_status[port]);
  513. if (!(status & PORT_CONNECT))
  514. return -ENODEV;
  515. /* hub_wq will finish the reset later */
  516. if (ehci_is_TDI(ehci)) {
  517. writel(PORT_RESET |
  518. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  519. &ehci->regs->port_status[port]);
  520. } else {
  521. writel(PORT_RESET, &ehci->regs->port_status[port]);
  522. }
  523. return 0;
  524. }
  525. #else
  526. #define ehci_start_port_reset NULL
  527. #endif /* CONFIG_USB_OTG */
  528. static const struct hc_driver ehci_fsl_hc_driver = {
  529. .description = hcd_name,
  530. .product_desc = "Freescale On-Chip EHCI Host Controller",
  531. .hcd_priv_size = sizeof(struct ehci_fsl),
  532. /*
  533. * generic hardware linkage
  534. */
  535. .irq = ehci_irq,
  536. .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
  537. /*
  538. * basic lifecycle operations
  539. */
  540. .reset = ehci_fsl_setup,
  541. .start = ehci_run,
  542. .stop = ehci_stop,
  543. .shutdown = ehci_shutdown,
  544. /*
  545. * managing i/o requests and associated device resources
  546. */
  547. .urb_enqueue = ehci_urb_enqueue,
  548. .urb_dequeue = ehci_urb_dequeue,
  549. .endpoint_disable = ehci_endpoint_disable,
  550. .endpoint_reset = ehci_endpoint_reset,
  551. /*
  552. * scheduling support
  553. */
  554. .get_frame_number = ehci_get_frame,
  555. /*
  556. * root hub support
  557. */
  558. .hub_status_data = ehci_hub_status_data,
  559. .hub_control = ehci_hub_control,
  560. .bus_suspend = ehci_bus_suspend,
  561. .bus_resume = ehci_bus_resume,
  562. .start_port_reset = ehci_start_port_reset,
  563. .relinquish_port = ehci_relinquish_port,
  564. .port_handed_over = ehci_port_handed_over,
  565. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  566. };
  567. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  568. {
  569. if (usb_disabled())
  570. return -ENODEV;
  571. /* FIXME we only want one one probe() not two */
  572. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  573. }
  574. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  575. {
  576. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  577. /* FIXME we only want one one remove() not two */
  578. usb_hcd_fsl_remove(hcd, pdev);
  579. return 0;
  580. }
  581. MODULE_ALIAS("platform:fsl-ehci");
  582. static struct platform_driver ehci_fsl_driver = {
  583. .probe = ehci_fsl_drv_probe,
  584. .remove = ehci_fsl_drv_remove,
  585. .shutdown = usb_hcd_platform_shutdown,
  586. .driver = {
  587. .name = "fsl-ehci",
  588. .pm = EHCI_FSL_PM_OPS,
  589. },
  590. };