amba-pl011.c 60 KB

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  1. /*
  2. * Driver for AMBA serial ports
  3. *
  4. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5. *
  6. * Copyright 1999 ARM Limited
  7. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  8. * Copyright (C) 2010 ST-Ericsson SA
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * This is a generic driver for ARM AMBA-type serial ports. They
  25. * have a lot of 16550-like features, but are not register compatible.
  26. * Note that although they do have CTS, DCD and DSR inputs, they do
  27. * not have an RI input, nor do they have DTR or RTS outputs. If
  28. * required, these have to be supplied via some other means (eg, GPIO)
  29. * and hooked into this driver.
  30. */
  31. #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  32. #define SUPPORT_SYSRQ
  33. #endif
  34. #include <linux/module.h>
  35. #include <linux/ioport.h>
  36. #include <linux/init.h>
  37. #include <linux/console.h>
  38. #include <linux/sysrq.h>
  39. #include <linux/device.h>
  40. #include <linux/tty.h>
  41. #include <linux/tty_flip.h>
  42. #include <linux/serial_core.h>
  43. #include <linux/serial.h>
  44. #include <linux/amba/bus.h>
  45. #include <linux/amba/serial.h>
  46. #include <linux/clk.h>
  47. #include <linux/slab.h>
  48. #include <linux/dmaengine.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/scatterlist.h>
  51. #include <linux/delay.h>
  52. #include <linux/types.h>
  53. #include <linux/of.h>
  54. #include <linux/of_device.h>
  55. #include <linux/pinctrl/consumer.h>
  56. #include <linux/sizes.h>
  57. #include <linux/io.h>
  58. #include <linux/workqueue.h>
  59. #define UART_NR 14
  60. #define SERIAL_AMBA_MAJOR 204
  61. #define SERIAL_AMBA_MINOR 64
  62. #define SERIAL_AMBA_NR UART_NR
  63. #define AMBA_ISR_PASS_LIMIT 256
  64. #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
  65. #define UART_DUMMY_DR_RX (1 << 16)
  66. /* There is by now at least one vendor with differing details, so handle it */
  67. struct vendor_data {
  68. unsigned int ifls;
  69. unsigned int lcrh_tx;
  70. unsigned int lcrh_rx;
  71. bool oversampling;
  72. bool dma_threshold;
  73. bool cts_event_workaround;
  74. unsigned int (*get_fifosize)(struct amba_device *dev);
  75. };
  76. static unsigned int get_fifosize_arm(struct amba_device *dev)
  77. {
  78. return amba_rev(dev) < 3 ? 16 : 32;
  79. }
  80. static struct vendor_data vendor_arm = {
  81. .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
  82. .lcrh_tx = UART011_LCRH,
  83. .lcrh_rx = UART011_LCRH,
  84. .oversampling = false,
  85. .dma_threshold = false,
  86. .cts_event_workaround = false,
  87. .get_fifosize = get_fifosize_arm,
  88. };
  89. static unsigned int get_fifosize_st(struct amba_device *dev)
  90. {
  91. return 64;
  92. }
  93. static struct vendor_data vendor_st = {
  94. .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
  95. .lcrh_tx = ST_UART011_LCRH_TX,
  96. .lcrh_rx = ST_UART011_LCRH_RX,
  97. .oversampling = true,
  98. .dma_threshold = true,
  99. .cts_event_workaround = true,
  100. .get_fifosize = get_fifosize_st,
  101. };
  102. /* Deals with DMA transactions */
  103. struct pl011_sgbuf {
  104. struct scatterlist sg;
  105. char *buf;
  106. };
  107. struct pl011_dmarx_data {
  108. struct dma_chan *chan;
  109. struct completion complete;
  110. bool use_buf_b;
  111. struct pl011_sgbuf sgbuf_a;
  112. struct pl011_sgbuf sgbuf_b;
  113. dma_cookie_t cookie;
  114. bool running;
  115. struct timer_list timer;
  116. unsigned int last_residue;
  117. unsigned long last_jiffies;
  118. bool auto_poll_rate;
  119. unsigned int poll_rate;
  120. unsigned int poll_timeout;
  121. };
  122. struct pl011_dmatx_data {
  123. struct dma_chan *chan;
  124. struct scatterlist sg;
  125. char *buf;
  126. bool queued;
  127. };
  128. /*
  129. * We wrap our port structure around the generic uart_port.
  130. */
  131. struct uart_amba_port {
  132. struct uart_port port;
  133. struct clk *clk;
  134. const struct vendor_data *vendor;
  135. unsigned int dmacr; /* dma control reg */
  136. unsigned int im; /* interrupt mask */
  137. unsigned int old_status;
  138. unsigned int fifosize; /* vendor-specific */
  139. unsigned int lcrh_tx; /* vendor-specific */
  140. unsigned int lcrh_rx; /* vendor-specific */
  141. unsigned int old_cr; /* state during shutdown */
  142. struct delayed_work tx_softirq_work;
  143. bool autorts;
  144. unsigned int tx_irq_seen; /* 0=none, 1=1, 2=2 or more */
  145. char type[12];
  146. #ifdef CONFIG_DMA_ENGINE
  147. /* DMA stuff */
  148. bool using_tx_dma;
  149. bool using_rx_dma;
  150. struct pl011_dmarx_data dmarx;
  151. struct pl011_dmatx_data dmatx;
  152. bool dma_probed;
  153. #endif
  154. };
  155. /*
  156. * Reads up to 256 characters from the FIFO or until it's empty and
  157. * inserts them into the TTY layer. Returns the number of characters
  158. * read from the FIFO.
  159. */
  160. static int pl011_fifo_to_tty(struct uart_amba_port *uap)
  161. {
  162. u16 status, ch;
  163. unsigned int flag, max_count = 256;
  164. int fifotaken = 0;
  165. while (max_count--) {
  166. status = readw(uap->port.membase + UART01x_FR);
  167. if (status & UART01x_FR_RXFE)
  168. break;
  169. /* Take chars from the FIFO and update status */
  170. ch = readw(uap->port.membase + UART01x_DR) |
  171. UART_DUMMY_DR_RX;
  172. flag = TTY_NORMAL;
  173. uap->port.icount.rx++;
  174. fifotaken++;
  175. if (unlikely(ch & UART_DR_ERROR)) {
  176. if (ch & UART011_DR_BE) {
  177. ch &= ~(UART011_DR_FE | UART011_DR_PE);
  178. uap->port.icount.brk++;
  179. if (uart_handle_break(&uap->port))
  180. continue;
  181. } else if (ch & UART011_DR_PE)
  182. uap->port.icount.parity++;
  183. else if (ch & UART011_DR_FE)
  184. uap->port.icount.frame++;
  185. if (ch & UART011_DR_OE)
  186. uap->port.icount.overrun++;
  187. ch &= uap->port.read_status_mask;
  188. if (ch & UART011_DR_BE)
  189. flag = TTY_BREAK;
  190. else if (ch & UART011_DR_PE)
  191. flag = TTY_PARITY;
  192. else if (ch & UART011_DR_FE)
  193. flag = TTY_FRAME;
  194. }
  195. if (uart_handle_sysrq_char(&uap->port, ch & 255))
  196. continue;
  197. uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
  198. }
  199. return fifotaken;
  200. }
  201. /*
  202. * All the DMA operation mode stuff goes inside this ifdef.
  203. * This assumes that you have a generic DMA device interface,
  204. * no custom DMA interfaces are supported.
  205. */
  206. #ifdef CONFIG_DMA_ENGINE
  207. #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
  208. static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
  209. enum dma_data_direction dir)
  210. {
  211. dma_addr_t dma_addr;
  212. sg->buf = dma_alloc_coherent(chan->device->dev,
  213. PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
  214. if (!sg->buf)
  215. return -ENOMEM;
  216. sg_init_table(&sg->sg, 1);
  217. sg_set_page(&sg->sg, phys_to_page(dma_addr),
  218. PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
  219. sg_dma_address(&sg->sg) = dma_addr;
  220. sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
  221. return 0;
  222. }
  223. static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
  224. enum dma_data_direction dir)
  225. {
  226. if (sg->buf) {
  227. dma_free_coherent(chan->device->dev,
  228. PL011_DMA_BUFFER_SIZE, sg->buf,
  229. sg_dma_address(&sg->sg));
  230. }
  231. }
  232. static void pl011_dma_probe(struct uart_amba_port *uap)
  233. {
  234. /* DMA is the sole user of the platform data right now */
  235. struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
  236. struct device *dev = uap->port.dev;
  237. struct dma_slave_config tx_conf = {
  238. .dst_addr = uap->port.mapbase + UART01x_DR,
  239. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  240. .direction = DMA_MEM_TO_DEV,
  241. .dst_maxburst = uap->fifosize >> 1,
  242. .device_fc = false,
  243. };
  244. struct dma_chan *chan;
  245. dma_cap_mask_t mask;
  246. uap->dma_probed = true;
  247. chan = dma_request_slave_channel_reason(dev, "tx");
  248. if (IS_ERR(chan)) {
  249. if (PTR_ERR(chan) == -EPROBE_DEFER) {
  250. uap->dma_probed = false;
  251. return;
  252. }
  253. /* We need platform data */
  254. if (!plat || !plat->dma_filter) {
  255. dev_info(uap->port.dev, "no DMA platform data\n");
  256. return;
  257. }
  258. /* Try to acquire a generic DMA engine slave TX channel */
  259. dma_cap_zero(mask);
  260. dma_cap_set(DMA_SLAVE, mask);
  261. chan = dma_request_channel(mask, plat->dma_filter,
  262. plat->dma_tx_param);
  263. if (!chan) {
  264. dev_err(uap->port.dev, "no TX DMA channel!\n");
  265. return;
  266. }
  267. }
  268. dmaengine_slave_config(chan, &tx_conf);
  269. uap->dmatx.chan = chan;
  270. dev_info(uap->port.dev, "DMA channel TX %s\n",
  271. dma_chan_name(uap->dmatx.chan));
  272. /* Optionally make use of an RX channel as well */
  273. chan = dma_request_slave_channel(dev, "rx");
  274. if (!chan && plat->dma_rx_param) {
  275. chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
  276. if (!chan) {
  277. dev_err(uap->port.dev, "no RX DMA channel!\n");
  278. return;
  279. }
  280. }
  281. if (chan) {
  282. struct dma_slave_config rx_conf = {
  283. .src_addr = uap->port.mapbase + UART01x_DR,
  284. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  285. .direction = DMA_DEV_TO_MEM,
  286. .src_maxburst = uap->fifosize >> 2,
  287. .device_fc = false,
  288. };
  289. struct dma_slave_caps caps;
  290. /*
  291. * Some DMA controllers provide information on their capabilities.
  292. * If the controller does, check for suitable residue processing
  293. * otherwise assime all is well.
  294. */
  295. if (0 == dma_get_slave_caps(chan, &caps)) {
  296. if (caps.residue_granularity ==
  297. DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
  298. dma_release_channel(chan);
  299. dev_info(uap->port.dev,
  300. "RX DMA disabled - no residue processing\n");
  301. return;
  302. }
  303. }
  304. dmaengine_slave_config(chan, &rx_conf);
  305. uap->dmarx.chan = chan;
  306. uap->dmarx.auto_poll_rate = false;
  307. if (plat && plat->dma_rx_poll_enable) {
  308. /* Set poll rate if specified. */
  309. if (plat->dma_rx_poll_rate) {
  310. uap->dmarx.auto_poll_rate = false;
  311. uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
  312. } else {
  313. /*
  314. * 100 ms defaults to poll rate if not
  315. * specified. This will be adjusted with
  316. * the baud rate at set_termios.
  317. */
  318. uap->dmarx.auto_poll_rate = true;
  319. uap->dmarx.poll_rate = 100;
  320. }
  321. /* 3 secs defaults poll_timeout if not specified. */
  322. if (plat->dma_rx_poll_timeout)
  323. uap->dmarx.poll_timeout =
  324. plat->dma_rx_poll_timeout;
  325. else
  326. uap->dmarx.poll_timeout = 3000;
  327. } else if (!plat && dev->of_node) {
  328. uap->dmarx.auto_poll_rate = of_property_read_bool(
  329. dev->of_node, "auto-poll");
  330. if (uap->dmarx.auto_poll_rate) {
  331. u32 x;
  332. if (0 == of_property_read_u32(dev->of_node,
  333. "poll-rate-ms", &x))
  334. uap->dmarx.poll_rate = x;
  335. else
  336. uap->dmarx.poll_rate = 100;
  337. if (0 == of_property_read_u32(dev->of_node,
  338. "poll-timeout-ms", &x))
  339. uap->dmarx.poll_timeout = x;
  340. else
  341. uap->dmarx.poll_timeout = 3000;
  342. }
  343. }
  344. dev_info(uap->port.dev, "DMA channel RX %s\n",
  345. dma_chan_name(uap->dmarx.chan));
  346. }
  347. }
  348. static void pl011_dma_remove(struct uart_amba_port *uap)
  349. {
  350. if (uap->dmatx.chan)
  351. dma_release_channel(uap->dmatx.chan);
  352. if (uap->dmarx.chan)
  353. dma_release_channel(uap->dmarx.chan);
  354. }
  355. /* Forward declare these for the refill routine */
  356. static int pl011_dma_tx_refill(struct uart_amba_port *uap);
  357. static void pl011_start_tx_pio(struct uart_amba_port *uap);
  358. /*
  359. * The current DMA TX buffer has been sent.
  360. * Try to queue up another DMA buffer.
  361. */
  362. static void pl011_dma_tx_callback(void *data)
  363. {
  364. struct uart_amba_port *uap = data;
  365. struct pl011_dmatx_data *dmatx = &uap->dmatx;
  366. unsigned long flags;
  367. u16 dmacr;
  368. spin_lock_irqsave(&uap->port.lock, flags);
  369. if (uap->dmatx.queued)
  370. dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
  371. DMA_TO_DEVICE);
  372. dmacr = uap->dmacr;
  373. uap->dmacr = dmacr & ~UART011_TXDMAE;
  374. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  375. /*
  376. * If TX DMA was disabled, it means that we've stopped the DMA for
  377. * some reason (eg, XOFF received, or we want to send an X-char.)
  378. *
  379. * Note: we need to be careful here of a potential race between DMA
  380. * and the rest of the driver - if the driver disables TX DMA while
  381. * a TX buffer completing, we must update the tx queued status to
  382. * get further refills (hence we check dmacr).
  383. */
  384. if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
  385. uart_circ_empty(&uap->port.state->xmit)) {
  386. uap->dmatx.queued = false;
  387. spin_unlock_irqrestore(&uap->port.lock, flags);
  388. return;
  389. }
  390. if (pl011_dma_tx_refill(uap) <= 0)
  391. /*
  392. * We didn't queue a DMA buffer for some reason, but we
  393. * have data pending to be sent. Re-enable the TX IRQ.
  394. */
  395. pl011_start_tx_pio(uap);
  396. spin_unlock_irqrestore(&uap->port.lock, flags);
  397. }
  398. /*
  399. * Try to refill the TX DMA buffer.
  400. * Locking: called with port lock held and IRQs disabled.
  401. * Returns:
  402. * 1 if we queued up a TX DMA buffer.
  403. * 0 if we didn't want to handle this by DMA
  404. * <0 on error
  405. */
  406. static int pl011_dma_tx_refill(struct uart_amba_port *uap)
  407. {
  408. struct pl011_dmatx_data *dmatx = &uap->dmatx;
  409. struct dma_chan *chan = dmatx->chan;
  410. struct dma_device *dma_dev = chan->device;
  411. struct dma_async_tx_descriptor *desc;
  412. struct circ_buf *xmit = &uap->port.state->xmit;
  413. unsigned int count;
  414. /*
  415. * Try to avoid the overhead involved in using DMA if the
  416. * transaction fits in the first half of the FIFO, by using
  417. * the standard interrupt handling. This ensures that we
  418. * issue a uart_write_wakeup() at the appropriate time.
  419. */
  420. count = uart_circ_chars_pending(xmit);
  421. if (count < (uap->fifosize >> 1)) {
  422. uap->dmatx.queued = false;
  423. return 0;
  424. }
  425. /*
  426. * Bodge: don't send the last character by DMA, as this
  427. * will prevent XON from notifying us to restart DMA.
  428. */
  429. count -= 1;
  430. /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
  431. if (count > PL011_DMA_BUFFER_SIZE)
  432. count = PL011_DMA_BUFFER_SIZE;
  433. if (xmit->tail < xmit->head)
  434. memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
  435. else {
  436. size_t first = UART_XMIT_SIZE - xmit->tail;
  437. size_t second;
  438. if (first > count)
  439. first = count;
  440. second = count - first;
  441. memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
  442. if (second)
  443. memcpy(&dmatx->buf[first], &xmit->buf[0], second);
  444. }
  445. dmatx->sg.length = count;
  446. if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
  447. uap->dmatx.queued = false;
  448. dev_dbg(uap->port.dev, "unable to map TX DMA\n");
  449. return -EBUSY;
  450. }
  451. desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
  452. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  453. if (!desc) {
  454. dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
  455. uap->dmatx.queued = false;
  456. /*
  457. * If DMA cannot be used right now, we complete this
  458. * transaction via IRQ and let the TTY layer retry.
  459. */
  460. dev_dbg(uap->port.dev, "TX DMA busy\n");
  461. return -EBUSY;
  462. }
  463. /* Some data to go along to the callback */
  464. desc->callback = pl011_dma_tx_callback;
  465. desc->callback_param = uap;
  466. /* All errors should happen at prepare time */
  467. dmaengine_submit(desc);
  468. /* Fire the DMA transaction */
  469. dma_dev->device_issue_pending(chan);
  470. uap->dmacr |= UART011_TXDMAE;
  471. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  472. uap->dmatx.queued = true;
  473. /*
  474. * Now we know that DMA will fire, so advance the ring buffer
  475. * with the stuff we just dispatched.
  476. */
  477. xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
  478. uap->port.icount.tx += count;
  479. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  480. uart_write_wakeup(&uap->port);
  481. return 1;
  482. }
  483. /*
  484. * We received a transmit interrupt without a pending X-char but with
  485. * pending characters.
  486. * Locking: called with port lock held and IRQs disabled.
  487. * Returns:
  488. * false if we want to use PIO to transmit
  489. * true if we queued a DMA buffer
  490. */
  491. static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
  492. {
  493. if (!uap->using_tx_dma)
  494. return false;
  495. /*
  496. * If we already have a TX buffer queued, but received a
  497. * TX interrupt, it will be because we've just sent an X-char.
  498. * Ensure the TX DMA is enabled and the TX IRQ is disabled.
  499. */
  500. if (uap->dmatx.queued) {
  501. uap->dmacr |= UART011_TXDMAE;
  502. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  503. uap->im &= ~UART011_TXIM;
  504. writew(uap->im, uap->port.membase + UART011_IMSC);
  505. return true;
  506. }
  507. /*
  508. * We don't have a TX buffer queued, so try to queue one.
  509. * If we successfully queued a buffer, mask the TX IRQ.
  510. */
  511. if (pl011_dma_tx_refill(uap) > 0) {
  512. uap->im &= ~UART011_TXIM;
  513. writew(uap->im, uap->port.membase + UART011_IMSC);
  514. return true;
  515. }
  516. return false;
  517. }
  518. /*
  519. * Stop the DMA transmit (eg, due to received XOFF).
  520. * Locking: called with port lock held and IRQs disabled.
  521. */
  522. static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
  523. {
  524. if (uap->dmatx.queued) {
  525. uap->dmacr &= ~UART011_TXDMAE;
  526. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  527. }
  528. }
  529. /*
  530. * Try to start a DMA transmit, or in the case of an XON/OFF
  531. * character queued for send, try to get that character out ASAP.
  532. * Locking: called with port lock held and IRQs disabled.
  533. * Returns:
  534. * false if we want the TX IRQ to be enabled
  535. * true if we have a buffer queued
  536. */
  537. static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
  538. {
  539. u16 dmacr;
  540. if (!uap->using_tx_dma)
  541. return false;
  542. if (!uap->port.x_char) {
  543. /* no X-char, try to push chars out in DMA mode */
  544. bool ret = true;
  545. if (!uap->dmatx.queued) {
  546. if (pl011_dma_tx_refill(uap) > 0) {
  547. uap->im &= ~UART011_TXIM;
  548. writew(uap->im, uap->port.membase +
  549. UART011_IMSC);
  550. } else
  551. ret = false;
  552. } else if (!(uap->dmacr & UART011_TXDMAE)) {
  553. uap->dmacr |= UART011_TXDMAE;
  554. writew(uap->dmacr,
  555. uap->port.membase + UART011_DMACR);
  556. }
  557. return ret;
  558. }
  559. /*
  560. * We have an X-char to send. Disable DMA to prevent it loading
  561. * the TX fifo, and then see if we can stuff it into the FIFO.
  562. */
  563. dmacr = uap->dmacr;
  564. uap->dmacr &= ~UART011_TXDMAE;
  565. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  566. if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
  567. /*
  568. * No space in the FIFO, so enable the transmit interrupt
  569. * so we know when there is space. Note that once we've
  570. * loaded the character, we should just re-enable DMA.
  571. */
  572. return false;
  573. }
  574. writew(uap->port.x_char, uap->port.membase + UART01x_DR);
  575. uap->port.icount.tx++;
  576. uap->port.x_char = 0;
  577. /* Success - restore the DMA state */
  578. uap->dmacr = dmacr;
  579. writew(dmacr, uap->port.membase + UART011_DMACR);
  580. return true;
  581. }
  582. /*
  583. * Flush the transmit buffer.
  584. * Locking: called with port lock held and IRQs disabled.
  585. */
  586. static void pl011_dma_flush_buffer(struct uart_port *port)
  587. __releases(&uap->port.lock)
  588. __acquires(&uap->port.lock)
  589. {
  590. struct uart_amba_port *uap =
  591. container_of(port, struct uart_amba_port, port);
  592. if (!uap->using_tx_dma)
  593. return;
  594. /* Avoid deadlock with the DMA engine callback */
  595. spin_unlock(&uap->port.lock);
  596. dmaengine_terminate_all(uap->dmatx.chan);
  597. spin_lock(&uap->port.lock);
  598. if (uap->dmatx.queued) {
  599. dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
  600. DMA_TO_DEVICE);
  601. uap->dmatx.queued = false;
  602. uap->dmacr &= ~UART011_TXDMAE;
  603. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  604. }
  605. }
  606. static void pl011_dma_rx_callback(void *data);
  607. static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
  608. {
  609. struct dma_chan *rxchan = uap->dmarx.chan;
  610. struct pl011_dmarx_data *dmarx = &uap->dmarx;
  611. struct dma_async_tx_descriptor *desc;
  612. struct pl011_sgbuf *sgbuf;
  613. if (!rxchan)
  614. return -EIO;
  615. /* Start the RX DMA job */
  616. sgbuf = uap->dmarx.use_buf_b ?
  617. &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
  618. desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
  619. DMA_DEV_TO_MEM,
  620. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  621. /*
  622. * If the DMA engine is busy and cannot prepare a
  623. * channel, no big deal, the driver will fall back
  624. * to interrupt mode as a result of this error code.
  625. */
  626. if (!desc) {
  627. uap->dmarx.running = false;
  628. dmaengine_terminate_all(rxchan);
  629. return -EBUSY;
  630. }
  631. /* Some data to go along to the callback */
  632. desc->callback = pl011_dma_rx_callback;
  633. desc->callback_param = uap;
  634. dmarx->cookie = dmaengine_submit(desc);
  635. dma_async_issue_pending(rxchan);
  636. uap->dmacr |= UART011_RXDMAE;
  637. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  638. uap->dmarx.running = true;
  639. uap->im &= ~UART011_RXIM;
  640. writew(uap->im, uap->port.membase + UART011_IMSC);
  641. return 0;
  642. }
  643. /*
  644. * This is called when either the DMA job is complete, or
  645. * the FIFO timeout interrupt occurred. This must be called
  646. * with the port spinlock uap->port.lock held.
  647. */
  648. static void pl011_dma_rx_chars(struct uart_amba_port *uap,
  649. u32 pending, bool use_buf_b,
  650. bool readfifo)
  651. {
  652. struct tty_port *port = &uap->port.state->port;
  653. struct pl011_sgbuf *sgbuf = use_buf_b ?
  654. &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
  655. int dma_count = 0;
  656. u32 fifotaken = 0; /* only used for vdbg() */
  657. struct pl011_dmarx_data *dmarx = &uap->dmarx;
  658. int dmataken = 0;
  659. if (uap->dmarx.poll_rate) {
  660. /* The data can be taken by polling */
  661. dmataken = sgbuf->sg.length - dmarx->last_residue;
  662. /* Recalculate the pending size */
  663. if (pending >= dmataken)
  664. pending -= dmataken;
  665. }
  666. /* Pick the remain data from the DMA */
  667. if (pending) {
  668. /*
  669. * First take all chars in the DMA pipe, then look in the FIFO.
  670. * Note that tty_insert_flip_buf() tries to take as many chars
  671. * as it can.
  672. */
  673. dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
  674. pending);
  675. uap->port.icount.rx += dma_count;
  676. if (dma_count < pending)
  677. dev_warn(uap->port.dev,
  678. "couldn't insert all characters (TTY is full?)\n");
  679. }
  680. /* Reset the last_residue for Rx DMA poll */
  681. if (uap->dmarx.poll_rate)
  682. dmarx->last_residue = sgbuf->sg.length;
  683. /*
  684. * Only continue with trying to read the FIFO if all DMA chars have
  685. * been taken first.
  686. */
  687. if (dma_count == pending && readfifo) {
  688. /* Clear any error flags */
  689. writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
  690. uap->port.membase + UART011_ICR);
  691. /*
  692. * If we read all the DMA'd characters, and we had an
  693. * incomplete buffer, that could be due to an rx error, or
  694. * maybe we just timed out. Read any pending chars and check
  695. * the error status.
  696. *
  697. * Error conditions will only occur in the FIFO, these will
  698. * trigger an immediate interrupt and stop the DMA job, so we
  699. * will always find the error in the FIFO, never in the DMA
  700. * buffer.
  701. */
  702. fifotaken = pl011_fifo_to_tty(uap);
  703. }
  704. spin_unlock(&uap->port.lock);
  705. dev_vdbg(uap->port.dev,
  706. "Took %d chars from DMA buffer and %d chars from the FIFO\n",
  707. dma_count, fifotaken);
  708. tty_flip_buffer_push(port);
  709. spin_lock(&uap->port.lock);
  710. }
  711. static void pl011_dma_rx_irq(struct uart_amba_port *uap)
  712. {
  713. struct pl011_dmarx_data *dmarx = &uap->dmarx;
  714. struct dma_chan *rxchan = dmarx->chan;
  715. struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
  716. &dmarx->sgbuf_b : &dmarx->sgbuf_a;
  717. size_t pending;
  718. struct dma_tx_state state;
  719. enum dma_status dmastat;
  720. /*
  721. * Pause the transfer so we can trust the current counter,
  722. * do this before we pause the PL011 block, else we may
  723. * overflow the FIFO.
  724. */
  725. if (dmaengine_pause(rxchan))
  726. dev_err(uap->port.dev, "unable to pause DMA transfer\n");
  727. dmastat = rxchan->device->device_tx_status(rxchan,
  728. dmarx->cookie, &state);
  729. if (dmastat != DMA_PAUSED)
  730. dev_err(uap->port.dev, "unable to pause DMA transfer\n");
  731. /* Disable RX DMA - incoming data will wait in the FIFO */
  732. uap->dmacr &= ~UART011_RXDMAE;
  733. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  734. uap->dmarx.running = false;
  735. pending = sgbuf->sg.length - state.residue;
  736. BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
  737. /* Then we terminate the transfer - we now know our residue */
  738. dmaengine_terminate_all(rxchan);
  739. /*
  740. * This will take the chars we have so far and insert
  741. * into the framework.
  742. */
  743. pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
  744. /* Switch buffer & re-trigger DMA job */
  745. dmarx->use_buf_b = !dmarx->use_buf_b;
  746. if (pl011_dma_rx_trigger_dma(uap)) {
  747. dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
  748. "fall back to interrupt mode\n");
  749. uap->im |= UART011_RXIM;
  750. writew(uap->im, uap->port.membase + UART011_IMSC);
  751. }
  752. }
  753. static void pl011_dma_rx_callback(void *data)
  754. {
  755. struct uart_amba_port *uap = data;
  756. struct pl011_dmarx_data *dmarx = &uap->dmarx;
  757. struct dma_chan *rxchan = dmarx->chan;
  758. bool lastbuf = dmarx->use_buf_b;
  759. struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
  760. &dmarx->sgbuf_b : &dmarx->sgbuf_a;
  761. size_t pending;
  762. struct dma_tx_state state;
  763. int ret;
  764. /*
  765. * This completion interrupt occurs typically when the
  766. * RX buffer is totally stuffed but no timeout has yet
  767. * occurred. When that happens, we just want the RX
  768. * routine to flush out the secondary DMA buffer while
  769. * we immediately trigger the next DMA job.
  770. */
  771. spin_lock_irq(&uap->port.lock);
  772. /*
  773. * Rx data can be taken by the UART interrupts during
  774. * the DMA irq handler. So we check the residue here.
  775. */
  776. rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
  777. pending = sgbuf->sg.length - state.residue;
  778. BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
  779. /* Then we terminate the transfer - we now know our residue */
  780. dmaengine_terminate_all(rxchan);
  781. uap->dmarx.running = false;
  782. dmarx->use_buf_b = !lastbuf;
  783. ret = pl011_dma_rx_trigger_dma(uap);
  784. pl011_dma_rx_chars(uap, pending, lastbuf, false);
  785. spin_unlock_irq(&uap->port.lock);
  786. /*
  787. * Do this check after we picked the DMA chars so we don't
  788. * get some IRQ immediately from RX.
  789. */
  790. if (ret) {
  791. dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
  792. "fall back to interrupt mode\n");
  793. uap->im |= UART011_RXIM;
  794. writew(uap->im, uap->port.membase + UART011_IMSC);
  795. }
  796. }
  797. /*
  798. * Stop accepting received characters, when we're shutting down or
  799. * suspending this port.
  800. * Locking: called with port lock held and IRQs disabled.
  801. */
  802. static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
  803. {
  804. /* FIXME. Just disable the DMA enable */
  805. uap->dmacr &= ~UART011_RXDMAE;
  806. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  807. }
  808. /*
  809. * Timer handler for Rx DMA polling.
  810. * Every polling, It checks the residue in the dma buffer and transfer
  811. * data to the tty. Also, last_residue is updated for the next polling.
  812. */
  813. static void pl011_dma_rx_poll(unsigned long args)
  814. {
  815. struct uart_amba_port *uap = (struct uart_amba_port *)args;
  816. struct tty_port *port = &uap->port.state->port;
  817. struct pl011_dmarx_data *dmarx = &uap->dmarx;
  818. struct dma_chan *rxchan = uap->dmarx.chan;
  819. unsigned long flags = 0;
  820. unsigned int dmataken = 0;
  821. unsigned int size = 0;
  822. struct pl011_sgbuf *sgbuf;
  823. int dma_count;
  824. struct dma_tx_state state;
  825. sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
  826. rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
  827. if (likely(state.residue < dmarx->last_residue)) {
  828. dmataken = sgbuf->sg.length - dmarx->last_residue;
  829. size = dmarx->last_residue - state.residue;
  830. dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
  831. size);
  832. if (dma_count == size)
  833. dmarx->last_residue = state.residue;
  834. dmarx->last_jiffies = jiffies;
  835. }
  836. tty_flip_buffer_push(port);
  837. /*
  838. * If no data is received in poll_timeout, the driver will fall back
  839. * to interrupt mode. We will retrigger DMA at the first interrupt.
  840. */
  841. if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
  842. > uap->dmarx.poll_timeout) {
  843. spin_lock_irqsave(&uap->port.lock, flags);
  844. pl011_dma_rx_stop(uap);
  845. uap->im |= UART011_RXIM;
  846. writew(uap->im, uap->port.membase + UART011_IMSC);
  847. spin_unlock_irqrestore(&uap->port.lock, flags);
  848. uap->dmarx.running = false;
  849. dmaengine_terminate_all(rxchan);
  850. del_timer(&uap->dmarx.timer);
  851. } else {
  852. mod_timer(&uap->dmarx.timer,
  853. jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
  854. }
  855. }
  856. static void pl011_dma_startup(struct uart_amba_port *uap)
  857. {
  858. int ret;
  859. if (!uap->dma_probed)
  860. pl011_dma_probe(uap);
  861. if (!uap->dmatx.chan)
  862. return;
  863. uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
  864. if (!uap->dmatx.buf) {
  865. dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
  866. uap->port.fifosize = uap->fifosize;
  867. return;
  868. }
  869. sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
  870. /* The DMA buffer is now the FIFO the TTY subsystem can use */
  871. uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
  872. uap->using_tx_dma = true;
  873. if (!uap->dmarx.chan)
  874. goto skip_rx;
  875. /* Allocate and map DMA RX buffers */
  876. ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
  877. DMA_FROM_DEVICE);
  878. if (ret) {
  879. dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
  880. "RX buffer A", ret);
  881. goto skip_rx;
  882. }
  883. ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
  884. DMA_FROM_DEVICE);
  885. if (ret) {
  886. dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
  887. "RX buffer B", ret);
  888. pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
  889. DMA_FROM_DEVICE);
  890. goto skip_rx;
  891. }
  892. uap->using_rx_dma = true;
  893. skip_rx:
  894. /* Turn on DMA error (RX/TX will be enabled on demand) */
  895. uap->dmacr |= UART011_DMAONERR;
  896. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  897. /*
  898. * ST Micro variants has some specific dma burst threshold
  899. * compensation. Set this to 16 bytes, so burst will only
  900. * be issued above/below 16 bytes.
  901. */
  902. if (uap->vendor->dma_threshold)
  903. writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
  904. uap->port.membase + ST_UART011_DMAWM);
  905. if (uap->using_rx_dma) {
  906. if (pl011_dma_rx_trigger_dma(uap))
  907. dev_dbg(uap->port.dev, "could not trigger initial "
  908. "RX DMA job, fall back to interrupt mode\n");
  909. if (uap->dmarx.poll_rate) {
  910. init_timer(&(uap->dmarx.timer));
  911. uap->dmarx.timer.function = pl011_dma_rx_poll;
  912. uap->dmarx.timer.data = (unsigned long)uap;
  913. mod_timer(&uap->dmarx.timer,
  914. jiffies +
  915. msecs_to_jiffies(uap->dmarx.poll_rate));
  916. uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
  917. uap->dmarx.last_jiffies = jiffies;
  918. }
  919. }
  920. }
  921. static void pl011_dma_shutdown(struct uart_amba_port *uap)
  922. {
  923. if (!(uap->using_tx_dma || uap->using_rx_dma))
  924. return;
  925. /* Disable RX and TX DMA */
  926. while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
  927. barrier();
  928. spin_lock_irq(&uap->port.lock);
  929. uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
  930. writew(uap->dmacr, uap->port.membase + UART011_DMACR);
  931. spin_unlock_irq(&uap->port.lock);
  932. if (uap->using_tx_dma) {
  933. /* In theory, this should already be done by pl011_dma_flush_buffer */
  934. dmaengine_terminate_all(uap->dmatx.chan);
  935. if (uap->dmatx.queued) {
  936. dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
  937. DMA_TO_DEVICE);
  938. uap->dmatx.queued = false;
  939. }
  940. kfree(uap->dmatx.buf);
  941. uap->using_tx_dma = false;
  942. }
  943. if (uap->using_rx_dma) {
  944. dmaengine_terminate_all(uap->dmarx.chan);
  945. /* Clean up the RX DMA */
  946. pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
  947. pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
  948. if (uap->dmarx.poll_rate)
  949. del_timer_sync(&uap->dmarx.timer);
  950. uap->using_rx_dma = false;
  951. }
  952. }
  953. static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
  954. {
  955. return uap->using_rx_dma;
  956. }
  957. static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
  958. {
  959. return uap->using_rx_dma && uap->dmarx.running;
  960. }
  961. #else
  962. /* Blank functions if the DMA engine is not available */
  963. static inline void pl011_dma_probe(struct uart_amba_port *uap)
  964. {
  965. }
  966. static inline void pl011_dma_remove(struct uart_amba_port *uap)
  967. {
  968. }
  969. static inline void pl011_dma_startup(struct uart_amba_port *uap)
  970. {
  971. }
  972. static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
  973. {
  974. }
  975. static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
  976. {
  977. return false;
  978. }
  979. static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
  980. {
  981. }
  982. static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
  983. {
  984. return false;
  985. }
  986. static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
  987. {
  988. }
  989. static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
  990. {
  991. }
  992. static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
  993. {
  994. return -EIO;
  995. }
  996. static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
  997. {
  998. return false;
  999. }
  1000. static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
  1001. {
  1002. return false;
  1003. }
  1004. #define pl011_dma_flush_buffer NULL
  1005. #endif
  1006. static void pl011_stop_tx(struct uart_port *port)
  1007. {
  1008. struct uart_amba_port *uap =
  1009. container_of(port, struct uart_amba_port, port);
  1010. uap->im &= ~UART011_TXIM;
  1011. writew(uap->im, uap->port.membase + UART011_IMSC);
  1012. pl011_dma_tx_stop(uap);
  1013. }
  1014. static bool pl011_tx_chars(struct uart_amba_port *uap);
  1015. /* Start TX with programmed I/O only (no DMA) */
  1016. static void pl011_start_tx_pio(struct uart_amba_port *uap)
  1017. {
  1018. uap->im |= UART011_TXIM;
  1019. writew(uap->im, uap->port.membase + UART011_IMSC);
  1020. if (!uap->tx_irq_seen)
  1021. pl011_tx_chars(uap);
  1022. }
  1023. static void pl011_start_tx(struct uart_port *port)
  1024. {
  1025. struct uart_amba_port *uap =
  1026. container_of(port, struct uart_amba_port, port);
  1027. if (!pl011_dma_tx_start(uap))
  1028. pl011_start_tx_pio(uap);
  1029. }
  1030. static void pl011_stop_rx(struct uart_port *port)
  1031. {
  1032. struct uart_amba_port *uap =
  1033. container_of(port, struct uart_amba_port, port);
  1034. uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
  1035. UART011_PEIM|UART011_BEIM|UART011_OEIM);
  1036. writew(uap->im, uap->port.membase + UART011_IMSC);
  1037. pl011_dma_rx_stop(uap);
  1038. }
  1039. static void pl011_enable_ms(struct uart_port *port)
  1040. {
  1041. struct uart_amba_port *uap =
  1042. container_of(port, struct uart_amba_port, port);
  1043. uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
  1044. writew(uap->im, uap->port.membase + UART011_IMSC);
  1045. }
  1046. static void pl011_rx_chars(struct uart_amba_port *uap)
  1047. __releases(&uap->port.lock)
  1048. __acquires(&uap->port.lock)
  1049. {
  1050. pl011_fifo_to_tty(uap);
  1051. spin_unlock(&uap->port.lock);
  1052. tty_flip_buffer_push(&uap->port.state->port);
  1053. /*
  1054. * If we were temporarily out of DMA mode for a while,
  1055. * attempt to switch back to DMA mode again.
  1056. */
  1057. if (pl011_dma_rx_available(uap)) {
  1058. if (pl011_dma_rx_trigger_dma(uap)) {
  1059. dev_dbg(uap->port.dev, "could not trigger RX DMA job "
  1060. "fall back to interrupt mode again\n");
  1061. uap->im |= UART011_RXIM;
  1062. writew(uap->im, uap->port.membase + UART011_IMSC);
  1063. } else {
  1064. #ifdef CONFIG_DMA_ENGINE
  1065. /* Start Rx DMA poll */
  1066. if (uap->dmarx.poll_rate) {
  1067. uap->dmarx.last_jiffies = jiffies;
  1068. uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
  1069. mod_timer(&uap->dmarx.timer,
  1070. jiffies +
  1071. msecs_to_jiffies(uap->dmarx.poll_rate));
  1072. }
  1073. #endif
  1074. }
  1075. }
  1076. spin_lock(&uap->port.lock);
  1077. }
  1078. /*
  1079. * Transmit a character
  1080. *
  1081. * Returns true if the character was successfully queued to the FIFO.
  1082. * Returns false otherwise.
  1083. */
  1084. static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c)
  1085. {
  1086. if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
  1087. return false; /* unable to transmit character */
  1088. writew(c, uap->port.membase + UART01x_DR);
  1089. uap->port.icount.tx++;
  1090. return true;
  1091. }
  1092. static bool pl011_tx_chars(struct uart_amba_port *uap)
  1093. {
  1094. struct circ_buf *xmit = &uap->port.state->xmit;
  1095. int count;
  1096. if (unlikely(uap->tx_irq_seen < 2))
  1097. /*
  1098. * Initial FIFO fill level unknown: we must check TXFF
  1099. * after each write, so just try to fill up the FIFO.
  1100. */
  1101. count = uap->fifosize;
  1102. else /* tx_irq_seen >= 2 */
  1103. /*
  1104. * FIFO initially at least half-empty, so we can simply
  1105. * write half the FIFO without polling TXFF.
  1106. * Note: the *first* TX IRQ can still race with
  1107. * pl011_start_tx_pio(), which can result in the FIFO
  1108. * being fuller than expected in that case.
  1109. */
  1110. count = uap->fifosize >> 1;
  1111. /*
  1112. * If the FIFO is full we're guaranteed a TX IRQ at some later point,
  1113. * and can't transmit immediately in any case:
  1114. */
  1115. if (unlikely(uap->tx_irq_seen < 2 &&
  1116. readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF))
  1117. return false;
  1118. if (uap->port.x_char) {
  1119. if (!pl011_tx_char(uap, uap->port.x_char))
  1120. goto done;
  1121. uap->port.x_char = 0;
  1122. --count;
  1123. }
  1124. if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
  1125. pl011_stop_tx(&uap->port);
  1126. goto done;
  1127. }
  1128. /* If we are using DMA mode, try to send some characters. */
  1129. if (pl011_dma_tx_irq(uap))
  1130. goto done;
  1131. while (count-- > 0 && pl011_tx_char(uap, xmit->buf[xmit->tail])) {
  1132. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  1133. if (uart_circ_empty(xmit))
  1134. break;
  1135. }
  1136. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  1137. uart_write_wakeup(&uap->port);
  1138. if (uart_circ_empty(xmit)) {
  1139. pl011_stop_tx(&uap->port);
  1140. goto done;
  1141. }
  1142. if (unlikely(!uap->tx_irq_seen))
  1143. schedule_delayed_work(&uap->tx_softirq_work, uap->port.timeout);
  1144. done:
  1145. return false;
  1146. }
  1147. static void pl011_modem_status(struct uart_amba_port *uap)
  1148. {
  1149. unsigned int status, delta;
  1150. status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  1151. delta = status ^ uap->old_status;
  1152. uap->old_status = status;
  1153. if (!delta)
  1154. return;
  1155. if (delta & UART01x_FR_DCD)
  1156. uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
  1157. if (delta & UART01x_FR_DSR)
  1158. uap->port.icount.dsr++;
  1159. if (delta & UART01x_FR_CTS)
  1160. uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
  1161. wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
  1162. }
  1163. static void pl011_tx_softirq(struct work_struct *work)
  1164. {
  1165. struct delayed_work *dwork = to_delayed_work(work);
  1166. struct uart_amba_port *uap =
  1167. container_of(dwork, struct uart_amba_port, tx_softirq_work);
  1168. spin_lock(&uap->port.lock);
  1169. while (pl011_tx_chars(uap)) ;
  1170. spin_unlock(&uap->port.lock);
  1171. }
  1172. static void pl011_tx_irq_seen(struct uart_amba_port *uap)
  1173. {
  1174. if (likely(uap->tx_irq_seen > 1))
  1175. return;
  1176. uap->tx_irq_seen++;
  1177. if (uap->tx_irq_seen < 2)
  1178. /* first TX IRQ */
  1179. cancel_delayed_work(&uap->tx_softirq_work);
  1180. }
  1181. static irqreturn_t pl011_int(int irq, void *dev_id)
  1182. {
  1183. struct uart_amba_port *uap = dev_id;
  1184. unsigned long flags;
  1185. unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
  1186. int handled = 0;
  1187. unsigned int dummy_read;
  1188. spin_lock_irqsave(&uap->port.lock, flags);
  1189. status = readw(uap->port.membase + UART011_MIS);
  1190. if (status) {
  1191. do {
  1192. if (uap->vendor->cts_event_workaround) {
  1193. /* workaround to make sure that all bits are unlocked.. */
  1194. writew(0x00, uap->port.membase + UART011_ICR);
  1195. /*
  1196. * WA: introduce 26ns(1 uart clk) delay before W1C;
  1197. * single apb access will incur 2 pclk(133.12Mhz) delay,
  1198. * so add 2 dummy reads
  1199. */
  1200. dummy_read = readw(uap->port.membase + UART011_ICR);
  1201. dummy_read = readw(uap->port.membase + UART011_ICR);
  1202. }
  1203. writew(status & ~(UART011_TXIS|UART011_RTIS|
  1204. UART011_RXIS),
  1205. uap->port.membase + UART011_ICR);
  1206. if (status & (UART011_RTIS|UART011_RXIS)) {
  1207. if (pl011_dma_rx_running(uap))
  1208. pl011_dma_rx_irq(uap);
  1209. else
  1210. pl011_rx_chars(uap);
  1211. }
  1212. if (status & (UART011_DSRMIS|UART011_DCDMIS|
  1213. UART011_CTSMIS|UART011_RIMIS))
  1214. pl011_modem_status(uap);
  1215. if (status & UART011_TXIS) {
  1216. pl011_tx_irq_seen(uap);
  1217. pl011_tx_chars(uap);
  1218. }
  1219. if (pass_counter-- == 0)
  1220. break;
  1221. status = readw(uap->port.membase + UART011_MIS);
  1222. } while (status != 0);
  1223. handled = 1;
  1224. }
  1225. spin_unlock_irqrestore(&uap->port.lock, flags);
  1226. return IRQ_RETVAL(handled);
  1227. }
  1228. static unsigned int pl011_tx_empty(struct uart_port *port)
  1229. {
  1230. struct uart_amba_port *uap =
  1231. container_of(port, struct uart_amba_port, port);
  1232. unsigned int status = readw(uap->port.membase + UART01x_FR);
  1233. return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
  1234. }
  1235. static unsigned int pl011_get_mctrl(struct uart_port *port)
  1236. {
  1237. struct uart_amba_port *uap =
  1238. container_of(port, struct uart_amba_port, port);
  1239. unsigned int result = 0;
  1240. unsigned int status = readw(uap->port.membase + UART01x_FR);
  1241. #define TIOCMBIT(uartbit, tiocmbit) \
  1242. if (status & uartbit) \
  1243. result |= tiocmbit
  1244. TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
  1245. TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
  1246. TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
  1247. TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
  1248. #undef TIOCMBIT
  1249. return result;
  1250. }
  1251. static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
  1252. {
  1253. struct uart_amba_port *uap =
  1254. container_of(port, struct uart_amba_port, port);
  1255. unsigned int cr;
  1256. cr = readw(uap->port.membase + UART011_CR);
  1257. #define TIOCMBIT(tiocmbit, uartbit) \
  1258. if (mctrl & tiocmbit) \
  1259. cr |= uartbit; \
  1260. else \
  1261. cr &= ~uartbit
  1262. TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
  1263. TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
  1264. TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
  1265. TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
  1266. TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
  1267. if (uap->autorts) {
  1268. /* We need to disable auto-RTS if we want to turn RTS off */
  1269. TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
  1270. }
  1271. #undef TIOCMBIT
  1272. writew(cr, uap->port.membase + UART011_CR);
  1273. }
  1274. static void pl011_break_ctl(struct uart_port *port, int break_state)
  1275. {
  1276. struct uart_amba_port *uap =
  1277. container_of(port, struct uart_amba_port, port);
  1278. unsigned long flags;
  1279. unsigned int lcr_h;
  1280. spin_lock_irqsave(&uap->port.lock, flags);
  1281. lcr_h = readw(uap->port.membase + uap->lcrh_tx);
  1282. if (break_state == -1)
  1283. lcr_h |= UART01x_LCRH_BRK;
  1284. else
  1285. lcr_h &= ~UART01x_LCRH_BRK;
  1286. writew(lcr_h, uap->port.membase + uap->lcrh_tx);
  1287. spin_unlock_irqrestore(&uap->port.lock, flags);
  1288. }
  1289. #ifdef CONFIG_CONSOLE_POLL
  1290. static void pl011_quiesce_irqs(struct uart_port *port)
  1291. {
  1292. struct uart_amba_port *uap =
  1293. container_of(port, struct uart_amba_port, port);
  1294. unsigned char __iomem *regs = uap->port.membase;
  1295. writew(readw(regs + UART011_MIS), regs + UART011_ICR);
  1296. /*
  1297. * There is no way to clear TXIM as this is "ready to transmit IRQ", so
  1298. * we simply mask it. start_tx() will unmask it.
  1299. *
  1300. * Note we can race with start_tx(), and if the race happens, the
  1301. * polling user might get another interrupt just after we clear it.
  1302. * But it should be OK and can happen even w/o the race, e.g.
  1303. * controller immediately got some new data and raised the IRQ.
  1304. *
  1305. * And whoever uses polling routines assumes that it manages the device
  1306. * (including tx queue), so we're also fine with start_tx()'s caller
  1307. * side.
  1308. */
  1309. writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
  1310. }
  1311. static int pl011_get_poll_char(struct uart_port *port)
  1312. {
  1313. struct uart_amba_port *uap =
  1314. container_of(port, struct uart_amba_port, port);
  1315. unsigned int status;
  1316. /*
  1317. * The caller might need IRQs lowered, e.g. if used with KDB NMI
  1318. * debugger.
  1319. */
  1320. pl011_quiesce_irqs(port);
  1321. status = readw(uap->port.membase + UART01x_FR);
  1322. if (status & UART01x_FR_RXFE)
  1323. return NO_POLL_CHAR;
  1324. return readw(uap->port.membase + UART01x_DR);
  1325. }
  1326. static void pl011_put_poll_char(struct uart_port *port,
  1327. unsigned char ch)
  1328. {
  1329. struct uart_amba_port *uap =
  1330. container_of(port, struct uart_amba_port, port);
  1331. while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
  1332. barrier();
  1333. writew(ch, uap->port.membase + UART01x_DR);
  1334. }
  1335. #endif /* CONFIG_CONSOLE_POLL */
  1336. static int pl011_hwinit(struct uart_port *port)
  1337. {
  1338. struct uart_amba_port *uap =
  1339. container_of(port, struct uart_amba_port, port);
  1340. int retval;
  1341. /* Optionaly enable pins to be muxed in and configured */
  1342. pinctrl_pm_select_default_state(port->dev);
  1343. /*
  1344. * Try to enable the clock producer.
  1345. */
  1346. retval = clk_prepare_enable(uap->clk);
  1347. if (retval)
  1348. return retval;
  1349. uap->port.uartclk = clk_get_rate(uap->clk);
  1350. /* Clear pending error and receive interrupts */
  1351. writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
  1352. UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
  1353. /*
  1354. * Save interrupts enable mask, and enable RX interrupts in case if
  1355. * the interrupt is used for NMI entry.
  1356. */
  1357. uap->im = readw(uap->port.membase + UART011_IMSC);
  1358. writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
  1359. if (dev_get_platdata(uap->port.dev)) {
  1360. struct amba_pl011_data *plat;
  1361. plat = dev_get_platdata(uap->port.dev);
  1362. if (plat->init)
  1363. plat->init();
  1364. }
  1365. return 0;
  1366. }
  1367. static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
  1368. {
  1369. writew(lcr_h, uap->port.membase + uap->lcrh_rx);
  1370. if (uap->lcrh_rx != uap->lcrh_tx) {
  1371. int i;
  1372. /*
  1373. * Wait 10 PCLKs before writing LCRH_TX register,
  1374. * to get this delay write read only register 10 times
  1375. */
  1376. for (i = 0; i < 10; ++i)
  1377. writew(0xff, uap->port.membase + UART011_MIS);
  1378. writew(lcr_h, uap->port.membase + uap->lcrh_tx);
  1379. }
  1380. }
  1381. static int pl011_startup(struct uart_port *port)
  1382. {
  1383. struct uart_amba_port *uap =
  1384. container_of(port, struct uart_amba_port, port);
  1385. unsigned int cr;
  1386. int retval;
  1387. retval = pl011_hwinit(port);
  1388. if (retval)
  1389. goto clk_dis;
  1390. writew(uap->im, uap->port.membase + UART011_IMSC);
  1391. /*
  1392. * Allocate the IRQ
  1393. */
  1394. retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
  1395. if (retval)
  1396. goto clk_dis;
  1397. writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
  1398. /* Assume that TX IRQ doesn't work until we see one: */
  1399. uap->tx_irq_seen = 0;
  1400. spin_lock_irq(&uap->port.lock);
  1401. /* restore RTS and DTR */
  1402. cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
  1403. cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
  1404. writew(cr, uap->port.membase + UART011_CR);
  1405. spin_unlock_irq(&uap->port.lock);
  1406. /*
  1407. * initialise the old status of the modem signals
  1408. */
  1409. uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  1410. /* Startup DMA */
  1411. pl011_dma_startup(uap);
  1412. /*
  1413. * Finally, enable interrupts, only timeouts when using DMA
  1414. * if initial RX DMA job failed, start in interrupt mode
  1415. * as well.
  1416. */
  1417. spin_lock_irq(&uap->port.lock);
  1418. /* Clear out any spuriously appearing RX interrupts */
  1419. writew(UART011_RTIS | UART011_RXIS,
  1420. uap->port.membase + UART011_ICR);
  1421. uap->im = UART011_RTIM;
  1422. if (!pl011_dma_rx_running(uap))
  1423. uap->im |= UART011_RXIM;
  1424. writew(uap->im, uap->port.membase + UART011_IMSC);
  1425. spin_unlock_irq(&uap->port.lock);
  1426. return 0;
  1427. clk_dis:
  1428. clk_disable_unprepare(uap->clk);
  1429. return retval;
  1430. }
  1431. static void pl011_shutdown_channel(struct uart_amba_port *uap,
  1432. unsigned int lcrh)
  1433. {
  1434. unsigned long val;
  1435. val = readw(uap->port.membase + lcrh);
  1436. val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
  1437. writew(val, uap->port.membase + lcrh);
  1438. }
  1439. static void pl011_shutdown(struct uart_port *port)
  1440. {
  1441. struct uart_amba_port *uap =
  1442. container_of(port, struct uart_amba_port, port);
  1443. unsigned int cr;
  1444. cancel_delayed_work_sync(&uap->tx_softirq_work);
  1445. /*
  1446. * disable all interrupts
  1447. */
  1448. spin_lock_irq(&uap->port.lock);
  1449. uap->im = 0;
  1450. writew(uap->im, uap->port.membase + UART011_IMSC);
  1451. writew(0xffff, uap->port.membase + UART011_ICR);
  1452. spin_unlock_irq(&uap->port.lock);
  1453. pl011_dma_shutdown(uap);
  1454. /*
  1455. * Free the interrupt
  1456. */
  1457. free_irq(uap->port.irq, uap);
  1458. /*
  1459. * disable the port
  1460. * disable the port. It should not disable RTS and DTR.
  1461. * Also RTS and DTR state should be preserved to restore
  1462. * it during startup().
  1463. */
  1464. uap->autorts = false;
  1465. spin_lock_irq(&uap->port.lock);
  1466. cr = readw(uap->port.membase + UART011_CR);
  1467. uap->old_cr = cr;
  1468. cr &= UART011_CR_RTS | UART011_CR_DTR;
  1469. cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
  1470. writew(cr, uap->port.membase + UART011_CR);
  1471. spin_unlock_irq(&uap->port.lock);
  1472. /*
  1473. * disable break condition and fifos
  1474. */
  1475. pl011_shutdown_channel(uap, uap->lcrh_rx);
  1476. if (uap->lcrh_rx != uap->lcrh_tx)
  1477. pl011_shutdown_channel(uap, uap->lcrh_tx);
  1478. /*
  1479. * Shut down the clock producer
  1480. */
  1481. clk_disable_unprepare(uap->clk);
  1482. /* Optionally let pins go into sleep states */
  1483. pinctrl_pm_select_sleep_state(port->dev);
  1484. if (dev_get_platdata(uap->port.dev)) {
  1485. struct amba_pl011_data *plat;
  1486. plat = dev_get_platdata(uap->port.dev);
  1487. if (plat->exit)
  1488. plat->exit();
  1489. }
  1490. if (uap->port.ops->flush_buffer)
  1491. uap->port.ops->flush_buffer(port);
  1492. }
  1493. static void
  1494. pl011_set_termios(struct uart_port *port, struct ktermios *termios,
  1495. struct ktermios *old)
  1496. {
  1497. struct uart_amba_port *uap =
  1498. container_of(port, struct uart_amba_port, port);
  1499. unsigned int lcr_h, old_cr;
  1500. unsigned long flags;
  1501. unsigned int baud, quot, clkdiv;
  1502. if (uap->vendor->oversampling)
  1503. clkdiv = 8;
  1504. else
  1505. clkdiv = 16;
  1506. /*
  1507. * Ask the core to calculate the divisor for us.
  1508. */
  1509. baud = uart_get_baud_rate(port, termios, old, 0,
  1510. port->uartclk / clkdiv);
  1511. #ifdef CONFIG_DMA_ENGINE
  1512. /*
  1513. * Adjust RX DMA polling rate with baud rate if not specified.
  1514. */
  1515. if (uap->dmarx.auto_poll_rate)
  1516. uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
  1517. #endif
  1518. if (baud > port->uartclk/16)
  1519. quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
  1520. else
  1521. quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
  1522. switch (termios->c_cflag & CSIZE) {
  1523. case CS5:
  1524. lcr_h = UART01x_LCRH_WLEN_5;
  1525. break;
  1526. case CS6:
  1527. lcr_h = UART01x_LCRH_WLEN_6;
  1528. break;
  1529. case CS7:
  1530. lcr_h = UART01x_LCRH_WLEN_7;
  1531. break;
  1532. default: // CS8
  1533. lcr_h = UART01x_LCRH_WLEN_8;
  1534. break;
  1535. }
  1536. if (termios->c_cflag & CSTOPB)
  1537. lcr_h |= UART01x_LCRH_STP2;
  1538. if (termios->c_cflag & PARENB) {
  1539. lcr_h |= UART01x_LCRH_PEN;
  1540. if (!(termios->c_cflag & PARODD))
  1541. lcr_h |= UART01x_LCRH_EPS;
  1542. }
  1543. if (uap->fifosize > 1)
  1544. lcr_h |= UART01x_LCRH_FEN;
  1545. spin_lock_irqsave(&port->lock, flags);
  1546. /*
  1547. * Update the per-port timeout.
  1548. */
  1549. uart_update_timeout(port, termios->c_cflag, baud);
  1550. port->read_status_mask = UART011_DR_OE | 255;
  1551. if (termios->c_iflag & INPCK)
  1552. port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
  1553. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  1554. port->read_status_mask |= UART011_DR_BE;
  1555. /*
  1556. * Characters to ignore
  1557. */
  1558. port->ignore_status_mask = 0;
  1559. if (termios->c_iflag & IGNPAR)
  1560. port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
  1561. if (termios->c_iflag & IGNBRK) {
  1562. port->ignore_status_mask |= UART011_DR_BE;
  1563. /*
  1564. * If we're ignoring parity and break indicators,
  1565. * ignore overruns too (for real raw support).
  1566. */
  1567. if (termios->c_iflag & IGNPAR)
  1568. port->ignore_status_mask |= UART011_DR_OE;
  1569. }
  1570. /*
  1571. * Ignore all characters if CREAD is not set.
  1572. */
  1573. if ((termios->c_cflag & CREAD) == 0)
  1574. port->ignore_status_mask |= UART_DUMMY_DR_RX;
  1575. if (UART_ENABLE_MS(port, termios->c_cflag))
  1576. pl011_enable_ms(port);
  1577. /* first, disable everything */
  1578. old_cr = readw(port->membase + UART011_CR);
  1579. writew(0, port->membase + UART011_CR);
  1580. if (termios->c_cflag & CRTSCTS) {
  1581. if (old_cr & UART011_CR_RTS)
  1582. old_cr |= UART011_CR_RTSEN;
  1583. old_cr |= UART011_CR_CTSEN;
  1584. uap->autorts = true;
  1585. } else {
  1586. old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
  1587. uap->autorts = false;
  1588. }
  1589. if (uap->vendor->oversampling) {
  1590. if (baud > port->uartclk / 16)
  1591. old_cr |= ST_UART011_CR_OVSFACT;
  1592. else
  1593. old_cr &= ~ST_UART011_CR_OVSFACT;
  1594. }
  1595. /*
  1596. * Workaround for the ST Micro oversampling variants to
  1597. * increase the bitrate slightly, by lowering the divisor,
  1598. * to avoid delayed sampling of start bit at high speeds,
  1599. * else we see data corruption.
  1600. */
  1601. if (uap->vendor->oversampling) {
  1602. if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
  1603. quot -= 1;
  1604. else if ((baud > 3250000) && (quot > 2))
  1605. quot -= 2;
  1606. }
  1607. /* Set baud rate */
  1608. writew(quot & 0x3f, port->membase + UART011_FBRD);
  1609. writew(quot >> 6, port->membase + UART011_IBRD);
  1610. /*
  1611. * ----------v----------v----------v----------v-----
  1612. * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
  1613. * UART011_FBRD & UART011_IBRD.
  1614. * ----------^----------^----------^----------^-----
  1615. */
  1616. pl011_write_lcr_h(uap, lcr_h);
  1617. writew(old_cr, port->membase + UART011_CR);
  1618. spin_unlock_irqrestore(&port->lock, flags);
  1619. }
  1620. static const char *pl011_type(struct uart_port *port)
  1621. {
  1622. struct uart_amba_port *uap =
  1623. container_of(port, struct uart_amba_port, port);
  1624. return uap->port.type == PORT_AMBA ? uap->type : NULL;
  1625. }
  1626. /*
  1627. * Release the memory region(s) being used by 'port'
  1628. */
  1629. static void pl011_release_port(struct uart_port *port)
  1630. {
  1631. release_mem_region(port->mapbase, SZ_4K);
  1632. }
  1633. /*
  1634. * Request the memory region(s) being used by 'port'
  1635. */
  1636. static int pl011_request_port(struct uart_port *port)
  1637. {
  1638. return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
  1639. != NULL ? 0 : -EBUSY;
  1640. }
  1641. /*
  1642. * Configure/autoconfigure the port.
  1643. */
  1644. static void pl011_config_port(struct uart_port *port, int flags)
  1645. {
  1646. if (flags & UART_CONFIG_TYPE) {
  1647. port->type = PORT_AMBA;
  1648. pl011_request_port(port);
  1649. }
  1650. }
  1651. /*
  1652. * verify the new serial_struct (for TIOCSSERIAL).
  1653. */
  1654. static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
  1655. {
  1656. int ret = 0;
  1657. if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
  1658. ret = -EINVAL;
  1659. if (ser->irq < 0 || ser->irq >= nr_irqs)
  1660. ret = -EINVAL;
  1661. if (ser->baud_base < 9600)
  1662. ret = -EINVAL;
  1663. return ret;
  1664. }
  1665. static struct uart_ops amba_pl011_pops = {
  1666. .tx_empty = pl011_tx_empty,
  1667. .set_mctrl = pl011_set_mctrl,
  1668. .get_mctrl = pl011_get_mctrl,
  1669. .stop_tx = pl011_stop_tx,
  1670. .start_tx = pl011_start_tx,
  1671. .stop_rx = pl011_stop_rx,
  1672. .enable_ms = pl011_enable_ms,
  1673. .break_ctl = pl011_break_ctl,
  1674. .startup = pl011_startup,
  1675. .shutdown = pl011_shutdown,
  1676. .flush_buffer = pl011_dma_flush_buffer,
  1677. .set_termios = pl011_set_termios,
  1678. .type = pl011_type,
  1679. .release_port = pl011_release_port,
  1680. .request_port = pl011_request_port,
  1681. .config_port = pl011_config_port,
  1682. .verify_port = pl011_verify_port,
  1683. #ifdef CONFIG_CONSOLE_POLL
  1684. .poll_init = pl011_hwinit,
  1685. .poll_get_char = pl011_get_poll_char,
  1686. .poll_put_char = pl011_put_poll_char,
  1687. #endif
  1688. };
  1689. static struct uart_amba_port *amba_ports[UART_NR];
  1690. #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
  1691. static void pl011_console_putchar(struct uart_port *port, int ch)
  1692. {
  1693. struct uart_amba_port *uap =
  1694. container_of(port, struct uart_amba_port, port);
  1695. while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
  1696. barrier();
  1697. writew(ch, uap->port.membase + UART01x_DR);
  1698. }
  1699. static void
  1700. pl011_console_write(struct console *co, const char *s, unsigned int count)
  1701. {
  1702. struct uart_amba_port *uap = amba_ports[co->index];
  1703. unsigned int status, old_cr, new_cr;
  1704. unsigned long flags;
  1705. int locked = 1;
  1706. clk_enable(uap->clk);
  1707. local_irq_save(flags);
  1708. if (uap->port.sysrq)
  1709. locked = 0;
  1710. else if (oops_in_progress)
  1711. locked = spin_trylock(&uap->port.lock);
  1712. else
  1713. spin_lock(&uap->port.lock);
  1714. /*
  1715. * First save the CR then disable the interrupts
  1716. */
  1717. old_cr = readw(uap->port.membase + UART011_CR);
  1718. new_cr = old_cr & ~UART011_CR_CTSEN;
  1719. new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
  1720. writew(new_cr, uap->port.membase + UART011_CR);
  1721. uart_console_write(&uap->port, s, count, pl011_console_putchar);
  1722. /*
  1723. * Finally, wait for transmitter to become empty
  1724. * and restore the TCR
  1725. */
  1726. do {
  1727. status = readw(uap->port.membase + UART01x_FR);
  1728. } while (status & UART01x_FR_BUSY);
  1729. writew(old_cr, uap->port.membase + UART011_CR);
  1730. if (locked)
  1731. spin_unlock(&uap->port.lock);
  1732. local_irq_restore(flags);
  1733. clk_disable(uap->clk);
  1734. }
  1735. static void __init
  1736. pl011_console_get_options(struct uart_amba_port *uap, int *baud,
  1737. int *parity, int *bits)
  1738. {
  1739. if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
  1740. unsigned int lcr_h, ibrd, fbrd;
  1741. lcr_h = readw(uap->port.membase + uap->lcrh_tx);
  1742. *parity = 'n';
  1743. if (lcr_h & UART01x_LCRH_PEN) {
  1744. if (lcr_h & UART01x_LCRH_EPS)
  1745. *parity = 'e';
  1746. else
  1747. *parity = 'o';
  1748. }
  1749. if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
  1750. *bits = 7;
  1751. else
  1752. *bits = 8;
  1753. ibrd = readw(uap->port.membase + UART011_IBRD);
  1754. fbrd = readw(uap->port.membase + UART011_FBRD);
  1755. *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
  1756. if (uap->vendor->oversampling) {
  1757. if (readw(uap->port.membase + UART011_CR)
  1758. & ST_UART011_CR_OVSFACT)
  1759. *baud *= 2;
  1760. }
  1761. }
  1762. }
  1763. static int __init pl011_console_setup(struct console *co, char *options)
  1764. {
  1765. struct uart_amba_port *uap;
  1766. int baud = 38400;
  1767. int bits = 8;
  1768. int parity = 'n';
  1769. int flow = 'n';
  1770. int ret;
  1771. /*
  1772. * Check whether an invalid uart number has been specified, and
  1773. * if so, search for the first available port that does have
  1774. * console support.
  1775. */
  1776. if (co->index >= UART_NR)
  1777. co->index = 0;
  1778. uap = amba_ports[co->index];
  1779. if (!uap)
  1780. return -ENODEV;
  1781. /* Allow pins to be muxed in and configured */
  1782. pinctrl_pm_select_default_state(uap->port.dev);
  1783. ret = clk_prepare(uap->clk);
  1784. if (ret)
  1785. return ret;
  1786. if (dev_get_platdata(uap->port.dev)) {
  1787. struct amba_pl011_data *plat;
  1788. plat = dev_get_platdata(uap->port.dev);
  1789. if (plat->init)
  1790. plat->init();
  1791. }
  1792. uap->port.uartclk = clk_get_rate(uap->clk);
  1793. if (options)
  1794. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1795. else
  1796. pl011_console_get_options(uap, &baud, &parity, &bits);
  1797. return uart_set_options(&uap->port, co, baud, parity, bits, flow);
  1798. }
  1799. static struct uart_driver amba_reg;
  1800. static struct console amba_console = {
  1801. .name = "ttyAMA",
  1802. .write = pl011_console_write,
  1803. .device = uart_console_device,
  1804. .setup = pl011_console_setup,
  1805. .flags = CON_PRINTBUFFER,
  1806. .index = -1,
  1807. .data = &amba_reg,
  1808. };
  1809. #define AMBA_CONSOLE (&amba_console)
  1810. static void pl011_putc(struct uart_port *port, int c)
  1811. {
  1812. while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
  1813. ;
  1814. writeb(c, port->membase + UART01x_DR);
  1815. while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
  1816. ;
  1817. }
  1818. static void pl011_early_write(struct console *con, const char *s, unsigned n)
  1819. {
  1820. struct earlycon_device *dev = con->data;
  1821. uart_console_write(&dev->port, s, n, pl011_putc);
  1822. }
  1823. static int __init pl011_early_console_setup(struct earlycon_device *device,
  1824. const char *opt)
  1825. {
  1826. if (!device->port.membase)
  1827. return -ENODEV;
  1828. device->con->write = pl011_early_write;
  1829. return 0;
  1830. }
  1831. EARLYCON_DECLARE(pl011, pl011_early_console_setup);
  1832. OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
  1833. #else
  1834. #define AMBA_CONSOLE NULL
  1835. #endif
  1836. static struct uart_driver amba_reg = {
  1837. .owner = THIS_MODULE,
  1838. .driver_name = "ttyAMA",
  1839. .dev_name = "ttyAMA",
  1840. .major = SERIAL_AMBA_MAJOR,
  1841. .minor = SERIAL_AMBA_MINOR,
  1842. .nr = UART_NR,
  1843. .cons = AMBA_CONSOLE,
  1844. };
  1845. static int pl011_probe_dt_alias(int index, struct device *dev)
  1846. {
  1847. struct device_node *np;
  1848. static bool seen_dev_with_alias = false;
  1849. static bool seen_dev_without_alias = false;
  1850. int ret = index;
  1851. if (!IS_ENABLED(CONFIG_OF))
  1852. return ret;
  1853. np = dev->of_node;
  1854. if (!np)
  1855. return ret;
  1856. ret = of_alias_get_id(np, "serial");
  1857. if (IS_ERR_VALUE(ret)) {
  1858. seen_dev_without_alias = true;
  1859. ret = index;
  1860. } else {
  1861. seen_dev_with_alias = true;
  1862. if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
  1863. dev_warn(dev, "requested serial port %d not available.\n", ret);
  1864. ret = index;
  1865. }
  1866. }
  1867. if (seen_dev_with_alias && seen_dev_without_alias)
  1868. dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
  1869. return ret;
  1870. }
  1871. static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
  1872. {
  1873. struct uart_amba_port *uap;
  1874. struct vendor_data *vendor = id->data;
  1875. void __iomem *base;
  1876. int i, ret;
  1877. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  1878. if (amba_ports[i] == NULL)
  1879. break;
  1880. if (i == ARRAY_SIZE(amba_ports))
  1881. return -EBUSY;
  1882. uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
  1883. GFP_KERNEL);
  1884. if (uap == NULL)
  1885. return -ENOMEM;
  1886. i = pl011_probe_dt_alias(i, &dev->dev);
  1887. base = devm_ioremap(&dev->dev, dev->res.start,
  1888. resource_size(&dev->res));
  1889. if (!base)
  1890. return -ENOMEM;
  1891. uap->clk = devm_clk_get(&dev->dev, NULL);
  1892. if (IS_ERR(uap->clk))
  1893. return PTR_ERR(uap->clk);
  1894. uap->vendor = vendor;
  1895. uap->lcrh_rx = vendor->lcrh_rx;
  1896. uap->lcrh_tx = vendor->lcrh_tx;
  1897. uap->old_cr = 0;
  1898. uap->fifosize = vendor->get_fifosize(dev);
  1899. uap->port.dev = &dev->dev;
  1900. uap->port.mapbase = dev->res.start;
  1901. uap->port.membase = base;
  1902. uap->port.iotype = UPIO_MEM;
  1903. uap->port.irq = dev->irq[0];
  1904. uap->port.fifosize = uap->fifosize;
  1905. uap->port.ops = &amba_pl011_pops;
  1906. uap->port.flags = UPF_BOOT_AUTOCONF;
  1907. uap->port.line = i;
  1908. INIT_DELAYED_WORK(&uap->tx_softirq_work, pl011_tx_softirq);
  1909. /* Ensure interrupts from this UART are masked and cleared */
  1910. writew(0, uap->port.membase + UART011_IMSC);
  1911. writew(0xffff, uap->port.membase + UART011_ICR);
  1912. snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
  1913. amba_ports[i] = uap;
  1914. amba_set_drvdata(dev, uap);
  1915. if (!amba_reg.state) {
  1916. ret = uart_register_driver(&amba_reg);
  1917. if (ret < 0) {
  1918. dev_err(&dev->dev,
  1919. "Failed to register AMBA-PL011 driver\n");
  1920. return ret;
  1921. }
  1922. }
  1923. ret = uart_add_one_port(&amba_reg, &uap->port);
  1924. if (ret) {
  1925. amba_ports[i] = NULL;
  1926. uart_unregister_driver(&amba_reg);
  1927. }
  1928. return ret;
  1929. }
  1930. static int pl011_remove(struct amba_device *dev)
  1931. {
  1932. struct uart_amba_port *uap = amba_get_drvdata(dev);
  1933. bool busy = false;
  1934. int i;
  1935. uart_remove_one_port(&amba_reg, &uap->port);
  1936. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  1937. if (amba_ports[i] == uap)
  1938. amba_ports[i] = NULL;
  1939. else if (amba_ports[i])
  1940. busy = true;
  1941. pl011_dma_remove(uap);
  1942. if (!busy)
  1943. uart_unregister_driver(&amba_reg);
  1944. return 0;
  1945. }
  1946. #ifdef CONFIG_PM_SLEEP
  1947. static int pl011_suspend(struct device *dev)
  1948. {
  1949. struct uart_amba_port *uap = dev_get_drvdata(dev);
  1950. if (!uap)
  1951. return -EINVAL;
  1952. return uart_suspend_port(&amba_reg, &uap->port);
  1953. }
  1954. static int pl011_resume(struct device *dev)
  1955. {
  1956. struct uart_amba_port *uap = dev_get_drvdata(dev);
  1957. if (!uap)
  1958. return -EINVAL;
  1959. return uart_resume_port(&amba_reg, &uap->port);
  1960. }
  1961. #endif
  1962. static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
  1963. static struct amba_id pl011_ids[] = {
  1964. {
  1965. .id = 0x00041011,
  1966. .mask = 0x000fffff,
  1967. .data = &vendor_arm,
  1968. },
  1969. {
  1970. .id = 0x00380802,
  1971. .mask = 0x00ffffff,
  1972. .data = &vendor_st,
  1973. },
  1974. { 0, 0 },
  1975. };
  1976. MODULE_DEVICE_TABLE(amba, pl011_ids);
  1977. static struct amba_driver pl011_driver = {
  1978. .drv = {
  1979. .name = "uart-pl011",
  1980. .pm = &pl011_dev_pm_ops,
  1981. },
  1982. .id_table = pl011_ids,
  1983. .probe = pl011_probe,
  1984. .remove = pl011_remove,
  1985. };
  1986. static int __init pl011_init(void)
  1987. {
  1988. printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
  1989. return amba_driver_register(&pl011_driver);
  1990. }
  1991. static void __exit pl011_exit(void)
  1992. {
  1993. amba_driver_unregister(&pl011_driver);
  1994. }
  1995. /*
  1996. * While this can be a module, if builtin it's most likely the console
  1997. * So let's leave module_exit but move module_init to an earlier place
  1998. */
  1999. arch_initcall(pl011_init);
  2000. module_exit(pl011_exit);
  2001. MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
  2002. MODULE_DESCRIPTION("ARM AMBA serial port driver");
  2003. MODULE_LICENSE("GPL");