rtc-ds1307.c 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258
  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/i2c.h>
  17. #include <linux/string.h>
  18. #include <linux/rtc.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc/ds1307.h>
  21. /*
  22. * We can't determine type by probing, but if we expect pre-Linux code
  23. * to have set the chip up as a clock (turning on the oscillator and
  24. * setting the date and time), Linux can ignore the non-clock features.
  25. * That's a natural job for a factory or repair bench.
  26. */
  27. enum ds_type {
  28. ds_1307,
  29. ds_1337,
  30. ds_1338,
  31. ds_1339,
  32. ds_1340,
  33. ds_1388,
  34. ds_3231,
  35. m41t00,
  36. mcp794xx,
  37. rx_8025,
  38. last_ds_type /* always last */
  39. /* rs5c372 too? different address... */
  40. };
  41. /* RTC registers don't differ much, except for the century flag */
  42. #define DS1307_REG_SECS 0x00 /* 00-59 */
  43. # define DS1307_BIT_CH 0x80
  44. # define DS1340_BIT_nEOSC 0x80
  45. # define MCP794XX_BIT_ST 0x80
  46. #define DS1307_REG_MIN 0x01 /* 00-59 */
  47. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  48. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  49. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  51. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  52. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  53. # define MCP794XX_BIT_VBATEN 0x08
  54. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  55. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  56. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  57. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  58. /*
  59. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  60. * start at 7, and they differ a LOT. Only control and status matter for
  61. * basic RTC date and time functionality; be careful using them.
  62. */
  63. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  64. # define DS1307_BIT_OUT 0x80
  65. # define DS1338_BIT_OSF 0x20
  66. # define DS1307_BIT_SQWE 0x10
  67. # define DS1307_BIT_RS1 0x02
  68. # define DS1307_BIT_RS0 0x01
  69. #define DS1337_REG_CONTROL 0x0e
  70. # define DS1337_BIT_nEOSC 0x80
  71. # define DS1339_BIT_BBSQI 0x20
  72. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  73. # define DS1337_BIT_RS2 0x10
  74. # define DS1337_BIT_RS1 0x08
  75. # define DS1337_BIT_INTCN 0x04
  76. # define DS1337_BIT_A2IE 0x02
  77. # define DS1337_BIT_A1IE 0x01
  78. #define DS1340_REG_CONTROL 0x07
  79. # define DS1340_BIT_OUT 0x80
  80. # define DS1340_BIT_FT 0x40
  81. # define DS1340_BIT_CALIB_SIGN 0x20
  82. # define DS1340_M_CALIBRATION 0x1f
  83. #define DS1340_REG_FLAG 0x09
  84. # define DS1340_BIT_OSF 0x80
  85. #define DS1337_REG_STATUS 0x0f
  86. # define DS1337_BIT_OSF 0x80
  87. # define DS1337_BIT_A2I 0x02
  88. # define DS1337_BIT_A1I 0x01
  89. #define DS1339_REG_ALARM1_SECS 0x07
  90. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  91. #define RX8025_REG_CTRL1 0x0e
  92. # define RX8025_BIT_2412 0x20
  93. #define RX8025_REG_CTRL2 0x0f
  94. # define RX8025_BIT_PON 0x10
  95. # define RX8025_BIT_VDET 0x40
  96. # define RX8025_BIT_XST 0x20
  97. struct ds1307 {
  98. u8 offset; /* register's offset */
  99. u8 regs[11];
  100. u16 nvram_offset;
  101. struct bin_attribute *nvram;
  102. enum ds_type type;
  103. unsigned long flags;
  104. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  105. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  106. struct i2c_client *client;
  107. struct rtc_device *rtc;
  108. struct work_struct work;
  109. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  110. u8 length, u8 *values);
  111. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  112. u8 length, const u8 *values);
  113. };
  114. struct chip_desc {
  115. unsigned alarm:1;
  116. u16 nvram_offset;
  117. u16 nvram_size;
  118. u16 trickle_charger_reg;
  119. u8 trickle_charger_setup;
  120. u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
  121. };
  122. static u8 do_trickle_setup_ds1339(struct i2c_client *,
  123. uint32_t ohms, bool diode);
  124. static struct chip_desc chips[last_ds_type] = {
  125. [ds_1307] = {
  126. .nvram_offset = 8,
  127. .nvram_size = 56,
  128. },
  129. [ds_1337] = {
  130. .alarm = 1,
  131. },
  132. [ds_1338] = {
  133. .nvram_offset = 8,
  134. .nvram_size = 56,
  135. },
  136. [ds_1339] = {
  137. .alarm = 1,
  138. .trickle_charger_reg = 0x10,
  139. .do_trickle_setup = &do_trickle_setup_ds1339,
  140. },
  141. [ds_1340] = {
  142. .trickle_charger_reg = 0x08,
  143. },
  144. [ds_1388] = {
  145. .trickle_charger_reg = 0x0a,
  146. },
  147. [ds_3231] = {
  148. .alarm = 1,
  149. },
  150. [mcp794xx] = {
  151. .alarm = 1,
  152. /* this is battery backed SRAM */
  153. .nvram_offset = 0x20,
  154. .nvram_size = 0x40,
  155. },
  156. };
  157. static const struct i2c_device_id ds1307_id[] = {
  158. { "ds1307", ds_1307 },
  159. { "ds1337", ds_1337 },
  160. { "ds1338", ds_1338 },
  161. { "ds1339", ds_1339 },
  162. { "ds1388", ds_1388 },
  163. { "ds1340", ds_1340 },
  164. { "ds3231", ds_3231 },
  165. { "m41t00", m41t00 },
  166. { "mcp7940x", mcp794xx },
  167. { "mcp7941x", mcp794xx },
  168. { "pt7c4338", ds_1307 },
  169. { "rx8025", rx_8025 },
  170. { }
  171. };
  172. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  173. /*----------------------------------------------------------------------*/
  174. #define BLOCK_DATA_MAX_TRIES 10
  175. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  176. u8 command, u8 length, u8 *values)
  177. {
  178. s32 i, data;
  179. for (i = 0; i < length; i++) {
  180. data = i2c_smbus_read_byte_data(client, command + i);
  181. if (data < 0)
  182. return data;
  183. values[i] = data;
  184. }
  185. return i;
  186. }
  187. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  188. u8 length, u8 *values)
  189. {
  190. u8 oldvalues[255];
  191. s32 ret;
  192. int tries = 0;
  193. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  194. ret = ds1307_read_block_data_once(client, command, length, values);
  195. if (ret < 0)
  196. return ret;
  197. do {
  198. if (++tries > BLOCK_DATA_MAX_TRIES) {
  199. dev_err(&client->dev,
  200. "ds1307_read_block_data failed\n");
  201. return -EIO;
  202. }
  203. memcpy(oldvalues, values, length);
  204. ret = ds1307_read_block_data_once(client, command, length,
  205. values);
  206. if (ret < 0)
  207. return ret;
  208. } while (memcmp(oldvalues, values, length));
  209. return length;
  210. }
  211. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  212. u8 length, const u8 *values)
  213. {
  214. u8 currvalues[255];
  215. int tries = 0;
  216. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  217. do {
  218. s32 i, ret;
  219. if (++tries > BLOCK_DATA_MAX_TRIES) {
  220. dev_err(&client->dev,
  221. "ds1307_write_block_data failed\n");
  222. return -EIO;
  223. }
  224. for (i = 0; i < length; i++) {
  225. ret = i2c_smbus_write_byte_data(client, command + i,
  226. values[i]);
  227. if (ret < 0)
  228. return ret;
  229. }
  230. ret = ds1307_read_block_data_once(client, command, length,
  231. currvalues);
  232. if (ret < 0)
  233. return ret;
  234. } while (memcmp(currvalues, values, length));
  235. return length;
  236. }
  237. /*----------------------------------------------------------------------*/
  238. /* These RTC devices are not designed to be connected to a SMbus adapter.
  239. SMbus limits block operations length to 32 bytes, whereas it's not
  240. limited on I2C buses. As a result, accesses may exceed 32 bytes;
  241. in that case, split them into smaller blocks */
  242. static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
  243. u8 command, u8 length, const u8 *values)
  244. {
  245. u8 suboffset = 0;
  246. if (length <= I2C_SMBUS_BLOCK_MAX)
  247. return i2c_smbus_write_i2c_block_data(client,
  248. command, length, values);
  249. while (suboffset < length) {
  250. s32 retval = i2c_smbus_write_i2c_block_data(client,
  251. command + suboffset,
  252. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  253. values + suboffset);
  254. if (retval < 0)
  255. return retval;
  256. suboffset += I2C_SMBUS_BLOCK_MAX;
  257. }
  258. return length;
  259. }
  260. static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
  261. u8 command, u8 length, u8 *values)
  262. {
  263. u8 suboffset = 0;
  264. if (length <= I2C_SMBUS_BLOCK_MAX)
  265. return i2c_smbus_read_i2c_block_data(client,
  266. command, length, values);
  267. while (suboffset < length) {
  268. s32 retval = i2c_smbus_read_i2c_block_data(client,
  269. command + suboffset,
  270. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  271. values + suboffset);
  272. if (retval < 0)
  273. return retval;
  274. suboffset += I2C_SMBUS_BLOCK_MAX;
  275. }
  276. return length;
  277. }
  278. /*----------------------------------------------------------------------*/
  279. /*
  280. * The IRQ logic includes a "real" handler running in IRQ context just
  281. * long enough to schedule this workqueue entry. We need a task context
  282. * to talk to the RTC, since I2C I/O calls require that; and disable the
  283. * IRQ until we clear its status on the chip, so that this handler can
  284. * work with any type of triggering (not just falling edge).
  285. *
  286. * The ds1337 and ds1339 both have two alarms, but we only use the first
  287. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  288. * signal; ds1339 chips have only one alarm signal.
  289. */
  290. static void ds1307_work(struct work_struct *work)
  291. {
  292. struct ds1307 *ds1307;
  293. struct i2c_client *client;
  294. struct mutex *lock;
  295. int stat, control;
  296. ds1307 = container_of(work, struct ds1307, work);
  297. client = ds1307->client;
  298. lock = &ds1307->rtc->ops_lock;
  299. mutex_lock(lock);
  300. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  301. if (stat < 0)
  302. goto out;
  303. if (stat & DS1337_BIT_A1I) {
  304. stat &= ~DS1337_BIT_A1I;
  305. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  306. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  307. if (control < 0)
  308. goto out;
  309. control &= ~DS1337_BIT_A1IE;
  310. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  311. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  312. }
  313. out:
  314. if (test_bit(HAS_ALARM, &ds1307->flags))
  315. enable_irq(client->irq);
  316. mutex_unlock(lock);
  317. }
  318. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  319. {
  320. struct i2c_client *client = dev_id;
  321. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  322. disable_irq_nosync(irq);
  323. schedule_work(&ds1307->work);
  324. return IRQ_HANDLED;
  325. }
  326. /*----------------------------------------------------------------------*/
  327. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  328. {
  329. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  330. int tmp;
  331. /* read the RTC date and time registers all at once */
  332. tmp = ds1307->read_block_data(ds1307->client,
  333. ds1307->offset, 7, ds1307->regs);
  334. if (tmp != 7) {
  335. dev_err(dev, "%s error %d\n", "read", tmp);
  336. return -EIO;
  337. }
  338. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  339. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  340. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  341. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  342. t->tm_hour = bcd2bin(tmp);
  343. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  344. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  345. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  346. t->tm_mon = bcd2bin(tmp) - 1;
  347. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  348. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  349. dev_dbg(dev, "%s secs=%d, mins=%d, "
  350. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  351. "read", t->tm_sec, t->tm_min,
  352. t->tm_hour, t->tm_mday,
  353. t->tm_mon, t->tm_year, t->tm_wday);
  354. /* initial clock setting can be undefined */
  355. return rtc_valid_tm(t);
  356. }
  357. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  358. {
  359. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  360. int result;
  361. int tmp;
  362. u8 *buf = ds1307->regs;
  363. dev_dbg(dev, "%s secs=%d, mins=%d, "
  364. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  365. "write", t->tm_sec, t->tm_min,
  366. t->tm_hour, t->tm_mday,
  367. t->tm_mon, t->tm_year, t->tm_wday);
  368. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  369. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  370. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  371. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  372. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  373. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  374. /* assume 20YY not 19YY */
  375. tmp = t->tm_year - 100;
  376. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  377. switch (ds1307->type) {
  378. case ds_1337:
  379. case ds_1339:
  380. case ds_3231:
  381. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  382. break;
  383. case ds_1340:
  384. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  385. | DS1340_BIT_CENTURY;
  386. break;
  387. case mcp794xx:
  388. /*
  389. * these bits were cleared when preparing the date/time
  390. * values and need to be set again before writing the
  391. * buffer out to the device.
  392. */
  393. buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
  394. buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
  395. break;
  396. default:
  397. break;
  398. }
  399. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  400. result = ds1307->write_block_data(ds1307->client,
  401. ds1307->offset, 7, buf);
  402. if (result < 0) {
  403. dev_err(dev, "%s error %d\n", "write", result);
  404. return result;
  405. }
  406. return 0;
  407. }
  408. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  409. {
  410. struct i2c_client *client = to_i2c_client(dev);
  411. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  412. int ret;
  413. if (!test_bit(HAS_ALARM, &ds1307->flags))
  414. return -EINVAL;
  415. /* read all ALARM1, ALARM2, and status registers at once */
  416. ret = ds1307->read_block_data(client,
  417. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  418. if (ret != 9) {
  419. dev_err(dev, "%s error %d\n", "alarm read", ret);
  420. return -EIO;
  421. }
  422. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  423. "alarm read",
  424. ds1307->regs[0], ds1307->regs[1],
  425. ds1307->regs[2], ds1307->regs[3],
  426. ds1307->regs[4], ds1307->regs[5],
  427. ds1307->regs[6], ds1307->regs[7],
  428. ds1307->regs[8]);
  429. /*
  430. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  431. * and that all four fields are checked matches
  432. */
  433. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  434. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  435. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  436. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  437. t->time.tm_mon = -1;
  438. t->time.tm_year = -1;
  439. t->time.tm_wday = -1;
  440. t->time.tm_yday = -1;
  441. t->time.tm_isdst = -1;
  442. /* ... and status */
  443. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  444. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  445. dev_dbg(dev, "%s secs=%d, mins=%d, "
  446. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  447. "alarm read", t->time.tm_sec, t->time.tm_min,
  448. t->time.tm_hour, t->time.tm_mday,
  449. t->enabled, t->pending);
  450. return 0;
  451. }
  452. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  453. {
  454. struct i2c_client *client = to_i2c_client(dev);
  455. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  456. unsigned char *buf = ds1307->regs;
  457. u8 control, status;
  458. int ret;
  459. if (!test_bit(HAS_ALARM, &ds1307->flags))
  460. return -EINVAL;
  461. dev_dbg(dev, "%s secs=%d, mins=%d, "
  462. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  463. "alarm set", t->time.tm_sec, t->time.tm_min,
  464. t->time.tm_hour, t->time.tm_mday,
  465. t->enabled, t->pending);
  466. /* read current status of both alarms and the chip */
  467. ret = ds1307->read_block_data(client,
  468. DS1339_REG_ALARM1_SECS, 9, buf);
  469. if (ret != 9) {
  470. dev_err(dev, "%s error %d\n", "alarm write", ret);
  471. return -EIO;
  472. }
  473. control = ds1307->regs[7];
  474. status = ds1307->regs[8];
  475. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  476. "alarm set (old status)",
  477. ds1307->regs[0], ds1307->regs[1],
  478. ds1307->regs[2], ds1307->regs[3],
  479. ds1307->regs[4], ds1307->regs[5],
  480. ds1307->regs[6], control, status);
  481. /* set ALARM1, using 24 hour and day-of-month modes */
  482. buf[0] = bin2bcd(t->time.tm_sec);
  483. buf[1] = bin2bcd(t->time.tm_min);
  484. buf[2] = bin2bcd(t->time.tm_hour);
  485. buf[3] = bin2bcd(t->time.tm_mday);
  486. /* set ALARM2 to non-garbage */
  487. buf[4] = 0;
  488. buf[5] = 0;
  489. buf[6] = 0;
  490. /* optionally enable ALARM1 */
  491. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  492. if (t->enabled) {
  493. dev_dbg(dev, "alarm IRQ armed\n");
  494. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  495. }
  496. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  497. ret = ds1307->write_block_data(client,
  498. DS1339_REG_ALARM1_SECS, 9, buf);
  499. if (ret < 0) {
  500. dev_err(dev, "can't set alarm time\n");
  501. return ret;
  502. }
  503. return 0;
  504. }
  505. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  506. {
  507. struct i2c_client *client = to_i2c_client(dev);
  508. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  509. int ret;
  510. if (!test_bit(HAS_ALARM, &ds1307->flags))
  511. return -ENOTTY;
  512. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  513. if (ret < 0)
  514. return ret;
  515. if (enabled)
  516. ret |= DS1337_BIT_A1IE;
  517. else
  518. ret &= ~DS1337_BIT_A1IE;
  519. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  520. if (ret < 0)
  521. return ret;
  522. return 0;
  523. }
  524. static const struct rtc_class_ops ds13xx_rtc_ops = {
  525. .read_time = ds1307_get_time,
  526. .set_time = ds1307_set_time,
  527. .read_alarm = ds1337_read_alarm,
  528. .set_alarm = ds1337_set_alarm,
  529. .alarm_irq_enable = ds1307_alarm_irq_enable,
  530. };
  531. /*----------------------------------------------------------------------*/
  532. /*
  533. * Alarm support for mcp794xx devices.
  534. */
  535. #define MCP794XX_REG_CONTROL 0x07
  536. # define MCP794XX_BIT_ALM0_EN 0x10
  537. # define MCP794XX_BIT_ALM1_EN 0x20
  538. #define MCP794XX_REG_ALARM0_BASE 0x0a
  539. #define MCP794XX_REG_ALARM0_CTRL 0x0d
  540. #define MCP794XX_REG_ALARM1_BASE 0x11
  541. #define MCP794XX_REG_ALARM1_CTRL 0x14
  542. # define MCP794XX_BIT_ALMX_IF (1 << 3)
  543. # define MCP794XX_BIT_ALMX_C0 (1 << 4)
  544. # define MCP794XX_BIT_ALMX_C1 (1 << 5)
  545. # define MCP794XX_BIT_ALMX_C2 (1 << 6)
  546. # define MCP794XX_BIT_ALMX_POL (1 << 7)
  547. # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
  548. MCP794XX_BIT_ALMX_C1 | \
  549. MCP794XX_BIT_ALMX_C2)
  550. static void mcp794xx_work(struct work_struct *work)
  551. {
  552. struct ds1307 *ds1307 = container_of(work, struct ds1307, work);
  553. struct i2c_client *client = ds1307->client;
  554. int reg, ret;
  555. mutex_lock(&ds1307->rtc->ops_lock);
  556. /* Check and clear alarm 0 interrupt flag. */
  557. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL);
  558. if (reg < 0)
  559. goto out;
  560. if (!(reg & MCP794XX_BIT_ALMX_IF))
  561. goto out;
  562. reg &= ~MCP794XX_BIT_ALMX_IF;
  563. ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg);
  564. if (ret < 0)
  565. goto out;
  566. /* Disable alarm 0. */
  567. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
  568. if (reg < 0)
  569. goto out;
  570. reg &= ~MCP794XX_BIT_ALM0_EN;
  571. ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
  572. if (ret < 0)
  573. goto out;
  574. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  575. out:
  576. if (test_bit(HAS_ALARM, &ds1307->flags))
  577. enable_irq(client->irq);
  578. mutex_unlock(&ds1307->rtc->ops_lock);
  579. }
  580. static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  581. {
  582. struct i2c_client *client = to_i2c_client(dev);
  583. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  584. u8 *regs = ds1307->regs;
  585. int ret;
  586. if (!test_bit(HAS_ALARM, &ds1307->flags))
  587. return -EINVAL;
  588. /* Read control and alarm 0 registers. */
  589. ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  590. if (ret < 0)
  591. return ret;
  592. t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
  593. /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
  594. t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
  595. t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
  596. t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
  597. t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
  598. t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
  599. t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
  600. t->time.tm_year = -1;
  601. t->time.tm_yday = -1;
  602. t->time.tm_isdst = -1;
  603. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  604. "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
  605. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  606. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
  607. !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
  608. !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
  609. (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
  610. return 0;
  611. }
  612. static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  613. {
  614. struct i2c_client *client = to_i2c_client(dev);
  615. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  616. unsigned char *regs = ds1307->regs;
  617. int ret;
  618. if (!test_bit(HAS_ALARM, &ds1307->flags))
  619. return -EINVAL;
  620. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  621. "enabled=%d pending=%d\n", __func__,
  622. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  623. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
  624. t->enabled, t->pending);
  625. /* Read control and alarm 0 registers. */
  626. ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  627. if (ret < 0)
  628. return ret;
  629. /* Set alarm 0, using 24-hour and day-of-month modes. */
  630. regs[3] = bin2bcd(t->time.tm_sec);
  631. regs[4] = bin2bcd(t->time.tm_min);
  632. regs[5] = bin2bcd(t->time.tm_hour);
  633. regs[6] = bin2bcd(t->time.tm_wday) + 1;
  634. regs[7] = bin2bcd(t->time.tm_mday);
  635. regs[8] = bin2bcd(t->time.tm_mon) + 1;
  636. /* Clear the alarm 0 interrupt flag. */
  637. regs[6] &= ~MCP794XX_BIT_ALMX_IF;
  638. /* Set alarm match: second, minute, hour, day, date, month. */
  639. regs[6] |= MCP794XX_MSK_ALMX_MATCH;
  640. if (t->enabled)
  641. regs[0] |= MCP794XX_BIT_ALM0_EN;
  642. else
  643. regs[0] &= ~MCP794XX_BIT_ALM0_EN;
  644. ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  645. if (ret < 0)
  646. return ret;
  647. return 0;
  648. }
  649. static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
  650. {
  651. struct i2c_client *client = to_i2c_client(dev);
  652. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  653. int reg;
  654. if (!test_bit(HAS_ALARM, &ds1307->flags))
  655. return -EINVAL;
  656. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
  657. if (reg < 0)
  658. return reg;
  659. if (enabled)
  660. reg |= MCP794XX_BIT_ALM0_EN;
  661. else
  662. reg &= ~MCP794XX_BIT_ALM0_EN;
  663. return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
  664. }
  665. static const struct rtc_class_ops mcp794xx_rtc_ops = {
  666. .read_time = ds1307_get_time,
  667. .set_time = ds1307_set_time,
  668. .read_alarm = mcp794xx_read_alarm,
  669. .set_alarm = mcp794xx_set_alarm,
  670. .alarm_irq_enable = mcp794xx_alarm_irq_enable,
  671. };
  672. /*----------------------------------------------------------------------*/
  673. static ssize_t
  674. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  675. struct bin_attribute *attr,
  676. char *buf, loff_t off, size_t count)
  677. {
  678. struct i2c_client *client;
  679. struct ds1307 *ds1307;
  680. int result;
  681. client = kobj_to_i2c_client(kobj);
  682. ds1307 = i2c_get_clientdata(client);
  683. if (unlikely(off >= ds1307->nvram->size))
  684. return 0;
  685. if ((off + count) > ds1307->nvram->size)
  686. count = ds1307->nvram->size - off;
  687. if (unlikely(!count))
  688. return count;
  689. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  690. count, buf);
  691. if (result < 0)
  692. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  693. return result;
  694. }
  695. static ssize_t
  696. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  697. struct bin_attribute *attr,
  698. char *buf, loff_t off, size_t count)
  699. {
  700. struct i2c_client *client;
  701. struct ds1307 *ds1307;
  702. int result;
  703. client = kobj_to_i2c_client(kobj);
  704. ds1307 = i2c_get_clientdata(client);
  705. if (unlikely(off >= ds1307->nvram->size))
  706. return -EFBIG;
  707. if ((off + count) > ds1307->nvram->size)
  708. count = ds1307->nvram->size - off;
  709. if (unlikely(!count))
  710. return count;
  711. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  712. count, buf);
  713. if (result < 0) {
  714. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  715. return result;
  716. }
  717. return count;
  718. }
  719. /*----------------------------------------------------------------------*/
  720. static u8 do_trickle_setup_ds1339(struct i2c_client *client,
  721. uint32_t ohms, bool diode)
  722. {
  723. u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
  724. DS1307_TRICKLE_CHARGER_NO_DIODE;
  725. switch (ohms) {
  726. case 250:
  727. setup |= DS1307_TRICKLE_CHARGER_250_OHM;
  728. break;
  729. case 2000:
  730. setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
  731. break;
  732. case 4000:
  733. setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
  734. break;
  735. default:
  736. dev_warn(&client->dev,
  737. "Unsupported ohm value %u in dt\n", ohms);
  738. return 0;
  739. }
  740. return setup;
  741. }
  742. static void ds1307_trickle_of_init(struct i2c_client *client,
  743. struct chip_desc *chip)
  744. {
  745. uint32_t ohms = 0;
  746. bool diode = true;
  747. if (!chip->do_trickle_setup)
  748. goto out;
  749. if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
  750. goto out;
  751. if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
  752. diode = false;
  753. chip->trickle_charger_setup = chip->do_trickle_setup(client,
  754. ohms, diode);
  755. out:
  756. return;
  757. }
  758. static int ds1307_probe(struct i2c_client *client,
  759. const struct i2c_device_id *id)
  760. {
  761. struct ds1307 *ds1307;
  762. int err = -ENODEV;
  763. int tmp;
  764. struct chip_desc *chip = &chips[id->driver_data];
  765. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  766. bool want_irq = false;
  767. unsigned char *buf;
  768. struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
  769. static const int bbsqi_bitpos[] = {
  770. [ds_1337] = 0,
  771. [ds_1339] = DS1339_BIT_BBSQI,
  772. [ds_3231] = DS3231_BIT_BBSQW,
  773. };
  774. const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
  775. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  776. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  777. return -EIO;
  778. ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
  779. if (!ds1307)
  780. return -ENOMEM;
  781. i2c_set_clientdata(client, ds1307);
  782. ds1307->client = client;
  783. ds1307->type = id->driver_data;
  784. if (!pdata && client->dev.of_node)
  785. ds1307_trickle_of_init(client, chip);
  786. else if (pdata && pdata->trickle_charger_setup)
  787. chip->trickle_charger_setup = pdata->trickle_charger_setup;
  788. if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
  789. dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
  790. DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
  791. chip->trickle_charger_reg);
  792. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  793. DS13XX_TRICKLE_CHARGER_MAGIC |
  794. chip->trickle_charger_setup);
  795. }
  796. buf = ds1307->regs;
  797. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  798. ds1307->read_block_data = ds1307_native_smbus_read_block_data;
  799. ds1307->write_block_data = ds1307_native_smbus_write_block_data;
  800. } else {
  801. ds1307->read_block_data = ds1307_read_block_data;
  802. ds1307->write_block_data = ds1307_write_block_data;
  803. }
  804. switch (ds1307->type) {
  805. case ds_1337:
  806. case ds_1339:
  807. case ds_3231:
  808. /* get registers that the "rtc" read below won't read... */
  809. tmp = ds1307->read_block_data(ds1307->client,
  810. DS1337_REG_CONTROL, 2, buf);
  811. if (tmp != 2) {
  812. dev_dbg(&client->dev, "read error %d\n", tmp);
  813. err = -EIO;
  814. goto exit;
  815. }
  816. /* oscillator off? turn it on, so clock can tick. */
  817. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  818. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  819. /*
  820. * Using IRQ? Disable the square wave and both alarms.
  821. * For some variants, be sure alarms can trigger when we're
  822. * running on Vbackup (BBSQI/BBSQW)
  823. */
  824. if (ds1307->client->irq > 0 && chip->alarm) {
  825. INIT_WORK(&ds1307->work, ds1307_work);
  826. ds1307->regs[0] |= DS1337_BIT_INTCN
  827. | bbsqi_bitpos[ds1307->type];
  828. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  829. want_irq = true;
  830. }
  831. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  832. ds1307->regs[0]);
  833. /* oscillator fault? clear flag, and warn */
  834. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  835. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  836. ds1307->regs[1] & ~DS1337_BIT_OSF);
  837. dev_warn(&client->dev, "SET TIME!\n");
  838. }
  839. break;
  840. case rx_8025:
  841. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  842. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  843. if (tmp != 2) {
  844. dev_dbg(&client->dev, "read error %d\n", tmp);
  845. err = -EIO;
  846. goto exit;
  847. }
  848. /* oscillator off? turn it on, so clock can tick. */
  849. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  850. ds1307->regs[1] |= RX8025_BIT_XST;
  851. i2c_smbus_write_byte_data(client,
  852. RX8025_REG_CTRL2 << 4 | 0x08,
  853. ds1307->regs[1]);
  854. dev_warn(&client->dev,
  855. "oscillator stop detected - SET TIME!\n");
  856. }
  857. if (ds1307->regs[1] & RX8025_BIT_PON) {
  858. ds1307->regs[1] &= ~RX8025_BIT_PON;
  859. i2c_smbus_write_byte_data(client,
  860. RX8025_REG_CTRL2 << 4 | 0x08,
  861. ds1307->regs[1]);
  862. dev_warn(&client->dev, "power-on detected\n");
  863. }
  864. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  865. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  866. i2c_smbus_write_byte_data(client,
  867. RX8025_REG_CTRL2 << 4 | 0x08,
  868. ds1307->regs[1]);
  869. dev_warn(&client->dev, "voltage drop detected\n");
  870. }
  871. /* make sure we are running in 24hour mode */
  872. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  873. u8 hour;
  874. /* switch to 24 hour mode */
  875. i2c_smbus_write_byte_data(client,
  876. RX8025_REG_CTRL1 << 4 | 0x08,
  877. ds1307->regs[0] |
  878. RX8025_BIT_2412);
  879. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  880. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  881. if (tmp != 2) {
  882. dev_dbg(&client->dev, "read error %d\n", tmp);
  883. err = -EIO;
  884. goto exit;
  885. }
  886. /* correct hour */
  887. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  888. if (hour == 12)
  889. hour = 0;
  890. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  891. hour += 12;
  892. i2c_smbus_write_byte_data(client,
  893. DS1307_REG_HOUR << 4 | 0x08,
  894. hour);
  895. }
  896. break;
  897. case ds_1388:
  898. ds1307->offset = 1; /* Seconds starts at 1 */
  899. break;
  900. case mcp794xx:
  901. rtc_ops = &mcp794xx_rtc_ops;
  902. if (ds1307->client->irq > 0 && chip->alarm) {
  903. INIT_WORK(&ds1307->work, mcp794xx_work);
  904. want_irq = true;
  905. }
  906. break;
  907. default:
  908. break;
  909. }
  910. read_rtc:
  911. /* read RTC registers */
  912. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  913. if (tmp != 8) {
  914. dev_dbg(&client->dev, "read error %d\n", tmp);
  915. err = -EIO;
  916. goto exit;
  917. }
  918. /*
  919. * minimal sanity checking; some chips (like DS1340) don't
  920. * specify the extra bits as must-be-zero, but there are
  921. * still a few values that are clearly out-of-range.
  922. */
  923. tmp = ds1307->regs[DS1307_REG_SECS];
  924. switch (ds1307->type) {
  925. case ds_1307:
  926. case m41t00:
  927. /* clock halted? turn it on, so clock can tick. */
  928. if (tmp & DS1307_BIT_CH) {
  929. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  930. dev_warn(&client->dev, "SET TIME!\n");
  931. goto read_rtc;
  932. }
  933. break;
  934. case ds_1338:
  935. /* clock halted? turn it on, so clock can tick. */
  936. if (tmp & DS1307_BIT_CH)
  937. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  938. /* oscillator fault? clear flag, and warn */
  939. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  940. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  941. ds1307->regs[DS1307_REG_CONTROL]
  942. & ~DS1338_BIT_OSF);
  943. dev_warn(&client->dev, "SET TIME!\n");
  944. goto read_rtc;
  945. }
  946. break;
  947. case ds_1340:
  948. /* clock halted? turn it on, so clock can tick. */
  949. if (tmp & DS1340_BIT_nEOSC)
  950. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  951. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  952. if (tmp < 0) {
  953. dev_dbg(&client->dev, "read error %d\n", tmp);
  954. err = -EIO;
  955. goto exit;
  956. }
  957. /* oscillator fault? clear flag, and warn */
  958. if (tmp & DS1340_BIT_OSF) {
  959. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  960. dev_warn(&client->dev, "SET TIME!\n");
  961. }
  962. break;
  963. case mcp794xx:
  964. /* make sure that the backup battery is enabled */
  965. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
  966. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  967. ds1307->regs[DS1307_REG_WDAY]
  968. | MCP794XX_BIT_VBATEN);
  969. }
  970. /* clock halted? turn it on, so clock can tick. */
  971. if (!(tmp & MCP794XX_BIT_ST)) {
  972. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  973. MCP794XX_BIT_ST);
  974. dev_warn(&client->dev, "SET TIME!\n");
  975. goto read_rtc;
  976. }
  977. break;
  978. default:
  979. break;
  980. }
  981. tmp = ds1307->regs[DS1307_REG_HOUR];
  982. switch (ds1307->type) {
  983. case ds_1340:
  984. case m41t00:
  985. /*
  986. * NOTE: ignores century bits; fix before deploying
  987. * systems that will run through year 2100.
  988. */
  989. break;
  990. case rx_8025:
  991. break;
  992. default:
  993. if (!(tmp & DS1307_BIT_12HR))
  994. break;
  995. /*
  996. * Be sure we're in 24 hour mode. Multi-master systems
  997. * take note...
  998. */
  999. tmp = bcd2bin(tmp & 0x1f);
  1000. if (tmp == 12)
  1001. tmp = 0;
  1002. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  1003. tmp += 12;
  1004. i2c_smbus_write_byte_data(client,
  1005. ds1307->offset + DS1307_REG_HOUR,
  1006. bin2bcd(tmp));
  1007. }
  1008. device_set_wakeup_capable(&client->dev, want_irq);
  1009. ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
  1010. rtc_ops, THIS_MODULE);
  1011. if (IS_ERR(ds1307->rtc)) {
  1012. return PTR_ERR(ds1307->rtc);
  1013. }
  1014. if (want_irq) {
  1015. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  1016. ds1307->rtc->name, client);
  1017. if (err) {
  1018. client->irq = 0;
  1019. dev_err(&client->dev, "unable to request IRQ!\n");
  1020. } else {
  1021. set_bit(HAS_ALARM, &ds1307->flags);
  1022. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  1023. }
  1024. }
  1025. if (chip->nvram_size) {
  1026. ds1307->nvram = devm_kzalloc(&client->dev,
  1027. sizeof(struct bin_attribute),
  1028. GFP_KERNEL);
  1029. if (!ds1307->nvram) {
  1030. dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
  1031. } else {
  1032. ds1307->nvram->attr.name = "nvram";
  1033. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  1034. sysfs_bin_attr_init(ds1307->nvram);
  1035. ds1307->nvram->read = ds1307_nvram_read;
  1036. ds1307->nvram->write = ds1307_nvram_write;
  1037. ds1307->nvram->size = chip->nvram_size;
  1038. ds1307->nvram_offset = chip->nvram_offset;
  1039. err = sysfs_create_bin_file(&client->dev.kobj,
  1040. ds1307->nvram);
  1041. if (err) {
  1042. dev_err(&client->dev,
  1043. "unable to create sysfs file: %s\n",
  1044. ds1307->nvram->attr.name);
  1045. } else {
  1046. set_bit(HAS_NVRAM, &ds1307->flags);
  1047. dev_info(&client->dev, "%zu bytes nvram\n",
  1048. ds1307->nvram->size);
  1049. }
  1050. }
  1051. }
  1052. return 0;
  1053. exit:
  1054. return err;
  1055. }
  1056. static int ds1307_remove(struct i2c_client *client)
  1057. {
  1058. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  1059. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  1060. free_irq(client->irq, client);
  1061. cancel_work_sync(&ds1307->work);
  1062. }
  1063. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
  1064. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  1065. return 0;
  1066. }
  1067. static struct i2c_driver ds1307_driver = {
  1068. .driver = {
  1069. .name = "rtc-ds1307",
  1070. .owner = THIS_MODULE,
  1071. },
  1072. .probe = ds1307_probe,
  1073. .remove = ds1307_remove,
  1074. .id_table = ds1307_id,
  1075. };
  1076. module_i2c_driver(ds1307_driver);
  1077. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  1078. MODULE_LICENSE("GPL");