dm.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../base.h"
  31. #include "../core.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "phy.h"
  35. #include "dm.h"
  36. #include "fw.h"
  37. static const u32 edca_setting_dl[PEER_MAX] = {
  38. 0xa44f, /* 0 UNKNOWN */
  39. 0x5ea44f, /* 1 REALTEK_90 */
  40. 0x5ea44f, /* 2 REALTEK_92SE */
  41. 0xa630, /* 3 BROAD */
  42. 0xa44f, /* 4 RAL */
  43. 0xa630, /* 5 ATH */
  44. 0xa630, /* 6 CISCO */
  45. 0xa42b, /* 7 MARV */
  46. };
  47. static const u32 edca_setting_dl_gmode[PEER_MAX] = {
  48. 0x4322, /* 0 UNKNOWN */
  49. 0xa44f, /* 1 REALTEK_90 */
  50. 0x5ea44f, /* 2 REALTEK_92SE */
  51. 0xa42b, /* 3 BROAD */
  52. 0x5e4322, /* 4 RAL */
  53. 0x4322, /* 5 ATH */
  54. 0xa430, /* 6 CISCO */
  55. 0x5ea44f, /* 7 MARV */
  56. };
  57. static const u32 edca_setting_ul[PEER_MAX] = {
  58. 0x5e4322, /* 0 UNKNOWN */
  59. 0xa44f, /* 1 REALTEK_90 */
  60. 0x5ea44f, /* 2 REALTEK_92SE */
  61. 0x5ea322, /* 3 BROAD */
  62. 0x5ea422, /* 4 RAL */
  63. 0x5ea322, /* 5 ATH */
  64. 0x3ea44f, /* 6 CISCO */
  65. 0x5ea44f, /* 7 MARV */
  66. };
  67. static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
  68. {
  69. struct rtl_priv *rtlpriv = rtl_priv(hw);
  70. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  71. static u64 last_txok_cnt;
  72. static u64 last_rxok_cnt;
  73. u64 cur_txok_cnt = 0;
  74. u64 cur_rxok_cnt = 0;
  75. u32 edca_be_ul = edca_setting_ul[mac->vendor];
  76. u32 edca_be_dl = edca_setting_dl[mac->vendor];
  77. u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
  78. if (mac->link_state != MAC80211_LINKED) {
  79. rtlpriv->dm.current_turbo_edca = false;
  80. goto dm_checkedcaturbo_exit;
  81. }
  82. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  83. (!rtlpriv->dm.disable_framebursting)) {
  84. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  85. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  86. if (rtlpriv->phy.rf_type == RF_1T2R) {
  87. if (cur_txok_cnt > 4 * cur_rxok_cnt) {
  88. /* Uplink TP is present. */
  89. if (rtlpriv->dm.is_cur_rdlstate ||
  90. !rtlpriv->dm.current_turbo_edca) {
  91. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  92. edca_be_ul);
  93. rtlpriv->dm.is_cur_rdlstate = false;
  94. }
  95. } else {/* Balance TP is present. */
  96. if (!rtlpriv->dm.is_cur_rdlstate ||
  97. !rtlpriv->dm.current_turbo_edca) {
  98. if (mac->mode == WIRELESS_MODE_G ||
  99. mac->mode == WIRELESS_MODE_B)
  100. rtl_write_dword(rtlpriv,
  101. EDCAPARA_BE,
  102. edca_gmode);
  103. else
  104. rtl_write_dword(rtlpriv,
  105. EDCAPARA_BE,
  106. edca_be_dl);
  107. rtlpriv->dm.is_cur_rdlstate = true;
  108. }
  109. }
  110. rtlpriv->dm.current_turbo_edca = true;
  111. } else {
  112. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  113. if (!rtlpriv->dm.is_cur_rdlstate ||
  114. !rtlpriv->dm.current_turbo_edca) {
  115. if (mac->mode == WIRELESS_MODE_G ||
  116. mac->mode == WIRELESS_MODE_B)
  117. rtl_write_dword(rtlpriv,
  118. EDCAPARA_BE,
  119. edca_gmode);
  120. else
  121. rtl_write_dword(rtlpriv,
  122. EDCAPARA_BE,
  123. edca_be_dl);
  124. rtlpriv->dm.is_cur_rdlstate = true;
  125. }
  126. } else {
  127. if (rtlpriv->dm.is_cur_rdlstate ||
  128. !rtlpriv->dm.current_turbo_edca) {
  129. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  130. edca_be_ul);
  131. rtlpriv->dm.is_cur_rdlstate = false;
  132. }
  133. }
  134. rtlpriv->dm.current_turbo_edca = true;
  135. }
  136. } else {
  137. if (rtlpriv->dm.current_turbo_edca) {
  138. u8 tmp = AC0_BE;
  139. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  140. &tmp);
  141. rtlpriv->dm.current_turbo_edca = false;
  142. }
  143. }
  144. dm_checkedcaturbo_exit:
  145. rtlpriv->dm.is_any_nonbepkts = false;
  146. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  147. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  148. }
  149. static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
  150. struct ieee80211_hw *hw)
  151. {
  152. struct rtl_priv *rtlpriv = rtl_priv(hw);
  153. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  154. u8 thermalvalue = 0;
  155. u32 fw_cmd = 0;
  156. rtlpriv->dm.txpower_trackinginit = true;
  157. thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  158. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  159. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermal meter 0x%x\n",
  160. thermalvalue,
  161. rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
  162. if (thermalvalue) {
  163. rtlpriv->dm.thermalvalue = thermalvalue;
  164. if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
  165. rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
  166. } else {
  167. fw_cmd = (FW_TXPWR_TRACK_THERMAL |
  168. (rtlpriv->efuse.thermalmeter[0] << 8) |
  169. (thermalvalue << 16));
  170. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  171. "Write to FW Thermal Val = 0x%x\n", fw_cmd);
  172. rtl_write_dword(rtlpriv, WFM5, fw_cmd);
  173. rtl92s_phy_chk_fwcmd_iodone(hw);
  174. }
  175. }
  176. rtlpriv->dm.txpowercount = 0;
  177. }
  178. static void _rtl92s_dm_check_txpowertracking_thermalmeter(
  179. struct ieee80211_hw *hw)
  180. {
  181. struct rtl_priv *rtlpriv = rtl_priv(hw);
  182. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  183. static u8 tm_trigger;
  184. u8 tx_power_checkcnt = 5;
  185. /* 2T2R TP issue */
  186. if (rtlphy->rf_type == RF_2T2R)
  187. return;
  188. if (!rtlpriv->dm.txpower_tracking)
  189. return;
  190. if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
  191. rtlpriv->dm.txpowercount++;
  192. return;
  193. }
  194. if (!tm_trigger) {
  195. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
  196. RFREG_OFFSET_MASK, 0x60);
  197. tm_trigger = 1;
  198. } else {
  199. _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
  200. tm_trigger = 0;
  201. }
  202. }
  203. static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
  204. {
  205. struct rtl_priv *rtlpriv = rtl_priv(hw);
  206. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  207. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  208. struct rate_adaptive *ra = &(rtlpriv->ra);
  209. struct ieee80211_sta *sta = NULL;
  210. u32 low_rssi_thresh = 0;
  211. u32 middle_rssi_thresh = 0;
  212. u32 high_rssi_thresh = 0;
  213. if (is_hal_stop(rtlhal))
  214. return;
  215. if (!rtlpriv->dm.useramask)
  216. return;
  217. if (hal_get_firmwareversion(rtlpriv) >= 61 &&
  218. !rtlpriv->dm.inform_fw_driverctrldm) {
  219. rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
  220. rtlpriv->dm.inform_fw_driverctrldm = true;
  221. }
  222. if ((mac->link_state == MAC80211_LINKED) &&
  223. (mac->opmode == NL80211_IFTYPE_STATION)) {
  224. switch (ra->pre_ratr_state) {
  225. case DM_RATR_STA_HIGH:
  226. high_rssi_thresh = 40;
  227. middle_rssi_thresh = 30;
  228. low_rssi_thresh = 20;
  229. break;
  230. case DM_RATR_STA_MIDDLE:
  231. high_rssi_thresh = 44;
  232. middle_rssi_thresh = 30;
  233. low_rssi_thresh = 20;
  234. break;
  235. case DM_RATR_STA_LOW:
  236. high_rssi_thresh = 44;
  237. middle_rssi_thresh = 34;
  238. low_rssi_thresh = 20;
  239. break;
  240. case DM_RATR_STA_ULTRALOW:
  241. high_rssi_thresh = 44;
  242. middle_rssi_thresh = 34;
  243. low_rssi_thresh = 24;
  244. break;
  245. default:
  246. high_rssi_thresh = 44;
  247. middle_rssi_thresh = 34;
  248. low_rssi_thresh = 24;
  249. break;
  250. }
  251. if (rtlpriv->dm.undec_sm_pwdb > (long)high_rssi_thresh) {
  252. ra->ratr_state = DM_RATR_STA_HIGH;
  253. } else if (rtlpriv->dm.undec_sm_pwdb >
  254. (long)middle_rssi_thresh) {
  255. ra->ratr_state = DM_RATR_STA_LOW;
  256. } else if (rtlpriv->dm.undec_sm_pwdb >
  257. (long)low_rssi_thresh) {
  258. ra->ratr_state = DM_RATR_STA_LOW;
  259. } else {
  260. ra->ratr_state = DM_RATR_STA_ULTRALOW;
  261. }
  262. if (ra->pre_ratr_state != ra->ratr_state) {
  263. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  264. "RSSI = %ld RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
  265. rtlpriv->dm.undec_sm_pwdb, ra->ratr_state,
  266. ra->pre_ratr_state, ra->ratr_state);
  267. rcu_read_lock();
  268. sta = rtl_find_sta(hw, mac->bssid);
  269. if (sta)
  270. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  271. ra->ratr_state);
  272. rcu_read_unlock();
  273. ra->pre_ratr_state = ra->ratr_state;
  274. }
  275. }
  276. }
  277. static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
  278. {
  279. struct rtl_priv *rtlpriv = rtl_priv(hw);
  280. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  281. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  282. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  283. bool current_mrc;
  284. bool enable_mrc = true;
  285. long tmpentry_maxpwdb = 0;
  286. u8 rssi_a = 0;
  287. u8 rssi_b = 0;
  288. if (is_hal_stop(rtlhal))
  289. return;
  290. if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
  291. return;
  292. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(&current_mrc));
  293. if (mac->link_state >= MAC80211_LINKED) {
  294. if (rtlpriv->dm.undec_sm_pwdb > tmpentry_maxpwdb) {
  295. rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
  296. rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
  297. }
  298. }
  299. /* MRC settings would NOT affect TP on Wireless B mode. */
  300. if (mac->mode != WIRELESS_MODE_B) {
  301. if ((rssi_a == 0) && (rssi_b == 0)) {
  302. enable_mrc = true;
  303. } else if (rssi_b > 30) {
  304. /* Turn on B-Path */
  305. enable_mrc = true;
  306. } else if (rssi_b < 5) {
  307. /* Turn off B-path */
  308. enable_mrc = false;
  309. /* Take care of RSSI differentiation. */
  310. } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
  311. if ((rssi_a - rssi_b) > 15)
  312. /* Turn off B-path */
  313. enable_mrc = false;
  314. else if ((rssi_a - rssi_b) < 10)
  315. /* Turn on B-Path */
  316. enable_mrc = true;
  317. else
  318. enable_mrc = current_mrc;
  319. } else {
  320. /* Turn on B-Path */
  321. enable_mrc = true;
  322. }
  323. }
  324. /* Update MRC settings if needed. */
  325. if (enable_mrc != current_mrc)
  326. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
  327. (u8 *)&enable_mrc);
  328. }
  329. void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
  330. {
  331. struct rtl_priv *rtlpriv = rtl_priv(hw);
  332. rtlpriv->dm.current_turbo_edca = false;
  333. rtlpriv->dm.is_any_nonbepkts = false;
  334. rtlpriv->dm.is_cur_rdlstate = false;
  335. }
  336. static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  337. {
  338. struct rtl_priv *rtlpriv = rtl_priv(hw);
  339. struct rate_adaptive *ra = &(rtlpriv->ra);
  340. ra->ratr_state = DM_RATR_STA_MAX;
  341. ra->pre_ratr_state = DM_RATR_STA_MAX;
  342. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER &&
  343. hal_get_firmwareversion(rtlpriv) >= 60)
  344. rtlpriv->dm.useramask = true;
  345. else
  346. rtlpriv->dm.useramask = false;
  347. rtlpriv->dm.useramask = false;
  348. rtlpriv->dm.inform_fw_driverctrldm = false;
  349. }
  350. static void _rtl92s_dm_init_txpowertracking_thermalmeter(
  351. struct ieee80211_hw *hw)
  352. {
  353. struct rtl_priv *rtlpriv = rtl_priv(hw);
  354. rtlpriv->dm.txpower_tracking = true;
  355. rtlpriv->dm.txpowercount = 0;
  356. rtlpriv->dm.txpower_trackinginit = false;
  357. }
  358. static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  359. {
  360. struct rtl_priv *rtlpriv = rtl_priv(hw);
  361. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  362. u32 ret_value;
  363. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  364. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  365. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  366. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  367. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  368. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  369. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  370. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  371. falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
  372. falsealm_cnt->cnt_mcs_fail;
  373. /* read CCK false alarm */
  374. ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
  375. falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
  376. falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
  377. falsealm_cnt->cnt_cck_fail;
  378. }
  379. static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
  380. {
  381. struct rtl_priv *rtlpriv = rtl_priv(hw);
  382. struct dig_t *digtable = &rtlpriv->dm_digtable;
  383. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  384. if (falsealm_cnt->cnt_all > digtable->fa_highthresh) {
  385. if ((digtable->back_val - 6) <
  386. digtable->backoffval_range_min)
  387. digtable->back_val = digtable->backoffval_range_min;
  388. else
  389. digtable->back_val -= 6;
  390. } else if (falsealm_cnt->cnt_all < digtable->fa_lowthresh) {
  391. if ((digtable->back_val + 6) >
  392. digtable->backoffval_range_max)
  393. digtable->back_val =
  394. digtable->backoffval_range_max;
  395. else
  396. digtable->back_val += 6;
  397. }
  398. }
  399. static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
  400. {
  401. struct rtl_priv *rtlpriv = rtl_priv(hw);
  402. struct dig_t *digtable = &rtlpriv->dm_digtable;
  403. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  404. static u8 initialized, force_write;
  405. u8 initial_gain = 0;
  406. if ((digtable->pre_sta_cstate == digtable->cur_sta_cstate) ||
  407. (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT)) {
  408. if (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) {
  409. if (rtlpriv->psc.rfpwr_state != ERFON)
  410. return;
  411. if (digtable->backoff_enable_flag)
  412. rtl92s_backoff_enable_flag(hw);
  413. else
  414. digtable->back_val = DM_DIG_BACKOFF_MAX;
  415. if ((digtable->rssi_val + 10 - digtable->back_val) >
  416. digtable->rx_gain_max)
  417. digtable->cur_igvalue =
  418. digtable->rx_gain_max;
  419. else if ((digtable->rssi_val + 10 - digtable->back_val)
  420. < digtable->rx_gain_min)
  421. digtable->cur_igvalue =
  422. digtable->rx_gain_min;
  423. else
  424. digtable->cur_igvalue = digtable->rssi_val + 10
  425. - digtable->back_val;
  426. if (falsealm_cnt->cnt_all > 10000)
  427. digtable->cur_igvalue =
  428. (digtable->cur_igvalue > 0x33) ?
  429. digtable->cur_igvalue : 0x33;
  430. if (falsealm_cnt->cnt_all > 16000)
  431. digtable->cur_igvalue =
  432. digtable->rx_gain_max;
  433. /* connected -> connected or disconnected -> disconnected */
  434. } else {
  435. /* Firmware control DIG, do nothing in driver dm */
  436. return;
  437. }
  438. /* disconnected -> connected or connected ->
  439. * disconnected or beforeconnect->(dis)connected */
  440. } else {
  441. /* Enable FW DIG */
  442. digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  443. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
  444. digtable->back_val = DM_DIG_BACKOFF_MAX;
  445. digtable->cur_igvalue = rtlpriv->phy.default_initialgain[0];
  446. digtable->pre_igvalue = 0;
  447. return;
  448. }
  449. /* Forced writing to prevent from fw-dig overwriting. */
  450. if (digtable->pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
  451. MASKBYTE0))
  452. force_write = 1;
  453. if ((digtable->pre_igvalue != digtable->cur_igvalue) ||
  454. !initialized || force_write) {
  455. /* Disable FW DIG */
  456. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
  457. initial_gain = (u8)digtable->cur_igvalue;
  458. /* Set initial gain. */
  459. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
  460. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
  461. digtable->pre_igvalue = digtable->cur_igvalue;
  462. initialized = 1;
  463. force_write = 0;
  464. }
  465. }
  466. static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
  467. {
  468. struct rtl_priv *rtlpriv = rtl_priv(hw);
  469. struct dig_t *dig = &rtlpriv->dm_digtable;
  470. if (rtlpriv->mac80211.act_scanning)
  471. return;
  472. /* Decide the current status and if modify initial gain or not */
  473. if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
  474. rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
  475. dig->cur_sta_cstate = DIG_STA_CONNECT;
  476. else
  477. dig->cur_sta_cstate = DIG_STA_DISCONNECT;
  478. dig->rssi_val = rtlpriv->dm.undec_sm_pwdb;
  479. /* Change dig mode to rssi */
  480. if (dig->cur_sta_cstate != DIG_STA_DISCONNECT) {
  481. if (dig->dig_twoport_algorithm ==
  482. DIG_TWO_PORT_ALGO_FALSE_ALARM) {
  483. dig->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  484. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
  485. }
  486. }
  487. _rtl92s_dm_false_alarm_counter_statistics(hw);
  488. _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
  489. dig->pre_sta_cstate = dig->cur_sta_cstate;
  490. }
  491. static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
  492. {
  493. struct rtl_priv *rtlpriv = rtl_priv(hw);
  494. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  495. struct dig_t *digtable = &rtlpriv->dm_digtable;
  496. /* 2T2R TP issue */
  497. if (rtlphy->rf_type == RF_2T2R)
  498. return;
  499. if (!rtlpriv->dm.dm_initialgain_enable)
  500. return;
  501. if (digtable->dig_enable_flag == false)
  502. return;
  503. _rtl92s_dm_ctrl_initgain_bytwoport(hw);
  504. }
  505. static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
  506. {
  507. struct rtl_priv *rtlpriv = rtl_priv(hw);
  508. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  509. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  510. long undec_sm_pwdb;
  511. long txpwr_threshold_lv1, txpwr_threshold_lv2;
  512. /* 2T2R TP issue */
  513. if (rtlphy->rf_type == RF_2T2R)
  514. return;
  515. if (!rtlpriv->dm.dynamic_txpower_enable ||
  516. rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  517. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  518. return;
  519. }
  520. if ((mac->link_state < MAC80211_LINKED) &&
  521. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  522. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  523. "Not connected to any\n");
  524. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  525. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  526. return;
  527. }
  528. if (mac->link_state >= MAC80211_LINKED) {
  529. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  530. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  531. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  532. "AP Client PWDB = 0x%lx\n",
  533. undec_sm_pwdb);
  534. } else {
  535. undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
  536. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  537. "STA Default Port PWDB = 0x%lx\n",
  538. undec_sm_pwdb);
  539. }
  540. } else {
  541. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  542. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  543. "AP Ext Port PWDB = 0x%lx\n",
  544. undec_sm_pwdb);
  545. }
  546. txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
  547. txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
  548. if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
  549. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  550. else if (undec_sm_pwdb >= txpwr_threshold_lv2)
  551. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
  552. else if ((undec_sm_pwdb < (txpwr_threshold_lv2 - 3)) &&
  553. (undec_sm_pwdb >= txpwr_threshold_lv1))
  554. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
  555. else if (undec_sm_pwdb < (txpwr_threshold_lv1 - 3))
  556. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  557. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
  558. rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
  559. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  560. }
  561. static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
  562. {
  563. struct rtl_priv *rtlpriv = rtl_priv(hw);
  564. struct dig_t *digtable = &rtlpriv->dm_digtable;
  565. /* Disable DIG scheme now.*/
  566. digtable->dig_enable_flag = true;
  567. digtable->backoff_enable_flag = true;
  568. if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
  569. (hal_get_firmwareversion(rtlpriv) >= 0x3c))
  570. digtable->dig_algorithm = DIG_ALGO_BY_TOW_PORT;
  571. else
  572. digtable->dig_algorithm =
  573. DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
  574. digtable->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  575. digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  576. /* off=by real rssi value, on=by digtable->rssi_val for new dig */
  577. digtable->dig_dbgmode = DM_DBG_OFF;
  578. digtable->dig_slgorithm_switch = 0;
  579. /* 2007/10/04 MH Define init gain threshol. */
  580. digtable->dig_state = DM_STA_DIG_MAX;
  581. digtable->dig_highpwrstate = DM_STA_DIG_MAX;
  582. digtable->cur_sta_cstate = DIG_STA_DISCONNECT;
  583. digtable->pre_sta_cstate = DIG_STA_DISCONNECT;
  584. digtable->cur_ap_cstate = DIG_AP_DISCONNECT;
  585. digtable->pre_ap_cstate = DIG_AP_DISCONNECT;
  586. digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
  587. digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
  588. digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  589. digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  590. digtable->rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
  591. digtable->rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
  592. /* for dig debug rssi value */
  593. digtable->rssi_val = 50;
  594. digtable->back_val = DM_DIG_BACKOFF_MAX;
  595. digtable->rx_gain_max = DM_DIG_MAX;
  596. digtable->rx_gain_min = DM_DIG_MIN;
  597. digtable->backoffval_range_max = DM_DIG_BACKOFF_MAX;
  598. digtable->backoffval_range_min = DM_DIG_BACKOFF_MIN;
  599. }
  600. static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  601. {
  602. struct rtl_priv *rtlpriv = rtl_priv(hw);
  603. if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
  604. (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
  605. rtlpriv->dm.dynamic_txpower_enable = true;
  606. else
  607. rtlpriv->dm.dynamic_txpower_enable = false;
  608. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  609. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  610. }
  611. void rtl92s_dm_init(struct ieee80211_hw *hw)
  612. {
  613. struct rtl_priv *rtlpriv = rtl_priv(hw);
  614. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  615. rtlpriv->dm.undec_sm_pwdb = -1;
  616. _rtl92s_dm_init_dynamic_txpower(hw);
  617. rtl92s_dm_init_edca_turbo(hw);
  618. _rtl92s_dm_init_rate_adaptive_mask(hw);
  619. _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
  620. _rtl92s_dm_init_dig(hw);
  621. rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
  622. }
  623. void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
  624. {
  625. _rtl92s_dm_check_edca_turbo(hw);
  626. _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
  627. _rtl92s_dm_ctrl_initgain_byrssi(hw);
  628. _rtl92s_dm_dynamic_txpower(hw);
  629. _rtl92s_dm_refresh_rateadaptive_mask(hw);
  630. _rtl92s_dm_switch_baseband_mrc(hw);
  631. }