ce.h 14 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef _CE_H_
  18. #define _CE_H_
  19. #include "hif.h"
  20. /* Maximum number of Copy Engine's supported */
  21. #define CE_COUNT_MAX 8
  22. #define CE_HTT_H2T_MSG_SRC_NENTRIES 4096
  23. /* Descriptor rings must be aligned to this boundary */
  24. #define CE_DESC_RING_ALIGN 8
  25. #define CE_SEND_FLAG_GATHER 0x00010000
  26. /*
  27. * Copy Engine support: low-level Target-side Copy Engine API.
  28. * This is a hardware access layer used by code that understands
  29. * how to use copy engines.
  30. */
  31. struct ath10k_ce_pipe;
  32. #define CE_DESC_FLAGS_GATHER (1 << 0)
  33. #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
  34. #define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC
  35. #define CE_DESC_FLAGS_META_DATA_LSB 2
  36. struct ce_desc {
  37. __le32 addr;
  38. __le16 nbytes;
  39. __le16 flags; /* %CE_DESC_FLAGS_ */
  40. };
  41. struct ath10k_ce_ring {
  42. /* Number of entries in this ring; must be power of 2 */
  43. unsigned int nentries;
  44. unsigned int nentries_mask;
  45. /*
  46. * For dest ring, this is the next index to be processed
  47. * by software after it was/is received into.
  48. *
  49. * For src ring, this is the last descriptor that was sent
  50. * and completion processed by software.
  51. *
  52. * Regardless of src or dest ring, this is an invariant
  53. * (modulo ring size):
  54. * write index >= read index >= sw_index
  55. */
  56. unsigned int sw_index;
  57. /* cached copy */
  58. unsigned int write_index;
  59. /*
  60. * For src ring, this is the next index not yet processed by HW.
  61. * This is a cached copy of the real HW index (read index), used
  62. * for avoiding reading the HW index register more often than
  63. * necessary.
  64. * This extends the invariant:
  65. * write index >= read index >= hw_index >= sw_index
  66. *
  67. * For dest ring, this is currently unused.
  68. */
  69. /* cached copy */
  70. unsigned int hw_index;
  71. /* Start of DMA-coherent area reserved for descriptors */
  72. /* Host address space */
  73. void *base_addr_owner_space_unaligned;
  74. /* CE address space */
  75. u32 base_addr_ce_space_unaligned;
  76. /*
  77. * Actual start of descriptors.
  78. * Aligned to descriptor-size boundary.
  79. * Points into reserved DMA-coherent area, above.
  80. */
  81. /* Host address space */
  82. void *base_addr_owner_space;
  83. /* CE address space */
  84. u32 base_addr_ce_space;
  85. /*
  86. * Start of shadow copy of descriptors, within regular memory.
  87. * Aligned to descriptor-size boundary.
  88. */
  89. void *shadow_base_unaligned;
  90. struct ce_desc *shadow_base;
  91. /* keep last */
  92. void *per_transfer_context[0];
  93. };
  94. struct ath10k_ce_pipe {
  95. struct ath10k *ar;
  96. unsigned int id;
  97. unsigned int attr_flags;
  98. u32 ctrl_addr;
  99. void (*send_cb)(struct ath10k_ce_pipe *);
  100. void (*recv_cb)(struct ath10k_ce_pipe *);
  101. unsigned int src_sz_max;
  102. struct ath10k_ce_ring *src_ring;
  103. struct ath10k_ce_ring *dest_ring;
  104. };
  105. /* Copy Engine settable attributes */
  106. struct ce_attr;
  107. /*==================Send====================*/
  108. /* ath10k_ce_send flags */
  109. #define CE_SEND_FLAG_BYTE_SWAP 1
  110. /*
  111. * Queue a source buffer to be sent to an anonymous destination buffer.
  112. * ce - which copy engine to use
  113. * buffer - address of buffer
  114. * nbytes - number of bytes to send
  115. * transfer_id - arbitrary ID; reflected to destination
  116. * flags - CE_SEND_FLAG_* values
  117. * Returns 0 on success; otherwise an error status.
  118. *
  119. * Note: If no flags are specified, use CE's default data swap mode.
  120. *
  121. * Implementation note: pushes 1 buffer to Source ring
  122. */
  123. int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
  124. void *per_transfer_send_context,
  125. u32 buffer,
  126. unsigned int nbytes,
  127. /* 14 bits */
  128. unsigned int transfer_id,
  129. unsigned int flags);
  130. int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
  131. void *per_transfer_context,
  132. u32 buffer,
  133. unsigned int nbytes,
  134. unsigned int transfer_id,
  135. unsigned int flags);
  136. void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
  137. int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
  138. /*==================Recv=======================*/
  139. int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
  140. int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
  141. int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
  142. /* recv flags */
  143. /* Data is byte-swapped */
  144. #define CE_RECV_FLAG_SWAPPED 1
  145. /*
  146. * Supply data for the next completed unprocessed receive descriptor.
  147. * Pops buffer from Dest ring.
  148. */
  149. int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
  150. void **per_transfer_contextp,
  151. u32 *bufferp,
  152. unsigned int *nbytesp,
  153. unsigned int *transfer_idp,
  154. unsigned int *flagsp);
  155. /*
  156. * Supply data for the next completed unprocessed send descriptor.
  157. * Pops 1 completed send buffer from Source ring.
  158. */
  159. int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
  160. void **per_transfer_contextp,
  161. u32 *bufferp,
  162. unsigned int *nbytesp,
  163. unsigned int *transfer_idp);
  164. int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
  165. void **per_transfer_contextp,
  166. u32 *bufferp,
  167. unsigned int *nbytesp,
  168. unsigned int *transfer_idp);
  169. /*==================CE Engine Initialization=======================*/
  170. int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
  171. const struct ce_attr *attr);
  172. void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
  173. int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
  174. const struct ce_attr *attr,
  175. void (*send_cb)(struct ath10k_ce_pipe *),
  176. void (*recv_cb)(struct ath10k_ce_pipe *));
  177. void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
  178. /*==================CE Engine Shutdown=======================*/
  179. /*
  180. * Support clean shutdown by allowing the caller to revoke
  181. * receive buffers. Target DMA must be stopped before using
  182. * this API.
  183. */
  184. int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
  185. void **per_transfer_contextp,
  186. u32 *bufferp);
  187. int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
  188. void **per_transfer_contextp,
  189. u32 *bufferp,
  190. unsigned int *nbytesp,
  191. unsigned int *transfer_idp,
  192. unsigned int *flagsp);
  193. /*
  194. * Support clean shutdown by allowing the caller to cancel
  195. * pending sends. Target DMA must be stopped before using
  196. * this API.
  197. */
  198. int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
  199. void **per_transfer_contextp,
  200. u32 *bufferp,
  201. unsigned int *nbytesp,
  202. unsigned int *transfer_idp);
  203. /*==================CE Interrupt Handlers====================*/
  204. void ath10k_ce_per_engine_service_any(struct ath10k *ar);
  205. void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
  206. int ath10k_ce_disable_interrupts(struct ath10k *ar);
  207. void ath10k_ce_enable_interrupts(struct ath10k *ar);
  208. /* ce_attr.flags values */
  209. /* Use NonSnooping PCIe accesses? */
  210. #define CE_ATTR_NO_SNOOP 1
  211. /* Byte swap data words */
  212. #define CE_ATTR_BYTE_SWAP_DATA 2
  213. /* Swizzle descriptors? */
  214. #define CE_ATTR_SWIZZLE_DESCRIPTORS 4
  215. /* no interrupt on copy completion */
  216. #define CE_ATTR_DIS_INTR 8
  217. /* Attributes of an instance of a Copy Engine */
  218. struct ce_attr {
  219. /* CE_ATTR_* values */
  220. unsigned int flags;
  221. /* #entries in source ring - Must be a power of 2 */
  222. unsigned int src_nentries;
  223. /*
  224. * Max source send size for this CE.
  225. * This is also the minimum size of a destination buffer.
  226. */
  227. unsigned int src_sz_max;
  228. /* #entries in destination ring - Must be a power of 2 */
  229. unsigned int dest_nentries;
  230. };
  231. #define SR_BA_ADDRESS 0x0000
  232. #define SR_SIZE_ADDRESS 0x0004
  233. #define DR_BA_ADDRESS 0x0008
  234. #define DR_SIZE_ADDRESS 0x000c
  235. #define CE_CMD_ADDRESS 0x0018
  236. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
  237. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
  238. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
  239. #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
  240. (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
  241. CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
  242. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
  243. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
  244. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
  245. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
  246. (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
  247. CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
  248. #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
  249. (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
  250. CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
  251. #define CE_CTRL1_DMAX_LENGTH_MSB 15
  252. #define CE_CTRL1_DMAX_LENGTH_LSB 0
  253. #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
  254. #define CE_CTRL1_DMAX_LENGTH_GET(x) \
  255. (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
  256. #define CE_CTRL1_DMAX_LENGTH_SET(x) \
  257. (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
  258. #define CE_CTRL1_ADDRESS 0x0010
  259. #define CE_CTRL1_HW_MASK 0x0007ffff
  260. #define CE_CTRL1_SW_MASK 0x0007ffff
  261. #define CE_CTRL1_HW_WRITE_MASK 0x00000000
  262. #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
  263. #define CE_CTRL1_RSTMASK 0xffffffff
  264. #define CE_CTRL1_RESET 0x00000080
  265. #define CE_CMD_HALT_STATUS_MSB 3
  266. #define CE_CMD_HALT_STATUS_LSB 3
  267. #define CE_CMD_HALT_STATUS_MASK 0x00000008
  268. #define CE_CMD_HALT_STATUS_GET(x) \
  269. (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
  270. #define CE_CMD_HALT_STATUS_SET(x) \
  271. (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
  272. #define CE_CMD_HALT_STATUS_RESET 0
  273. #define CE_CMD_HALT_MSB 0
  274. #define CE_CMD_HALT_MASK 0x00000001
  275. #define HOST_IE_COPY_COMPLETE_MSB 0
  276. #define HOST_IE_COPY_COMPLETE_LSB 0
  277. #define HOST_IE_COPY_COMPLETE_MASK 0x00000001
  278. #define HOST_IE_COPY_COMPLETE_GET(x) \
  279. (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
  280. #define HOST_IE_COPY_COMPLETE_SET(x) \
  281. (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
  282. #define HOST_IE_COPY_COMPLETE_RESET 0
  283. #define HOST_IE_ADDRESS 0x002c
  284. #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
  285. #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
  286. #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
  287. #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
  288. #define HOST_IS_COPY_COMPLETE_MASK 0x00000001
  289. #define HOST_IS_ADDRESS 0x0030
  290. #define MISC_IE_ADDRESS 0x0034
  291. #define MISC_IS_AXI_ERR_MASK 0x00000400
  292. #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
  293. #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
  294. #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
  295. #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
  296. #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
  297. #define MISC_IS_ADDRESS 0x0038
  298. #define SR_WR_INDEX_ADDRESS 0x003c
  299. #define DST_WR_INDEX_ADDRESS 0x0040
  300. #define CURRENT_SRRI_ADDRESS 0x0044
  301. #define CURRENT_DRRI_ADDRESS 0x0048
  302. #define SRC_WATERMARK_LOW_MSB 31
  303. #define SRC_WATERMARK_LOW_LSB 16
  304. #define SRC_WATERMARK_LOW_MASK 0xffff0000
  305. #define SRC_WATERMARK_LOW_GET(x) \
  306. (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
  307. #define SRC_WATERMARK_LOW_SET(x) \
  308. (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
  309. #define SRC_WATERMARK_LOW_RESET 0
  310. #define SRC_WATERMARK_HIGH_MSB 15
  311. #define SRC_WATERMARK_HIGH_LSB 0
  312. #define SRC_WATERMARK_HIGH_MASK 0x0000ffff
  313. #define SRC_WATERMARK_HIGH_GET(x) \
  314. (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
  315. #define SRC_WATERMARK_HIGH_SET(x) \
  316. (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
  317. #define SRC_WATERMARK_HIGH_RESET 0
  318. #define SRC_WATERMARK_ADDRESS 0x004c
  319. #define DST_WATERMARK_LOW_LSB 16
  320. #define DST_WATERMARK_LOW_MASK 0xffff0000
  321. #define DST_WATERMARK_LOW_SET(x) \
  322. (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
  323. #define DST_WATERMARK_LOW_RESET 0
  324. #define DST_WATERMARK_HIGH_MSB 15
  325. #define DST_WATERMARK_HIGH_LSB 0
  326. #define DST_WATERMARK_HIGH_MASK 0x0000ffff
  327. #define DST_WATERMARK_HIGH_GET(x) \
  328. (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
  329. #define DST_WATERMARK_HIGH_SET(x) \
  330. (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
  331. #define DST_WATERMARK_HIGH_RESET 0
  332. #define DST_WATERMARK_ADDRESS 0x0050
  333. static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
  334. {
  335. return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
  336. }
  337. #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
  338. HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
  339. HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
  340. HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
  341. #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
  342. MISC_IS_DST_ADDR_ERR_MASK | \
  343. MISC_IS_SRC_LEN_ERR_MASK | \
  344. MISC_IS_DST_MAX_LEN_VIO_MASK | \
  345. MISC_IS_DST_RING_OVERFLOW_MASK | \
  346. MISC_IS_SRC_RING_OVERFLOW_MASK)
  347. #define CE_SRC_RING_TO_DESC(baddr, idx) \
  348. (&(((struct ce_desc *)baddr)[idx]))
  349. #define CE_DEST_RING_TO_DESC(baddr, idx) \
  350. (&(((struct ce_desc *)baddr)[idx]))
  351. /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
  352. #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
  353. (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
  354. #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
  355. #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
  356. #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
  357. #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
  358. (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
  359. CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
  360. #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
  361. #define CE_INTERRUPT_SUMMARY(ar) \
  362. CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
  363. ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
  364. CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
  365. #endif /* _CE_H_ */