r8152.c 94 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Version Information */
  28. #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
  29. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  30. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  31. #define MODULENAME "r8152"
  32. #define R8152_PHY_ID 32
  33. #define PLA_IDR 0xc000
  34. #define PLA_RCR 0xc010
  35. #define PLA_RMS 0xc016
  36. #define PLA_RXFIFO_CTRL0 0xc0a0
  37. #define PLA_RXFIFO_CTRL1 0xc0a4
  38. #define PLA_RXFIFO_CTRL2 0xc0a8
  39. #define PLA_DMY_REG0 0xc0b0
  40. #define PLA_FMC 0xc0b4
  41. #define PLA_CFG_WOL 0xc0b6
  42. #define PLA_TEREDO_CFG 0xc0bc
  43. #define PLA_MAR 0xcd00
  44. #define PLA_BACKUP 0xd000
  45. #define PAL_BDC_CR 0xd1a0
  46. #define PLA_TEREDO_TIMER 0xd2cc
  47. #define PLA_REALWOW_TIMER 0xd2e8
  48. #define PLA_LEDSEL 0xdd90
  49. #define PLA_LED_FEATURE 0xdd92
  50. #define PLA_PHYAR 0xde00
  51. #define PLA_BOOT_CTRL 0xe004
  52. #define PLA_GPHY_INTR_IMR 0xe022
  53. #define PLA_EEE_CR 0xe040
  54. #define PLA_EEEP_CR 0xe080
  55. #define PLA_MAC_PWR_CTRL 0xe0c0
  56. #define PLA_MAC_PWR_CTRL2 0xe0ca
  57. #define PLA_MAC_PWR_CTRL3 0xe0cc
  58. #define PLA_MAC_PWR_CTRL4 0xe0ce
  59. #define PLA_WDT6_CTRL 0xe428
  60. #define PLA_TCR0 0xe610
  61. #define PLA_TCR1 0xe612
  62. #define PLA_MTPS 0xe615
  63. #define PLA_TXFIFO_CTRL 0xe618
  64. #define PLA_RSTTALLY 0xe800
  65. #define PLA_CR 0xe813
  66. #define PLA_CRWECR 0xe81c
  67. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  68. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  69. #define PLA_CONFIG5 0xe822
  70. #define PLA_PHY_PWR 0xe84c
  71. #define PLA_OOB_CTRL 0xe84f
  72. #define PLA_CPCR 0xe854
  73. #define PLA_MISC_0 0xe858
  74. #define PLA_MISC_1 0xe85a
  75. #define PLA_OCP_GPHY_BASE 0xe86c
  76. #define PLA_TALLYCNT 0xe890
  77. #define PLA_SFF_STS_7 0xe8de
  78. #define PLA_PHYSTATUS 0xe908
  79. #define PLA_BP_BA 0xfc26
  80. #define PLA_BP_0 0xfc28
  81. #define PLA_BP_1 0xfc2a
  82. #define PLA_BP_2 0xfc2c
  83. #define PLA_BP_3 0xfc2e
  84. #define PLA_BP_4 0xfc30
  85. #define PLA_BP_5 0xfc32
  86. #define PLA_BP_6 0xfc34
  87. #define PLA_BP_7 0xfc36
  88. #define PLA_BP_EN 0xfc38
  89. #define USB_USB2PHY 0xb41e
  90. #define USB_SSPHYLINK2 0xb428
  91. #define USB_U2P3_CTRL 0xb460
  92. #define USB_CSR_DUMMY1 0xb464
  93. #define USB_CSR_DUMMY2 0xb466
  94. #define USB_DEV_STAT 0xb808
  95. #define USB_CONNECT_TIMER 0xcbf8
  96. #define USB_BURST_SIZE 0xcfc0
  97. #define USB_USB_CTRL 0xd406
  98. #define USB_PHY_CTRL 0xd408
  99. #define USB_TX_AGG 0xd40a
  100. #define USB_RX_BUF_TH 0xd40c
  101. #define USB_USB_TIMER 0xd428
  102. #define USB_RX_EARLY_TIMEOUT 0xd42c
  103. #define USB_RX_EARLY_SIZE 0xd42e
  104. #define USB_PM_CTRL_STATUS 0xd432
  105. #define USB_TX_DMA 0xd434
  106. #define USB_TOLERANCE 0xd490
  107. #define USB_LPM_CTRL 0xd41a
  108. #define USB_UPS_CTRL 0xd800
  109. #define USB_MISC_0 0xd81a
  110. #define USB_POWER_CUT 0xd80a
  111. #define USB_AFE_CTRL2 0xd824
  112. #define USB_WDT11_CTRL 0xe43c
  113. #define USB_BP_BA 0xfc26
  114. #define USB_BP_0 0xfc28
  115. #define USB_BP_1 0xfc2a
  116. #define USB_BP_2 0xfc2c
  117. #define USB_BP_3 0xfc2e
  118. #define USB_BP_4 0xfc30
  119. #define USB_BP_5 0xfc32
  120. #define USB_BP_6 0xfc34
  121. #define USB_BP_7 0xfc36
  122. #define USB_BP_EN 0xfc38
  123. /* OCP Registers */
  124. #define OCP_ALDPS_CONFIG 0x2010
  125. #define OCP_EEE_CONFIG1 0x2080
  126. #define OCP_EEE_CONFIG2 0x2092
  127. #define OCP_EEE_CONFIG3 0x2094
  128. #define OCP_BASE_MII 0xa400
  129. #define OCP_EEE_AR 0xa41a
  130. #define OCP_EEE_DATA 0xa41c
  131. #define OCP_PHY_STATUS 0xa420
  132. #define OCP_POWER_CFG 0xa430
  133. #define OCP_EEE_CFG 0xa432
  134. #define OCP_SRAM_ADDR 0xa436
  135. #define OCP_SRAM_DATA 0xa438
  136. #define OCP_DOWN_SPEED 0xa442
  137. #define OCP_EEE_ABLE 0xa5c4
  138. #define OCP_EEE_ADV 0xa5d0
  139. #define OCP_EEE_LPABLE 0xa5d2
  140. #define OCP_ADC_CFG 0xbc06
  141. /* SRAM Register */
  142. #define SRAM_LPF_CFG 0x8012
  143. #define SRAM_10M_AMP1 0x8080
  144. #define SRAM_10M_AMP2 0x8082
  145. #define SRAM_IMPEDANCE 0x8084
  146. /* PLA_RCR */
  147. #define RCR_AAP 0x00000001
  148. #define RCR_APM 0x00000002
  149. #define RCR_AM 0x00000004
  150. #define RCR_AB 0x00000008
  151. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  152. /* PLA_RXFIFO_CTRL0 */
  153. #define RXFIFO_THR1_NORMAL 0x00080002
  154. #define RXFIFO_THR1_OOB 0x01800003
  155. /* PLA_RXFIFO_CTRL1 */
  156. #define RXFIFO_THR2_FULL 0x00000060
  157. #define RXFIFO_THR2_HIGH 0x00000038
  158. #define RXFIFO_THR2_OOB 0x0000004a
  159. #define RXFIFO_THR2_NORMAL 0x00a0
  160. /* PLA_RXFIFO_CTRL2 */
  161. #define RXFIFO_THR3_FULL 0x00000078
  162. #define RXFIFO_THR3_HIGH 0x00000048
  163. #define RXFIFO_THR3_OOB 0x0000005a
  164. #define RXFIFO_THR3_NORMAL 0x0110
  165. /* PLA_TXFIFO_CTRL */
  166. #define TXFIFO_THR_NORMAL 0x00400008
  167. #define TXFIFO_THR_NORMAL2 0x01000008
  168. /* PLA_DMY_REG0 */
  169. #define ECM_ALDPS 0x0002
  170. /* PLA_FMC */
  171. #define FMC_FCR_MCU_EN 0x0001
  172. /* PLA_EEEP_CR */
  173. #define EEEP_CR_EEEP_TX 0x0002
  174. /* PLA_WDT6_CTRL */
  175. #define WDT6_SET_MODE 0x0010
  176. /* PLA_TCR0 */
  177. #define TCR0_TX_EMPTY 0x0800
  178. #define TCR0_AUTO_FIFO 0x0080
  179. /* PLA_TCR1 */
  180. #define VERSION_MASK 0x7cf0
  181. /* PLA_MTPS */
  182. #define MTPS_JUMBO (12 * 1024 / 64)
  183. #define MTPS_DEFAULT (6 * 1024 / 64)
  184. /* PLA_RSTTALLY */
  185. #define TALLY_RESET 0x0001
  186. /* PLA_CR */
  187. #define CR_RST 0x10
  188. #define CR_RE 0x08
  189. #define CR_TE 0x04
  190. /* PLA_CRWECR */
  191. #define CRWECR_NORAML 0x00
  192. #define CRWECR_CONFIG 0xc0
  193. /* PLA_OOB_CTRL */
  194. #define NOW_IS_OOB 0x80
  195. #define TXFIFO_EMPTY 0x20
  196. #define RXFIFO_EMPTY 0x10
  197. #define LINK_LIST_READY 0x02
  198. #define DIS_MCU_CLROOB 0x01
  199. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  200. /* PLA_MISC_1 */
  201. #define RXDY_GATED_EN 0x0008
  202. /* PLA_SFF_STS_7 */
  203. #define RE_INIT_LL 0x8000
  204. #define MCU_BORW_EN 0x4000
  205. /* PLA_CPCR */
  206. #define CPCR_RX_VLAN 0x0040
  207. /* PLA_CFG_WOL */
  208. #define MAGIC_EN 0x0001
  209. /* PLA_TEREDO_CFG */
  210. #define TEREDO_SEL 0x8000
  211. #define TEREDO_WAKE_MASK 0x7f00
  212. #define TEREDO_RS_EVENT_MASK 0x00fe
  213. #define OOB_TEREDO_EN 0x0001
  214. /* PAL_BDC_CR */
  215. #define ALDPS_PROXY_MODE 0x0001
  216. /* PLA_CONFIG34 */
  217. #define LINK_ON_WAKE_EN 0x0010
  218. #define LINK_OFF_WAKE_EN 0x0008
  219. /* PLA_CONFIG5 */
  220. #define BWF_EN 0x0040
  221. #define MWF_EN 0x0020
  222. #define UWF_EN 0x0010
  223. #define LAN_WAKE_EN 0x0002
  224. /* PLA_LED_FEATURE */
  225. #define LED_MODE_MASK 0x0700
  226. /* PLA_PHY_PWR */
  227. #define TX_10M_IDLE_EN 0x0080
  228. #define PFM_PWM_SWITCH 0x0040
  229. /* PLA_MAC_PWR_CTRL */
  230. #define D3_CLK_GATED_EN 0x00004000
  231. #define MCU_CLK_RATIO 0x07010f07
  232. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  233. #define ALDPS_SPDWN_RATIO 0x0f87
  234. /* PLA_MAC_PWR_CTRL2 */
  235. #define EEE_SPDWN_RATIO 0x8007
  236. /* PLA_MAC_PWR_CTRL3 */
  237. #define PKT_AVAIL_SPDWN_EN 0x0100
  238. #define SUSPEND_SPDWN_EN 0x0004
  239. #define U1U2_SPDWN_EN 0x0002
  240. #define L1_SPDWN_EN 0x0001
  241. /* PLA_MAC_PWR_CTRL4 */
  242. #define PWRSAVE_SPDWN_EN 0x1000
  243. #define RXDV_SPDWN_EN 0x0800
  244. #define TX10MIDLE_EN 0x0100
  245. #define TP100_SPDWN_EN 0x0020
  246. #define TP500_SPDWN_EN 0x0010
  247. #define TP1000_SPDWN_EN 0x0008
  248. #define EEE_SPDWN_EN 0x0001
  249. /* PLA_GPHY_INTR_IMR */
  250. #define GPHY_STS_MSK 0x0001
  251. #define SPEED_DOWN_MSK 0x0002
  252. #define SPDWN_RXDV_MSK 0x0004
  253. #define SPDWN_LINKCHG_MSK 0x0008
  254. /* PLA_PHYAR */
  255. #define PHYAR_FLAG 0x80000000
  256. /* PLA_EEE_CR */
  257. #define EEE_RX_EN 0x0001
  258. #define EEE_TX_EN 0x0002
  259. /* PLA_BOOT_CTRL */
  260. #define AUTOLOAD_DONE 0x0002
  261. /* USB_USB2PHY */
  262. #define USB2PHY_SUSPEND 0x0001
  263. #define USB2PHY_L1 0x0002
  264. /* USB_SSPHYLINK2 */
  265. #define pwd_dn_scale_mask 0x3ffe
  266. #define pwd_dn_scale(x) ((x) << 1)
  267. /* USB_CSR_DUMMY1 */
  268. #define DYNAMIC_BURST 0x0001
  269. /* USB_CSR_DUMMY2 */
  270. #define EP4_FULL_FC 0x0001
  271. /* USB_DEV_STAT */
  272. #define STAT_SPEED_MASK 0x0006
  273. #define STAT_SPEED_HIGH 0x0000
  274. #define STAT_SPEED_FULL 0x0002
  275. /* USB_TX_AGG */
  276. #define TX_AGG_MAX_THRESHOLD 0x03
  277. /* USB_RX_BUF_TH */
  278. #define RX_THR_SUPPER 0x0c350180
  279. #define RX_THR_HIGH 0x7a120180
  280. #define RX_THR_SLOW 0xffff0180
  281. /* USB_TX_DMA */
  282. #define TEST_MODE_DISABLE 0x00000001
  283. #define TX_SIZE_ADJUST1 0x00000100
  284. /* USB_UPS_CTRL */
  285. #define POWER_CUT 0x0100
  286. /* USB_PM_CTRL_STATUS */
  287. #define RESUME_INDICATE 0x0001
  288. /* USB_USB_CTRL */
  289. #define RX_AGG_DISABLE 0x0010
  290. /* USB_U2P3_CTRL */
  291. #define U2P3_ENABLE 0x0001
  292. /* USB_POWER_CUT */
  293. #define PWR_EN 0x0001
  294. #define PHASE2_EN 0x0008
  295. /* USB_MISC_0 */
  296. #define PCUT_STATUS 0x0001
  297. /* USB_RX_EARLY_TIMEOUT */
  298. #define COALESCE_SUPER 85000U
  299. #define COALESCE_HIGH 250000U
  300. #define COALESCE_SLOW 524280U
  301. /* USB_WDT11_CTRL */
  302. #define TIMER11_EN 0x0001
  303. /* USB_LPM_CTRL */
  304. /* bit 4 ~ 5: fifo empty boundary */
  305. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  306. /* bit 2 ~ 3: LMP timer */
  307. #define LPM_TIMER_MASK 0x0c
  308. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  309. #define LPM_TIMER_500US 0x0c /* 500 us */
  310. #define ROK_EXIT_LPM 0x02
  311. /* USB_AFE_CTRL2 */
  312. #define SEN_VAL_MASK 0xf800
  313. #define SEN_VAL_NORMAL 0xa000
  314. #define SEL_RXIDLE 0x0100
  315. /* OCP_ALDPS_CONFIG */
  316. #define ENPWRSAVE 0x8000
  317. #define ENPDNPS 0x0200
  318. #define LINKENA 0x0100
  319. #define DIS_SDSAVE 0x0010
  320. /* OCP_PHY_STATUS */
  321. #define PHY_STAT_MASK 0x0007
  322. #define PHY_STAT_LAN_ON 3
  323. #define PHY_STAT_PWRDN 5
  324. /* OCP_POWER_CFG */
  325. #define EEE_CLKDIV_EN 0x8000
  326. #define EN_ALDPS 0x0004
  327. #define EN_10M_PLLOFF 0x0001
  328. /* OCP_EEE_CONFIG1 */
  329. #define RG_TXLPI_MSK_HFDUP 0x8000
  330. #define RG_MATCLR_EN 0x4000
  331. #define EEE_10_CAP 0x2000
  332. #define EEE_NWAY_EN 0x1000
  333. #define TX_QUIET_EN 0x0200
  334. #define RX_QUIET_EN 0x0100
  335. #define sd_rise_time_mask 0x0070
  336. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  337. #define RG_RXLPI_MSK_HFDUP 0x0008
  338. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  339. /* OCP_EEE_CONFIG2 */
  340. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  341. #define RG_DACQUIET_EN 0x0400
  342. #define RG_LDVQUIET_EN 0x0200
  343. #define RG_CKRSEL 0x0020
  344. #define RG_EEEPRG_EN 0x0010
  345. /* OCP_EEE_CONFIG3 */
  346. #define fast_snr_mask 0xff80
  347. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  348. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  349. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  350. /* OCP_EEE_AR */
  351. /* bit[15:14] function */
  352. #define FUN_ADDR 0x0000
  353. #define FUN_DATA 0x4000
  354. /* bit[4:0] device addr */
  355. /* OCP_EEE_CFG */
  356. #define CTAP_SHORT_EN 0x0040
  357. #define EEE10_EN 0x0010
  358. /* OCP_DOWN_SPEED */
  359. #define EN_10M_BGOFF 0x0080
  360. /* OCP_ADC_CFG */
  361. #define CKADSEL_L 0x0100
  362. #define ADC_EN 0x0080
  363. #define EN_EMI_L 0x0040
  364. /* SRAM_LPF_CFG */
  365. #define LPF_AUTO_TUNE 0x8000
  366. /* SRAM_10M_AMP1 */
  367. #define GDAC_IB_UPALL 0x0008
  368. /* SRAM_10M_AMP2 */
  369. #define AMP_DN 0x0200
  370. /* SRAM_IMPEDANCE */
  371. #define RX_DRIVING_MASK 0x6000
  372. enum rtl_register_content {
  373. _1000bps = 0x10,
  374. _100bps = 0x08,
  375. _10bps = 0x04,
  376. LINK_STATUS = 0x02,
  377. FULL_DUP = 0x01,
  378. };
  379. #define RTL8152_MAX_TX 4
  380. #define RTL8152_MAX_RX 10
  381. #define INTBUFSIZE 2
  382. #define CRC_SIZE 4
  383. #define TX_ALIGN 4
  384. #define RX_ALIGN 8
  385. #define INTR_LINK 0x0004
  386. #define RTL8152_REQT_READ 0xc0
  387. #define RTL8152_REQT_WRITE 0x40
  388. #define RTL8152_REQ_GET_REGS 0x05
  389. #define RTL8152_REQ_SET_REGS 0x05
  390. #define BYTE_EN_DWORD 0xff
  391. #define BYTE_EN_WORD 0x33
  392. #define BYTE_EN_BYTE 0x11
  393. #define BYTE_EN_SIX_BYTES 0x3f
  394. #define BYTE_EN_START_MASK 0x0f
  395. #define BYTE_EN_END_MASK 0xf0
  396. #define RTL8153_MAX_PACKET 9216 /* 9K */
  397. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  398. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  399. #define RTL8153_RMS RTL8153_MAX_PACKET
  400. #define RTL8152_TX_TIMEOUT (5 * HZ)
  401. #define RTL8152_NAPI_WEIGHT 64
  402. /* rtl8152 flags */
  403. enum rtl8152_flags {
  404. RTL8152_UNPLUG = 0,
  405. RTL8152_SET_RX_MODE,
  406. WORK_ENABLE,
  407. RTL8152_LINK_CHG,
  408. SELECTIVE_SUSPEND,
  409. PHY_RESET,
  410. SCHEDULE_NAPI,
  411. };
  412. /* Define these values to match your device */
  413. #define VENDOR_ID_REALTEK 0x0bda
  414. #define VENDOR_ID_SAMSUNG 0x04e8
  415. #define VENDOR_ID_LENOVO 0x17ef
  416. #define MCU_TYPE_PLA 0x0100
  417. #define MCU_TYPE_USB 0x0000
  418. struct tally_counter {
  419. __le64 tx_packets;
  420. __le64 rx_packets;
  421. __le64 tx_errors;
  422. __le32 rx_errors;
  423. __le16 rx_missed;
  424. __le16 align_errors;
  425. __le32 tx_one_collision;
  426. __le32 tx_multi_collision;
  427. __le64 rx_unicast;
  428. __le64 rx_broadcast;
  429. __le32 rx_multicast;
  430. __le16 tx_aborted;
  431. __le16 tx_underrun;
  432. };
  433. struct rx_desc {
  434. __le32 opts1;
  435. #define RX_LEN_MASK 0x7fff
  436. __le32 opts2;
  437. #define RD_UDP_CS BIT(23)
  438. #define RD_TCP_CS BIT(22)
  439. #define RD_IPV6_CS BIT(20)
  440. #define RD_IPV4_CS BIT(19)
  441. __le32 opts3;
  442. #define IPF BIT(23) /* IP checksum fail */
  443. #define UDPF BIT(22) /* UDP checksum fail */
  444. #define TCPF BIT(21) /* TCP checksum fail */
  445. #define RX_VLAN_TAG BIT(16)
  446. __le32 opts4;
  447. __le32 opts5;
  448. __le32 opts6;
  449. };
  450. struct tx_desc {
  451. __le32 opts1;
  452. #define TX_FS BIT(31) /* First segment of a packet */
  453. #define TX_LS BIT(30) /* Final segment of a packet */
  454. #define GTSENDV4 BIT(28)
  455. #define GTSENDV6 BIT(27)
  456. #define GTTCPHO_SHIFT 18
  457. #define GTTCPHO_MAX 0x7fU
  458. #define TX_LEN_MAX 0x3ffffU
  459. __le32 opts2;
  460. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  461. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  462. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  463. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  464. #define MSS_SHIFT 17
  465. #define MSS_MAX 0x7ffU
  466. #define TCPHO_SHIFT 17
  467. #define TCPHO_MAX 0x7ffU
  468. #define TX_VLAN_TAG BIT(16)
  469. };
  470. struct r8152;
  471. struct rx_agg {
  472. struct list_head list;
  473. struct urb *urb;
  474. struct r8152 *context;
  475. void *buffer;
  476. void *head;
  477. };
  478. struct tx_agg {
  479. struct list_head list;
  480. struct urb *urb;
  481. struct r8152 *context;
  482. void *buffer;
  483. void *head;
  484. u32 skb_num;
  485. u32 skb_len;
  486. };
  487. struct r8152 {
  488. unsigned long flags;
  489. struct usb_device *udev;
  490. struct napi_struct napi;
  491. struct usb_interface *intf;
  492. struct net_device *netdev;
  493. struct urb *intr_urb;
  494. struct tx_agg tx_info[RTL8152_MAX_TX];
  495. struct rx_agg rx_info[RTL8152_MAX_RX];
  496. struct list_head rx_done, tx_free;
  497. struct sk_buff_head tx_queue, rx_queue;
  498. spinlock_t rx_lock, tx_lock;
  499. struct delayed_work schedule;
  500. struct mii_if_info mii;
  501. struct mutex control; /* use for hw setting */
  502. struct rtl_ops {
  503. void (*init)(struct r8152 *);
  504. int (*enable)(struct r8152 *);
  505. void (*disable)(struct r8152 *);
  506. void (*up)(struct r8152 *);
  507. void (*down)(struct r8152 *);
  508. void (*unload)(struct r8152 *);
  509. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  510. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  511. } rtl_ops;
  512. int intr_interval;
  513. u32 saved_wolopts;
  514. u32 msg_enable;
  515. u32 tx_qlen;
  516. u32 coalesce;
  517. u16 ocp_base;
  518. u8 *intr_buff;
  519. u8 version;
  520. };
  521. enum rtl_version {
  522. RTL_VER_UNKNOWN = 0,
  523. RTL_VER_01,
  524. RTL_VER_02,
  525. RTL_VER_03,
  526. RTL_VER_04,
  527. RTL_VER_05,
  528. RTL_VER_MAX
  529. };
  530. enum tx_csum_stat {
  531. TX_CSUM_SUCCESS = 0,
  532. TX_CSUM_TSO,
  533. TX_CSUM_NONE
  534. };
  535. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  536. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  537. */
  538. static const int multicast_filter_limit = 32;
  539. static unsigned int agg_buf_sz = 16384;
  540. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  541. VLAN_ETH_HLEN - VLAN_HLEN)
  542. static
  543. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  544. {
  545. int ret;
  546. void *tmp;
  547. tmp = kmalloc(size, GFP_KERNEL);
  548. if (!tmp)
  549. return -ENOMEM;
  550. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  551. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  552. value, index, tmp, size, 500);
  553. memcpy(data, tmp, size);
  554. kfree(tmp);
  555. return ret;
  556. }
  557. static
  558. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  559. {
  560. int ret;
  561. void *tmp;
  562. tmp = kmemdup(data, size, GFP_KERNEL);
  563. if (!tmp)
  564. return -ENOMEM;
  565. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  566. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  567. value, index, tmp, size, 500);
  568. kfree(tmp);
  569. return ret;
  570. }
  571. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  572. void *data, u16 type)
  573. {
  574. u16 limit = 64;
  575. int ret = 0;
  576. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  577. return -ENODEV;
  578. /* both size and indix must be 4 bytes align */
  579. if ((size & 3) || !size || (index & 3) || !data)
  580. return -EPERM;
  581. if ((u32)index + (u32)size > 0xffff)
  582. return -EPERM;
  583. while (size) {
  584. if (size > limit) {
  585. ret = get_registers(tp, index, type, limit, data);
  586. if (ret < 0)
  587. break;
  588. index += limit;
  589. data += limit;
  590. size -= limit;
  591. } else {
  592. ret = get_registers(tp, index, type, size, data);
  593. if (ret < 0)
  594. break;
  595. index += size;
  596. data += size;
  597. size = 0;
  598. break;
  599. }
  600. }
  601. if (ret == -ENODEV)
  602. set_bit(RTL8152_UNPLUG, &tp->flags);
  603. return ret;
  604. }
  605. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  606. u16 size, void *data, u16 type)
  607. {
  608. int ret;
  609. u16 byteen_start, byteen_end, byen;
  610. u16 limit = 512;
  611. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  612. return -ENODEV;
  613. /* both size and indix must be 4 bytes align */
  614. if ((size & 3) || !size || (index & 3) || !data)
  615. return -EPERM;
  616. if ((u32)index + (u32)size > 0xffff)
  617. return -EPERM;
  618. byteen_start = byteen & BYTE_EN_START_MASK;
  619. byteen_end = byteen & BYTE_EN_END_MASK;
  620. byen = byteen_start | (byteen_start << 4);
  621. ret = set_registers(tp, index, type | byen, 4, data);
  622. if (ret < 0)
  623. goto error1;
  624. index += 4;
  625. data += 4;
  626. size -= 4;
  627. if (size) {
  628. size -= 4;
  629. while (size) {
  630. if (size > limit) {
  631. ret = set_registers(tp, index,
  632. type | BYTE_EN_DWORD,
  633. limit, data);
  634. if (ret < 0)
  635. goto error1;
  636. index += limit;
  637. data += limit;
  638. size -= limit;
  639. } else {
  640. ret = set_registers(tp, index,
  641. type | BYTE_EN_DWORD,
  642. size, data);
  643. if (ret < 0)
  644. goto error1;
  645. index += size;
  646. data += size;
  647. size = 0;
  648. break;
  649. }
  650. }
  651. byen = byteen_end | (byteen_end >> 4);
  652. ret = set_registers(tp, index, type | byen, 4, data);
  653. if (ret < 0)
  654. goto error1;
  655. }
  656. error1:
  657. if (ret == -ENODEV)
  658. set_bit(RTL8152_UNPLUG, &tp->flags);
  659. return ret;
  660. }
  661. static inline
  662. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  663. {
  664. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  665. }
  666. static inline
  667. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  668. {
  669. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  670. }
  671. static inline
  672. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  673. {
  674. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  675. }
  676. static inline
  677. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  678. {
  679. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  680. }
  681. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  682. {
  683. __le32 data;
  684. generic_ocp_read(tp, index, sizeof(data), &data, type);
  685. return __le32_to_cpu(data);
  686. }
  687. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  688. {
  689. __le32 tmp = __cpu_to_le32(data);
  690. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  691. }
  692. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  693. {
  694. u32 data;
  695. __le32 tmp;
  696. u8 shift = index & 2;
  697. index &= ~3;
  698. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  699. data = __le32_to_cpu(tmp);
  700. data >>= (shift * 8);
  701. data &= 0xffff;
  702. return (u16)data;
  703. }
  704. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  705. {
  706. u32 mask = 0xffff;
  707. __le32 tmp;
  708. u16 byen = BYTE_EN_WORD;
  709. u8 shift = index & 2;
  710. data &= mask;
  711. if (index & 2) {
  712. byen <<= shift;
  713. mask <<= (shift * 8);
  714. data <<= (shift * 8);
  715. index &= ~3;
  716. }
  717. tmp = __cpu_to_le32(data);
  718. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  719. }
  720. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  721. {
  722. u32 data;
  723. __le32 tmp;
  724. u8 shift = index & 3;
  725. index &= ~3;
  726. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  727. data = __le32_to_cpu(tmp);
  728. data >>= (shift * 8);
  729. data &= 0xff;
  730. return (u8)data;
  731. }
  732. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  733. {
  734. u32 mask = 0xff;
  735. __le32 tmp;
  736. u16 byen = BYTE_EN_BYTE;
  737. u8 shift = index & 3;
  738. data &= mask;
  739. if (index & 3) {
  740. byen <<= shift;
  741. mask <<= (shift * 8);
  742. data <<= (shift * 8);
  743. index &= ~3;
  744. }
  745. tmp = __cpu_to_le32(data);
  746. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  747. }
  748. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  749. {
  750. u16 ocp_base, ocp_index;
  751. ocp_base = addr & 0xf000;
  752. if (ocp_base != tp->ocp_base) {
  753. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  754. tp->ocp_base = ocp_base;
  755. }
  756. ocp_index = (addr & 0x0fff) | 0xb000;
  757. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  758. }
  759. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  760. {
  761. u16 ocp_base, ocp_index;
  762. ocp_base = addr & 0xf000;
  763. if (ocp_base != tp->ocp_base) {
  764. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  765. tp->ocp_base = ocp_base;
  766. }
  767. ocp_index = (addr & 0x0fff) | 0xb000;
  768. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  769. }
  770. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  771. {
  772. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  773. }
  774. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  775. {
  776. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  777. }
  778. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  779. {
  780. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  781. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  782. }
  783. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  784. {
  785. struct r8152 *tp = netdev_priv(netdev);
  786. int ret;
  787. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  788. return -ENODEV;
  789. if (phy_id != R8152_PHY_ID)
  790. return -EINVAL;
  791. ret = r8152_mdio_read(tp, reg);
  792. return ret;
  793. }
  794. static
  795. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  796. {
  797. struct r8152 *tp = netdev_priv(netdev);
  798. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  799. return;
  800. if (phy_id != R8152_PHY_ID)
  801. return;
  802. r8152_mdio_write(tp, reg, val);
  803. }
  804. static int
  805. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  806. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  807. {
  808. struct r8152 *tp = netdev_priv(netdev);
  809. struct sockaddr *addr = p;
  810. int ret = -EADDRNOTAVAIL;
  811. if (!is_valid_ether_addr(addr->sa_data))
  812. goto out1;
  813. ret = usb_autopm_get_interface(tp->intf);
  814. if (ret < 0)
  815. goto out1;
  816. mutex_lock(&tp->control);
  817. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  818. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  819. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  820. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  821. mutex_unlock(&tp->control);
  822. usb_autopm_put_interface(tp->intf);
  823. out1:
  824. return ret;
  825. }
  826. static int set_ethernet_addr(struct r8152 *tp)
  827. {
  828. struct net_device *dev = tp->netdev;
  829. struct sockaddr sa;
  830. int ret;
  831. if (tp->version == RTL_VER_01)
  832. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  833. else
  834. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  835. if (ret < 0) {
  836. netif_err(tp, probe, dev, "Get ether addr fail\n");
  837. } else if (!is_valid_ether_addr(sa.sa_data)) {
  838. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  839. sa.sa_data);
  840. eth_hw_addr_random(dev);
  841. ether_addr_copy(sa.sa_data, dev->dev_addr);
  842. ret = rtl8152_set_mac_address(dev, &sa);
  843. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  844. sa.sa_data);
  845. } else {
  846. if (tp->version == RTL_VER_01)
  847. ether_addr_copy(dev->dev_addr, sa.sa_data);
  848. else
  849. ret = rtl8152_set_mac_address(dev, &sa);
  850. }
  851. return ret;
  852. }
  853. static void read_bulk_callback(struct urb *urb)
  854. {
  855. struct net_device *netdev;
  856. int status = urb->status;
  857. struct rx_agg *agg;
  858. struct r8152 *tp;
  859. agg = urb->context;
  860. if (!agg)
  861. return;
  862. tp = agg->context;
  863. if (!tp)
  864. return;
  865. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  866. return;
  867. if (!test_bit(WORK_ENABLE, &tp->flags))
  868. return;
  869. netdev = tp->netdev;
  870. /* When link down, the driver would cancel all bulks. */
  871. /* This avoid the re-submitting bulk */
  872. if (!netif_carrier_ok(netdev))
  873. return;
  874. usb_mark_last_busy(tp->udev);
  875. switch (status) {
  876. case 0:
  877. if (urb->actual_length < ETH_ZLEN)
  878. break;
  879. spin_lock(&tp->rx_lock);
  880. list_add_tail(&agg->list, &tp->rx_done);
  881. spin_unlock(&tp->rx_lock);
  882. napi_schedule(&tp->napi);
  883. return;
  884. case -ESHUTDOWN:
  885. set_bit(RTL8152_UNPLUG, &tp->flags);
  886. netif_device_detach(tp->netdev);
  887. return;
  888. case -ENOENT:
  889. return; /* the urb is in unlink state */
  890. case -ETIME:
  891. if (net_ratelimit())
  892. netdev_warn(netdev, "maybe reset is needed?\n");
  893. break;
  894. default:
  895. if (net_ratelimit())
  896. netdev_warn(netdev, "Rx status %d\n", status);
  897. break;
  898. }
  899. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  900. }
  901. static void write_bulk_callback(struct urb *urb)
  902. {
  903. struct net_device_stats *stats;
  904. struct net_device *netdev;
  905. struct tx_agg *agg;
  906. struct r8152 *tp;
  907. int status = urb->status;
  908. agg = urb->context;
  909. if (!agg)
  910. return;
  911. tp = agg->context;
  912. if (!tp)
  913. return;
  914. netdev = tp->netdev;
  915. stats = &netdev->stats;
  916. if (status) {
  917. if (net_ratelimit())
  918. netdev_warn(netdev, "Tx status %d\n", status);
  919. stats->tx_errors += agg->skb_num;
  920. } else {
  921. stats->tx_packets += agg->skb_num;
  922. stats->tx_bytes += agg->skb_len;
  923. }
  924. spin_lock(&tp->tx_lock);
  925. list_add_tail(&agg->list, &tp->tx_free);
  926. spin_unlock(&tp->tx_lock);
  927. usb_autopm_put_interface_async(tp->intf);
  928. if (!netif_carrier_ok(netdev))
  929. return;
  930. if (!test_bit(WORK_ENABLE, &tp->flags))
  931. return;
  932. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  933. return;
  934. if (!skb_queue_empty(&tp->tx_queue))
  935. napi_schedule(&tp->napi);
  936. }
  937. static void intr_callback(struct urb *urb)
  938. {
  939. struct r8152 *tp;
  940. __le16 *d;
  941. int status = urb->status;
  942. int res;
  943. tp = urb->context;
  944. if (!tp)
  945. return;
  946. if (!test_bit(WORK_ENABLE, &tp->flags))
  947. return;
  948. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  949. return;
  950. switch (status) {
  951. case 0: /* success */
  952. break;
  953. case -ECONNRESET: /* unlink */
  954. case -ESHUTDOWN:
  955. netif_device_detach(tp->netdev);
  956. case -ENOENT:
  957. case -EPROTO:
  958. netif_info(tp, intr, tp->netdev,
  959. "Stop submitting intr, status %d\n", status);
  960. return;
  961. case -EOVERFLOW:
  962. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  963. goto resubmit;
  964. /* -EPIPE: should clear the halt */
  965. default:
  966. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  967. goto resubmit;
  968. }
  969. d = urb->transfer_buffer;
  970. if (INTR_LINK & __le16_to_cpu(d[0])) {
  971. if (!netif_carrier_ok(tp->netdev)) {
  972. set_bit(RTL8152_LINK_CHG, &tp->flags);
  973. schedule_delayed_work(&tp->schedule, 0);
  974. }
  975. } else {
  976. if (netif_carrier_ok(tp->netdev)) {
  977. set_bit(RTL8152_LINK_CHG, &tp->flags);
  978. schedule_delayed_work(&tp->schedule, 0);
  979. }
  980. }
  981. resubmit:
  982. res = usb_submit_urb(urb, GFP_ATOMIC);
  983. if (res == -ENODEV) {
  984. set_bit(RTL8152_UNPLUG, &tp->flags);
  985. netif_device_detach(tp->netdev);
  986. } else if (res) {
  987. netif_err(tp, intr, tp->netdev,
  988. "can't resubmit intr, status %d\n", res);
  989. }
  990. }
  991. static inline void *rx_agg_align(void *data)
  992. {
  993. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  994. }
  995. static inline void *tx_agg_align(void *data)
  996. {
  997. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  998. }
  999. static void free_all_mem(struct r8152 *tp)
  1000. {
  1001. int i;
  1002. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1003. usb_free_urb(tp->rx_info[i].urb);
  1004. tp->rx_info[i].urb = NULL;
  1005. kfree(tp->rx_info[i].buffer);
  1006. tp->rx_info[i].buffer = NULL;
  1007. tp->rx_info[i].head = NULL;
  1008. }
  1009. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1010. usb_free_urb(tp->tx_info[i].urb);
  1011. tp->tx_info[i].urb = NULL;
  1012. kfree(tp->tx_info[i].buffer);
  1013. tp->tx_info[i].buffer = NULL;
  1014. tp->tx_info[i].head = NULL;
  1015. }
  1016. usb_free_urb(tp->intr_urb);
  1017. tp->intr_urb = NULL;
  1018. kfree(tp->intr_buff);
  1019. tp->intr_buff = NULL;
  1020. }
  1021. static int alloc_all_mem(struct r8152 *tp)
  1022. {
  1023. struct net_device *netdev = tp->netdev;
  1024. struct usb_interface *intf = tp->intf;
  1025. struct usb_host_interface *alt = intf->cur_altsetting;
  1026. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1027. struct urb *urb;
  1028. int node, i;
  1029. u8 *buf;
  1030. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1031. spin_lock_init(&tp->rx_lock);
  1032. spin_lock_init(&tp->tx_lock);
  1033. INIT_LIST_HEAD(&tp->tx_free);
  1034. skb_queue_head_init(&tp->tx_queue);
  1035. skb_queue_head_init(&tp->rx_queue);
  1036. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1037. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1038. if (!buf)
  1039. goto err1;
  1040. if (buf != rx_agg_align(buf)) {
  1041. kfree(buf);
  1042. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1043. node);
  1044. if (!buf)
  1045. goto err1;
  1046. }
  1047. urb = usb_alloc_urb(0, GFP_KERNEL);
  1048. if (!urb) {
  1049. kfree(buf);
  1050. goto err1;
  1051. }
  1052. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1053. tp->rx_info[i].context = tp;
  1054. tp->rx_info[i].urb = urb;
  1055. tp->rx_info[i].buffer = buf;
  1056. tp->rx_info[i].head = rx_agg_align(buf);
  1057. }
  1058. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1059. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1060. if (!buf)
  1061. goto err1;
  1062. if (buf != tx_agg_align(buf)) {
  1063. kfree(buf);
  1064. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1065. node);
  1066. if (!buf)
  1067. goto err1;
  1068. }
  1069. urb = usb_alloc_urb(0, GFP_KERNEL);
  1070. if (!urb) {
  1071. kfree(buf);
  1072. goto err1;
  1073. }
  1074. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1075. tp->tx_info[i].context = tp;
  1076. tp->tx_info[i].urb = urb;
  1077. tp->tx_info[i].buffer = buf;
  1078. tp->tx_info[i].head = tx_agg_align(buf);
  1079. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1080. }
  1081. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1082. if (!tp->intr_urb)
  1083. goto err1;
  1084. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1085. if (!tp->intr_buff)
  1086. goto err1;
  1087. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1088. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1089. tp->intr_buff, INTBUFSIZE, intr_callback,
  1090. tp, tp->intr_interval);
  1091. return 0;
  1092. err1:
  1093. free_all_mem(tp);
  1094. return -ENOMEM;
  1095. }
  1096. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1097. {
  1098. struct tx_agg *agg = NULL;
  1099. unsigned long flags;
  1100. if (list_empty(&tp->tx_free))
  1101. return NULL;
  1102. spin_lock_irqsave(&tp->tx_lock, flags);
  1103. if (!list_empty(&tp->tx_free)) {
  1104. struct list_head *cursor;
  1105. cursor = tp->tx_free.next;
  1106. list_del_init(cursor);
  1107. agg = list_entry(cursor, struct tx_agg, list);
  1108. }
  1109. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1110. return agg;
  1111. }
  1112. /* r8152_csum_workaround()
  1113. * The hw limites the value the transport offset. When the offset is out of the
  1114. * range, calculate the checksum by sw.
  1115. */
  1116. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1117. struct sk_buff_head *list)
  1118. {
  1119. if (skb_shinfo(skb)->gso_size) {
  1120. netdev_features_t features = tp->netdev->features;
  1121. struct sk_buff_head seg_list;
  1122. struct sk_buff *segs, *nskb;
  1123. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1124. segs = skb_gso_segment(skb, features);
  1125. if (IS_ERR(segs) || !segs)
  1126. goto drop;
  1127. __skb_queue_head_init(&seg_list);
  1128. do {
  1129. nskb = segs;
  1130. segs = segs->next;
  1131. nskb->next = NULL;
  1132. __skb_queue_tail(&seg_list, nskb);
  1133. } while (segs);
  1134. skb_queue_splice(&seg_list, list);
  1135. dev_kfree_skb(skb);
  1136. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1137. if (skb_checksum_help(skb) < 0)
  1138. goto drop;
  1139. __skb_queue_head(list, skb);
  1140. } else {
  1141. struct net_device_stats *stats;
  1142. drop:
  1143. stats = &tp->netdev->stats;
  1144. stats->tx_dropped++;
  1145. dev_kfree_skb(skb);
  1146. }
  1147. }
  1148. /* msdn_giant_send_check()
  1149. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1150. * packet length for IPv6 TCP large packets.
  1151. */
  1152. static int msdn_giant_send_check(struct sk_buff *skb)
  1153. {
  1154. const struct ipv6hdr *ipv6h;
  1155. struct tcphdr *th;
  1156. int ret;
  1157. ret = skb_cow_head(skb, 0);
  1158. if (ret)
  1159. return ret;
  1160. ipv6h = ipv6_hdr(skb);
  1161. th = tcp_hdr(skb);
  1162. th->check = 0;
  1163. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1164. return ret;
  1165. }
  1166. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1167. {
  1168. if (skb_vlan_tag_present(skb)) {
  1169. u32 opts2;
  1170. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1171. desc->opts2 |= cpu_to_le32(opts2);
  1172. }
  1173. }
  1174. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1175. {
  1176. u32 opts2 = le32_to_cpu(desc->opts2);
  1177. if (opts2 & RX_VLAN_TAG)
  1178. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1179. swab16(opts2 & 0xffff));
  1180. }
  1181. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1182. struct sk_buff *skb, u32 len, u32 transport_offset)
  1183. {
  1184. u32 mss = skb_shinfo(skb)->gso_size;
  1185. u32 opts1, opts2 = 0;
  1186. int ret = TX_CSUM_SUCCESS;
  1187. WARN_ON_ONCE(len > TX_LEN_MAX);
  1188. opts1 = len | TX_FS | TX_LS;
  1189. if (mss) {
  1190. if (transport_offset > GTTCPHO_MAX) {
  1191. netif_warn(tp, tx_err, tp->netdev,
  1192. "Invalid transport offset 0x%x for TSO\n",
  1193. transport_offset);
  1194. ret = TX_CSUM_TSO;
  1195. goto unavailable;
  1196. }
  1197. switch (vlan_get_protocol(skb)) {
  1198. case htons(ETH_P_IP):
  1199. opts1 |= GTSENDV4;
  1200. break;
  1201. case htons(ETH_P_IPV6):
  1202. if (msdn_giant_send_check(skb)) {
  1203. ret = TX_CSUM_TSO;
  1204. goto unavailable;
  1205. }
  1206. opts1 |= GTSENDV6;
  1207. break;
  1208. default:
  1209. WARN_ON_ONCE(1);
  1210. break;
  1211. }
  1212. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1213. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1214. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1215. u8 ip_protocol;
  1216. if (transport_offset > TCPHO_MAX) {
  1217. netif_warn(tp, tx_err, tp->netdev,
  1218. "Invalid transport offset 0x%x\n",
  1219. transport_offset);
  1220. ret = TX_CSUM_NONE;
  1221. goto unavailable;
  1222. }
  1223. switch (vlan_get_protocol(skb)) {
  1224. case htons(ETH_P_IP):
  1225. opts2 |= IPV4_CS;
  1226. ip_protocol = ip_hdr(skb)->protocol;
  1227. break;
  1228. case htons(ETH_P_IPV6):
  1229. opts2 |= IPV6_CS;
  1230. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1231. break;
  1232. default:
  1233. ip_protocol = IPPROTO_RAW;
  1234. break;
  1235. }
  1236. if (ip_protocol == IPPROTO_TCP)
  1237. opts2 |= TCP_CS;
  1238. else if (ip_protocol == IPPROTO_UDP)
  1239. opts2 |= UDP_CS;
  1240. else
  1241. WARN_ON_ONCE(1);
  1242. opts2 |= transport_offset << TCPHO_SHIFT;
  1243. }
  1244. desc->opts2 = cpu_to_le32(opts2);
  1245. desc->opts1 = cpu_to_le32(opts1);
  1246. unavailable:
  1247. return ret;
  1248. }
  1249. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1250. {
  1251. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1252. int remain, ret;
  1253. u8 *tx_data;
  1254. __skb_queue_head_init(&skb_head);
  1255. spin_lock(&tx_queue->lock);
  1256. skb_queue_splice_init(tx_queue, &skb_head);
  1257. spin_unlock(&tx_queue->lock);
  1258. tx_data = agg->head;
  1259. agg->skb_num = 0;
  1260. agg->skb_len = 0;
  1261. remain = agg_buf_sz;
  1262. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1263. struct tx_desc *tx_desc;
  1264. struct sk_buff *skb;
  1265. unsigned int len;
  1266. u32 offset;
  1267. skb = __skb_dequeue(&skb_head);
  1268. if (!skb)
  1269. break;
  1270. len = skb->len + sizeof(*tx_desc);
  1271. if (len > remain) {
  1272. __skb_queue_head(&skb_head, skb);
  1273. break;
  1274. }
  1275. tx_data = tx_agg_align(tx_data);
  1276. tx_desc = (struct tx_desc *)tx_data;
  1277. offset = (u32)skb_transport_offset(skb);
  1278. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1279. r8152_csum_workaround(tp, skb, &skb_head);
  1280. continue;
  1281. }
  1282. rtl_tx_vlan_tag(tx_desc, skb);
  1283. tx_data += sizeof(*tx_desc);
  1284. len = skb->len;
  1285. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1286. struct net_device_stats *stats = &tp->netdev->stats;
  1287. stats->tx_dropped++;
  1288. dev_kfree_skb_any(skb);
  1289. tx_data -= sizeof(*tx_desc);
  1290. continue;
  1291. }
  1292. tx_data += len;
  1293. agg->skb_len += len;
  1294. agg->skb_num++;
  1295. dev_kfree_skb_any(skb);
  1296. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1297. }
  1298. if (!skb_queue_empty(&skb_head)) {
  1299. spin_lock(&tx_queue->lock);
  1300. skb_queue_splice(&skb_head, tx_queue);
  1301. spin_unlock(&tx_queue->lock);
  1302. }
  1303. netif_tx_lock(tp->netdev);
  1304. if (netif_queue_stopped(tp->netdev) &&
  1305. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1306. netif_wake_queue(tp->netdev);
  1307. netif_tx_unlock(tp->netdev);
  1308. ret = usb_autopm_get_interface_async(tp->intf);
  1309. if (ret < 0)
  1310. goto out_tx_fill;
  1311. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1312. agg->head, (int)(tx_data - (u8 *)agg->head),
  1313. (usb_complete_t)write_bulk_callback, agg);
  1314. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1315. if (ret < 0)
  1316. usb_autopm_put_interface_async(tp->intf);
  1317. out_tx_fill:
  1318. return ret;
  1319. }
  1320. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1321. {
  1322. u8 checksum = CHECKSUM_NONE;
  1323. u32 opts2, opts3;
  1324. if (tp->version == RTL_VER_01)
  1325. goto return_result;
  1326. opts2 = le32_to_cpu(rx_desc->opts2);
  1327. opts3 = le32_to_cpu(rx_desc->opts3);
  1328. if (opts2 & RD_IPV4_CS) {
  1329. if (opts3 & IPF)
  1330. checksum = CHECKSUM_NONE;
  1331. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1332. checksum = CHECKSUM_NONE;
  1333. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1334. checksum = CHECKSUM_NONE;
  1335. else
  1336. checksum = CHECKSUM_UNNECESSARY;
  1337. } else if (RD_IPV6_CS) {
  1338. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1339. checksum = CHECKSUM_UNNECESSARY;
  1340. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1341. checksum = CHECKSUM_UNNECESSARY;
  1342. }
  1343. return_result:
  1344. return checksum;
  1345. }
  1346. static int rx_bottom(struct r8152 *tp, int budget)
  1347. {
  1348. unsigned long flags;
  1349. struct list_head *cursor, *next, rx_queue;
  1350. int ret = 0, work_done = 0;
  1351. if (!skb_queue_empty(&tp->rx_queue)) {
  1352. while (work_done < budget) {
  1353. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1354. struct net_device *netdev = tp->netdev;
  1355. struct net_device_stats *stats = &netdev->stats;
  1356. unsigned int pkt_len;
  1357. if (!skb)
  1358. break;
  1359. pkt_len = skb->len;
  1360. napi_gro_receive(&tp->napi, skb);
  1361. work_done++;
  1362. stats->rx_packets++;
  1363. stats->rx_bytes += pkt_len;
  1364. }
  1365. }
  1366. if (list_empty(&tp->rx_done))
  1367. goto out1;
  1368. INIT_LIST_HEAD(&rx_queue);
  1369. spin_lock_irqsave(&tp->rx_lock, flags);
  1370. list_splice_init(&tp->rx_done, &rx_queue);
  1371. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1372. list_for_each_safe(cursor, next, &rx_queue) {
  1373. struct rx_desc *rx_desc;
  1374. struct rx_agg *agg;
  1375. int len_used = 0;
  1376. struct urb *urb;
  1377. u8 *rx_data;
  1378. list_del_init(cursor);
  1379. agg = list_entry(cursor, struct rx_agg, list);
  1380. urb = agg->urb;
  1381. if (urb->actual_length < ETH_ZLEN)
  1382. goto submit;
  1383. rx_desc = agg->head;
  1384. rx_data = agg->head;
  1385. len_used += sizeof(struct rx_desc);
  1386. while (urb->actual_length > len_used) {
  1387. struct net_device *netdev = tp->netdev;
  1388. struct net_device_stats *stats = &netdev->stats;
  1389. unsigned int pkt_len;
  1390. struct sk_buff *skb;
  1391. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1392. if (pkt_len < ETH_ZLEN)
  1393. break;
  1394. len_used += pkt_len;
  1395. if (urb->actual_length < len_used)
  1396. break;
  1397. pkt_len -= CRC_SIZE;
  1398. rx_data += sizeof(struct rx_desc);
  1399. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1400. if (!skb) {
  1401. stats->rx_dropped++;
  1402. goto find_next_rx;
  1403. }
  1404. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1405. memcpy(skb->data, rx_data, pkt_len);
  1406. skb_put(skb, pkt_len);
  1407. skb->protocol = eth_type_trans(skb, netdev);
  1408. rtl_rx_vlan_tag(rx_desc, skb);
  1409. if (work_done < budget) {
  1410. napi_gro_receive(&tp->napi, skb);
  1411. work_done++;
  1412. stats->rx_packets++;
  1413. stats->rx_bytes += pkt_len;
  1414. } else {
  1415. __skb_queue_tail(&tp->rx_queue, skb);
  1416. }
  1417. find_next_rx:
  1418. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1419. rx_desc = (struct rx_desc *)rx_data;
  1420. len_used = (int)(rx_data - (u8 *)agg->head);
  1421. len_used += sizeof(struct rx_desc);
  1422. }
  1423. submit:
  1424. if (!ret) {
  1425. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1426. } else {
  1427. urb->actual_length = 0;
  1428. list_add_tail(&agg->list, next);
  1429. }
  1430. }
  1431. if (!list_empty(&rx_queue)) {
  1432. spin_lock_irqsave(&tp->rx_lock, flags);
  1433. list_splice_tail(&rx_queue, &tp->rx_done);
  1434. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1435. }
  1436. out1:
  1437. return work_done;
  1438. }
  1439. static void tx_bottom(struct r8152 *tp)
  1440. {
  1441. int res;
  1442. do {
  1443. struct tx_agg *agg;
  1444. if (skb_queue_empty(&tp->tx_queue))
  1445. break;
  1446. agg = r8152_get_tx_agg(tp);
  1447. if (!agg)
  1448. break;
  1449. res = r8152_tx_agg_fill(tp, agg);
  1450. if (res) {
  1451. struct net_device *netdev = tp->netdev;
  1452. if (res == -ENODEV) {
  1453. set_bit(RTL8152_UNPLUG, &tp->flags);
  1454. netif_device_detach(netdev);
  1455. } else {
  1456. struct net_device_stats *stats = &netdev->stats;
  1457. unsigned long flags;
  1458. netif_warn(tp, tx_err, netdev,
  1459. "failed tx_urb %d\n", res);
  1460. stats->tx_dropped += agg->skb_num;
  1461. spin_lock_irqsave(&tp->tx_lock, flags);
  1462. list_add_tail(&agg->list, &tp->tx_free);
  1463. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1464. }
  1465. }
  1466. } while (res == 0);
  1467. }
  1468. static void bottom_half(struct r8152 *tp)
  1469. {
  1470. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1471. return;
  1472. if (!test_bit(WORK_ENABLE, &tp->flags))
  1473. return;
  1474. /* When link down, the driver would cancel all bulks. */
  1475. /* This avoid the re-submitting bulk */
  1476. if (!netif_carrier_ok(tp->netdev))
  1477. return;
  1478. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1479. tx_bottom(tp);
  1480. }
  1481. static int r8152_poll(struct napi_struct *napi, int budget)
  1482. {
  1483. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1484. int work_done;
  1485. work_done = rx_bottom(tp, budget);
  1486. bottom_half(tp);
  1487. if (work_done < budget) {
  1488. napi_complete(napi);
  1489. if (!list_empty(&tp->rx_done))
  1490. napi_schedule(napi);
  1491. }
  1492. return work_done;
  1493. }
  1494. static
  1495. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1496. {
  1497. int ret;
  1498. /* The rx would be stopped, so skip submitting */
  1499. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1500. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1501. return 0;
  1502. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1503. agg->head, agg_buf_sz,
  1504. (usb_complete_t)read_bulk_callback, agg);
  1505. ret = usb_submit_urb(agg->urb, mem_flags);
  1506. if (ret == -ENODEV) {
  1507. set_bit(RTL8152_UNPLUG, &tp->flags);
  1508. netif_device_detach(tp->netdev);
  1509. } else if (ret) {
  1510. struct urb *urb = agg->urb;
  1511. unsigned long flags;
  1512. urb->actual_length = 0;
  1513. spin_lock_irqsave(&tp->rx_lock, flags);
  1514. list_add_tail(&agg->list, &tp->rx_done);
  1515. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1516. netif_err(tp, rx_err, tp->netdev,
  1517. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1518. napi_schedule(&tp->napi);
  1519. }
  1520. return ret;
  1521. }
  1522. static void rtl_drop_queued_tx(struct r8152 *tp)
  1523. {
  1524. struct net_device_stats *stats = &tp->netdev->stats;
  1525. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1526. struct sk_buff *skb;
  1527. if (skb_queue_empty(tx_queue))
  1528. return;
  1529. __skb_queue_head_init(&skb_head);
  1530. spin_lock_bh(&tx_queue->lock);
  1531. skb_queue_splice_init(tx_queue, &skb_head);
  1532. spin_unlock_bh(&tx_queue->lock);
  1533. while ((skb = __skb_dequeue(&skb_head))) {
  1534. dev_kfree_skb(skb);
  1535. stats->tx_dropped++;
  1536. }
  1537. }
  1538. static void rtl8152_tx_timeout(struct net_device *netdev)
  1539. {
  1540. struct r8152 *tp = netdev_priv(netdev);
  1541. int i;
  1542. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1543. for (i = 0; i < RTL8152_MAX_TX; i++)
  1544. usb_unlink_urb(tp->tx_info[i].urb);
  1545. }
  1546. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1547. {
  1548. struct r8152 *tp = netdev_priv(netdev);
  1549. if (netif_carrier_ok(netdev)) {
  1550. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1551. schedule_delayed_work(&tp->schedule, 0);
  1552. }
  1553. }
  1554. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1555. {
  1556. struct r8152 *tp = netdev_priv(netdev);
  1557. u32 mc_filter[2]; /* Multicast hash filter */
  1558. __le32 tmp[2];
  1559. u32 ocp_data;
  1560. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1561. netif_stop_queue(netdev);
  1562. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1563. ocp_data &= ~RCR_ACPT_ALL;
  1564. ocp_data |= RCR_AB | RCR_APM;
  1565. if (netdev->flags & IFF_PROMISC) {
  1566. /* Unconditionally log net taps. */
  1567. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1568. ocp_data |= RCR_AM | RCR_AAP;
  1569. mc_filter[1] = 0xffffffff;
  1570. mc_filter[0] = 0xffffffff;
  1571. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1572. (netdev->flags & IFF_ALLMULTI)) {
  1573. /* Too many to filter perfectly -- accept all multicasts. */
  1574. ocp_data |= RCR_AM;
  1575. mc_filter[1] = 0xffffffff;
  1576. mc_filter[0] = 0xffffffff;
  1577. } else {
  1578. struct netdev_hw_addr *ha;
  1579. mc_filter[1] = 0;
  1580. mc_filter[0] = 0;
  1581. netdev_for_each_mc_addr(ha, netdev) {
  1582. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1583. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1584. ocp_data |= RCR_AM;
  1585. }
  1586. }
  1587. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1588. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1589. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1590. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1591. netif_wake_queue(netdev);
  1592. }
  1593. static netdev_features_t
  1594. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1595. netdev_features_t features)
  1596. {
  1597. u32 mss = skb_shinfo(skb)->gso_size;
  1598. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1599. int offset = skb_transport_offset(skb);
  1600. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1601. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1602. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1603. features &= ~NETIF_F_GSO_MASK;
  1604. return features;
  1605. }
  1606. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1607. struct net_device *netdev)
  1608. {
  1609. struct r8152 *tp = netdev_priv(netdev);
  1610. skb_tx_timestamp(skb);
  1611. skb_queue_tail(&tp->tx_queue, skb);
  1612. if (!list_empty(&tp->tx_free)) {
  1613. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1614. set_bit(SCHEDULE_NAPI, &tp->flags);
  1615. schedule_delayed_work(&tp->schedule, 0);
  1616. } else {
  1617. usb_mark_last_busy(tp->udev);
  1618. napi_schedule(&tp->napi);
  1619. }
  1620. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1621. netif_stop_queue(netdev);
  1622. }
  1623. return NETDEV_TX_OK;
  1624. }
  1625. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1626. {
  1627. u32 ocp_data;
  1628. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1629. ocp_data &= ~FMC_FCR_MCU_EN;
  1630. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1631. ocp_data |= FMC_FCR_MCU_EN;
  1632. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1633. }
  1634. static void rtl8152_nic_reset(struct r8152 *tp)
  1635. {
  1636. int i;
  1637. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1638. for (i = 0; i < 1000; i++) {
  1639. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1640. break;
  1641. usleep_range(100, 400);
  1642. }
  1643. }
  1644. static void set_tx_qlen(struct r8152 *tp)
  1645. {
  1646. struct net_device *netdev = tp->netdev;
  1647. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1648. sizeof(struct tx_desc));
  1649. }
  1650. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1651. {
  1652. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1653. }
  1654. static void rtl_set_eee_plus(struct r8152 *tp)
  1655. {
  1656. u32 ocp_data;
  1657. u8 speed;
  1658. speed = rtl8152_get_speed(tp);
  1659. if (speed & _10bps) {
  1660. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1661. ocp_data |= EEEP_CR_EEEP_TX;
  1662. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1663. } else {
  1664. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1665. ocp_data &= ~EEEP_CR_EEEP_TX;
  1666. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1667. }
  1668. }
  1669. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1670. {
  1671. u32 ocp_data;
  1672. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1673. if (enable)
  1674. ocp_data |= RXDY_GATED_EN;
  1675. else
  1676. ocp_data &= ~RXDY_GATED_EN;
  1677. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1678. }
  1679. static int rtl_start_rx(struct r8152 *tp)
  1680. {
  1681. int i, ret = 0;
  1682. napi_disable(&tp->napi);
  1683. INIT_LIST_HEAD(&tp->rx_done);
  1684. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1685. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1686. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1687. if (ret)
  1688. break;
  1689. }
  1690. napi_enable(&tp->napi);
  1691. if (ret && ++i < RTL8152_MAX_RX) {
  1692. struct list_head rx_queue;
  1693. unsigned long flags;
  1694. INIT_LIST_HEAD(&rx_queue);
  1695. do {
  1696. struct rx_agg *agg = &tp->rx_info[i++];
  1697. struct urb *urb = agg->urb;
  1698. urb->actual_length = 0;
  1699. list_add_tail(&agg->list, &rx_queue);
  1700. } while (i < RTL8152_MAX_RX);
  1701. spin_lock_irqsave(&tp->rx_lock, flags);
  1702. list_splice_tail(&rx_queue, &tp->rx_done);
  1703. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1704. }
  1705. return ret;
  1706. }
  1707. static int rtl_stop_rx(struct r8152 *tp)
  1708. {
  1709. int i;
  1710. for (i = 0; i < RTL8152_MAX_RX; i++)
  1711. usb_kill_urb(tp->rx_info[i].urb);
  1712. while (!skb_queue_empty(&tp->rx_queue))
  1713. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1714. return 0;
  1715. }
  1716. static int rtl_enable(struct r8152 *tp)
  1717. {
  1718. u32 ocp_data;
  1719. r8152b_reset_packet_filter(tp);
  1720. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1721. ocp_data |= CR_RE | CR_TE;
  1722. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1723. rxdy_gated_en(tp, false);
  1724. return 0;
  1725. }
  1726. static int rtl8152_enable(struct r8152 *tp)
  1727. {
  1728. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1729. return -ENODEV;
  1730. set_tx_qlen(tp);
  1731. rtl_set_eee_plus(tp);
  1732. return rtl_enable(tp);
  1733. }
  1734. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1735. {
  1736. u32 ocp_data = tp->coalesce / 8;
  1737. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1738. }
  1739. static void r8153_set_rx_early_size(struct r8152 *tp)
  1740. {
  1741. u32 mtu = tp->netdev->mtu;
  1742. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1743. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1744. }
  1745. static int rtl8153_enable(struct r8152 *tp)
  1746. {
  1747. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1748. return -ENODEV;
  1749. set_tx_qlen(tp);
  1750. rtl_set_eee_plus(tp);
  1751. r8153_set_rx_early_timeout(tp);
  1752. r8153_set_rx_early_size(tp);
  1753. return rtl_enable(tp);
  1754. }
  1755. static void rtl_disable(struct r8152 *tp)
  1756. {
  1757. u32 ocp_data;
  1758. int i;
  1759. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1760. rtl_drop_queued_tx(tp);
  1761. return;
  1762. }
  1763. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1764. ocp_data &= ~RCR_ACPT_ALL;
  1765. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1766. rtl_drop_queued_tx(tp);
  1767. for (i = 0; i < RTL8152_MAX_TX; i++)
  1768. usb_kill_urb(tp->tx_info[i].urb);
  1769. rxdy_gated_en(tp, true);
  1770. for (i = 0; i < 1000; i++) {
  1771. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1772. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1773. break;
  1774. usleep_range(1000, 2000);
  1775. }
  1776. for (i = 0; i < 1000; i++) {
  1777. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1778. break;
  1779. usleep_range(1000, 2000);
  1780. }
  1781. rtl_stop_rx(tp);
  1782. rtl8152_nic_reset(tp);
  1783. }
  1784. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1785. {
  1786. u32 ocp_data;
  1787. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1788. if (enable)
  1789. ocp_data |= POWER_CUT;
  1790. else
  1791. ocp_data &= ~POWER_CUT;
  1792. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1793. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1794. ocp_data &= ~RESUME_INDICATE;
  1795. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1796. }
  1797. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1798. {
  1799. u32 ocp_data;
  1800. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1801. if (enable)
  1802. ocp_data |= CPCR_RX_VLAN;
  1803. else
  1804. ocp_data &= ~CPCR_RX_VLAN;
  1805. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1806. }
  1807. static int rtl8152_set_features(struct net_device *dev,
  1808. netdev_features_t features)
  1809. {
  1810. netdev_features_t changed = features ^ dev->features;
  1811. struct r8152 *tp = netdev_priv(dev);
  1812. int ret;
  1813. ret = usb_autopm_get_interface(tp->intf);
  1814. if (ret < 0)
  1815. goto out;
  1816. mutex_lock(&tp->control);
  1817. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1818. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1819. rtl_rx_vlan_en(tp, true);
  1820. else
  1821. rtl_rx_vlan_en(tp, false);
  1822. }
  1823. mutex_unlock(&tp->control);
  1824. usb_autopm_put_interface(tp->intf);
  1825. out:
  1826. return ret;
  1827. }
  1828. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1829. static u32 __rtl_get_wol(struct r8152 *tp)
  1830. {
  1831. u32 ocp_data;
  1832. u32 wolopts = 0;
  1833. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1834. if (!(ocp_data & LAN_WAKE_EN))
  1835. return 0;
  1836. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1837. if (ocp_data & LINK_ON_WAKE_EN)
  1838. wolopts |= WAKE_PHY;
  1839. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1840. if (ocp_data & UWF_EN)
  1841. wolopts |= WAKE_UCAST;
  1842. if (ocp_data & BWF_EN)
  1843. wolopts |= WAKE_BCAST;
  1844. if (ocp_data & MWF_EN)
  1845. wolopts |= WAKE_MCAST;
  1846. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1847. if (ocp_data & MAGIC_EN)
  1848. wolopts |= WAKE_MAGIC;
  1849. return wolopts;
  1850. }
  1851. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1852. {
  1853. u32 ocp_data;
  1854. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1855. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1856. ocp_data &= ~LINK_ON_WAKE_EN;
  1857. if (wolopts & WAKE_PHY)
  1858. ocp_data |= LINK_ON_WAKE_EN;
  1859. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1860. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1861. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1862. if (wolopts & WAKE_UCAST)
  1863. ocp_data |= UWF_EN;
  1864. if (wolopts & WAKE_BCAST)
  1865. ocp_data |= BWF_EN;
  1866. if (wolopts & WAKE_MCAST)
  1867. ocp_data |= MWF_EN;
  1868. if (wolopts & WAKE_ANY)
  1869. ocp_data |= LAN_WAKE_EN;
  1870. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1871. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1872. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1873. ocp_data &= ~MAGIC_EN;
  1874. if (wolopts & WAKE_MAGIC)
  1875. ocp_data |= MAGIC_EN;
  1876. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1877. if (wolopts & WAKE_ANY)
  1878. device_set_wakeup_enable(&tp->udev->dev, true);
  1879. else
  1880. device_set_wakeup_enable(&tp->udev->dev, false);
  1881. }
  1882. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1883. {
  1884. if (enable) {
  1885. u32 ocp_data;
  1886. __rtl_set_wol(tp, WAKE_ANY);
  1887. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1888. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1889. ocp_data |= LINK_OFF_WAKE_EN;
  1890. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1891. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1892. } else {
  1893. __rtl_set_wol(tp, tp->saved_wolopts);
  1894. }
  1895. }
  1896. static void rtl_phy_reset(struct r8152 *tp)
  1897. {
  1898. u16 data;
  1899. int i;
  1900. clear_bit(PHY_RESET, &tp->flags);
  1901. data = r8152_mdio_read(tp, MII_BMCR);
  1902. /* don't reset again before the previous one complete */
  1903. if (data & BMCR_RESET)
  1904. return;
  1905. data |= BMCR_RESET;
  1906. r8152_mdio_write(tp, MII_BMCR, data);
  1907. for (i = 0; i < 50; i++) {
  1908. msleep(20);
  1909. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1910. break;
  1911. }
  1912. }
  1913. static void r8153_teredo_off(struct r8152 *tp)
  1914. {
  1915. u32 ocp_data;
  1916. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1917. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1918. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1919. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1920. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1921. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1922. }
  1923. static void r8152b_disable_aldps(struct r8152 *tp)
  1924. {
  1925. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1926. msleep(20);
  1927. }
  1928. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1929. {
  1930. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1931. LINKENA | DIS_SDSAVE);
  1932. }
  1933. static void rtl8152_disable(struct r8152 *tp)
  1934. {
  1935. r8152b_disable_aldps(tp);
  1936. rtl_disable(tp);
  1937. r8152b_enable_aldps(tp);
  1938. }
  1939. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1940. {
  1941. u16 data;
  1942. data = r8152_mdio_read(tp, MII_BMCR);
  1943. if (data & BMCR_PDOWN) {
  1944. data &= ~BMCR_PDOWN;
  1945. r8152_mdio_write(tp, MII_BMCR, data);
  1946. }
  1947. set_bit(PHY_RESET, &tp->flags);
  1948. }
  1949. static void r8152b_exit_oob(struct r8152 *tp)
  1950. {
  1951. u32 ocp_data;
  1952. int i;
  1953. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1954. ocp_data &= ~RCR_ACPT_ALL;
  1955. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1956. rxdy_gated_en(tp, true);
  1957. r8153_teredo_off(tp);
  1958. r8152b_hw_phy_cfg(tp);
  1959. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1960. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1961. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1962. ocp_data &= ~NOW_IS_OOB;
  1963. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1964. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1965. ocp_data &= ~MCU_BORW_EN;
  1966. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1967. for (i = 0; i < 1000; i++) {
  1968. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1969. if (ocp_data & LINK_LIST_READY)
  1970. break;
  1971. usleep_range(1000, 2000);
  1972. }
  1973. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1974. ocp_data |= RE_INIT_LL;
  1975. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1976. for (i = 0; i < 1000; i++) {
  1977. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1978. if (ocp_data & LINK_LIST_READY)
  1979. break;
  1980. usleep_range(1000, 2000);
  1981. }
  1982. rtl8152_nic_reset(tp);
  1983. /* rx share fifo credit full threshold */
  1984. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1985. if (tp->udev->speed == USB_SPEED_FULL ||
  1986. tp->udev->speed == USB_SPEED_LOW) {
  1987. /* rx share fifo credit near full threshold */
  1988. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1989. RXFIFO_THR2_FULL);
  1990. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1991. RXFIFO_THR3_FULL);
  1992. } else {
  1993. /* rx share fifo credit near full threshold */
  1994. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1995. RXFIFO_THR2_HIGH);
  1996. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1997. RXFIFO_THR3_HIGH);
  1998. }
  1999. /* TX share fifo free credit full threshold */
  2000. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2001. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2002. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2003. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2004. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2005. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2006. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2007. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2008. ocp_data |= TCR0_AUTO_FIFO;
  2009. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2010. }
  2011. static void r8152b_enter_oob(struct r8152 *tp)
  2012. {
  2013. u32 ocp_data;
  2014. int i;
  2015. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2016. ocp_data &= ~NOW_IS_OOB;
  2017. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2018. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2019. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2020. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2021. rtl_disable(tp);
  2022. for (i = 0; i < 1000; i++) {
  2023. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2024. if (ocp_data & LINK_LIST_READY)
  2025. break;
  2026. usleep_range(1000, 2000);
  2027. }
  2028. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2029. ocp_data |= RE_INIT_LL;
  2030. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2031. for (i = 0; i < 1000; i++) {
  2032. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2033. if (ocp_data & LINK_LIST_READY)
  2034. break;
  2035. usleep_range(1000, 2000);
  2036. }
  2037. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2038. rtl_rx_vlan_en(tp, true);
  2039. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2040. ocp_data |= ALDPS_PROXY_MODE;
  2041. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2042. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2043. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2044. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2045. rxdy_gated_en(tp, false);
  2046. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2047. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2048. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2049. }
  2050. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2051. {
  2052. u32 ocp_data;
  2053. u16 data;
  2054. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2055. data = r8152_mdio_read(tp, MII_BMCR);
  2056. if (data & BMCR_PDOWN) {
  2057. data &= ~BMCR_PDOWN;
  2058. r8152_mdio_write(tp, MII_BMCR, data);
  2059. }
  2060. if (tp->version == RTL_VER_03) {
  2061. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2062. data &= ~CTAP_SHORT_EN;
  2063. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2064. }
  2065. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2066. data |= EEE_CLKDIV_EN;
  2067. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2068. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2069. data |= EN_10M_BGOFF;
  2070. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2071. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2072. data |= EN_10M_PLLOFF;
  2073. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2074. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2075. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2076. ocp_data |= PFM_PWM_SWITCH;
  2077. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2078. /* Enable LPF corner auto tune */
  2079. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2080. /* Adjust 10M Amplitude */
  2081. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2082. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2083. set_bit(PHY_RESET, &tp->flags);
  2084. }
  2085. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2086. {
  2087. u8 u1u2[8];
  2088. if (enable)
  2089. memset(u1u2, 0xff, sizeof(u1u2));
  2090. else
  2091. memset(u1u2, 0x00, sizeof(u1u2));
  2092. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2093. }
  2094. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2095. {
  2096. u32 ocp_data;
  2097. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2098. if (enable)
  2099. ocp_data |= U2P3_ENABLE;
  2100. else
  2101. ocp_data &= ~U2P3_ENABLE;
  2102. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2103. }
  2104. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2105. {
  2106. u32 ocp_data;
  2107. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2108. if (enable)
  2109. ocp_data |= PWR_EN | PHASE2_EN;
  2110. else
  2111. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2112. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2113. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2114. ocp_data &= ~PCUT_STATUS;
  2115. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2116. }
  2117. static void r8153_first_init(struct r8152 *tp)
  2118. {
  2119. u32 ocp_data;
  2120. int i;
  2121. rxdy_gated_en(tp, true);
  2122. r8153_teredo_off(tp);
  2123. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2124. ocp_data &= ~RCR_ACPT_ALL;
  2125. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2126. r8153_hw_phy_cfg(tp);
  2127. rtl8152_nic_reset(tp);
  2128. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2129. ocp_data &= ~NOW_IS_OOB;
  2130. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2131. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2132. ocp_data &= ~MCU_BORW_EN;
  2133. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2134. for (i = 0; i < 1000; i++) {
  2135. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2136. if (ocp_data & LINK_LIST_READY)
  2137. break;
  2138. usleep_range(1000, 2000);
  2139. }
  2140. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2141. ocp_data |= RE_INIT_LL;
  2142. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2143. for (i = 0; i < 1000; i++) {
  2144. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2145. if (ocp_data & LINK_LIST_READY)
  2146. break;
  2147. usleep_range(1000, 2000);
  2148. }
  2149. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2150. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2151. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2152. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2153. ocp_data |= TCR0_AUTO_FIFO;
  2154. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2155. rtl8152_nic_reset(tp);
  2156. /* rx share fifo credit full threshold */
  2157. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2158. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2159. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2160. /* TX share fifo free credit full threshold */
  2161. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2162. /* rx aggregation */
  2163. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2164. ocp_data &= ~RX_AGG_DISABLE;
  2165. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2166. }
  2167. static void r8153_enter_oob(struct r8152 *tp)
  2168. {
  2169. u32 ocp_data;
  2170. int i;
  2171. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2172. ocp_data &= ~NOW_IS_OOB;
  2173. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2174. rtl_disable(tp);
  2175. for (i = 0; i < 1000; i++) {
  2176. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2177. if (ocp_data & LINK_LIST_READY)
  2178. break;
  2179. usleep_range(1000, 2000);
  2180. }
  2181. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2182. ocp_data |= RE_INIT_LL;
  2183. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2184. for (i = 0; i < 1000; i++) {
  2185. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2186. if (ocp_data & LINK_LIST_READY)
  2187. break;
  2188. usleep_range(1000, 2000);
  2189. }
  2190. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2191. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2192. ocp_data &= ~TEREDO_WAKE_MASK;
  2193. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2194. rtl_rx_vlan_en(tp, true);
  2195. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2196. ocp_data |= ALDPS_PROXY_MODE;
  2197. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2198. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2199. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2200. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2201. rxdy_gated_en(tp, false);
  2202. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2203. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2204. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2205. }
  2206. static void r8153_disable_aldps(struct r8152 *tp)
  2207. {
  2208. u16 data;
  2209. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2210. data &= ~EN_ALDPS;
  2211. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2212. msleep(20);
  2213. }
  2214. static void r8153_enable_aldps(struct r8152 *tp)
  2215. {
  2216. u16 data;
  2217. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2218. data |= EN_ALDPS;
  2219. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2220. }
  2221. static void rtl8153_disable(struct r8152 *tp)
  2222. {
  2223. r8153_disable_aldps(tp);
  2224. rtl_disable(tp);
  2225. r8153_enable_aldps(tp);
  2226. }
  2227. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2228. {
  2229. u16 bmcr, anar, gbcr;
  2230. int ret = 0;
  2231. cancel_delayed_work_sync(&tp->schedule);
  2232. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2233. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2234. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2235. if (tp->mii.supports_gmii) {
  2236. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2237. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2238. } else {
  2239. gbcr = 0;
  2240. }
  2241. if (autoneg == AUTONEG_DISABLE) {
  2242. if (speed == SPEED_10) {
  2243. bmcr = 0;
  2244. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2245. } else if (speed == SPEED_100) {
  2246. bmcr = BMCR_SPEED100;
  2247. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2248. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2249. bmcr = BMCR_SPEED1000;
  2250. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2251. } else {
  2252. ret = -EINVAL;
  2253. goto out;
  2254. }
  2255. if (duplex == DUPLEX_FULL)
  2256. bmcr |= BMCR_FULLDPLX;
  2257. } else {
  2258. if (speed == SPEED_10) {
  2259. if (duplex == DUPLEX_FULL)
  2260. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2261. else
  2262. anar |= ADVERTISE_10HALF;
  2263. } else if (speed == SPEED_100) {
  2264. if (duplex == DUPLEX_FULL) {
  2265. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2266. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2267. } else {
  2268. anar |= ADVERTISE_10HALF;
  2269. anar |= ADVERTISE_100HALF;
  2270. }
  2271. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2272. if (duplex == DUPLEX_FULL) {
  2273. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2274. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2275. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2276. } else {
  2277. anar |= ADVERTISE_10HALF;
  2278. anar |= ADVERTISE_100HALF;
  2279. gbcr |= ADVERTISE_1000HALF;
  2280. }
  2281. } else {
  2282. ret = -EINVAL;
  2283. goto out;
  2284. }
  2285. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2286. }
  2287. if (test_bit(PHY_RESET, &tp->flags))
  2288. bmcr |= BMCR_RESET;
  2289. if (tp->mii.supports_gmii)
  2290. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2291. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2292. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2293. if (test_bit(PHY_RESET, &tp->flags)) {
  2294. int i;
  2295. clear_bit(PHY_RESET, &tp->flags);
  2296. for (i = 0; i < 50; i++) {
  2297. msleep(20);
  2298. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2299. break;
  2300. }
  2301. }
  2302. out:
  2303. return ret;
  2304. }
  2305. static void rtl8152_up(struct r8152 *tp)
  2306. {
  2307. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2308. return;
  2309. r8152b_disable_aldps(tp);
  2310. r8152b_exit_oob(tp);
  2311. r8152b_enable_aldps(tp);
  2312. }
  2313. static void rtl8152_down(struct r8152 *tp)
  2314. {
  2315. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2316. rtl_drop_queued_tx(tp);
  2317. return;
  2318. }
  2319. r8152_power_cut_en(tp, false);
  2320. r8152b_disable_aldps(tp);
  2321. r8152b_enter_oob(tp);
  2322. r8152b_enable_aldps(tp);
  2323. }
  2324. static void rtl8153_up(struct r8152 *tp)
  2325. {
  2326. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2327. return;
  2328. r8153_disable_aldps(tp);
  2329. r8153_first_init(tp);
  2330. r8153_enable_aldps(tp);
  2331. }
  2332. static void rtl8153_down(struct r8152 *tp)
  2333. {
  2334. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2335. rtl_drop_queued_tx(tp);
  2336. return;
  2337. }
  2338. r8153_u1u2en(tp, false);
  2339. r8153_power_cut_en(tp, false);
  2340. r8153_disable_aldps(tp);
  2341. r8153_enter_oob(tp);
  2342. r8153_enable_aldps(tp);
  2343. }
  2344. static void set_carrier(struct r8152 *tp)
  2345. {
  2346. struct net_device *netdev = tp->netdev;
  2347. u8 speed;
  2348. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  2349. speed = rtl8152_get_speed(tp);
  2350. if (speed & LINK_STATUS) {
  2351. if (!netif_carrier_ok(netdev)) {
  2352. tp->rtl_ops.enable(tp);
  2353. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2354. netif_carrier_on(netdev);
  2355. rtl_start_rx(tp);
  2356. }
  2357. } else {
  2358. if (netif_carrier_ok(netdev)) {
  2359. netif_carrier_off(netdev);
  2360. napi_disable(&tp->napi);
  2361. tp->rtl_ops.disable(tp);
  2362. napi_enable(&tp->napi);
  2363. }
  2364. }
  2365. }
  2366. static void rtl_work_func_t(struct work_struct *work)
  2367. {
  2368. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2369. /* If the device is unplugged or !netif_running(), the workqueue
  2370. * doesn't need to wake the device, and could return directly.
  2371. */
  2372. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2373. return;
  2374. if (usb_autopm_get_interface(tp->intf) < 0)
  2375. return;
  2376. if (!test_bit(WORK_ENABLE, &tp->flags))
  2377. goto out1;
  2378. if (!mutex_trylock(&tp->control)) {
  2379. schedule_delayed_work(&tp->schedule, 0);
  2380. goto out1;
  2381. }
  2382. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  2383. set_carrier(tp);
  2384. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2385. _rtl8152_set_rx_mode(tp->netdev);
  2386. /* don't schedule napi before linking */
  2387. if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
  2388. netif_carrier_ok(tp->netdev)) {
  2389. clear_bit(SCHEDULE_NAPI, &tp->flags);
  2390. napi_schedule(&tp->napi);
  2391. }
  2392. if (test_bit(PHY_RESET, &tp->flags))
  2393. rtl_phy_reset(tp);
  2394. mutex_unlock(&tp->control);
  2395. out1:
  2396. usb_autopm_put_interface(tp->intf);
  2397. }
  2398. static int rtl8152_open(struct net_device *netdev)
  2399. {
  2400. struct r8152 *tp = netdev_priv(netdev);
  2401. int res = 0;
  2402. res = alloc_all_mem(tp);
  2403. if (res)
  2404. goto out;
  2405. netif_carrier_off(netdev);
  2406. res = usb_autopm_get_interface(tp->intf);
  2407. if (res < 0) {
  2408. free_all_mem(tp);
  2409. goto out;
  2410. }
  2411. mutex_lock(&tp->control);
  2412. /* The WORK_ENABLE may be set when autoresume occurs */
  2413. if (test_bit(WORK_ENABLE, &tp->flags)) {
  2414. clear_bit(WORK_ENABLE, &tp->flags);
  2415. usb_kill_urb(tp->intr_urb);
  2416. cancel_delayed_work_sync(&tp->schedule);
  2417. /* disable the tx/rx, if the workqueue has enabled them. */
  2418. if (netif_carrier_ok(netdev))
  2419. tp->rtl_ops.disable(tp);
  2420. }
  2421. tp->rtl_ops.up(tp);
  2422. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2423. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2424. DUPLEX_FULL);
  2425. netif_carrier_off(netdev);
  2426. netif_start_queue(netdev);
  2427. set_bit(WORK_ENABLE, &tp->flags);
  2428. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2429. if (res) {
  2430. if (res == -ENODEV)
  2431. netif_device_detach(tp->netdev);
  2432. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2433. res);
  2434. free_all_mem(tp);
  2435. } else {
  2436. napi_enable(&tp->napi);
  2437. }
  2438. mutex_unlock(&tp->control);
  2439. usb_autopm_put_interface(tp->intf);
  2440. out:
  2441. return res;
  2442. }
  2443. static int rtl8152_close(struct net_device *netdev)
  2444. {
  2445. struct r8152 *tp = netdev_priv(netdev);
  2446. int res = 0;
  2447. napi_disable(&tp->napi);
  2448. clear_bit(WORK_ENABLE, &tp->flags);
  2449. usb_kill_urb(tp->intr_urb);
  2450. cancel_delayed_work_sync(&tp->schedule);
  2451. netif_stop_queue(netdev);
  2452. res = usb_autopm_get_interface(tp->intf);
  2453. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2454. rtl_drop_queued_tx(tp);
  2455. rtl_stop_rx(tp);
  2456. } else {
  2457. mutex_lock(&tp->control);
  2458. /* The autosuspend may have been enabled and wouldn't
  2459. * be disable when autoresume occurs, because the
  2460. * netif_running() would be false.
  2461. */
  2462. rtl_runtime_suspend_enable(tp, false);
  2463. tp->rtl_ops.down(tp);
  2464. mutex_unlock(&tp->control);
  2465. usb_autopm_put_interface(tp->intf);
  2466. }
  2467. free_all_mem(tp);
  2468. return res;
  2469. }
  2470. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2471. {
  2472. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2473. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2474. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2475. }
  2476. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2477. {
  2478. u16 data;
  2479. r8152_mmd_indirect(tp, dev, reg);
  2480. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2481. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2482. return data;
  2483. }
  2484. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2485. {
  2486. r8152_mmd_indirect(tp, dev, reg);
  2487. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2488. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2489. }
  2490. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2491. {
  2492. u16 config1, config2, config3;
  2493. u32 ocp_data;
  2494. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2495. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2496. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2497. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2498. if (enable) {
  2499. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2500. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2501. config1 |= sd_rise_time(1);
  2502. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2503. config3 |= fast_snr(42);
  2504. } else {
  2505. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2506. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2507. RX_QUIET_EN);
  2508. config1 |= sd_rise_time(7);
  2509. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2510. config3 |= fast_snr(511);
  2511. }
  2512. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2513. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2514. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2515. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2516. }
  2517. static void r8152b_enable_eee(struct r8152 *tp)
  2518. {
  2519. r8152_eee_en(tp, true);
  2520. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2521. }
  2522. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2523. {
  2524. u32 ocp_data;
  2525. u16 config;
  2526. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2527. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2528. if (enable) {
  2529. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2530. config |= EEE10_EN;
  2531. } else {
  2532. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2533. config &= ~EEE10_EN;
  2534. }
  2535. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2536. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2537. }
  2538. static void r8153_enable_eee(struct r8152 *tp)
  2539. {
  2540. r8153_eee_en(tp, true);
  2541. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2542. }
  2543. static void r8152b_enable_fc(struct r8152 *tp)
  2544. {
  2545. u16 anar;
  2546. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2547. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2548. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2549. }
  2550. static void rtl_tally_reset(struct r8152 *tp)
  2551. {
  2552. u32 ocp_data;
  2553. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2554. ocp_data |= TALLY_RESET;
  2555. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2556. }
  2557. static void r8152b_init(struct r8152 *tp)
  2558. {
  2559. u32 ocp_data;
  2560. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2561. return;
  2562. r8152b_disable_aldps(tp);
  2563. if (tp->version == RTL_VER_01) {
  2564. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2565. ocp_data &= ~LED_MODE_MASK;
  2566. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2567. }
  2568. r8152_power_cut_en(tp, false);
  2569. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2570. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2571. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2572. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2573. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2574. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2575. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2576. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2577. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2578. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2579. r8152b_enable_eee(tp);
  2580. r8152b_enable_aldps(tp);
  2581. r8152b_enable_fc(tp);
  2582. rtl_tally_reset(tp);
  2583. /* enable rx aggregation */
  2584. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2585. ocp_data &= ~RX_AGG_DISABLE;
  2586. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2587. }
  2588. static void r8153_init(struct r8152 *tp)
  2589. {
  2590. u32 ocp_data;
  2591. int i;
  2592. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2593. return;
  2594. r8153_disable_aldps(tp);
  2595. r8153_u1u2en(tp, false);
  2596. for (i = 0; i < 500; i++) {
  2597. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2598. AUTOLOAD_DONE)
  2599. break;
  2600. msleep(20);
  2601. }
  2602. for (i = 0; i < 500; i++) {
  2603. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2604. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2605. break;
  2606. msleep(20);
  2607. }
  2608. r8153_u2p3en(tp, false);
  2609. if (tp->version == RTL_VER_04) {
  2610. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2611. ocp_data &= ~pwd_dn_scale_mask;
  2612. ocp_data |= pwd_dn_scale(96);
  2613. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2614. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2615. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2616. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2617. } else if (tp->version == RTL_VER_05) {
  2618. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2619. ocp_data &= ~ECM_ALDPS;
  2620. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2621. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2622. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2623. ocp_data &= ~DYNAMIC_BURST;
  2624. else
  2625. ocp_data |= DYNAMIC_BURST;
  2626. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2627. }
  2628. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2629. ocp_data |= EP4_FULL_FC;
  2630. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2631. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2632. ocp_data &= ~TIMER11_EN;
  2633. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2634. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2635. ocp_data &= ~LED_MODE_MASK;
  2636. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2637. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2638. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2639. ocp_data |= LPM_TIMER_500MS;
  2640. else
  2641. ocp_data |= LPM_TIMER_500US;
  2642. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2643. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2644. ocp_data &= ~SEN_VAL_MASK;
  2645. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2646. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2647. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2648. r8153_power_cut_en(tp, false);
  2649. r8153_u1u2en(tp, true);
  2650. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2651. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2652. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2653. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2654. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2655. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2656. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2657. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2658. EEE_SPDWN_EN);
  2659. r8153_enable_eee(tp);
  2660. r8153_enable_aldps(tp);
  2661. r8152b_enable_fc(tp);
  2662. rtl_tally_reset(tp);
  2663. }
  2664. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2665. {
  2666. struct r8152 *tp = usb_get_intfdata(intf);
  2667. struct net_device *netdev = tp->netdev;
  2668. int ret = 0;
  2669. mutex_lock(&tp->control);
  2670. if (PMSG_IS_AUTO(message)) {
  2671. if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
  2672. ret = -EBUSY;
  2673. goto out1;
  2674. }
  2675. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2676. } else {
  2677. netif_device_detach(netdev);
  2678. }
  2679. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2680. clear_bit(WORK_ENABLE, &tp->flags);
  2681. usb_kill_urb(tp->intr_urb);
  2682. napi_disable(&tp->napi);
  2683. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2684. rtl_stop_rx(tp);
  2685. rtl_runtime_suspend_enable(tp, true);
  2686. } else {
  2687. cancel_delayed_work_sync(&tp->schedule);
  2688. tp->rtl_ops.down(tp);
  2689. }
  2690. napi_enable(&tp->napi);
  2691. }
  2692. out1:
  2693. mutex_unlock(&tp->control);
  2694. return ret;
  2695. }
  2696. static int rtl8152_resume(struct usb_interface *intf)
  2697. {
  2698. struct r8152 *tp = usb_get_intfdata(intf);
  2699. mutex_lock(&tp->control);
  2700. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2701. tp->rtl_ops.init(tp);
  2702. netif_device_attach(tp->netdev);
  2703. }
  2704. if (netif_running(tp->netdev)) {
  2705. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2706. rtl_runtime_suspend_enable(tp, false);
  2707. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2708. set_bit(WORK_ENABLE, &tp->flags);
  2709. if (netif_carrier_ok(tp->netdev))
  2710. rtl_start_rx(tp);
  2711. } else {
  2712. tp->rtl_ops.up(tp);
  2713. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2714. tp->mii.supports_gmii ?
  2715. SPEED_1000 : SPEED_100,
  2716. DUPLEX_FULL);
  2717. netif_carrier_off(tp->netdev);
  2718. set_bit(WORK_ENABLE, &tp->flags);
  2719. }
  2720. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2721. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2722. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2723. }
  2724. mutex_unlock(&tp->control);
  2725. return 0;
  2726. }
  2727. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2728. {
  2729. struct r8152 *tp = netdev_priv(dev);
  2730. if (usb_autopm_get_interface(tp->intf) < 0)
  2731. return;
  2732. mutex_lock(&tp->control);
  2733. wol->supported = WAKE_ANY;
  2734. wol->wolopts = __rtl_get_wol(tp);
  2735. mutex_unlock(&tp->control);
  2736. usb_autopm_put_interface(tp->intf);
  2737. }
  2738. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2739. {
  2740. struct r8152 *tp = netdev_priv(dev);
  2741. int ret;
  2742. ret = usb_autopm_get_interface(tp->intf);
  2743. if (ret < 0)
  2744. goto out_set_wol;
  2745. mutex_lock(&tp->control);
  2746. __rtl_set_wol(tp, wol->wolopts);
  2747. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2748. mutex_unlock(&tp->control);
  2749. usb_autopm_put_interface(tp->intf);
  2750. out_set_wol:
  2751. return ret;
  2752. }
  2753. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2754. {
  2755. struct r8152 *tp = netdev_priv(dev);
  2756. return tp->msg_enable;
  2757. }
  2758. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2759. {
  2760. struct r8152 *tp = netdev_priv(dev);
  2761. tp->msg_enable = value;
  2762. }
  2763. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2764. struct ethtool_drvinfo *info)
  2765. {
  2766. struct r8152 *tp = netdev_priv(netdev);
  2767. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2768. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2769. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2770. }
  2771. static
  2772. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2773. {
  2774. struct r8152 *tp = netdev_priv(netdev);
  2775. int ret;
  2776. if (!tp->mii.mdio_read)
  2777. return -EOPNOTSUPP;
  2778. ret = usb_autopm_get_interface(tp->intf);
  2779. if (ret < 0)
  2780. goto out;
  2781. mutex_lock(&tp->control);
  2782. ret = mii_ethtool_gset(&tp->mii, cmd);
  2783. mutex_unlock(&tp->control);
  2784. usb_autopm_put_interface(tp->intf);
  2785. out:
  2786. return ret;
  2787. }
  2788. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2789. {
  2790. struct r8152 *tp = netdev_priv(dev);
  2791. int ret;
  2792. ret = usb_autopm_get_interface(tp->intf);
  2793. if (ret < 0)
  2794. goto out;
  2795. mutex_lock(&tp->control);
  2796. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2797. mutex_unlock(&tp->control);
  2798. usb_autopm_put_interface(tp->intf);
  2799. out:
  2800. return ret;
  2801. }
  2802. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2803. "tx_packets",
  2804. "rx_packets",
  2805. "tx_errors",
  2806. "rx_errors",
  2807. "rx_missed",
  2808. "align_errors",
  2809. "tx_single_collisions",
  2810. "tx_multi_collisions",
  2811. "rx_unicast",
  2812. "rx_broadcast",
  2813. "rx_multicast",
  2814. "tx_aborted",
  2815. "tx_underrun",
  2816. };
  2817. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2818. {
  2819. switch (sset) {
  2820. case ETH_SS_STATS:
  2821. return ARRAY_SIZE(rtl8152_gstrings);
  2822. default:
  2823. return -EOPNOTSUPP;
  2824. }
  2825. }
  2826. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2827. struct ethtool_stats *stats, u64 *data)
  2828. {
  2829. struct r8152 *tp = netdev_priv(dev);
  2830. struct tally_counter tally;
  2831. if (usb_autopm_get_interface(tp->intf) < 0)
  2832. return;
  2833. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2834. usb_autopm_put_interface(tp->intf);
  2835. data[0] = le64_to_cpu(tally.tx_packets);
  2836. data[1] = le64_to_cpu(tally.rx_packets);
  2837. data[2] = le64_to_cpu(tally.tx_errors);
  2838. data[3] = le32_to_cpu(tally.rx_errors);
  2839. data[4] = le16_to_cpu(tally.rx_missed);
  2840. data[5] = le16_to_cpu(tally.align_errors);
  2841. data[6] = le32_to_cpu(tally.tx_one_collision);
  2842. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2843. data[8] = le64_to_cpu(tally.rx_unicast);
  2844. data[9] = le64_to_cpu(tally.rx_broadcast);
  2845. data[10] = le32_to_cpu(tally.rx_multicast);
  2846. data[11] = le16_to_cpu(tally.tx_aborted);
  2847. data[12] = le16_to_cpu(tally.tx_underrun);
  2848. }
  2849. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2850. {
  2851. switch (stringset) {
  2852. case ETH_SS_STATS:
  2853. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2854. break;
  2855. }
  2856. }
  2857. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2858. {
  2859. u32 ocp_data, lp, adv, supported = 0;
  2860. u16 val;
  2861. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2862. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2863. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2864. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2865. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2866. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2867. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2868. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2869. eee->eee_enabled = !!ocp_data;
  2870. eee->eee_active = !!(supported & adv & lp);
  2871. eee->supported = supported;
  2872. eee->advertised = adv;
  2873. eee->lp_advertised = lp;
  2874. return 0;
  2875. }
  2876. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2877. {
  2878. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2879. r8152_eee_en(tp, eee->eee_enabled);
  2880. if (!eee->eee_enabled)
  2881. val = 0;
  2882. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2883. return 0;
  2884. }
  2885. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2886. {
  2887. u32 ocp_data, lp, adv, supported = 0;
  2888. u16 val;
  2889. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  2890. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2891. val = ocp_reg_read(tp, OCP_EEE_ADV);
  2892. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2893. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  2894. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2895. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2896. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2897. eee->eee_enabled = !!ocp_data;
  2898. eee->eee_active = !!(supported & adv & lp);
  2899. eee->supported = supported;
  2900. eee->advertised = adv;
  2901. eee->lp_advertised = lp;
  2902. return 0;
  2903. }
  2904. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2905. {
  2906. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2907. r8153_eee_en(tp, eee->eee_enabled);
  2908. if (!eee->eee_enabled)
  2909. val = 0;
  2910. ocp_reg_write(tp, OCP_EEE_ADV, val);
  2911. return 0;
  2912. }
  2913. static int
  2914. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  2915. {
  2916. struct r8152 *tp = netdev_priv(net);
  2917. int ret;
  2918. ret = usb_autopm_get_interface(tp->intf);
  2919. if (ret < 0)
  2920. goto out;
  2921. mutex_lock(&tp->control);
  2922. ret = tp->rtl_ops.eee_get(tp, edata);
  2923. mutex_unlock(&tp->control);
  2924. usb_autopm_put_interface(tp->intf);
  2925. out:
  2926. return ret;
  2927. }
  2928. static int
  2929. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  2930. {
  2931. struct r8152 *tp = netdev_priv(net);
  2932. int ret;
  2933. ret = usb_autopm_get_interface(tp->intf);
  2934. if (ret < 0)
  2935. goto out;
  2936. mutex_lock(&tp->control);
  2937. ret = tp->rtl_ops.eee_set(tp, edata);
  2938. if (!ret)
  2939. ret = mii_nway_restart(&tp->mii);
  2940. mutex_unlock(&tp->control);
  2941. usb_autopm_put_interface(tp->intf);
  2942. out:
  2943. return ret;
  2944. }
  2945. static int rtl8152_nway_reset(struct net_device *dev)
  2946. {
  2947. struct r8152 *tp = netdev_priv(dev);
  2948. int ret;
  2949. ret = usb_autopm_get_interface(tp->intf);
  2950. if (ret < 0)
  2951. goto out;
  2952. mutex_lock(&tp->control);
  2953. ret = mii_nway_restart(&tp->mii);
  2954. mutex_unlock(&tp->control);
  2955. usb_autopm_put_interface(tp->intf);
  2956. out:
  2957. return ret;
  2958. }
  2959. static int rtl8152_get_coalesce(struct net_device *netdev,
  2960. struct ethtool_coalesce *coalesce)
  2961. {
  2962. struct r8152 *tp = netdev_priv(netdev);
  2963. switch (tp->version) {
  2964. case RTL_VER_01:
  2965. case RTL_VER_02:
  2966. return -EOPNOTSUPP;
  2967. default:
  2968. break;
  2969. }
  2970. coalesce->rx_coalesce_usecs = tp->coalesce;
  2971. return 0;
  2972. }
  2973. static int rtl8152_set_coalesce(struct net_device *netdev,
  2974. struct ethtool_coalesce *coalesce)
  2975. {
  2976. struct r8152 *tp = netdev_priv(netdev);
  2977. int ret;
  2978. switch (tp->version) {
  2979. case RTL_VER_01:
  2980. case RTL_VER_02:
  2981. return -EOPNOTSUPP;
  2982. default:
  2983. break;
  2984. }
  2985. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  2986. return -EINVAL;
  2987. ret = usb_autopm_get_interface(tp->intf);
  2988. if (ret < 0)
  2989. return ret;
  2990. mutex_lock(&tp->control);
  2991. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  2992. tp->coalesce = coalesce->rx_coalesce_usecs;
  2993. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  2994. r8153_set_rx_early_timeout(tp);
  2995. }
  2996. mutex_unlock(&tp->control);
  2997. usb_autopm_put_interface(tp->intf);
  2998. return ret;
  2999. }
  3000. static struct ethtool_ops ops = {
  3001. .get_drvinfo = rtl8152_get_drvinfo,
  3002. .get_settings = rtl8152_get_settings,
  3003. .set_settings = rtl8152_set_settings,
  3004. .get_link = ethtool_op_get_link,
  3005. .nway_reset = rtl8152_nway_reset,
  3006. .get_msglevel = rtl8152_get_msglevel,
  3007. .set_msglevel = rtl8152_set_msglevel,
  3008. .get_wol = rtl8152_get_wol,
  3009. .set_wol = rtl8152_set_wol,
  3010. .get_strings = rtl8152_get_strings,
  3011. .get_sset_count = rtl8152_get_sset_count,
  3012. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3013. .get_coalesce = rtl8152_get_coalesce,
  3014. .set_coalesce = rtl8152_set_coalesce,
  3015. .get_eee = rtl_ethtool_get_eee,
  3016. .set_eee = rtl_ethtool_set_eee,
  3017. };
  3018. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3019. {
  3020. struct r8152 *tp = netdev_priv(netdev);
  3021. struct mii_ioctl_data *data = if_mii(rq);
  3022. int res;
  3023. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3024. return -ENODEV;
  3025. res = usb_autopm_get_interface(tp->intf);
  3026. if (res < 0)
  3027. goto out;
  3028. switch (cmd) {
  3029. case SIOCGMIIPHY:
  3030. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3031. break;
  3032. case SIOCGMIIREG:
  3033. mutex_lock(&tp->control);
  3034. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3035. mutex_unlock(&tp->control);
  3036. break;
  3037. case SIOCSMIIREG:
  3038. if (!capable(CAP_NET_ADMIN)) {
  3039. res = -EPERM;
  3040. break;
  3041. }
  3042. mutex_lock(&tp->control);
  3043. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3044. mutex_unlock(&tp->control);
  3045. break;
  3046. default:
  3047. res = -EOPNOTSUPP;
  3048. }
  3049. usb_autopm_put_interface(tp->intf);
  3050. out:
  3051. return res;
  3052. }
  3053. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3054. {
  3055. struct r8152 *tp = netdev_priv(dev);
  3056. int ret;
  3057. switch (tp->version) {
  3058. case RTL_VER_01:
  3059. case RTL_VER_02:
  3060. return eth_change_mtu(dev, new_mtu);
  3061. default:
  3062. break;
  3063. }
  3064. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3065. return -EINVAL;
  3066. ret = usb_autopm_get_interface(tp->intf);
  3067. if (ret < 0)
  3068. return ret;
  3069. mutex_lock(&tp->control);
  3070. dev->mtu = new_mtu;
  3071. if (netif_running(dev) && netif_carrier_ok(dev))
  3072. r8153_set_rx_early_size(tp);
  3073. mutex_unlock(&tp->control);
  3074. usb_autopm_put_interface(tp->intf);
  3075. return ret;
  3076. }
  3077. static const struct net_device_ops rtl8152_netdev_ops = {
  3078. .ndo_open = rtl8152_open,
  3079. .ndo_stop = rtl8152_close,
  3080. .ndo_do_ioctl = rtl8152_ioctl,
  3081. .ndo_start_xmit = rtl8152_start_xmit,
  3082. .ndo_tx_timeout = rtl8152_tx_timeout,
  3083. .ndo_set_features = rtl8152_set_features,
  3084. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3085. .ndo_set_mac_address = rtl8152_set_mac_address,
  3086. .ndo_change_mtu = rtl8152_change_mtu,
  3087. .ndo_validate_addr = eth_validate_addr,
  3088. .ndo_features_check = rtl8152_features_check,
  3089. };
  3090. static void r8152b_get_version(struct r8152 *tp)
  3091. {
  3092. u32 ocp_data;
  3093. u16 version;
  3094. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3095. version = (u16)(ocp_data & VERSION_MASK);
  3096. switch (version) {
  3097. case 0x4c00:
  3098. tp->version = RTL_VER_01;
  3099. break;
  3100. case 0x4c10:
  3101. tp->version = RTL_VER_02;
  3102. break;
  3103. case 0x5c00:
  3104. tp->version = RTL_VER_03;
  3105. tp->mii.supports_gmii = 1;
  3106. break;
  3107. case 0x5c10:
  3108. tp->version = RTL_VER_04;
  3109. tp->mii.supports_gmii = 1;
  3110. break;
  3111. case 0x5c20:
  3112. tp->version = RTL_VER_05;
  3113. tp->mii.supports_gmii = 1;
  3114. break;
  3115. default:
  3116. netif_info(tp, probe, tp->netdev,
  3117. "Unknown version 0x%04x\n", version);
  3118. break;
  3119. }
  3120. }
  3121. static void rtl8152_unload(struct r8152 *tp)
  3122. {
  3123. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3124. return;
  3125. if (tp->version != RTL_VER_01)
  3126. r8152_power_cut_en(tp, true);
  3127. }
  3128. static void rtl8153_unload(struct r8152 *tp)
  3129. {
  3130. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3131. return;
  3132. r8153_power_cut_en(tp, false);
  3133. }
  3134. static int rtl_ops_init(struct r8152 *tp)
  3135. {
  3136. struct rtl_ops *ops = &tp->rtl_ops;
  3137. int ret = 0;
  3138. switch (tp->version) {
  3139. case RTL_VER_01:
  3140. case RTL_VER_02:
  3141. ops->init = r8152b_init;
  3142. ops->enable = rtl8152_enable;
  3143. ops->disable = rtl8152_disable;
  3144. ops->up = rtl8152_up;
  3145. ops->down = rtl8152_down;
  3146. ops->unload = rtl8152_unload;
  3147. ops->eee_get = r8152_get_eee;
  3148. ops->eee_set = r8152_set_eee;
  3149. break;
  3150. case RTL_VER_03:
  3151. case RTL_VER_04:
  3152. case RTL_VER_05:
  3153. ops->init = r8153_init;
  3154. ops->enable = rtl8153_enable;
  3155. ops->disable = rtl8153_disable;
  3156. ops->up = rtl8153_up;
  3157. ops->down = rtl8153_down;
  3158. ops->unload = rtl8153_unload;
  3159. ops->eee_get = r8153_get_eee;
  3160. ops->eee_set = r8153_set_eee;
  3161. break;
  3162. default:
  3163. ret = -ENODEV;
  3164. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3165. break;
  3166. }
  3167. return ret;
  3168. }
  3169. static int rtl8152_probe(struct usb_interface *intf,
  3170. const struct usb_device_id *id)
  3171. {
  3172. struct usb_device *udev = interface_to_usbdev(intf);
  3173. struct r8152 *tp;
  3174. struct net_device *netdev;
  3175. int ret;
  3176. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3177. usb_driver_set_configuration(udev, 1);
  3178. return -ENODEV;
  3179. }
  3180. usb_reset_device(udev);
  3181. netdev = alloc_etherdev(sizeof(struct r8152));
  3182. if (!netdev) {
  3183. dev_err(&intf->dev, "Out of memory\n");
  3184. return -ENOMEM;
  3185. }
  3186. SET_NETDEV_DEV(netdev, &intf->dev);
  3187. tp = netdev_priv(netdev);
  3188. tp->msg_enable = 0x7FFF;
  3189. tp->udev = udev;
  3190. tp->netdev = netdev;
  3191. tp->intf = intf;
  3192. r8152b_get_version(tp);
  3193. ret = rtl_ops_init(tp);
  3194. if (ret)
  3195. goto out;
  3196. mutex_init(&tp->control);
  3197. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3198. netdev->netdev_ops = &rtl8152_netdev_ops;
  3199. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3200. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3201. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3202. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3203. NETIF_F_HW_VLAN_CTAG_TX;
  3204. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3205. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3206. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3207. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3208. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3209. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3210. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3211. netdev->ethtool_ops = &ops;
  3212. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3213. tp->mii.dev = netdev;
  3214. tp->mii.mdio_read = read_mii_word;
  3215. tp->mii.mdio_write = write_mii_word;
  3216. tp->mii.phy_id_mask = 0x3f;
  3217. tp->mii.reg_num_mask = 0x1f;
  3218. tp->mii.phy_id = R8152_PHY_ID;
  3219. switch (udev->speed) {
  3220. case USB_SPEED_SUPER:
  3221. tp->coalesce = COALESCE_SUPER;
  3222. break;
  3223. case USB_SPEED_HIGH:
  3224. tp->coalesce = COALESCE_HIGH;
  3225. break;
  3226. default:
  3227. tp->coalesce = COALESCE_SLOW;
  3228. break;
  3229. }
  3230. intf->needs_remote_wakeup = 1;
  3231. tp->rtl_ops.init(tp);
  3232. set_ethernet_addr(tp);
  3233. usb_set_intfdata(intf, tp);
  3234. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3235. ret = register_netdev(netdev);
  3236. if (ret != 0) {
  3237. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3238. goto out1;
  3239. }
  3240. tp->saved_wolopts = __rtl_get_wol(tp);
  3241. if (tp->saved_wolopts)
  3242. device_set_wakeup_enable(&udev->dev, true);
  3243. else
  3244. device_set_wakeup_enable(&udev->dev, false);
  3245. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3246. return 0;
  3247. out1:
  3248. netif_napi_del(&tp->napi);
  3249. usb_set_intfdata(intf, NULL);
  3250. out:
  3251. free_netdev(netdev);
  3252. return ret;
  3253. }
  3254. static void rtl8152_disconnect(struct usb_interface *intf)
  3255. {
  3256. struct r8152 *tp = usb_get_intfdata(intf);
  3257. usb_set_intfdata(intf, NULL);
  3258. if (tp) {
  3259. struct usb_device *udev = tp->udev;
  3260. if (udev->state == USB_STATE_NOTATTACHED)
  3261. set_bit(RTL8152_UNPLUG, &tp->flags);
  3262. netif_napi_del(&tp->napi);
  3263. unregister_netdev(tp->netdev);
  3264. tp->rtl_ops.unload(tp);
  3265. free_netdev(tp->netdev);
  3266. }
  3267. }
  3268. #define REALTEK_USB_DEVICE(vend, prod) \
  3269. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3270. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3271. .idVendor = (vend), \
  3272. .idProduct = (prod), \
  3273. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3274. }, \
  3275. { \
  3276. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3277. USB_DEVICE_ID_MATCH_DEVICE, \
  3278. .idVendor = (vend), \
  3279. .idProduct = (prod), \
  3280. .bInterfaceClass = USB_CLASS_COMM, \
  3281. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3282. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3283. /* table of devices that work with this driver */
  3284. static struct usb_device_id rtl8152_table[] = {
  3285. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3286. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3287. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3288. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3289. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3290. {}
  3291. };
  3292. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3293. static struct usb_driver rtl8152_driver = {
  3294. .name = MODULENAME,
  3295. .id_table = rtl8152_table,
  3296. .probe = rtl8152_probe,
  3297. .disconnect = rtl8152_disconnect,
  3298. .suspend = rtl8152_suspend,
  3299. .resume = rtl8152_resume,
  3300. .reset_resume = rtl8152_resume,
  3301. .supports_autosuspend = 1,
  3302. .disable_hub_initiated_lpm = 1,
  3303. };
  3304. module_usb_driver(rtl8152_driver);
  3305. MODULE_AUTHOR(DRIVER_AUTHOR);
  3306. MODULE_DESCRIPTION(DRIVER_DESC);
  3307. MODULE_LICENSE("GPL");