cnic.c 148 KB

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  1. /* cnic.c: QLogic CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2014 Broadcom Corporation
  4. * Copyright (c) 2014-2015 QLogic Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation.
  9. *
  10. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  11. * Previously modified and maintained by: Michael Chan <mchan@broadcom.com>
  12. * Maintained By: Dept-HSGLinuxNICDev@qlogic.com
  13. */
  14. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/errno.h>
  18. #include <linux/list.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/uio_driver.h>
  24. #include <linux/in.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/delay.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/if_vlan.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/random.h>
  31. #if IS_ENABLED(CONFIG_VLAN_8021Q)
  32. #define BCM_VLAN 1
  33. #endif
  34. #include <net/ip.h>
  35. #include <net/tcp.h>
  36. #include <net/route.h>
  37. #include <net/ipv6.h>
  38. #include <net/ip6_route.h>
  39. #include <net/ip6_checksum.h>
  40. #include <scsi/iscsi_if.h>
  41. #define BCM_CNIC 1
  42. #include "cnic_if.h"
  43. #include "bnx2.h"
  44. #include "bnx2x/bnx2x.h"
  45. #include "bnx2x/bnx2x_reg.h"
  46. #include "bnx2x/bnx2x_fw_defs.h"
  47. #include "bnx2x/bnx2x_hsi.h"
  48. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  49. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  50. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  51. #include "cnic.h"
  52. #include "cnic_defs.h"
  53. #define CNIC_MODULE_NAME "cnic"
  54. static char version[] =
  55. "QLogic " CNIC_MODULE_NAME "Driver v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  56. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  57. "Chen (zongxi@broadcom.com");
  58. MODULE_DESCRIPTION("QLogic cnic Driver");
  59. MODULE_LICENSE("GPL");
  60. MODULE_VERSION(CNIC_MODULE_VERSION);
  61. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  62. static LIST_HEAD(cnic_dev_list);
  63. static LIST_HEAD(cnic_udev_list);
  64. static DEFINE_RWLOCK(cnic_dev_lock);
  65. static DEFINE_MUTEX(cnic_lock);
  66. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  67. /* helper function, assuming cnic_lock is held */
  68. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  69. {
  70. return rcu_dereference_protected(cnic_ulp_tbl[type],
  71. lockdep_is_held(&cnic_lock));
  72. }
  73. static int cnic_service_bnx2(void *, void *);
  74. static int cnic_service_bnx2x(void *, void *);
  75. static int cnic_ctl(void *, struct cnic_ctl_info *);
  76. static struct cnic_ops cnic_bnx2_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct cnic_ops cnic_bnx2x_ops = {
  82. .cnic_owner = THIS_MODULE,
  83. .cnic_handler = cnic_service_bnx2x,
  84. .cnic_ctl = cnic_ctl,
  85. };
  86. static struct workqueue_struct *cnic_wq;
  87. static void cnic_shutdown_rings(struct cnic_dev *);
  88. static void cnic_init_rings(struct cnic_dev *);
  89. static int cnic_cm_set_pg(struct cnic_sock *);
  90. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  91. {
  92. struct cnic_uio_dev *udev = uinfo->priv;
  93. struct cnic_dev *dev;
  94. if (!capable(CAP_NET_ADMIN))
  95. return -EPERM;
  96. if (udev->uio_dev != -1)
  97. return -EBUSY;
  98. rtnl_lock();
  99. dev = udev->dev;
  100. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  101. rtnl_unlock();
  102. return -ENODEV;
  103. }
  104. udev->uio_dev = iminor(inode);
  105. cnic_shutdown_rings(dev);
  106. cnic_init_rings(dev);
  107. rtnl_unlock();
  108. return 0;
  109. }
  110. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  111. {
  112. struct cnic_uio_dev *udev = uinfo->priv;
  113. udev->uio_dev = -1;
  114. return 0;
  115. }
  116. static inline void cnic_hold(struct cnic_dev *dev)
  117. {
  118. atomic_inc(&dev->ref_count);
  119. }
  120. static inline void cnic_put(struct cnic_dev *dev)
  121. {
  122. atomic_dec(&dev->ref_count);
  123. }
  124. static inline void csk_hold(struct cnic_sock *csk)
  125. {
  126. atomic_inc(&csk->ref_count);
  127. }
  128. static inline void csk_put(struct cnic_sock *csk)
  129. {
  130. atomic_dec(&csk->ref_count);
  131. }
  132. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  133. {
  134. struct cnic_dev *cdev;
  135. read_lock(&cnic_dev_lock);
  136. list_for_each_entry(cdev, &cnic_dev_list, list) {
  137. if (netdev == cdev->netdev) {
  138. cnic_hold(cdev);
  139. read_unlock(&cnic_dev_lock);
  140. return cdev;
  141. }
  142. }
  143. read_unlock(&cnic_dev_lock);
  144. return NULL;
  145. }
  146. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_inc(&ulp_ops->ref_count);
  149. }
  150. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  151. {
  152. atomic_dec(&ulp_ops->ref_count);
  153. }
  154. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  155. {
  156. struct cnic_local *cp = dev->cnic_priv;
  157. struct cnic_eth_dev *ethdev = cp->ethdev;
  158. struct drv_ctl_info info;
  159. struct drv_ctl_io *io = &info.data.io;
  160. info.cmd = DRV_CTL_CTX_WR_CMD;
  161. io->cid_addr = cid_addr;
  162. io->offset = off;
  163. io->data = val;
  164. ethdev->drv_ctl(dev->netdev, &info);
  165. }
  166. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  167. {
  168. struct cnic_local *cp = dev->cnic_priv;
  169. struct cnic_eth_dev *ethdev = cp->ethdev;
  170. struct drv_ctl_info info;
  171. struct drv_ctl_io *io = &info.data.io;
  172. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  173. io->offset = off;
  174. io->dma_addr = addr;
  175. ethdev->drv_ctl(dev->netdev, &info);
  176. }
  177. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  178. {
  179. struct cnic_local *cp = dev->cnic_priv;
  180. struct cnic_eth_dev *ethdev = cp->ethdev;
  181. struct drv_ctl_info info;
  182. struct drv_ctl_l2_ring *ring = &info.data.ring;
  183. if (start)
  184. info.cmd = DRV_CTL_START_L2_CMD;
  185. else
  186. info.cmd = DRV_CTL_STOP_L2_CMD;
  187. ring->cid = cid;
  188. ring->client_id = cl_id;
  189. ethdev->drv_ctl(dev->netdev, &info);
  190. }
  191. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  192. {
  193. struct cnic_local *cp = dev->cnic_priv;
  194. struct cnic_eth_dev *ethdev = cp->ethdev;
  195. struct drv_ctl_info info;
  196. struct drv_ctl_io *io = &info.data.io;
  197. info.cmd = DRV_CTL_IO_WR_CMD;
  198. io->offset = off;
  199. io->data = val;
  200. ethdev->drv_ctl(dev->netdev, &info);
  201. }
  202. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  203. {
  204. struct cnic_local *cp = dev->cnic_priv;
  205. struct cnic_eth_dev *ethdev = cp->ethdev;
  206. struct drv_ctl_info info;
  207. struct drv_ctl_io *io = &info.data.io;
  208. info.cmd = DRV_CTL_IO_RD_CMD;
  209. io->offset = off;
  210. ethdev->drv_ctl(dev->netdev, &info);
  211. return io->data;
  212. }
  213. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  214. {
  215. struct cnic_local *cp = dev->cnic_priv;
  216. struct cnic_eth_dev *ethdev = cp->ethdev;
  217. struct drv_ctl_info info;
  218. struct fcoe_capabilities *fcoe_cap =
  219. &info.data.register_data.fcoe_features;
  220. if (reg) {
  221. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  222. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  223. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  224. } else {
  225. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  226. }
  227. info.data.ulp_type = ulp_type;
  228. ethdev->drv_ctl(dev->netdev, &info);
  229. }
  230. static int cnic_in_use(struct cnic_sock *csk)
  231. {
  232. return test_bit(SK_F_INUSE, &csk->flags);
  233. }
  234. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  235. {
  236. struct cnic_local *cp = dev->cnic_priv;
  237. struct cnic_eth_dev *ethdev = cp->ethdev;
  238. struct drv_ctl_info info;
  239. info.cmd = cmd;
  240. info.data.credit.credit_count = count;
  241. ethdev->drv_ctl(dev->netdev, &info);
  242. }
  243. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  244. {
  245. u32 i;
  246. if (!cp->ctx_tbl)
  247. return -EINVAL;
  248. for (i = 0; i < cp->max_cid_space; i++) {
  249. if (cp->ctx_tbl[i].cid == cid) {
  250. *l5_cid = i;
  251. return 0;
  252. }
  253. }
  254. return -EINVAL;
  255. }
  256. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  257. struct cnic_sock *csk)
  258. {
  259. struct iscsi_path path_req;
  260. char *buf = NULL;
  261. u16 len = 0;
  262. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  263. struct cnic_ulp_ops *ulp_ops;
  264. struct cnic_uio_dev *udev = cp->udev;
  265. int rc = 0, retry = 0;
  266. if (!udev || udev->uio_dev == -1)
  267. return -ENODEV;
  268. if (csk) {
  269. len = sizeof(path_req);
  270. buf = (char *) &path_req;
  271. memset(&path_req, 0, len);
  272. msg_type = ISCSI_KEVENT_PATH_REQ;
  273. path_req.handle = (u64) csk->l5_cid;
  274. if (test_bit(SK_F_IPV6, &csk->flags)) {
  275. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  276. sizeof(struct in6_addr));
  277. path_req.ip_addr_len = 16;
  278. } else {
  279. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  280. sizeof(struct in_addr));
  281. path_req.ip_addr_len = 4;
  282. }
  283. path_req.vlan_id = csk->vlan_id;
  284. path_req.pmtu = csk->mtu;
  285. }
  286. while (retry < 3) {
  287. rc = 0;
  288. rcu_read_lock();
  289. ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
  290. if (ulp_ops)
  291. rc = ulp_ops->iscsi_nl_send_msg(
  292. cp->ulp_handle[CNIC_ULP_ISCSI],
  293. msg_type, buf, len);
  294. rcu_read_unlock();
  295. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  296. break;
  297. msleep(100);
  298. retry++;
  299. }
  300. return rc;
  301. }
  302. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  303. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  304. char *buf, u16 len)
  305. {
  306. int rc = -EINVAL;
  307. switch (msg_type) {
  308. case ISCSI_UEVENT_PATH_UPDATE: {
  309. struct cnic_local *cp;
  310. u32 l5_cid;
  311. struct cnic_sock *csk;
  312. struct iscsi_path *path_resp;
  313. if (len < sizeof(*path_resp))
  314. break;
  315. path_resp = (struct iscsi_path *) buf;
  316. cp = dev->cnic_priv;
  317. l5_cid = (u32) path_resp->handle;
  318. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  319. break;
  320. if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
  321. rc = -ENODEV;
  322. break;
  323. }
  324. csk = &cp->csk_tbl[l5_cid];
  325. csk_hold(csk);
  326. if (cnic_in_use(csk) &&
  327. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  328. csk->vlan_id = path_resp->vlan_id;
  329. memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
  330. if (test_bit(SK_F_IPV6, &csk->flags))
  331. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  332. sizeof(struct in6_addr));
  333. else
  334. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  335. sizeof(struct in_addr));
  336. if (is_valid_ether_addr(csk->ha)) {
  337. cnic_cm_set_pg(csk);
  338. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  339. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  340. cnic_cm_upcall(cp, csk,
  341. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  342. clear_bit(SK_F_CONNECT_START, &csk->flags);
  343. }
  344. }
  345. csk_put(csk);
  346. rc = 0;
  347. }
  348. }
  349. return rc;
  350. }
  351. static int cnic_offld_prep(struct cnic_sock *csk)
  352. {
  353. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. return 0;
  355. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  356. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  357. return 0;
  358. }
  359. return 1;
  360. }
  361. static int cnic_close_prep(struct cnic_sock *csk)
  362. {
  363. clear_bit(SK_F_CONNECT_START, &csk->flags);
  364. smp_mb__after_atomic();
  365. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  366. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  367. msleep(1);
  368. return 1;
  369. }
  370. return 0;
  371. }
  372. static int cnic_abort_prep(struct cnic_sock *csk)
  373. {
  374. clear_bit(SK_F_CONNECT_START, &csk->flags);
  375. smp_mb__after_atomic();
  376. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  377. msleep(1);
  378. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  379. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  380. return 1;
  381. }
  382. return 0;
  383. }
  384. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  385. {
  386. struct cnic_dev *dev;
  387. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  388. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  389. return -EINVAL;
  390. }
  391. mutex_lock(&cnic_lock);
  392. if (cnic_ulp_tbl_prot(ulp_type)) {
  393. pr_err("%s: Type %d has already been registered\n",
  394. __func__, ulp_type);
  395. mutex_unlock(&cnic_lock);
  396. return -EBUSY;
  397. }
  398. read_lock(&cnic_dev_lock);
  399. list_for_each_entry(dev, &cnic_dev_list, list) {
  400. struct cnic_local *cp = dev->cnic_priv;
  401. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  402. }
  403. read_unlock(&cnic_dev_lock);
  404. atomic_set(&ulp_ops->ref_count, 0);
  405. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  406. mutex_unlock(&cnic_lock);
  407. /* Prevent race conditions with netdev_event */
  408. rtnl_lock();
  409. list_for_each_entry(dev, &cnic_dev_list, list) {
  410. struct cnic_local *cp = dev->cnic_priv;
  411. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  412. ulp_ops->cnic_init(dev);
  413. }
  414. rtnl_unlock();
  415. return 0;
  416. }
  417. int cnic_unregister_driver(int ulp_type)
  418. {
  419. struct cnic_dev *dev;
  420. struct cnic_ulp_ops *ulp_ops;
  421. int i = 0;
  422. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  423. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  424. return -EINVAL;
  425. }
  426. mutex_lock(&cnic_lock);
  427. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  428. if (!ulp_ops) {
  429. pr_err("%s: Type %d has not been registered\n",
  430. __func__, ulp_type);
  431. goto out_unlock;
  432. }
  433. read_lock(&cnic_dev_lock);
  434. list_for_each_entry(dev, &cnic_dev_list, list) {
  435. struct cnic_local *cp = dev->cnic_priv;
  436. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  437. pr_err("%s: Type %d still has devices registered\n",
  438. __func__, ulp_type);
  439. read_unlock(&cnic_dev_lock);
  440. goto out_unlock;
  441. }
  442. }
  443. read_unlock(&cnic_dev_lock);
  444. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  445. mutex_unlock(&cnic_lock);
  446. synchronize_rcu();
  447. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  448. msleep(100);
  449. i++;
  450. }
  451. if (atomic_read(&ulp_ops->ref_count) != 0)
  452. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  453. __func__);
  454. return 0;
  455. out_unlock:
  456. mutex_unlock(&cnic_lock);
  457. return -EINVAL;
  458. }
  459. static int cnic_start_hw(struct cnic_dev *);
  460. static void cnic_stop_hw(struct cnic_dev *);
  461. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  462. void *ulp_ctx)
  463. {
  464. struct cnic_local *cp = dev->cnic_priv;
  465. struct cnic_ulp_ops *ulp_ops;
  466. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  467. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  468. return -EINVAL;
  469. }
  470. mutex_lock(&cnic_lock);
  471. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  472. pr_err("%s: Driver with type %d has not been registered\n",
  473. __func__, ulp_type);
  474. mutex_unlock(&cnic_lock);
  475. return -EAGAIN;
  476. }
  477. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  478. pr_err("%s: Type %d has already been registered to this device\n",
  479. __func__, ulp_type);
  480. mutex_unlock(&cnic_lock);
  481. return -EBUSY;
  482. }
  483. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  484. cp->ulp_handle[ulp_type] = ulp_ctx;
  485. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  486. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  487. cnic_hold(dev);
  488. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  489. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  490. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  491. mutex_unlock(&cnic_lock);
  492. cnic_ulp_ctl(dev, ulp_type, true);
  493. return 0;
  494. }
  495. EXPORT_SYMBOL(cnic_register_driver);
  496. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  497. {
  498. struct cnic_local *cp = dev->cnic_priv;
  499. int i = 0;
  500. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  501. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  502. return -EINVAL;
  503. }
  504. if (ulp_type == CNIC_ULP_ISCSI)
  505. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  506. mutex_lock(&cnic_lock);
  507. if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
  508. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  509. cnic_put(dev);
  510. } else {
  511. pr_err("%s: device not registered to this ulp type %d\n",
  512. __func__, ulp_type);
  513. mutex_unlock(&cnic_lock);
  514. return -EINVAL;
  515. }
  516. mutex_unlock(&cnic_lock);
  517. if (ulp_type == CNIC_ULP_FCOE)
  518. dev->fcoe_cap = NULL;
  519. synchronize_rcu();
  520. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  521. i < 20) {
  522. msleep(100);
  523. i++;
  524. }
  525. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  526. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  527. cnic_ulp_ctl(dev, ulp_type, false);
  528. return 0;
  529. }
  530. EXPORT_SYMBOL(cnic_unregister_driver);
  531. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  532. u32 next)
  533. {
  534. id_tbl->start = start_id;
  535. id_tbl->max = size;
  536. id_tbl->next = next;
  537. spin_lock_init(&id_tbl->lock);
  538. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  539. if (!id_tbl->table)
  540. return -ENOMEM;
  541. return 0;
  542. }
  543. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  544. {
  545. kfree(id_tbl->table);
  546. id_tbl->table = NULL;
  547. }
  548. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  549. {
  550. int ret = -1;
  551. id -= id_tbl->start;
  552. if (id >= id_tbl->max)
  553. return ret;
  554. spin_lock(&id_tbl->lock);
  555. if (!test_bit(id, id_tbl->table)) {
  556. set_bit(id, id_tbl->table);
  557. ret = 0;
  558. }
  559. spin_unlock(&id_tbl->lock);
  560. return ret;
  561. }
  562. /* Returns -1 if not successful */
  563. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  564. {
  565. u32 id;
  566. spin_lock(&id_tbl->lock);
  567. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  568. if (id >= id_tbl->max) {
  569. id = -1;
  570. if (id_tbl->next != 0) {
  571. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  572. if (id >= id_tbl->next)
  573. id = -1;
  574. }
  575. }
  576. if (id < id_tbl->max) {
  577. set_bit(id, id_tbl->table);
  578. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  579. id += id_tbl->start;
  580. }
  581. spin_unlock(&id_tbl->lock);
  582. return id;
  583. }
  584. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  585. {
  586. if (id == -1)
  587. return;
  588. id -= id_tbl->start;
  589. if (id >= id_tbl->max)
  590. return;
  591. clear_bit(id, id_tbl->table);
  592. }
  593. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  594. {
  595. int i;
  596. if (!dma->pg_arr)
  597. return;
  598. for (i = 0; i < dma->num_pages; i++) {
  599. if (dma->pg_arr[i]) {
  600. dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
  601. dma->pg_arr[i], dma->pg_map_arr[i]);
  602. dma->pg_arr[i] = NULL;
  603. }
  604. }
  605. if (dma->pgtbl) {
  606. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  607. dma->pgtbl, dma->pgtbl_map);
  608. dma->pgtbl = NULL;
  609. }
  610. kfree(dma->pg_arr);
  611. dma->pg_arr = NULL;
  612. dma->num_pages = 0;
  613. }
  614. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  615. {
  616. int i;
  617. __le32 *page_table = (__le32 *) dma->pgtbl;
  618. for (i = 0; i < dma->num_pages; i++) {
  619. /* Each entry needs to be in big endian format. */
  620. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  621. page_table++;
  622. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  623. page_table++;
  624. }
  625. }
  626. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  627. {
  628. int i;
  629. __le32 *page_table = (__le32 *) dma->pgtbl;
  630. for (i = 0; i < dma->num_pages; i++) {
  631. /* Each entry needs to be in little endian format. */
  632. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  633. page_table++;
  634. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  635. page_table++;
  636. }
  637. }
  638. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  639. int pages, int use_pg_tbl)
  640. {
  641. int i, size;
  642. struct cnic_local *cp = dev->cnic_priv;
  643. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  644. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  645. if (dma->pg_arr == NULL)
  646. return -ENOMEM;
  647. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  648. dma->num_pages = pages;
  649. for (i = 0; i < pages; i++) {
  650. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  651. CNIC_PAGE_SIZE,
  652. &dma->pg_map_arr[i],
  653. GFP_ATOMIC);
  654. if (dma->pg_arr[i] == NULL)
  655. goto error;
  656. }
  657. if (!use_pg_tbl)
  658. return 0;
  659. dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
  660. ~(CNIC_PAGE_SIZE - 1);
  661. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  662. &dma->pgtbl_map, GFP_ATOMIC);
  663. if (dma->pgtbl == NULL)
  664. goto error;
  665. cp->setup_pgtbl(dev, dma);
  666. return 0;
  667. error:
  668. cnic_free_dma(dev, dma);
  669. return -ENOMEM;
  670. }
  671. static void cnic_free_context(struct cnic_dev *dev)
  672. {
  673. struct cnic_local *cp = dev->cnic_priv;
  674. int i;
  675. for (i = 0; i < cp->ctx_blks; i++) {
  676. if (cp->ctx_arr[i].ctx) {
  677. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  678. cp->ctx_arr[i].ctx,
  679. cp->ctx_arr[i].mapping);
  680. cp->ctx_arr[i].ctx = NULL;
  681. }
  682. }
  683. }
  684. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  685. {
  686. if (udev->l2_buf) {
  687. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  688. udev->l2_buf, udev->l2_buf_map);
  689. udev->l2_buf = NULL;
  690. }
  691. if (udev->l2_ring) {
  692. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  693. udev->l2_ring, udev->l2_ring_map);
  694. udev->l2_ring = NULL;
  695. }
  696. }
  697. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  698. {
  699. uio_unregister_device(&udev->cnic_uinfo);
  700. __cnic_free_uio_rings(udev);
  701. pci_dev_put(udev->pdev);
  702. kfree(udev);
  703. }
  704. static void cnic_free_uio(struct cnic_uio_dev *udev)
  705. {
  706. if (!udev)
  707. return;
  708. write_lock(&cnic_dev_lock);
  709. list_del_init(&udev->list);
  710. write_unlock(&cnic_dev_lock);
  711. __cnic_free_uio(udev);
  712. }
  713. static void cnic_free_resc(struct cnic_dev *dev)
  714. {
  715. struct cnic_local *cp = dev->cnic_priv;
  716. struct cnic_uio_dev *udev = cp->udev;
  717. if (udev) {
  718. udev->dev = NULL;
  719. cp->udev = NULL;
  720. if (udev->uio_dev == -1)
  721. __cnic_free_uio_rings(udev);
  722. }
  723. cnic_free_context(dev);
  724. kfree(cp->ctx_arr);
  725. cp->ctx_arr = NULL;
  726. cp->ctx_blks = 0;
  727. cnic_free_dma(dev, &cp->gbl_buf_info);
  728. cnic_free_dma(dev, &cp->kwq_info);
  729. cnic_free_dma(dev, &cp->kwq_16_data_info);
  730. cnic_free_dma(dev, &cp->kcq2.dma);
  731. cnic_free_dma(dev, &cp->kcq1.dma);
  732. kfree(cp->iscsi_tbl);
  733. cp->iscsi_tbl = NULL;
  734. kfree(cp->ctx_tbl);
  735. cp->ctx_tbl = NULL;
  736. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  737. cnic_free_id_tbl(&cp->cid_tbl);
  738. }
  739. static int cnic_alloc_context(struct cnic_dev *dev)
  740. {
  741. struct cnic_local *cp = dev->cnic_priv;
  742. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  743. int i, k, arr_size;
  744. cp->ctx_blk_size = CNIC_PAGE_SIZE;
  745. cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
  746. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  747. sizeof(struct cnic_ctx);
  748. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  749. if (cp->ctx_arr == NULL)
  750. return -ENOMEM;
  751. k = 0;
  752. for (i = 0; i < 2; i++) {
  753. u32 j, reg, off, lo, hi;
  754. if (i == 0)
  755. off = BNX2_PG_CTX_MAP;
  756. else
  757. off = BNX2_ISCSI_CTX_MAP;
  758. reg = cnic_reg_rd_ind(dev, off);
  759. lo = reg >> 16;
  760. hi = reg & 0xffff;
  761. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  762. cp->ctx_arr[k].cid = j;
  763. }
  764. cp->ctx_blks = k;
  765. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  766. cp->ctx_blks = 0;
  767. return -ENOMEM;
  768. }
  769. for (i = 0; i < cp->ctx_blks; i++) {
  770. cp->ctx_arr[i].ctx =
  771. dma_alloc_coherent(&dev->pcidev->dev,
  772. CNIC_PAGE_SIZE,
  773. &cp->ctx_arr[i].mapping,
  774. GFP_KERNEL);
  775. if (cp->ctx_arr[i].ctx == NULL)
  776. return -ENOMEM;
  777. }
  778. }
  779. return 0;
  780. }
  781. static u16 cnic_bnx2_next_idx(u16 idx)
  782. {
  783. return idx + 1;
  784. }
  785. static u16 cnic_bnx2_hw_idx(u16 idx)
  786. {
  787. return idx;
  788. }
  789. static u16 cnic_bnx2x_next_idx(u16 idx)
  790. {
  791. idx++;
  792. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  793. idx++;
  794. return idx;
  795. }
  796. static u16 cnic_bnx2x_hw_idx(u16 idx)
  797. {
  798. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  799. idx++;
  800. return idx;
  801. }
  802. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  803. bool use_pg_tbl)
  804. {
  805. int err, i, use_page_tbl = 0;
  806. struct kcqe **kcq;
  807. if (use_pg_tbl)
  808. use_page_tbl = 1;
  809. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  810. if (err)
  811. return err;
  812. kcq = (struct kcqe **) info->dma.pg_arr;
  813. info->kcq = kcq;
  814. info->next_idx = cnic_bnx2_next_idx;
  815. info->hw_idx = cnic_bnx2_hw_idx;
  816. if (use_pg_tbl)
  817. return 0;
  818. info->next_idx = cnic_bnx2x_next_idx;
  819. info->hw_idx = cnic_bnx2x_hw_idx;
  820. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  821. struct bnx2x_bd_chain_next *next =
  822. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  823. int j = i + 1;
  824. if (j >= KCQ_PAGE_CNT)
  825. j = 0;
  826. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  827. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  828. }
  829. return 0;
  830. }
  831. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  832. {
  833. struct cnic_local *cp = udev->dev->cnic_priv;
  834. if (udev->l2_ring)
  835. return 0;
  836. udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
  837. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  838. &udev->l2_ring_map,
  839. GFP_KERNEL | __GFP_COMP);
  840. if (!udev->l2_ring)
  841. return -ENOMEM;
  842. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  843. udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
  844. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  845. &udev->l2_buf_map,
  846. GFP_KERNEL | __GFP_COMP);
  847. if (!udev->l2_buf) {
  848. __cnic_free_uio_rings(udev);
  849. return -ENOMEM;
  850. }
  851. return 0;
  852. }
  853. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  854. {
  855. struct cnic_local *cp = dev->cnic_priv;
  856. struct cnic_uio_dev *udev;
  857. list_for_each_entry(udev, &cnic_udev_list, list) {
  858. if (udev->pdev == dev->pcidev) {
  859. udev->dev = dev;
  860. if (__cnic_alloc_uio_rings(udev, pages)) {
  861. udev->dev = NULL;
  862. return -ENOMEM;
  863. }
  864. cp->udev = udev;
  865. return 0;
  866. }
  867. }
  868. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  869. if (!udev)
  870. return -ENOMEM;
  871. udev->uio_dev = -1;
  872. udev->dev = dev;
  873. udev->pdev = dev->pcidev;
  874. if (__cnic_alloc_uio_rings(udev, pages))
  875. goto err_udev;
  876. list_add(&udev->list, &cnic_udev_list);
  877. pci_dev_get(udev->pdev);
  878. cp->udev = udev;
  879. return 0;
  880. err_udev:
  881. kfree(udev);
  882. return -ENOMEM;
  883. }
  884. static int cnic_init_uio(struct cnic_dev *dev)
  885. {
  886. struct cnic_local *cp = dev->cnic_priv;
  887. struct cnic_uio_dev *udev = cp->udev;
  888. struct uio_info *uinfo;
  889. int ret = 0;
  890. if (!udev)
  891. return -ENOMEM;
  892. uinfo = &udev->cnic_uinfo;
  893. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  894. uinfo->mem[0].internal_addr = dev->regview;
  895. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  896. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  897. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  898. TX_MAX_TSS_RINGS + 1);
  899. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  900. CNIC_PAGE_MASK;
  901. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  902. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  903. else
  904. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  905. uinfo->name = "bnx2_cnic";
  906. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  907. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  908. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  909. CNIC_PAGE_MASK;
  910. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  911. uinfo->name = "bnx2x_cnic";
  912. }
  913. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  914. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  915. uinfo->mem[2].size = udev->l2_ring_size;
  916. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  917. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  918. uinfo->mem[3].size = udev->l2_buf_size;
  919. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  920. uinfo->version = CNIC_MODULE_VERSION;
  921. uinfo->irq = UIO_IRQ_CUSTOM;
  922. uinfo->open = cnic_uio_open;
  923. uinfo->release = cnic_uio_close;
  924. if (udev->uio_dev == -1) {
  925. if (!uinfo->priv) {
  926. uinfo->priv = udev;
  927. ret = uio_register_device(&udev->pdev->dev, uinfo);
  928. }
  929. } else {
  930. cnic_init_rings(dev);
  931. }
  932. return ret;
  933. }
  934. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  935. {
  936. struct cnic_local *cp = dev->cnic_priv;
  937. int ret;
  938. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  939. if (ret)
  940. goto error;
  941. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  942. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  943. if (ret)
  944. goto error;
  945. ret = cnic_alloc_context(dev);
  946. if (ret)
  947. goto error;
  948. ret = cnic_alloc_uio_rings(dev, 2);
  949. if (ret)
  950. goto error;
  951. ret = cnic_init_uio(dev);
  952. if (ret)
  953. goto error;
  954. return 0;
  955. error:
  956. cnic_free_resc(dev);
  957. return ret;
  958. }
  959. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  960. {
  961. struct cnic_local *cp = dev->cnic_priv;
  962. struct bnx2x *bp = netdev_priv(dev->netdev);
  963. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  964. int total_mem, blks, i;
  965. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  966. blks = total_mem / ctx_blk_size;
  967. if (total_mem % ctx_blk_size)
  968. blks++;
  969. if (blks > cp->ethdev->ctx_tbl_len)
  970. return -ENOMEM;
  971. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  972. if (cp->ctx_arr == NULL)
  973. return -ENOMEM;
  974. cp->ctx_blks = blks;
  975. cp->ctx_blk_size = ctx_blk_size;
  976. if (!CHIP_IS_E1(bp))
  977. cp->ctx_align = 0;
  978. else
  979. cp->ctx_align = ctx_blk_size;
  980. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  981. for (i = 0; i < blks; i++) {
  982. cp->ctx_arr[i].ctx =
  983. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  984. &cp->ctx_arr[i].mapping,
  985. GFP_KERNEL);
  986. if (cp->ctx_arr[i].ctx == NULL)
  987. return -ENOMEM;
  988. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  989. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  990. cnic_free_context(dev);
  991. cp->ctx_blk_size += cp->ctx_align;
  992. i = -1;
  993. continue;
  994. }
  995. }
  996. }
  997. return 0;
  998. }
  999. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1000. {
  1001. struct cnic_local *cp = dev->cnic_priv;
  1002. struct bnx2x *bp = netdev_priv(dev->netdev);
  1003. struct cnic_eth_dev *ethdev = cp->ethdev;
  1004. u32 start_cid = ethdev->starting_cid;
  1005. int i, j, n, ret, pages;
  1006. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1007. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1008. cp->iscsi_start_cid = start_cid;
  1009. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1010. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  1011. cp->max_cid_space += dev->max_fcoe_conn;
  1012. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1013. if (!cp->fcoe_init_cid)
  1014. cp->fcoe_init_cid = 0x10;
  1015. }
  1016. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1017. GFP_KERNEL);
  1018. if (!cp->iscsi_tbl)
  1019. goto error;
  1020. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1021. cp->max_cid_space, GFP_KERNEL);
  1022. if (!cp->ctx_tbl)
  1023. goto error;
  1024. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1025. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1026. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1027. }
  1028. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1029. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1030. pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1031. CNIC_PAGE_SIZE;
  1032. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1033. if (ret)
  1034. return -ENOMEM;
  1035. n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1036. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1037. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1038. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1039. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1040. off;
  1041. if ((i % n) == (n - 1))
  1042. j++;
  1043. }
  1044. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1045. if (ret)
  1046. goto error;
  1047. if (CNIC_SUPPORTS_FCOE(bp)) {
  1048. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1049. if (ret)
  1050. goto error;
  1051. }
  1052. pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
  1053. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1054. if (ret)
  1055. goto error;
  1056. ret = cnic_alloc_bnx2x_context(dev);
  1057. if (ret)
  1058. goto error;
  1059. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1060. return 0;
  1061. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1062. cp->l2_rx_ring_size = 15;
  1063. ret = cnic_alloc_uio_rings(dev, 4);
  1064. if (ret)
  1065. goto error;
  1066. ret = cnic_init_uio(dev);
  1067. if (ret)
  1068. goto error;
  1069. return 0;
  1070. error:
  1071. cnic_free_resc(dev);
  1072. return -ENOMEM;
  1073. }
  1074. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1075. {
  1076. return cp->max_kwq_idx -
  1077. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1078. }
  1079. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1080. u32 num_wqes)
  1081. {
  1082. struct cnic_local *cp = dev->cnic_priv;
  1083. struct kwqe *prod_qe;
  1084. u16 prod, sw_prod, i;
  1085. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1086. return -EAGAIN; /* bnx2 is down */
  1087. spin_lock_bh(&cp->cnic_ulp_lock);
  1088. if (num_wqes > cnic_kwq_avail(cp) &&
  1089. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1090. spin_unlock_bh(&cp->cnic_ulp_lock);
  1091. return -EAGAIN;
  1092. }
  1093. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1094. prod = cp->kwq_prod_idx;
  1095. sw_prod = prod & MAX_KWQ_IDX;
  1096. for (i = 0; i < num_wqes; i++) {
  1097. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1098. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1099. prod++;
  1100. sw_prod = prod & MAX_KWQ_IDX;
  1101. }
  1102. cp->kwq_prod_idx = prod;
  1103. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1104. spin_unlock_bh(&cp->cnic_ulp_lock);
  1105. return 0;
  1106. }
  1107. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1108. union l5cm_specific_data *l5_data)
  1109. {
  1110. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1111. dma_addr_t map;
  1112. map = ctx->kwqe_data_mapping;
  1113. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1114. l5_data->phy_address.hi = (u64) map >> 32;
  1115. return ctx->kwqe_data;
  1116. }
  1117. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1118. u32 type, union l5cm_specific_data *l5_data)
  1119. {
  1120. struct cnic_local *cp = dev->cnic_priv;
  1121. struct bnx2x *bp = netdev_priv(dev->netdev);
  1122. struct l5cm_spe kwqe;
  1123. struct kwqe_16 *kwq[1];
  1124. u16 type_16;
  1125. int ret;
  1126. kwqe.hdr.conn_and_cmd_data =
  1127. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1128. BNX2X_HW_CID(bp, cid)));
  1129. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1130. type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1131. SPE_HDR_FUNCTION_ID;
  1132. kwqe.hdr.type = cpu_to_le16(type_16);
  1133. kwqe.hdr.reserved1 = 0;
  1134. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1135. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1136. kwq[0] = (struct kwqe_16 *) &kwqe;
  1137. spin_lock_bh(&cp->cnic_ulp_lock);
  1138. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1139. spin_unlock_bh(&cp->cnic_ulp_lock);
  1140. if (ret == 1)
  1141. return 0;
  1142. return ret;
  1143. }
  1144. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1145. struct kcqe *cqes[], u32 num_cqes)
  1146. {
  1147. struct cnic_local *cp = dev->cnic_priv;
  1148. struct cnic_ulp_ops *ulp_ops;
  1149. rcu_read_lock();
  1150. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1151. if (likely(ulp_ops)) {
  1152. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1153. cqes, num_cqes);
  1154. }
  1155. rcu_read_unlock();
  1156. }
  1157. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1158. int en_tcp_dack)
  1159. {
  1160. struct bnx2x *bp = netdev_priv(dev->netdev);
  1161. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1162. u16 tstorm_flags = 0;
  1163. if (time_stamps) {
  1164. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1165. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1166. }
  1167. if (en_tcp_dack)
  1168. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1169. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1170. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
  1171. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1172. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
  1173. }
  1174. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1175. {
  1176. struct cnic_local *cp = dev->cnic_priv;
  1177. struct bnx2x *bp = netdev_priv(dev->netdev);
  1178. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1179. int hq_bds, pages;
  1180. u32 pfid = bp->pfid;
  1181. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1182. cp->num_ccells = req1->num_ccells_per_conn;
  1183. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1184. cp->num_iscsi_tasks;
  1185. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1186. BNX2X_ISCSI_R2TQE_SIZE;
  1187. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1188. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1189. hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1190. cp->num_cqs = req1->num_cqs;
  1191. if (!dev->max_iscsi_conn)
  1192. return 0;
  1193. /* init Tstorm RAM */
  1194. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1195. req1->rq_num_wqes);
  1196. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1197. CNIC_PAGE_SIZE);
  1198. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1199. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1200. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1201. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1202. req1->num_tasks_per_conn);
  1203. /* init Ustorm RAM */
  1204. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1205. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1206. req1->rq_buffer_size);
  1207. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1208. CNIC_PAGE_SIZE);
  1209. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1210. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1211. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1212. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1213. req1->num_tasks_per_conn);
  1214. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1215. req1->rq_num_wqes);
  1216. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1217. req1->cq_num_wqes);
  1218. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1219. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1220. /* init Xstorm RAM */
  1221. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1222. CNIC_PAGE_SIZE);
  1223. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1224. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1225. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1226. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1227. req1->num_tasks_per_conn);
  1228. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1229. hq_bds);
  1230. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1231. req1->num_tasks_per_conn);
  1232. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1233. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1234. /* init Cstorm RAM */
  1235. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1236. CNIC_PAGE_SIZE);
  1237. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1238. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
  1239. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1240. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1241. req1->num_tasks_per_conn);
  1242. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1243. req1->cq_num_wqes);
  1244. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1245. hq_bds);
  1246. cnic_bnx2x_set_tcp_options(dev,
  1247. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1248. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1249. return 0;
  1250. }
  1251. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1252. {
  1253. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1254. struct bnx2x *bp = netdev_priv(dev->netdev);
  1255. u32 pfid = bp->pfid;
  1256. struct iscsi_kcqe kcqe;
  1257. struct kcqe *cqes[1];
  1258. memset(&kcqe, 0, sizeof(kcqe));
  1259. if (!dev->max_iscsi_conn) {
  1260. kcqe.completion_status =
  1261. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1262. goto done;
  1263. }
  1264. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1265. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1266. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1267. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1268. req2->error_bit_map[1]);
  1269. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1270. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1271. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1272. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1273. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1274. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1275. req2->error_bit_map[1]);
  1276. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1277. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1278. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1279. done:
  1280. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1281. cqes[0] = (struct kcqe *) &kcqe;
  1282. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1283. return 0;
  1284. }
  1285. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1286. {
  1287. struct cnic_local *cp = dev->cnic_priv;
  1288. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1289. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1290. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1291. cnic_free_dma(dev, &iscsi->hq_info);
  1292. cnic_free_dma(dev, &iscsi->r2tq_info);
  1293. cnic_free_dma(dev, &iscsi->task_array_info);
  1294. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1295. } else {
  1296. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1297. }
  1298. ctx->cid = 0;
  1299. }
  1300. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1301. {
  1302. u32 cid;
  1303. int ret, pages;
  1304. struct cnic_local *cp = dev->cnic_priv;
  1305. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1306. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1307. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1308. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1309. if (cid == -1) {
  1310. ret = -ENOMEM;
  1311. goto error;
  1312. }
  1313. ctx->cid = cid;
  1314. return 0;
  1315. }
  1316. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1317. if (cid == -1) {
  1318. ret = -ENOMEM;
  1319. goto error;
  1320. }
  1321. ctx->cid = cid;
  1322. pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
  1323. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1324. if (ret)
  1325. goto error;
  1326. pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
  1327. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1328. if (ret)
  1329. goto error;
  1330. pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
  1331. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1332. if (ret)
  1333. goto error;
  1334. return 0;
  1335. error:
  1336. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1337. return ret;
  1338. }
  1339. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1340. struct regpair *ctx_addr)
  1341. {
  1342. struct cnic_local *cp = dev->cnic_priv;
  1343. struct cnic_eth_dev *ethdev = cp->ethdev;
  1344. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1345. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1346. unsigned long align_off = 0;
  1347. dma_addr_t ctx_map;
  1348. void *ctx;
  1349. if (cp->ctx_align) {
  1350. unsigned long mask = cp->ctx_align - 1;
  1351. if (cp->ctx_arr[blk].mapping & mask)
  1352. align_off = cp->ctx_align -
  1353. (cp->ctx_arr[blk].mapping & mask);
  1354. }
  1355. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1356. (off * BNX2X_CONTEXT_MEM_SIZE);
  1357. ctx = cp->ctx_arr[blk].ctx + align_off +
  1358. (off * BNX2X_CONTEXT_MEM_SIZE);
  1359. if (init)
  1360. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1361. ctx_addr->lo = ctx_map & 0xffffffff;
  1362. ctx_addr->hi = (u64) ctx_map >> 32;
  1363. return ctx;
  1364. }
  1365. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1366. u32 num)
  1367. {
  1368. struct cnic_local *cp = dev->cnic_priv;
  1369. struct bnx2x *bp = netdev_priv(dev->netdev);
  1370. struct iscsi_kwqe_conn_offload1 *req1 =
  1371. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1372. struct iscsi_kwqe_conn_offload2 *req2 =
  1373. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1374. struct iscsi_kwqe_conn_offload3 *req3;
  1375. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1376. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1377. u32 cid = ctx->cid;
  1378. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1379. struct iscsi_context *ictx;
  1380. struct regpair context_addr;
  1381. int i, j, n = 2, n_max;
  1382. u8 port = BP_PORT(bp);
  1383. ctx->ctx_flags = 0;
  1384. if (!req2->num_additional_wqes)
  1385. return -EINVAL;
  1386. n_max = req2->num_additional_wqes + 2;
  1387. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1388. if (ictx == NULL)
  1389. return -ENOMEM;
  1390. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1391. ictx->xstorm_ag_context.hq_prod = 1;
  1392. ictx->xstorm_st_context.iscsi.first_burst_length =
  1393. ISCSI_DEF_FIRST_BURST_LEN;
  1394. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1395. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1396. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1397. req1->sq_page_table_addr_lo;
  1398. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1399. req1->sq_page_table_addr_hi;
  1400. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1401. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1402. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1403. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1404. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1405. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1406. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1407. iscsi->hq_info.pgtbl[0];
  1408. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1409. iscsi->hq_info.pgtbl[1];
  1410. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1411. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1412. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1413. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1414. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1415. iscsi->r2tq_info.pgtbl[0];
  1416. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1417. iscsi->r2tq_info.pgtbl[1];
  1418. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1419. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1420. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1421. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1422. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1423. BNX2X_ISCSI_PBL_NOT_CACHED;
  1424. ictx->xstorm_st_context.iscsi.flags.flags |=
  1425. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1426. ictx->xstorm_st_context.iscsi.flags.flags |=
  1427. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1428. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1429. ETH_P_8021Q;
  1430. if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
  1431. bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
  1432. port = 0;
  1433. }
  1434. ictx->xstorm_st_context.common.flags =
  1435. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1436. ictx->xstorm_st_context.common.flags =
  1437. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1438. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1439. /* TSTORM requires the base address of RQ DB & not PTE */
  1440. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1441. req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
  1442. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1443. req2->rq_page_table_addr_hi;
  1444. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1445. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1446. ictx->tstorm_st_context.tcp.flags2 |=
  1447. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1448. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1449. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1450. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1451. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1452. req2->rq_page_table_addr_lo;
  1453. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1454. req2->rq_page_table_addr_hi;
  1455. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1456. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1457. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1458. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1459. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1460. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1461. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1462. iscsi->r2tq_info.pgtbl[0];
  1463. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1464. iscsi->r2tq_info.pgtbl[1];
  1465. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1466. req1->cq_page_table_addr_lo;
  1467. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1468. req1->cq_page_table_addr_hi;
  1469. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1470. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1471. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1472. ictx->ustorm_st_context.task_pbe_cache_index =
  1473. BNX2X_ISCSI_PBL_NOT_CACHED;
  1474. ictx->ustorm_st_context.task_pdu_cache_index =
  1475. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1476. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1477. if (j == 3) {
  1478. if (n >= n_max)
  1479. break;
  1480. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1481. j = 0;
  1482. }
  1483. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1484. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1485. req3->qp_first_pte[j].hi;
  1486. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1487. req3->qp_first_pte[j].lo;
  1488. }
  1489. ictx->ustorm_st_context.task_pbl_base.lo =
  1490. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1491. ictx->ustorm_st_context.task_pbl_base.hi =
  1492. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1493. ictx->ustorm_st_context.tce_phy_addr.lo =
  1494. iscsi->task_array_info.pgtbl[0];
  1495. ictx->ustorm_st_context.tce_phy_addr.hi =
  1496. iscsi->task_array_info.pgtbl[1];
  1497. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1498. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1499. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1500. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1501. ISCSI_DEF_MAX_BURST_LEN;
  1502. ictx->ustorm_st_context.negotiated_rx |=
  1503. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1504. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1505. ictx->cstorm_st_context.hq_pbl_base.lo =
  1506. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1507. ictx->cstorm_st_context.hq_pbl_base.hi =
  1508. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1509. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1510. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1511. ictx->cstorm_st_context.task_pbl_base.lo =
  1512. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1513. ictx->cstorm_st_context.task_pbl_base.hi =
  1514. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1515. /* CSTORM and USTORM initialization is different, CSTORM requires
  1516. * CQ DB base & not PTE addr */
  1517. ictx->cstorm_st_context.cq_db_base.lo =
  1518. req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
  1519. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1520. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1521. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1522. for (i = 0; i < cp->num_cqs; i++) {
  1523. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1524. ISCSI_INITIAL_SN;
  1525. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1526. ISCSI_INITIAL_SN;
  1527. }
  1528. ictx->xstorm_ag_context.cdu_reserved =
  1529. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1530. ISCSI_CONNECTION_TYPE);
  1531. ictx->ustorm_ag_context.cdu_usage =
  1532. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1533. ISCSI_CONNECTION_TYPE);
  1534. return 0;
  1535. }
  1536. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1537. u32 num, int *work)
  1538. {
  1539. struct iscsi_kwqe_conn_offload1 *req1;
  1540. struct iscsi_kwqe_conn_offload2 *req2;
  1541. struct cnic_local *cp = dev->cnic_priv;
  1542. struct bnx2x *bp = netdev_priv(dev->netdev);
  1543. struct cnic_context *ctx;
  1544. struct iscsi_kcqe kcqe;
  1545. struct kcqe *cqes[1];
  1546. u32 l5_cid;
  1547. int ret = 0;
  1548. if (num < 2) {
  1549. *work = num;
  1550. return -EINVAL;
  1551. }
  1552. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1553. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1554. if ((num - 2) < req2->num_additional_wqes) {
  1555. *work = num;
  1556. return -EINVAL;
  1557. }
  1558. *work = 2 + req2->num_additional_wqes;
  1559. l5_cid = req1->iscsi_conn_id;
  1560. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1561. return -EINVAL;
  1562. memset(&kcqe, 0, sizeof(kcqe));
  1563. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1564. kcqe.iscsi_conn_id = l5_cid;
  1565. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1566. ctx = &cp->ctx_tbl[l5_cid];
  1567. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1568. kcqe.completion_status =
  1569. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1570. goto done;
  1571. }
  1572. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1573. atomic_dec(&cp->iscsi_conn);
  1574. goto done;
  1575. }
  1576. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1577. if (ret) {
  1578. atomic_dec(&cp->iscsi_conn);
  1579. ret = 0;
  1580. goto done;
  1581. }
  1582. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1583. if (ret < 0) {
  1584. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1585. atomic_dec(&cp->iscsi_conn);
  1586. goto done;
  1587. }
  1588. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1589. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
  1590. done:
  1591. cqes[0] = (struct kcqe *) &kcqe;
  1592. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1593. return 0;
  1594. }
  1595. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1596. {
  1597. struct cnic_local *cp = dev->cnic_priv;
  1598. struct iscsi_kwqe_conn_update *req =
  1599. (struct iscsi_kwqe_conn_update *) kwqe;
  1600. void *data;
  1601. union l5cm_specific_data l5_data;
  1602. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1603. int ret;
  1604. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1605. return -EINVAL;
  1606. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1607. if (!data)
  1608. return -ENOMEM;
  1609. memcpy(data, kwqe, sizeof(struct kwqe));
  1610. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1611. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1612. return ret;
  1613. }
  1614. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1615. {
  1616. struct cnic_local *cp = dev->cnic_priv;
  1617. struct bnx2x *bp = netdev_priv(dev->netdev);
  1618. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1619. union l5cm_specific_data l5_data;
  1620. int ret;
  1621. u32 hw_cid;
  1622. init_waitqueue_head(&ctx->waitq);
  1623. ctx->wait_cond = 0;
  1624. memset(&l5_data, 0, sizeof(l5_data));
  1625. hw_cid = BNX2X_HW_CID(bp, ctx->cid);
  1626. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1627. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1628. if (ret == 0) {
  1629. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1630. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1631. return -EBUSY;
  1632. }
  1633. return 0;
  1634. }
  1635. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1636. {
  1637. struct cnic_local *cp = dev->cnic_priv;
  1638. struct iscsi_kwqe_conn_destroy *req =
  1639. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1640. u32 l5_cid = req->reserved0;
  1641. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1642. int ret = 0;
  1643. struct iscsi_kcqe kcqe;
  1644. struct kcqe *cqes[1];
  1645. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1646. goto skip_cfc_delete;
  1647. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1648. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1649. if (delta > (2 * HZ))
  1650. delta = 0;
  1651. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1652. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1653. goto destroy_reply;
  1654. }
  1655. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1656. skip_cfc_delete:
  1657. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1658. if (!ret) {
  1659. atomic_dec(&cp->iscsi_conn);
  1660. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1661. }
  1662. destroy_reply:
  1663. memset(&kcqe, 0, sizeof(kcqe));
  1664. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1665. kcqe.iscsi_conn_id = l5_cid;
  1666. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1667. kcqe.iscsi_conn_context_id = req->context_id;
  1668. cqes[0] = (struct kcqe *) &kcqe;
  1669. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1670. return 0;
  1671. }
  1672. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1673. struct l4_kwq_connect_req1 *kwqe1,
  1674. struct l4_kwq_connect_req3 *kwqe3,
  1675. struct l5cm_active_conn_buffer *conn_buf)
  1676. {
  1677. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1678. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1679. &conn_buf->xstorm_conn_buffer;
  1680. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1681. &conn_buf->tstorm_conn_buffer;
  1682. struct regpair context_addr;
  1683. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1684. struct in6_addr src_ip, dst_ip;
  1685. int i;
  1686. u32 *addrp;
  1687. addrp = (u32 *) &conn_addr->local_ip_addr;
  1688. for (i = 0; i < 4; i++, addrp++)
  1689. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1690. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1691. for (i = 0; i < 4; i++, addrp++)
  1692. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1693. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1694. xstorm_buf->context_addr.hi = context_addr.hi;
  1695. xstorm_buf->context_addr.lo = context_addr.lo;
  1696. xstorm_buf->mss = 0xffff;
  1697. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1698. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1699. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1700. xstorm_buf->pseudo_header_checksum =
  1701. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1702. if (kwqe3->ka_timeout) {
  1703. tstorm_buf->ka_enable = 1;
  1704. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1705. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1706. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1707. }
  1708. tstorm_buf->max_rt_time = 0xffffffff;
  1709. }
  1710. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1711. {
  1712. struct bnx2x *bp = netdev_priv(dev->netdev);
  1713. u32 pfid = bp->pfid;
  1714. u8 *mac = dev->mac_addr;
  1715. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1716. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1717. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1718. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1719. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1720. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1721. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1722. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1723. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1724. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1725. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1726. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1727. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1728. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1729. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1730. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1731. mac[4]);
  1732. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1733. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1734. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1735. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1736. mac[2]);
  1737. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1738. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1739. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1740. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1741. mac[0]);
  1742. }
  1743. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1744. u32 num, int *work)
  1745. {
  1746. struct cnic_local *cp = dev->cnic_priv;
  1747. struct bnx2x *bp = netdev_priv(dev->netdev);
  1748. struct l4_kwq_connect_req1 *kwqe1 =
  1749. (struct l4_kwq_connect_req1 *) wqes[0];
  1750. struct l4_kwq_connect_req3 *kwqe3;
  1751. struct l5cm_active_conn_buffer *conn_buf;
  1752. struct l5cm_conn_addr_params *conn_addr;
  1753. union l5cm_specific_data l5_data;
  1754. u32 l5_cid = kwqe1->pg_cid;
  1755. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1756. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1757. int ret;
  1758. if (num < 2) {
  1759. *work = num;
  1760. return -EINVAL;
  1761. }
  1762. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1763. *work = 3;
  1764. else
  1765. *work = 2;
  1766. if (num < *work) {
  1767. *work = num;
  1768. return -EINVAL;
  1769. }
  1770. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1771. netdev_err(dev->netdev, "conn_buf size too big\n");
  1772. return -ENOMEM;
  1773. }
  1774. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1775. if (!conn_buf)
  1776. return -ENOMEM;
  1777. memset(conn_buf, 0, sizeof(*conn_buf));
  1778. conn_addr = &conn_buf->conn_addr_buf;
  1779. conn_addr->remote_addr_0 = csk->ha[0];
  1780. conn_addr->remote_addr_1 = csk->ha[1];
  1781. conn_addr->remote_addr_2 = csk->ha[2];
  1782. conn_addr->remote_addr_3 = csk->ha[3];
  1783. conn_addr->remote_addr_4 = csk->ha[4];
  1784. conn_addr->remote_addr_5 = csk->ha[5];
  1785. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1786. struct l4_kwq_connect_req2 *kwqe2 =
  1787. (struct l4_kwq_connect_req2 *) wqes[1];
  1788. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1789. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1790. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1791. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1792. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1793. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1794. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1795. }
  1796. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1797. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1798. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1799. conn_addr->local_tcp_port = kwqe1->src_port;
  1800. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1801. conn_addr->pmtu = kwqe3->pmtu;
  1802. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1803. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1804. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
  1805. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1806. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1807. if (!ret)
  1808. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1809. return ret;
  1810. }
  1811. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1812. {
  1813. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1814. union l5cm_specific_data l5_data;
  1815. int ret;
  1816. memset(&l5_data, 0, sizeof(l5_data));
  1817. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1818. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1819. return ret;
  1820. }
  1821. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1822. {
  1823. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1824. union l5cm_specific_data l5_data;
  1825. int ret;
  1826. memset(&l5_data, 0, sizeof(l5_data));
  1827. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1828. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1829. return ret;
  1830. }
  1831. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1832. {
  1833. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1834. struct l4_kcq kcqe;
  1835. struct kcqe *cqes[1];
  1836. memset(&kcqe, 0, sizeof(kcqe));
  1837. kcqe.pg_host_opaque = req->host_opaque;
  1838. kcqe.pg_cid = req->host_opaque;
  1839. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1840. cqes[0] = (struct kcqe *) &kcqe;
  1841. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1842. return 0;
  1843. }
  1844. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1845. {
  1846. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1847. struct l4_kcq kcqe;
  1848. struct kcqe *cqes[1];
  1849. memset(&kcqe, 0, sizeof(kcqe));
  1850. kcqe.pg_host_opaque = req->pg_host_opaque;
  1851. kcqe.pg_cid = req->pg_cid;
  1852. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1853. cqes[0] = (struct kcqe *) &kcqe;
  1854. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1855. return 0;
  1856. }
  1857. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1858. {
  1859. struct fcoe_kwqe_stat *req;
  1860. struct fcoe_stat_ramrod_params *fcoe_stat;
  1861. union l5cm_specific_data l5_data;
  1862. struct cnic_local *cp = dev->cnic_priv;
  1863. struct bnx2x *bp = netdev_priv(dev->netdev);
  1864. int ret;
  1865. u32 cid;
  1866. req = (struct fcoe_kwqe_stat *) kwqe;
  1867. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1868. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1869. if (!fcoe_stat)
  1870. return -ENOMEM;
  1871. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1872. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1873. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1874. FCOE_CONNECTION_TYPE, &l5_data);
  1875. return ret;
  1876. }
  1877. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1878. u32 num, int *work)
  1879. {
  1880. int ret;
  1881. struct cnic_local *cp = dev->cnic_priv;
  1882. struct bnx2x *bp = netdev_priv(dev->netdev);
  1883. u32 cid;
  1884. struct fcoe_init_ramrod_params *fcoe_init;
  1885. struct fcoe_kwqe_init1 *req1;
  1886. struct fcoe_kwqe_init2 *req2;
  1887. struct fcoe_kwqe_init3 *req3;
  1888. union l5cm_specific_data l5_data;
  1889. if (num < 3) {
  1890. *work = num;
  1891. return -EINVAL;
  1892. }
  1893. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1894. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1895. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1896. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1897. *work = 1;
  1898. return -EINVAL;
  1899. }
  1900. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1901. *work = 2;
  1902. return -EINVAL;
  1903. }
  1904. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1905. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1906. return -ENOMEM;
  1907. }
  1908. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1909. if (!fcoe_init)
  1910. return -ENOMEM;
  1911. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1912. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1913. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1914. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1915. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1916. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1917. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1918. fcoe_init->sb_num = cp->status_blk_num;
  1919. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1920. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1921. cp->kcq2.sw_prod_idx = 0;
  1922. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  1923. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1924. FCOE_CONNECTION_TYPE, &l5_data);
  1925. *work = 3;
  1926. return ret;
  1927. }
  1928. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1929. u32 num, int *work)
  1930. {
  1931. int ret = 0;
  1932. u32 cid = -1, l5_cid;
  1933. struct cnic_local *cp = dev->cnic_priv;
  1934. struct bnx2x *bp = netdev_priv(dev->netdev);
  1935. struct fcoe_kwqe_conn_offload1 *req1;
  1936. struct fcoe_kwqe_conn_offload2 *req2;
  1937. struct fcoe_kwqe_conn_offload3 *req3;
  1938. struct fcoe_kwqe_conn_offload4 *req4;
  1939. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1940. struct cnic_context *ctx;
  1941. struct fcoe_context *fctx;
  1942. struct regpair ctx_addr;
  1943. union l5cm_specific_data l5_data;
  1944. struct fcoe_kcqe kcqe;
  1945. struct kcqe *cqes[1];
  1946. if (num < 4) {
  1947. *work = num;
  1948. return -EINVAL;
  1949. }
  1950. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1951. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1952. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1953. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1954. *work = 4;
  1955. l5_cid = req1->fcoe_conn_id;
  1956. if (l5_cid >= dev->max_fcoe_conn)
  1957. goto err_reply;
  1958. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1959. ctx = &cp->ctx_tbl[l5_cid];
  1960. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1961. goto err_reply;
  1962. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1963. if (ret) {
  1964. ret = 0;
  1965. goto err_reply;
  1966. }
  1967. cid = ctx->cid;
  1968. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1969. if (fctx) {
  1970. u32 hw_cid = BNX2X_HW_CID(bp, cid);
  1971. u32 val;
  1972. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1973. FCOE_CONNECTION_TYPE);
  1974. fctx->xstorm_ag_context.cdu_reserved = val;
  1975. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1976. FCOE_CONNECTION_TYPE);
  1977. fctx->ustorm_ag_context.cdu_usage = val;
  1978. }
  1979. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1980. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1981. goto err_reply;
  1982. }
  1983. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1984. if (!fcoe_offload)
  1985. goto err_reply;
  1986. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1987. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1988. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1989. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1990. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1991. cid = BNX2X_HW_CID(bp, cid);
  1992. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1993. FCOE_CONNECTION_TYPE, &l5_data);
  1994. if (!ret)
  1995. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1996. return ret;
  1997. err_reply:
  1998. if (cid != -1)
  1999. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2000. memset(&kcqe, 0, sizeof(kcqe));
  2001. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2002. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2003. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2004. cqes[0] = (struct kcqe *) &kcqe;
  2005. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2006. return ret;
  2007. }
  2008. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2009. {
  2010. struct fcoe_kwqe_conn_enable_disable *req;
  2011. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2012. union l5cm_specific_data l5_data;
  2013. int ret;
  2014. u32 cid, l5_cid;
  2015. struct cnic_local *cp = dev->cnic_priv;
  2016. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2017. cid = req->context_id;
  2018. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2019. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2020. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2021. return -ENOMEM;
  2022. }
  2023. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2024. if (!fcoe_enable)
  2025. return -ENOMEM;
  2026. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2027. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2028. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2029. FCOE_CONNECTION_TYPE, &l5_data);
  2030. return ret;
  2031. }
  2032. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2033. {
  2034. struct fcoe_kwqe_conn_enable_disable *req;
  2035. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2036. union l5cm_specific_data l5_data;
  2037. int ret;
  2038. u32 cid, l5_cid;
  2039. struct cnic_local *cp = dev->cnic_priv;
  2040. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2041. cid = req->context_id;
  2042. l5_cid = req->conn_id;
  2043. if (l5_cid >= dev->max_fcoe_conn)
  2044. return -EINVAL;
  2045. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2046. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2047. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2048. return -ENOMEM;
  2049. }
  2050. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2051. if (!fcoe_disable)
  2052. return -ENOMEM;
  2053. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2054. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2055. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2056. FCOE_CONNECTION_TYPE, &l5_data);
  2057. return ret;
  2058. }
  2059. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2060. {
  2061. struct fcoe_kwqe_conn_destroy *req;
  2062. union l5cm_specific_data l5_data;
  2063. int ret;
  2064. u32 cid, l5_cid;
  2065. struct cnic_local *cp = dev->cnic_priv;
  2066. struct cnic_context *ctx;
  2067. struct fcoe_kcqe kcqe;
  2068. struct kcqe *cqes[1];
  2069. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2070. cid = req->context_id;
  2071. l5_cid = req->conn_id;
  2072. if (l5_cid >= dev->max_fcoe_conn)
  2073. return -EINVAL;
  2074. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2075. ctx = &cp->ctx_tbl[l5_cid];
  2076. init_waitqueue_head(&ctx->waitq);
  2077. ctx->wait_cond = 0;
  2078. memset(&kcqe, 0, sizeof(kcqe));
  2079. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2080. memset(&l5_data, 0, sizeof(l5_data));
  2081. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2082. FCOE_CONNECTION_TYPE, &l5_data);
  2083. if (ret == 0) {
  2084. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2085. if (ctx->wait_cond)
  2086. kcqe.completion_status = 0;
  2087. }
  2088. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2089. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2090. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2091. kcqe.fcoe_conn_id = req->conn_id;
  2092. kcqe.fcoe_conn_context_id = cid;
  2093. cqes[0] = (struct kcqe *) &kcqe;
  2094. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2095. return ret;
  2096. }
  2097. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2098. {
  2099. struct cnic_local *cp = dev->cnic_priv;
  2100. u32 i;
  2101. for (i = start_cid; i < cp->max_cid_space; i++) {
  2102. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2103. int j;
  2104. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2105. msleep(10);
  2106. for (j = 0; j < 5; j++) {
  2107. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2108. break;
  2109. msleep(20);
  2110. }
  2111. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2112. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2113. ctx->cid);
  2114. }
  2115. }
  2116. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2117. {
  2118. struct fcoe_kwqe_destroy *req;
  2119. union l5cm_specific_data l5_data;
  2120. struct cnic_local *cp = dev->cnic_priv;
  2121. struct bnx2x *bp = netdev_priv(dev->netdev);
  2122. int ret;
  2123. u32 cid;
  2124. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2125. req = (struct fcoe_kwqe_destroy *) kwqe;
  2126. cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
  2127. memset(&l5_data, 0, sizeof(l5_data));
  2128. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2129. FCOE_CONNECTION_TYPE, &l5_data);
  2130. return ret;
  2131. }
  2132. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2133. {
  2134. struct cnic_local *cp = dev->cnic_priv;
  2135. struct kcqe kcqe;
  2136. struct kcqe *cqes[1];
  2137. u32 cid;
  2138. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2139. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2140. u32 kcqe_op;
  2141. int ulp_type;
  2142. cid = kwqe->kwqe_info0;
  2143. memset(&kcqe, 0, sizeof(kcqe));
  2144. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2145. u32 l5_cid = 0;
  2146. ulp_type = CNIC_ULP_FCOE;
  2147. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2148. struct fcoe_kwqe_conn_enable_disable *req;
  2149. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2150. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2151. cid = req->context_id;
  2152. l5_cid = req->conn_id;
  2153. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2154. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2155. } else {
  2156. return;
  2157. }
  2158. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2159. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2160. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2161. kcqe.kcqe_info2 = cid;
  2162. kcqe.kcqe_info0 = l5_cid;
  2163. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2164. ulp_type = CNIC_ULP_ISCSI;
  2165. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2166. cid = kwqe->kwqe_info1;
  2167. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2168. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2169. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2170. kcqe.kcqe_info2 = cid;
  2171. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2172. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2173. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2174. ulp_type = CNIC_ULP_L4;
  2175. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2176. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2177. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2178. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2179. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2180. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2181. else
  2182. return;
  2183. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2184. KCQE_FLAGS_LAYER_MASK_L4;
  2185. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2186. l4kcqe->cid = cid;
  2187. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2188. } else {
  2189. return;
  2190. }
  2191. cqes[0] = &kcqe;
  2192. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2193. }
  2194. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2195. struct kwqe *wqes[], u32 num_wqes)
  2196. {
  2197. int i, work, ret;
  2198. u32 opcode;
  2199. struct kwqe *kwqe;
  2200. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2201. return -EAGAIN; /* bnx2 is down */
  2202. for (i = 0; i < num_wqes; ) {
  2203. kwqe = wqes[i];
  2204. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2205. work = 1;
  2206. switch (opcode) {
  2207. case ISCSI_KWQE_OPCODE_INIT1:
  2208. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2209. break;
  2210. case ISCSI_KWQE_OPCODE_INIT2:
  2211. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2212. break;
  2213. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2214. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2215. num_wqes - i, &work);
  2216. break;
  2217. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2218. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2219. break;
  2220. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2221. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2222. break;
  2223. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2224. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2225. &work);
  2226. break;
  2227. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2228. ret = cnic_bnx2x_close(dev, kwqe);
  2229. break;
  2230. case L4_KWQE_OPCODE_VALUE_RESET:
  2231. ret = cnic_bnx2x_reset(dev, kwqe);
  2232. break;
  2233. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2234. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2235. break;
  2236. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2237. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2238. break;
  2239. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2240. ret = 0;
  2241. break;
  2242. default:
  2243. ret = 0;
  2244. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2245. opcode);
  2246. break;
  2247. }
  2248. if (ret < 0) {
  2249. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2250. opcode);
  2251. /* Possibly bnx2x parity error, send completion
  2252. * to ulp drivers with error code to speed up
  2253. * cleanup and reset recovery.
  2254. */
  2255. if (ret == -EIO || ret == -EAGAIN)
  2256. cnic_bnx2x_kwqe_err(dev, kwqe);
  2257. }
  2258. i += work;
  2259. }
  2260. return 0;
  2261. }
  2262. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2263. struct kwqe *wqes[], u32 num_wqes)
  2264. {
  2265. struct bnx2x *bp = netdev_priv(dev->netdev);
  2266. int i, work, ret;
  2267. u32 opcode;
  2268. struct kwqe *kwqe;
  2269. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2270. return -EAGAIN; /* bnx2 is down */
  2271. if (!BNX2X_CHIP_IS_E2_PLUS(bp))
  2272. return -EINVAL;
  2273. for (i = 0; i < num_wqes; ) {
  2274. kwqe = wqes[i];
  2275. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2276. work = 1;
  2277. switch (opcode) {
  2278. case FCOE_KWQE_OPCODE_INIT1:
  2279. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2280. num_wqes - i, &work);
  2281. break;
  2282. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2283. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2284. num_wqes - i, &work);
  2285. break;
  2286. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2287. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2288. break;
  2289. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2290. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2291. break;
  2292. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2293. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2294. break;
  2295. case FCOE_KWQE_OPCODE_DESTROY:
  2296. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2297. break;
  2298. case FCOE_KWQE_OPCODE_STAT:
  2299. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2300. break;
  2301. default:
  2302. ret = 0;
  2303. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2304. opcode);
  2305. break;
  2306. }
  2307. if (ret < 0) {
  2308. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2309. opcode);
  2310. /* Possibly bnx2x parity error, send completion
  2311. * to ulp drivers with error code to speed up
  2312. * cleanup and reset recovery.
  2313. */
  2314. if (ret == -EIO || ret == -EAGAIN)
  2315. cnic_bnx2x_kwqe_err(dev, kwqe);
  2316. }
  2317. i += work;
  2318. }
  2319. return 0;
  2320. }
  2321. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2322. u32 num_wqes)
  2323. {
  2324. int ret = -EINVAL;
  2325. u32 layer_code;
  2326. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2327. return -EAGAIN; /* bnx2x is down */
  2328. if (!num_wqes)
  2329. return 0;
  2330. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2331. switch (layer_code) {
  2332. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2333. case KWQE_FLAGS_LAYER_MASK_L4:
  2334. case KWQE_FLAGS_LAYER_MASK_L2:
  2335. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2336. break;
  2337. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2338. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2339. break;
  2340. }
  2341. return ret;
  2342. }
  2343. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2344. {
  2345. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2346. return KCQE_FLAGS_LAYER_MASK_L4;
  2347. return opflag & KCQE_FLAGS_LAYER_MASK;
  2348. }
  2349. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2350. {
  2351. struct cnic_local *cp = dev->cnic_priv;
  2352. int i, j, comp = 0;
  2353. i = 0;
  2354. j = 1;
  2355. while (num_cqes) {
  2356. struct cnic_ulp_ops *ulp_ops;
  2357. int ulp_type;
  2358. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2359. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2360. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2361. comp++;
  2362. while (j < num_cqes) {
  2363. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2364. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2365. break;
  2366. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2367. comp++;
  2368. j++;
  2369. }
  2370. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2371. ulp_type = CNIC_ULP_RDMA;
  2372. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2373. ulp_type = CNIC_ULP_ISCSI;
  2374. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2375. ulp_type = CNIC_ULP_FCOE;
  2376. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2377. ulp_type = CNIC_ULP_L4;
  2378. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2379. goto end;
  2380. else {
  2381. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2382. kcqe_op_flag);
  2383. goto end;
  2384. }
  2385. rcu_read_lock();
  2386. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2387. if (likely(ulp_ops)) {
  2388. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2389. cp->completed_kcq + i, j);
  2390. }
  2391. rcu_read_unlock();
  2392. end:
  2393. num_cqes -= j;
  2394. i += j;
  2395. j = 1;
  2396. }
  2397. if (unlikely(comp))
  2398. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2399. }
  2400. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2401. {
  2402. struct cnic_local *cp = dev->cnic_priv;
  2403. u16 i, ri, hw_prod, last;
  2404. struct kcqe *kcqe;
  2405. int kcqe_cnt = 0, last_cnt = 0;
  2406. i = ri = last = info->sw_prod_idx;
  2407. ri &= MAX_KCQ_IDX;
  2408. hw_prod = *info->hw_prod_idx_ptr;
  2409. hw_prod = info->hw_idx(hw_prod);
  2410. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2411. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2412. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2413. i = info->next_idx(i);
  2414. ri = i & MAX_KCQ_IDX;
  2415. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2416. last_cnt = kcqe_cnt;
  2417. last = i;
  2418. }
  2419. }
  2420. info->sw_prod_idx = last;
  2421. return last_cnt;
  2422. }
  2423. static int cnic_l2_completion(struct cnic_local *cp)
  2424. {
  2425. u16 hw_cons, sw_cons;
  2426. struct cnic_uio_dev *udev = cp->udev;
  2427. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2428. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  2429. u32 cmd;
  2430. int comp = 0;
  2431. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2432. return 0;
  2433. hw_cons = *cp->rx_cons_ptr;
  2434. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2435. hw_cons++;
  2436. sw_cons = cp->rx_cons;
  2437. while (sw_cons != hw_cons) {
  2438. u8 cqe_fp_flags;
  2439. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2440. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2441. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2442. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2443. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2444. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2445. cmd == RAMROD_CMD_ID_ETH_HALT)
  2446. comp++;
  2447. }
  2448. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2449. }
  2450. return comp;
  2451. }
  2452. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2453. {
  2454. u16 rx_cons, tx_cons;
  2455. int comp = 0;
  2456. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2457. return;
  2458. rx_cons = *cp->rx_cons_ptr;
  2459. tx_cons = *cp->tx_cons_ptr;
  2460. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2461. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2462. comp = cnic_l2_completion(cp);
  2463. cp->tx_cons = tx_cons;
  2464. cp->rx_cons = rx_cons;
  2465. if (cp->udev)
  2466. uio_event_notify(&cp->udev->cnic_uinfo);
  2467. }
  2468. if (comp)
  2469. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2470. }
  2471. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2472. {
  2473. struct cnic_local *cp = dev->cnic_priv;
  2474. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2475. int kcqe_cnt;
  2476. /* status block index must be read before reading other fields */
  2477. rmb();
  2478. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2479. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2480. service_kcqes(dev, kcqe_cnt);
  2481. /* Tell compiler that status_blk fields can change. */
  2482. barrier();
  2483. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2484. /* status block index must be read first */
  2485. rmb();
  2486. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2487. }
  2488. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2489. cnic_chk_pkt_rings(cp);
  2490. return status_idx;
  2491. }
  2492. static int cnic_service_bnx2(void *data, void *status_blk)
  2493. {
  2494. struct cnic_dev *dev = data;
  2495. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2496. struct status_block *sblk = status_blk;
  2497. return sblk->status_idx;
  2498. }
  2499. return cnic_service_bnx2_queues(dev);
  2500. }
  2501. static void cnic_service_bnx2_msix(unsigned long data)
  2502. {
  2503. struct cnic_dev *dev = (struct cnic_dev *) data;
  2504. struct cnic_local *cp = dev->cnic_priv;
  2505. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2506. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2507. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2508. }
  2509. static void cnic_doirq(struct cnic_dev *dev)
  2510. {
  2511. struct cnic_local *cp = dev->cnic_priv;
  2512. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2513. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2514. prefetch(cp->status_blk.gen);
  2515. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2516. tasklet_schedule(&cp->cnic_irq_task);
  2517. }
  2518. }
  2519. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2520. {
  2521. struct cnic_dev *dev = dev_instance;
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. if (cp->ack_int)
  2524. cp->ack_int(dev);
  2525. cnic_doirq(dev);
  2526. return IRQ_HANDLED;
  2527. }
  2528. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2529. u16 index, u8 op, u8 update)
  2530. {
  2531. struct bnx2x *bp = netdev_priv(dev->netdev);
  2532. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
  2533. COMMAND_REG_INT_ACK);
  2534. struct igu_ack_register igu_ack;
  2535. igu_ack.status_block_index = index;
  2536. igu_ack.sb_id_and_flags =
  2537. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2538. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2539. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2540. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2541. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2542. }
  2543. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2544. u16 index, u8 op, u8 update)
  2545. {
  2546. struct igu_regular cmd_data;
  2547. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2548. cmd_data.sb_id_and_flags =
  2549. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2550. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2551. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2552. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2553. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2554. }
  2555. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2556. {
  2557. struct cnic_local *cp = dev->cnic_priv;
  2558. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2559. IGU_INT_DISABLE, 0);
  2560. }
  2561. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2562. {
  2563. struct cnic_local *cp = dev->cnic_priv;
  2564. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2565. IGU_INT_DISABLE, 0);
  2566. }
  2567. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2568. {
  2569. struct cnic_local *cp = dev->cnic_priv;
  2570. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2571. IGU_INT_ENABLE, 1);
  2572. }
  2573. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2574. {
  2575. struct cnic_local *cp = dev->cnic_priv;
  2576. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2577. IGU_INT_ENABLE, 1);
  2578. }
  2579. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2580. {
  2581. u32 last_status = *info->status_idx_ptr;
  2582. int kcqe_cnt;
  2583. /* status block index must be read before reading the KCQ */
  2584. rmb();
  2585. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2586. service_kcqes(dev, kcqe_cnt);
  2587. /* Tell compiler that sblk fields can change. */
  2588. barrier();
  2589. last_status = *info->status_idx_ptr;
  2590. /* status block index must be read before reading the KCQ */
  2591. rmb();
  2592. }
  2593. return last_status;
  2594. }
  2595. static void cnic_service_bnx2x_bh(unsigned long data)
  2596. {
  2597. struct cnic_dev *dev = (struct cnic_dev *) data;
  2598. struct cnic_local *cp = dev->cnic_priv;
  2599. struct bnx2x *bp = netdev_priv(dev->netdev);
  2600. u32 status_idx, new_status_idx;
  2601. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2602. return;
  2603. while (1) {
  2604. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2605. CNIC_WR16(dev, cp->kcq1.io_addr,
  2606. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2607. if (!CNIC_SUPPORTS_FCOE(bp)) {
  2608. cp->arm_int(dev, status_idx);
  2609. break;
  2610. }
  2611. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2612. if (new_status_idx != status_idx)
  2613. continue;
  2614. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2615. MAX_KCQ_IDX);
  2616. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2617. status_idx, IGU_INT_ENABLE, 1);
  2618. break;
  2619. }
  2620. }
  2621. static int cnic_service_bnx2x(void *data, void *status_blk)
  2622. {
  2623. struct cnic_dev *dev = data;
  2624. struct cnic_local *cp = dev->cnic_priv;
  2625. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2626. cnic_doirq(dev);
  2627. cnic_chk_pkt_rings(cp);
  2628. return 0;
  2629. }
  2630. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2631. {
  2632. struct cnic_ulp_ops *ulp_ops;
  2633. if (if_type == CNIC_ULP_ISCSI)
  2634. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2635. mutex_lock(&cnic_lock);
  2636. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2637. lockdep_is_held(&cnic_lock));
  2638. if (!ulp_ops) {
  2639. mutex_unlock(&cnic_lock);
  2640. return;
  2641. }
  2642. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2643. mutex_unlock(&cnic_lock);
  2644. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2645. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2646. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2647. }
  2648. static void cnic_ulp_stop(struct cnic_dev *dev)
  2649. {
  2650. struct cnic_local *cp = dev->cnic_priv;
  2651. int if_type;
  2652. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2653. cnic_ulp_stop_one(cp, if_type);
  2654. }
  2655. static void cnic_ulp_start(struct cnic_dev *dev)
  2656. {
  2657. struct cnic_local *cp = dev->cnic_priv;
  2658. int if_type;
  2659. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2660. struct cnic_ulp_ops *ulp_ops;
  2661. mutex_lock(&cnic_lock);
  2662. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2663. lockdep_is_held(&cnic_lock));
  2664. if (!ulp_ops || !ulp_ops->cnic_start) {
  2665. mutex_unlock(&cnic_lock);
  2666. continue;
  2667. }
  2668. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2669. mutex_unlock(&cnic_lock);
  2670. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2671. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2672. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2673. }
  2674. }
  2675. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2676. {
  2677. struct cnic_local *cp = dev->cnic_priv;
  2678. struct cnic_ulp_ops *ulp_ops;
  2679. int rc;
  2680. mutex_lock(&cnic_lock);
  2681. ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
  2682. lockdep_is_held(&cnic_lock));
  2683. if (ulp_ops && ulp_ops->cnic_get_stats)
  2684. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2685. else
  2686. rc = -ENODEV;
  2687. mutex_unlock(&cnic_lock);
  2688. return rc;
  2689. }
  2690. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2691. {
  2692. struct cnic_dev *dev = data;
  2693. int ulp_type = CNIC_ULP_ISCSI;
  2694. switch (info->cmd) {
  2695. case CNIC_CTL_STOP_CMD:
  2696. cnic_hold(dev);
  2697. cnic_ulp_stop(dev);
  2698. cnic_stop_hw(dev);
  2699. cnic_put(dev);
  2700. break;
  2701. case CNIC_CTL_START_CMD:
  2702. cnic_hold(dev);
  2703. if (!cnic_start_hw(dev))
  2704. cnic_ulp_start(dev);
  2705. cnic_put(dev);
  2706. break;
  2707. case CNIC_CTL_STOP_ISCSI_CMD: {
  2708. struct cnic_local *cp = dev->cnic_priv;
  2709. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2710. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2711. break;
  2712. }
  2713. case CNIC_CTL_COMPLETION_CMD: {
  2714. struct cnic_ctl_completion *comp = &info->data.comp;
  2715. u32 cid = BNX2X_SW_CID(comp->cid);
  2716. u32 l5_cid;
  2717. struct cnic_local *cp = dev->cnic_priv;
  2718. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2719. break;
  2720. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2721. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2722. if (unlikely(comp->error)) {
  2723. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2724. netdev_err(dev->netdev,
  2725. "CID %x CFC delete comp error %x\n",
  2726. cid, comp->error);
  2727. }
  2728. ctx->wait_cond = 1;
  2729. wake_up(&ctx->waitq);
  2730. }
  2731. break;
  2732. }
  2733. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2734. ulp_type = CNIC_ULP_FCOE;
  2735. /* fall through */
  2736. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2737. cnic_hold(dev);
  2738. cnic_copy_ulp_stats(dev, ulp_type);
  2739. cnic_put(dev);
  2740. break;
  2741. default:
  2742. return -EINVAL;
  2743. }
  2744. return 0;
  2745. }
  2746. static void cnic_ulp_init(struct cnic_dev *dev)
  2747. {
  2748. int i;
  2749. struct cnic_local *cp = dev->cnic_priv;
  2750. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2751. struct cnic_ulp_ops *ulp_ops;
  2752. mutex_lock(&cnic_lock);
  2753. ulp_ops = cnic_ulp_tbl_prot(i);
  2754. if (!ulp_ops || !ulp_ops->cnic_init) {
  2755. mutex_unlock(&cnic_lock);
  2756. continue;
  2757. }
  2758. ulp_get(ulp_ops);
  2759. mutex_unlock(&cnic_lock);
  2760. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2761. ulp_ops->cnic_init(dev);
  2762. ulp_put(ulp_ops);
  2763. }
  2764. }
  2765. static void cnic_ulp_exit(struct cnic_dev *dev)
  2766. {
  2767. int i;
  2768. struct cnic_local *cp = dev->cnic_priv;
  2769. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2770. struct cnic_ulp_ops *ulp_ops;
  2771. mutex_lock(&cnic_lock);
  2772. ulp_ops = cnic_ulp_tbl_prot(i);
  2773. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2774. mutex_unlock(&cnic_lock);
  2775. continue;
  2776. }
  2777. ulp_get(ulp_ops);
  2778. mutex_unlock(&cnic_lock);
  2779. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2780. ulp_ops->cnic_exit(dev);
  2781. ulp_put(ulp_ops);
  2782. }
  2783. }
  2784. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2785. {
  2786. struct cnic_dev *dev = csk->dev;
  2787. struct l4_kwq_offload_pg *l4kwqe;
  2788. struct kwqe *wqes[1];
  2789. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2790. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2791. wqes[0] = (struct kwqe *) l4kwqe;
  2792. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2793. l4kwqe->flags =
  2794. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2795. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2796. l4kwqe->da0 = csk->ha[0];
  2797. l4kwqe->da1 = csk->ha[1];
  2798. l4kwqe->da2 = csk->ha[2];
  2799. l4kwqe->da3 = csk->ha[3];
  2800. l4kwqe->da4 = csk->ha[4];
  2801. l4kwqe->da5 = csk->ha[5];
  2802. l4kwqe->sa0 = dev->mac_addr[0];
  2803. l4kwqe->sa1 = dev->mac_addr[1];
  2804. l4kwqe->sa2 = dev->mac_addr[2];
  2805. l4kwqe->sa3 = dev->mac_addr[3];
  2806. l4kwqe->sa4 = dev->mac_addr[4];
  2807. l4kwqe->sa5 = dev->mac_addr[5];
  2808. l4kwqe->etype = ETH_P_IP;
  2809. l4kwqe->ipid_start = DEF_IPID_START;
  2810. l4kwqe->host_opaque = csk->l5_cid;
  2811. if (csk->vlan_id) {
  2812. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2813. l4kwqe->vlan_tag = csk->vlan_id;
  2814. l4kwqe->l2hdr_nbytes += 4;
  2815. }
  2816. return dev->submit_kwqes(dev, wqes, 1);
  2817. }
  2818. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2819. {
  2820. struct cnic_dev *dev = csk->dev;
  2821. struct l4_kwq_update_pg *l4kwqe;
  2822. struct kwqe *wqes[1];
  2823. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2824. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2825. wqes[0] = (struct kwqe *) l4kwqe;
  2826. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2827. l4kwqe->flags =
  2828. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2829. l4kwqe->pg_cid = csk->pg_cid;
  2830. l4kwqe->da0 = csk->ha[0];
  2831. l4kwqe->da1 = csk->ha[1];
  2832. l4kwqe->da2 = csk->ha[2];
  2833. l4kwqe->da3 = csk->ha[3];
  2834. l4kwqe->da4 = csk->ha[4];
  2835. l4kwqe->da5 = csk->ha[5];
  2836. l4kwqe->pg_host_opaque = csk->l5_cid;
  2837. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2838. return dev->submit_kwqes(dev, wqes, 1);
  2839. }
  2840. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2841. {
  2842. struct cnic_dev *dev = csk->dev;
  2843. struct l4_kwq_upload *l4kwqe;
  2844. struct kwqe *wqes[1];
  2845. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2846. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2847. wqes[0] = (struct kwqe *) l4kwqe;
  2848. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2849. l4kwqe->flags =
  2850. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2851. l4kwqe->cid = csk->pg_cid;
  2852. return dev->submit_kwqes(dev, wqes, 1);
  2853. }
  2854. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2855. {
  2856. struct cnic_dev *dev = csk->dev;
  2857. struct l4_kwq_connect_req1 *l4kwqe1;
  2858. struct l4_kwq_connect_req2 *l4kwqe2;
  2859. struct l4_kwq_connect_req3 *l4kwqe3;
  2860. struct kwqe *wqes[3];
  2861. u8 tcp_flags = 0;
  2862. int num_wqes = 2;
  2863. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2864. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2865. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2866. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2867. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2868. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2869. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2870. l4kwqe3->flags =
  2871. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2872. l4kwqe3->ka_timeout = csk->ka_timeout;
  2873. l4kwqe3->ka_interval = csk->ka_interval;
  2874. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2875. l4kwqe3->tos = csk->tos;
  2876. l4kwqe3->ttl = csk->ttl;
  2877. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2878. l4kwqe3->pmtu = csk->mtu;
  2879. l4kwqe3->rcv_buf = csk->rcv_buf;
  2880. l4kwqe3->snd_buf = csk->snd_buf;
  2881. l4kwqe3->seed = csk->seed;
  2882. wqes[0] = (struct kwqe *) l4kwqe1;
  2883. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2884. wqes[1] = (struct kwqe *) l4kwqe2;
  2885. wqes[2] = (struct kwqe *) l4kwqe3;
  2886. num_wqes = 3;
  2887. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2888. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2889. l4kwqe2->flags =
  2890. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2891. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2892. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2893. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2894. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2895. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2896. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2897. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2898. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2899. sizeof(struct tcphdr);
  2900. } else {
  2901. wqes[1] = (struct kwqe *) l4kwqe3;
  2902. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2903. sizeof(struct tcphdr);
  2904. }
  2905. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2906. l4kwqe1->flags =
  2907. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2908. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2909. l4kwqe1->cid = csk->cid;
  2910. l4kwqe1->pg_cid = csk->pg_cid;
  2911. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2912. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2913. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2914. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2915. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2916. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2917. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2918. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2919. if (csk->tcp_flags & SK_TCP_NAGLE)
  2920. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2921. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2922. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2923. if (csk->tcp_flags & SK_TCP_SACK)
  2924. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2925. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2926. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2927. l4kwqe1->tcp_flags = tcp_flags;
  2928. return dev->submit_kwqes(dev, wqes, num_wqes);
  2929. }
  2930. static int cnic_cm_close_req(struct cnic_sock *csk)
  2931. {
  2932. struct cnic_dev *dev = csk->dev;
  2933. struct l4_kwq_close_req *l4kwqe;
  2934. struct kwqe *wqes[1];
  2935. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2936. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2937. wqes[0] = (struct kwqe *) l4kwqe;
  2938. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2939. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2940. l4kwqe->cid = csk->cid;
  2941. return dev->submit_kwqes(dev, wqes, 1);
  2942. }
  2943. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2944. {
  2945. struct cnic_dev *dev = csk->dev;
  2946. struct l4_kwq_reset_req *l4kwqe;
  2947. struct kwqe *wqes[1];
  2948. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2949. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2950. wqes[0] = (struct kwqe *) l4kwqe;
  2951. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2952. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2953. l4kwqe->cid = csk->cid;
  2954. return dev->submit_kwqes(dev, wqes, 1);
  2955. }
  2956. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2957. u32 l5_cid, struct cnic_sock **csk, void *context)
  2958. {
  2959. struct cnic_local *cp = dev->cnic_priv;
  2960. struct cnic_sock *csk1;
  2961. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2962. return -EINVAL;
  2963. if (cp->ctx_tbl) {
  2964. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2965. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2966. return -EAGAIN;
  2967. }
  2968. csk1 = &cp->csk_tbl[l5_cid];
  2969. if (atomic_read(&csk1->ref_count))
  2970. return -EAGAIN;
  2971. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2972. return -EBUSY;
  2973. csk1->dev = dev;
  2974. csk1->cid = cid;
  2975. csk1->l5_cid = l5_cid;
  2976. csk1->ulp_type = ulp_type;
  2977. csk1->context = context;
  2978. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2979. csk1->ka_interval = DEF_KA_INTERVAL;
  2980. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2981. csk1->tos = DEF_TOS;
  2982. csk1->ttl = DEF_TTL;
  2983. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2984. csk1->rcv_buf = DEF_RCV_BUF;
  2985. csk1->snd_buf = DEF_SND_BUF;
  2986. csk1->seed = DEF_SEED;
  2987. csk1->tcp_flags = 0;
  2988. *csk = csk1;
  2989. return 0;
  2990. }
  2991. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2992. {
  2993. if (csk->src_port) {
  2994. struct cnic_dev *dev = csk->dev;
  2995. struct cnic_local *cp = dev->cnic_priv;
  2996. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2997. csk->src_port = 0;
  2998. }
  2999. }
  3000. static void cnic_close_conn(struct cnic_sock *csk)
  3001. {
  3002. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3003. cnic_cm_upload_pg(csk);
  3004. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3005. }
  3006. cnic_cm_cleanup(csk);
  3007. }
  3008. static int cnic_cm_destroy(struct cnic_sock *csk)
  3009. {
  3010. if (!cnic_in_use(csk))
  3011. return -EINVAL;
  3012. csk_hold(csk);
  3013. clear_bit(SK_F_INUSE, &csk->flags);
  3014. smp_mb__after_atomic();
  3015. while (atomic_read(&csk->ref_count) != 1)
  3016. msleep(1);
  3017. cnic_cm_cleanup(csk);
  3018. csk->flags = 0;
  3019. csk_put(csk);
  3020. return 0;
  3021. }
  3022. static inline u16 cnic_get_vlan(struct net_device *dev,
  3023. struct net_device **vlan_dev)
  3024. {
  3025. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3026. *vlan_dev = vlan_dev_real_dev(dev);
  3027. return vlan_dev_vlan_id(dev);
  3028. }
  3029. *vlan_dev = dev;
  3030. return 0;
  3031. }
  3032. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3033. struct dst_entry **dst)
  3034. {
  3035. #if defined(CONFIG_INET)
  3036. struct rtable *rt;
  3037. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3038. if (!IS_ERR(rt)) {
  3039. *dst = &rt->dst;
  3040. return 0;
  3041. }
  3042. return PTR_ERR(rt);
  3043. #else
  3044. return -ENETUNREACH;
  3045. #endif
  3046. }
  3047. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3048. struct dst_entry **dst)
  3049. {
  3050. #if IS_ENABLED(CONFIG_IPV6)
  3051. struct flowi6 fl6;
  3052. memset(&fl6, 0, sizeof(fl6));
  3053. fl6.daddr = dst_addr->sin6_addr;
  3054. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3055. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3056. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3057. if ((*dst)->error) {
  3058. dst_release(*dst);
  3059. *dst = NULL;
  3060. return -ENETUNREACH;
  3061. } else
  3062. return 0;
  3063. #endif
  3064. return -ENETUNREACH;
  3065. }
  3066. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3067. int ulp_type)
  3068. {
  3069. struct cnic_dev *dev = NULL;
  3070. struct dst_entry *dst;
  3071. struct net_device *netdev = NULL;
  3072. int err = -ENETUNREACH;
  3073. if (dst_addr->sin_family == AF_INET)
  3074. err = cnic_get_v4_route(dst_addr, &dst);
  3075. else if (dst_addr->sin_family == AF_INET6) {
  3076. struct sockaddr_in6 *dst_addr6 =
  3077. (struct sockaddr_in6 *) dst_addr;
  3078. err = cnic_get_v6_route(dst_addr6, &dst);
  3079. } else
  3080. return NULL;
  3081. if (err)
  3082. return NULL;
  3083. if (!dst->dev)
  3084. goto done;
  3085. cnic_get_vlan(dst->dev, &netdev);
  3086. dev = cnic_from_netdev(netdev);
  3087. done:
  3088. dst_release(dst);
  3089. if (dev)
  3090. cnic_put(dev);
  3091. return dev;
  3092. }
  3093. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3094. {
  3095. struct cnic_dev *dev = csk->dev;
  3096. struct cnic_local *cp = dev->cnic_priv;
  3097. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3098. }
  3099. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3100. {
  3101. struct cnic_dev *dev = csk->dev;
  3102. struct cnic_local *cp = dev->cnic_priv;
  3103. int is_v6, rc = 0;
  3104. struct dst_entry *dst = NULL;
  3105. struct net_device *realdev;
  3106. __be16 local_port;
  3107. u32 port_id;
  3108. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3109. saddr->remote.v6.sin6_family == AF_INET6)
  3110. is_v6 = 1;
  3111. else if (saddr->local.v4.sin_family == AF_INET &&
  3112. saddr->remote.v4.sin_family == AF_INET)
  3113. is_v6 = 0;
  3114. else
  3115. return -EINVAL;
  3116. clear_bit(SK_F_IPV6, &csk->flags);
  3117. if (is_v6) {
  3118. set_bit(SK_F_IPV6, &csk->flags);
  3119. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3120. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3121. sizeof(struct in6_addr));
  3122. csk->dst_port = saddr->remote.v6.sin6_port;
  3123. local_port = saddr->local.v6.sin6_port;
  3124. } else {
  3125. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3126. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3127. csk->dst_port = saddr->remote.v4.sin_port;
  3128. local_port = saddr->local.v4.sin_port;
  3129. }
  3130. csk->vlan_id = 0;
  3131. csk->mtu = dev->netdev->mtu;
  3132. if (dst && dst->dev) {
  3133. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3134. if (realdev == dev->netdev) {
  3135. csk->vlan_id = vlan;
  3136. csk->mtu = dst_mtu(dst);
  3137. }
  3138. }
  3139. port_id = be16_to_cpu(local_port);
  3140. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3141. port_id < CNIC_LOCAL_PORT_MAX) {
  3142. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3143. port_id = 0;
  3144. } else
  3145. port_id = 0;
  3146. if (!port_id) {
  3147. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3148. if (port_id == -1) {
  3149. rc = -ENOMEM;
  3150. goto err_out;
  3151. }
  3152. local_port = cpu_to_be16(port_id);
  3153. }
  3154. csk->src_port = local_port;
  3155. err_out:
  3156. dst_release(dst);
  3157. return rc;
  3158. }
  3159. static void cnic_init_csk_state(struct cnic_sock *csk)
  3160. {
  3161. csk->state = 0;
  3162. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3163. clear_bit(SK_F_CLOSING, &csk->flags);
  3164. }
  3165. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3166. {
  3167. struct cnic_local *cp = csk->dev->cnic_priv;
  3168. int err = 0;
  3169. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3170. return -EOPNOTSUPP;
  3171. if (!cnic_in_use(csk))
  3172. return -EINVAL;
  3173. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3174. return -EINVAL;
  3175. cnic_init_csk_state(csk);
  3176. err = cnic_get_route(csk, saddr);
  3177. if (err)
  3178. goto err_out;
  3179. err = cnic_resolve_addr(csk, saddr);
  3180. if (!err)
  3181. return 0;
  3182. err_out:
  3183. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3184. return err;
  3185. }
  3186. static int cnic_cm_abort(struct cnic_sock *csk)
  3187. {
  3188. struct cnic_local *cp = csk->dev->cnic_priv;
  3189. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3190. if (!cnic_in_use(csk))
  3191. return -EINVAL;
  3192. if (cnic_abort_prep(csk))
  3193. return cnic_cm_abort_req(csk);
  3194. /* Getting here means that we haven't started connect, or
  3195. * connect was not successful, or it has been reset by the target.
  3196. */
  3197. cp->close_conn(csk, opcode);
  3198. if (csk->state != opcode) {
  3199. /* Wait for remote reset sequence to complete */
  3200. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3201. msleep(1);
  3202. return -EALREADY;
  3203. }
  3204. return 0;
  3205. }
  3206. static int cnic_cm_close(struct cnic_sock *csk)
  3207. {
  3208. if (!cnic_in_use(csk))
  3209. return -EINVAL;
  3210. if (cnic_close_prep(csk)) {
  3211. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3212. return cnic_cm_close_req(csk);
  3213. } else {
  3214. /* Wait for remote reset sequence to complete */
  3215. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3216. msleep(1);
  3217. return -EALREADY;
  3218. }
  3219. return 0;
  3220. }
  3221. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3222. u8 opcode)
  3223. {
  3224. struct cnic_ulp_ops *ulp_ops;
  3225. int ulp_type = csk->ulp_type;
  3226. rcu_read_lock();
  3227. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3228. if (ulp_ops) {
  3229. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3230. ulp_ops->cm_connect_complete(csk);
  3231. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3232. ulp_ops->cm_close_complete(csk);
  3233. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3234. ulp_ops->cm_remote_abort(csk);
  3235. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3236. ulp_ops->cm_abort_complete(csk);
  3237. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3238. ulp_ops->cm_remote_close(csk);
  3239. }
  3240. rcu_read_unlock();
  3241. }
  3242. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3243. {
  3244. if (cnic_offld_prep(csk)) {
  3245. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3246. cnic_cm_update_pg(csk);
  3247. else
  3248. cnic_cm_offload_pg(csk);
  3249. }
  3250. return 0;
  3251. }
  3252. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3253. {
  3254. struct cnic_local *cp = dev->cnic_priv;
  3255. u32 l5_cid = kcqe->pg_host_opaque;
  3256. u8 opcode = kcqe->op_code;
  3257. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3258. csk_hold(csk);
  3259. if (!cnic_in_use(csk))
  3260. goto done;
  3261. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3262. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3263. goto done;
  3264. }
  3265. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3266. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3267. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3268. cnic_cm_upcall(cp, csk,
  3269. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3270. goto done;
  3271. }
  3272. csk->pg_cid = kcqe->pg_cid;
  3273. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3274. cnic_cm_conn_req(csk);
  3275. done:
  3276. csk_put(csk);
  3277. }
  3278. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3279. {
  3280. struct cnic_local *cp = dev->cnic_priv;
  3281. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3282. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3283. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3284. ctx->timestamp = jiffies;
  3285. ctx->wait_cond = 1;
  3286. wake_up(&ctx->waitq);
  3287. }
  3288. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3289. {
  3290. struct cnic_local *cp = dev->cnic_priv;
  3291. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3292. u8 opcode = l4kcqe->op_code;
  3293. u32 l5_cid;
  3294. struct cnic_sock *csk;
  3295. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3296. cnic_process_fcoe_term_conn(dev, kcqe);
  3297. return;
  3298. }
  3299. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3300. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3301. cnic_cm_process_offld_pg(dev, l4kcqe);
  3302. return;
  3303. }
  3304. l5_cid = l4kcqe->conn_id;
  3305. if (opcode & 0x80)
  3306. l5_cid = l4kcqe->cid;
  3307. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3308. return;
  3309. csk = &cp->csk_tbl[l5_cid];
  3310. csk_hold(csk);
  3311. if (!cnic_in_use(csk)) {
  3312. csk_put(csk);
  3313. return;
  3314. }
  3315. switch (opcode) {
  3316. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3317. if (l4kcqe->status != 0) {
  3318. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3319. cnic_cm_upcall(cp, csk,
  3320. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3321. }
  3322. break;
  3323. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3324. if (l4kcqe->status == 0)
  3325. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3326. else if (l4kcqe->status ==
  3327. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3328. set_bit(SK_F_HW_ERR, &csk->flags);
  3329. smp_mb__before_atomic();
  3330. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3331. cnic_cm_upcall(cp, csk, opcode);
  3332. break;
  3333. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3334. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3335. if (l4kcqe->status != 0 || l5kcqe->completion_status != 0) {
  3336. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3337. l4kcqe->status, l5kcqe->completion_status);
  3338. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3339. /* Fall through */
  3340. } else {
  3341. break;
  3342. }
  3343. }
  3344. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3345. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3346. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3347. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3348. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3349. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3350. set_bit(SK_F_HW_ERR, &csk->flags);
  3351. cp->close_conn(csk, opcode);
  3352. break;
  3353. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3354. /* after we already sent CLOSE_REQ */
  3355. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3356. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3357. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3358. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3359. else
  3360. cnic_cm_upcall(cp, csk, opcode);
  3361. break;
  3362. }
  3363. csk_put(csk);
  3364. }
  3365. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3366. {
  3367. struct cnic_dev *dev = data;
  3368. int i;
  3369. for (i = 0; i < num; i++)
  3370. cnic_cm_process_kcqe(dev, kcqe[i]);
  3371. }
  3372. static struct cnic_ulp_ops cm_ulp_ops = {
  3373. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3374. };
  3375. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3376. {
  3377. struct cnic_local *cp = dev->cnic_priv;
  3378. kfree(cp->csk_tbl);
  3379. cp->csk_tbl = NULL;
  3380. cnic_free_id_tbl(&cp->csk_port_tbl);
  3381. }
  3382. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3383. {
  3384. struct cnic_local *cp = dev->cnic_priv;
  3385. u32 port_id;
  3386. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3387. GFP_KERNEL);
  3388. if (!cp->csk_tbl)
  3389. return -ENOMEM;
  3390. port_id = prandom_u32();
  3391. port_id %= CNIC_LOCAL_PORT_RANGE;
  3392. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3393. CNIC_LOCAL_PORT_MIN, port_id)) {
  3394. cnic_cm_free_mem(dev);
  3395. return -ENOMEM;
  3396. }
  3397. return 0;
  3398. }
  3399. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3400. {
  3401. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3402. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3403. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3404. csk->state = opcode;
  3405. }
  3406. /* 1. If event opcode matches the expected event in csk->state
  3407. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3408. * event
  3409. * 3. If the expected event is 0, meaning the connection was never
  3410. * never established, we accept the opcode from cm_abort.
  3411. */
  3412. if (opcode == csk->state || csk->state == 0 ||
  3413. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3414. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3415. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3416. if (csk->state == 0)
  3417. csk->state = opcode;
  3418. return 1;
  3419. }
  3420. }
  3421. return 0;
  3422. }
  3423. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3424. {
  3425. struct cnic_dev *dev = csk->dev;
  3426. struct cnic_local *cp = dev->cnic_priv;
  3427. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3428. cnic_cm_upcall(cp, csk, opcode);
  3429. return;
  3430. }
  3431. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3432. cnic_close_conn(csk);
  3433. csk->state = opcode;
  3434. cnic_cm_upcall(cp, csk, opcode);
  3435. }
  3436. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3437. {
  3438. }
  3439. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3440. {
  3441. u32 seed;
  3442. seed = prandom_u32();
  3443. cnic_ctx_wr(dev, 45, 0, seed);
  3444. return 0;
  3445. }
  3446. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3447. {
  3448. struct cnic_dev *dev = csk->dev;
  3449. struct cnic_local *cp = dev->cnic_priv;
  3450. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3451. union l5cm_specific_data l5_data;
  3452. u32 cmd = 0;
  3453. int close_complete = 0;
  3454. switch (opcode) {
  3455. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3456. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3457. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3458. if (cnic_ready_to_close(csk, opcode)) {
  3459. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3460. close_complete = 1;
  3461. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3462. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3463. else
  3464. close_complete = 1;
  3465. }
  3466. break;
  3467. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3468. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3469. break;
  3470. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3471. close_complete = 1;
  3472. break;
  3473. }
  3474. if (cmd) {
  3475. memset(&l5_data, 0, sizeof(l5_data));
  3476. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3477. &l5_data);
  3478. } else if (close_complete) {
  3479. ctx->timestamp = jiffies;
  3480. cnic_close_conn(csk);
  3481. cnic_cm_upcall(cp, csk, csk->state);
  3482. }
  3483. }
  3484. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3485. {
  3486. struct cnic_local *cp = dev->cnic_priv;
  3487. if (!cp->ctx_tbl)
  3488. return;
  3489. if (!netif_running(dev->netdev))
  3490. return;
  3491. cnic_bnx2x_delete_wait(dev, 0);
  3492. cancel_delayed_work(&cp->delete_task);
  3493. flush_workqueue(cnic_wq);
  3494. if (atomic_read(&cp->iscsi_conn) != 0)
  3495. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3496. atomic_read(&cp->iscsi_conn));
  3497. }
  3498. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3499. {
  3500. struct bnx2x *bp = netdev_priv(dev->netdev);
  3501. u32 pfid = bp->pfid;
  3502. u32 port = BP_PORT(bp);
  3503. cnic_init_bnx2x_mac(dev);
  3504. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3505. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3506. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3507. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3508. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3509. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3510. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3511. DEF_MAX_DA_COUNT);
  3512. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3513. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3514. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3515. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3516. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3517. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3518. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3519. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3520. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3521. DEF_MAX_CWND);
  3522. return 0;
  3523. }
  3524. static void cnic_delete_task(struct work_struct *work)
  3525. {
  3526. struct cnic_local *cp;
  3527. struct cnic_dev *dev;
  3528. u32 i;
  3529. int need_resched = 0;
  3530. cp = container_of(work, struct cnic_local, delete_task.work);
  3531. dev = cp->dev;
  3532. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3533. struct drv_ctl_info info;
  3534. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3535. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3536. cp->ethdev->drv_ctl(dev->netdev, &info);
  3537. }
  3538. for (i = 0; i < cp->max_cid_space; i++) {
  3539. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3540. int err;
  3541. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3542. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3543. continue;
  3544. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3545. need_resched = 1;
  3546. continue;
  3547. }
  3548. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3549. continue;
  3550. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3551. cnic_free_bnx2x_conn_resc(dev, i);
  3552. if (!err) {
  3553. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3554. atomic_dec(&cp->iscsi_conn);
  3555. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3556. }
  3557. }
  3558. if (need_resched)
  3559. queue_delayed_work(cnic_wq, &cp->delete_task,
  3560. msecs_to_jiffies(10));
  3561. }
  3562. static int cnic_cm_open(struct cnic_dev *dev)
  3563. {
  3564. struct cnic_local *cp = dev->cnic_priv;
  3565. int err;
  3566. err = cnic_cm_alloc_mem(dev);
  3567. if (err)
  3568. return err;
  3569. err = cp->start_cm(dev);
  3570. if (err)
  3571. goto err_out;
  3572. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3573. dev->cm_create = cnic_cm_create;
  3574. dev->cm_destroy = cnic_cm_destroy;
  3575. dev->cm_connect = cnic_cm_connect;
  3576. dev->cm_abort = cnic_cm_abort;
  3577. dev->cm_close = cnic_cm_close;
  3578. dev->cm_select_dev = cnic_cm_select_dev;
  3579. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3580. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3581. return 0;
  3582. err_out:
  3583. cnic_cm_free_mem(dev);
  3584. return err;
  3585. }
  3586. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. int i;
  3590. if (!cp->csk_tbl)
  3591. return 0;
  3592. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3593. struct cnic_sock *csk = &cp->csk_tbl[i];
  3594. clear_bit(SK_F_INUSE, &csk->flags);
  3595. cnic_cm_cleanup(csk);
  3596. }
  3597. cnic_cm_free_mem(dev);
  3598. return 0;
  3599. }
  3600. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3601. {
  3602. u32 cid_addr;
  3603. int i;
  3604. cid_addr = GET_CID_ADDR(cid);
  3605. for (i = 0; i < CTX_SIZE; i += 4)
  3606. cnic_ctx_wr(dev, cid_addr, i, 0);
  3607. }
  3608. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3609. {
  3610. struct cnic_local *cp = dev->cnic_priv;
  3611. int ret = 0, i;
  3612. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3613. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3614. return 0;
  3615. for (i = 0; i < cp->ctx_blks; i++) {
  3616. int j;
  3617. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3618. u32 val;
  3619. memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
  3620. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3621. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3622. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3623. (u64) cp->ctx_arr[i].mapping >> 32);
  3624. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3625. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3626. for (j = 0; j < 10; j++) {
  3627. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3628. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3629. break;
  3630. udelay(5);
  3631. }
  3632. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3633. ret = -EBUSY;
  3634. break;
  3635. }
  3636. }
  3637. return ret;
  3638. }
  3639. static void cnic_free_irq(struct cnic_dev *dev)
  3640. {
  3641. struct cnic_local *cp = dev->cnic_priv;
  3642. struct cnic_eth_dev *ethdev = cp->ethdev;
  3643. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3644. cp->disable_int_sync(dev);
  3645. tasklet_kill(&cp->cnic_irq_task);
  3646. free_irq(ethdev->irq_arr[0].vector, dev);
  3647. }
  3648. }
  3649. static int cnic_request_irq(struct cnic_dev *dev)
  3650. {
  3651. struct cnic_local *cp = dev->cnic_priv;
  3652. struct cnic_eth_dev *ethdev = cp->ethdev;
  3653. int err;
  3654. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3655. if (err)
  3656. tasklet_disable(&cp->cnic_irq_task);
  3657. return err;
  3658. }
  3659. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3660. {
  3661. struct cnic_local *cp = dev->cnic_priv;
  3662. struct cnic_eth_dev *ethdev = cp->ethdev;
  3663. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3664. int err, i = 0;
  3665. int sblk_num = cp->status_blk_num;
  3666. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3667. BNX2_HC_SB_CONFIG_1;
  3668. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3669. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3670. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3671. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3672. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3673. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3674. (unsigned long) dev);
  3675. err = cnic_request_irq(dev);
  3676. if (err)
  3677. return err;
  3678. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3679. i < 10) {
  3680. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3681. 1 << (11 + sblk_num));
  3682. udelay(10);
  3683. i++;
  3684. barrier();
  3685. }
  3686. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3687. cnic_free_irq(dev);
  3688. goto failed;
  3689. }
  3690. } else {
  3691. struct status_block *sblk = cp->status_blk.gen;
  3692. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3693. int i = 0;
  3694. while (sblk->status_completion_producer_index && i < 10) {
  3695. CNIC_WR(dev, BNX2_HC_COMMAND,
  3696. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3697. udelay(10);
  3698. i++;
  3699. barrier();
  3700. }
  3701. if (sblk->status_completion_producer_index)
  3702. goto failed;
  3703. }
  3704. return 0;
  3705. failed:
  3706. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3707. return -EBUSY;
  3708. }
  3709. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3710. {
  3711. struct cnic_local *cp = dev->cnic_priv;
  3712. struct cnic_eth_dev *ethdev = cp->ethdev;
  3713. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3714. return;
  3715. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3716. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3717. }
  3718. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3719. {
  3720. struct cnic_local *cp = dev->cnic_priv;
  3721. struct cnic_eth_dev *ethdev = cp->ethdev;
  3722. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3723. return;
  3724. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3725. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3726. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3727. synchronize_irq(ethdev->irq_arr[0].vector);
  3728. }
  3729. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3730. {
  3731. struct cnic_local *cp = dev->cnic_priv;
  3732. struct cnic_eth_dev *ethdev = cp->ethdev;
  3733. struct cnic_uio_dev *udev = cp->udev;
  3734. u32 cid_addr, tx_cid, sb_id;
  3735. u32 val, offset0, offset1, offset2, offset3;
  3736. int i;
  3737. struct bnx2_tx_bd *txbd;
  3738. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3739. struct status_block *s_blk = cp->status_blk.gen;
  3740. sb_id = cp->status_blk_num;
  3741. tx_cid = 20;
  3742. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3743. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3744. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3745. tx_cid = TX_TSS_CID + sb_id - 1;
  3746. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3747. (TX_TSS_CID << 7));
  3748. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3749. }
  3750. cp->tx_cons = *cp->tx_cons_ptr;
  3751. cid_addr = GET_CID_ADDR(tx_cid);
  3752. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3753. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3754. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3755. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3756. offset0 = BNX2_L2CTX_TYPE_XI;
  3757. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3758. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3759. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3760. } else {
  3761. cnic_init_context(dev, tx_cid);
  3762. cnic_init_context(dev, tx_cid + 1);
  3763. offset0 = BNX2_L2CTX_TYPE;
  3764. offset1 = BNX2_L2CTX_CMD_TYPE;
  3765. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3766. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3767. }
  3768. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3769. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3770. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3771. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3772. txbd = udev->l2_ring;
  3773. buf_map = udev->l2_buf_map;
  3774. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3775. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3776. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3777. }
  3778. val = (u64) ring_map >> 32;
  3779. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3780. txbd->tx_bd_haddr_hi = val;
  3781. val = (u64) ring_map & 0xffffffff;
  3782. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3783. txbd->tx_bd_haddr_lo = val;
  3784. }
  3785. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3786. {
  3787. struct cnic_local *cp = dev->cnic_priv;
  3788. struct cnic_eth_dev *ethdev = cp->ethdev;
  3789. struct cnic_uio_dev *udev = cp->udev;
  3790. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3791. int i;
  3792. struct bnx2_rx_bd *rxbd;
  3793. struct status_block *s_blk = cp->status_blk.gen;
  3794. dma_addr_t ring_map = udev->l2_ring_map;
  3795. sb_id = cp->status_blk_num;
  3796. cnic_init_context(dev, 2);
  3797. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3798. coal_reg = BNX2_HC_COMMAND;
  3799. coal_val = CNIC_RD(dev, coal_reg);
  3800. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3801. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3802. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3803. coal_reg = BNX2_HC_COALESCE_NOW;
  3804. coal_val = 1 << (11 + sb_id);
  3805. }
  3806. i = 0;
  3807. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3808. CNIC_WR(dev, coal_reg, coal_val);
  3809. udelay(10);
  3810. i++;
  3811. barrier();
  3812. }
  3813. cp->rx_cons = *cp->rx_cons_ptr;
  3814. cid_addr = GET_CID_ADDR(2);
  3815. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3816. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3817. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3818. if (sb_id == 0)
  3819. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3820. else
  3821. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3822. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3823. rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
  3824. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3825. dma_addr_t buf_map;
  3826. int n = (i % cp->l2_rx_ring_size) + 1;
  3827. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3828. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3829. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3830. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3831. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3832. }
  3833. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  3834. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3835. rxbd->rx_bd_haddr_hi = val;
  3836. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  3837. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3838. rxbd->rx_bd_haddr_lo = val;
  3839. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3840. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3841. }
  3842. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3843. {
  3844. struct kwqe *wqes[1], l2kwqe;
  3845. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3846. wqes[0] = &l2kwqe;
  3847. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3848. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3849. KWQE_OPCODE_SHIFT) | 2;
  3850. dev->submit_kwqes(dev, wqes, 1);
  3851. }
  3852. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3853. {
  3854. struct cnic_local *cp = dev->cnic_priv;
  3855. u32 val;
  3856. val = cp->func << 2;
  3857. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3858. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3859. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3860. dev->mac_addr[0] = (u8) (val >> 8);
  3861. dev->mac_addr[1] = (u8) val;
  3862. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3863. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3864. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3865. dev->mac_addr[2] = (u8) (val >> 24);
  3866. dev->mac_addr[3] = (u8) (val >> 16);
  3867. dev->mac_addr[4] = (u8) (val >> 8);
  3868. dev->mac_addr[5] = (u8) val;
  3869. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3870. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3871. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3872. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3873. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3874. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3875. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3876. }
  3877. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3878. {
  3879. struct cnic_local *cp = dev->cnic_priv;
  3880. struct cnic_eth_dev *ethdev = cp->ethdev;
  3881. struct status_block *sblk = cp->status_blk.gen;
  3882. u32 val, kcq_cid_addr, kwq_cid_addr;
  3883. int err;
  3884. cnic_set_bnx2_mac(dev);
  3885. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3886. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3887. if (CNIC_PAGE_BITS > 12)
  3888. val |= (12 - 8) << 4;
  3889. else
  3890. val |= (CNIC_PAGE_BITS - 8) << 4;
  3891. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3892. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3893. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3894. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3895. err = cnic_setup_5709_context(dev, 1);
  3896. if (err)
  3897. return err;
  3898. cnic_init_context(dev, KWQ_CID);
  3899. cnic_init_context(dev, KCQ_CID);
  3900. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3901. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3902. cp->max_kwq_idx = MAX_KWQ_IDX;
  3903. cp->kwq_prod_idx = 0;
  3904. cp->kwq_con_idx = 0;
  3905. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3906. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3907. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3908. else
  3909. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3910. /* Initialize the kernel work queue context. */
  3911. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3912. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3913. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3914. val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3915. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3916. val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3917. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3918. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3919. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3920. val = (u32) cp->kwq_info.pgtbl_map;
  3921. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3922. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3923. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3924. cp->kcq1.sw_prod_idx = 0;
  3925. cp->kcq1.hw_prod_idx_ptr =
  3926. &sblk->status_completion_producer_index;
  3927. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3928. /* Initialize the kernel complete queue context. */
  3929. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3930. (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3931. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3932. val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3933. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3934. val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3935. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3936. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3937. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3938. val = (u32) cp->kcq1.dma.pgtbl_map;
  3939. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3940. cp->int_num = 0;
  3941. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3942. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3943. u32 sb_id = cp->status_blk_num;
  3944. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3945. cp->kcq1.hw_prod_idx_ptr =
  3946. &msblk->status_completion_producer_index;
  3947. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3948. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3949. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3950. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3951. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3952. }
  3953. /* Enable Commnad Scheduler notification when we write to the
  3954. * host producer index of the kernel contexts. */
  3955. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3956. /* Enable Command Scheduler notification when we write to either
  3957. * the Send Queue or Receive Queue producer indexes of the kernel
  3958. * bypass contexts. */
  3959. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3960. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3961. /* Notify COM when the driver post an application buffer. */
  3962. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3963. /* Set the CP and COM doorbells. These two processors polls the
  3964. * doorbell for a non zero value before running. This must be done
  3965. * after setting up the kernel queue contexts. */
  3966. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3967. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3968. cnic_init_bnx2_tx_ring(dev);
  3969. cnic_init_bnx2_rx_ring(dev);
  3970. err = cnic_init_bnx2_irq(dev);
  3971. if (err) {
  3972. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3973. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3974. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3975. return err;
  3976. }
  3977. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3978. return 0;
  3979. }
  3980. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3981. {
  3982. struct cnic_local *cp = dev->cnic_priv;
  3983. struct cnic_eth_dev *ethdev = cp->ethdev;
  3984. u32 start_offset = ethdev->ctx_tbl_offset;
  3985. int i;
  3986. for (i = 0; i < cp->ctx_blks; i++) {
  3987. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3988. dma_addr_t map = ctx->mapping;
  3989. if (cp->ctx_align) {
  3990. unsigned long mask = cp->ctx_align - 1;
  3991. map = (map + mask) & ~mask;
  3992. }
  3993. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3994. }
  3995. }
  3996. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3997. {
  3998. struct cnic_local *cp = dev->cnic_priv;
  3999. struct cnic_eth_dev *ethdev = cp->ethdev;
  4000. int err = 0;
  4001. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  4002. (unsigned long) dev);
  4003. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4004. err = cnic_request_irq(dev);
  4005. return err;
  4006. }
  4007. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4008. u16 sb_id, u8 sb_index,
  4009. u8 disable)
  4010. {
  4011. struct bnx2x *bp = netdev_priv(dev->netdev);
  4012. u32 addr = BAR_CSTRORM_INTMEM +
  4013. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4014. offsetof(struct hc_status_block_data_e1x, index_data) +
  4015. sizeof(struct hc_index_data)*sb_index +
  4016. offsetof(struct hc_index_data, flags);
  4017. u16 flags = CNIC_RD16(dev, addr);
  4018. /* clear and set */
  4019. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4020. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4021. HC_INDEX_DATA_HC_ENABLED);
  4022. CNIC_WR16(dev, addr, flags);
  4023. }
  4024. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4025. {
  4026. struct cnic_local *cp = dev->cnic_priv;
  4027. struct bnx2x *bp = netdev_priv(dev->netdev);
  4028. u8 sb_id = cp->status_blk_num;
  4029. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4030. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4031. offsetof(struct hc_status_block_data_e1x, index_data) +
  4032. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4033. offsetof(struct hc_index_data, timeout), 64 / 4);
  4034. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4035. }
  4036. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4037. {
  4038. }
  4039. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4040. struct client_init_ramrod_data *data)
  4041. {
  4042. struct cnic_local *cp = dev->cnic_priv;
  4043. struct bnx2x *bp = netdev_priv(dev->netdev);
  4044. struct cnic_uio_dev *udev = cp->udev;
  4045. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4046. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4047. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4048. int i;
  4049. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4050. u32 val;
  4051. memset(txbd, 0, CNIC_PAGE_SIZE);
  4052. buf_map = udev->l2_buf_map;
  4053. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4054. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4055. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4056. &((txbd + 1)->parse_bd_e1x);
  4057. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4058. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4059. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4060. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4061. reg_bd->addr_hi = start_bd->addr_hi;
  4062. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4063. start_bd->nbytes = cpu_to_le16(0x10);
  4064. start_bd->nbd = cpu_to_le16(3);
  4065. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4066. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4067. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4068. if (BNX2X_CHIP_IS_E2_PLUS(bp))
  4069. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4070. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4071. else
  4072. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4073. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4074. }
  4075. val = (u64) ring_map >> 32;
  4076. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4077. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4078. val = (u64) ring_map & 0xffffffff;
  4079. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4080. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4081. /* Other ramrod params */
  4082. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4083. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4084. /* reset xstorm per client statistics */
  4085. if (cli < MAX_STAT_COUNTER_ID) {
  4086. data->general.statistics_zero_flg = 1;
  4087. data->general.statistics_en_flg = 1;
  4088. data->general.statistics_counter_id = cli;
  4089. }
  4090. cp->tx_cons_ptr =
  4091. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4092. }
  4093. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4094. struct client_init_ramrod_data *data)
  4095. {
  4096. struct cnic_local *cp = dev->cnic_priv;
  4097. struct bnx2x *bp = netdev_priv(dev->netdev);
  4098. struct cnic_uio_dev *udev = cp->udev;
  4099. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4100. CNIC_PAGE_SIZE);
  4101. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4102. (udev->l2_ring + (2 * CNIC_PAGE_SIZE));
  4103. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4104. int i;
  4105. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4106. int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4107. u32 val;
  4108. dma_addr_t ring_map = udev->l2_ring_map;
  4109. /* General data */
  4110. data->general.client_id = cli;
  4111. data->general.activate_flg = 1;
  4112. data->general.sp_client_id = cli;
  4113. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4114. data->general.func_id = bp->pfid;
  4115. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4116. dma_addr_t buf_map;
  4117. int n = (i % cp->l2_rx_ring_size) + 1;
  4118. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4119. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4120. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4121. }
  4122. val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
  4123. rxbd->addr_hi = cpu_to_le32(val);
  4124. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4125. val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
  4126. rxbd->addr_lo = cpu_to_le32(val);
  4127. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4128. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4129. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
  4130. rxcqe->addr_hi = cpu_to_le32(val);
  4131. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4132. val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
  4133. rxcqe->addr_lo = cpu_to_le32(val);
  4134. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4135. /* Other ramrod params */
  4136. data->rx.client_qzone_id = cl_qzone_id;
  4137. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4138. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4139. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4140. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4141. data->rx.outer_vlan_removal_enable_flg = 1;
  4142. data->rx.silent_vlan_removal_flg = 1;
  4143. data->rx.silent_vlan_value = 0;
  4144. data->rx.silent_vlan_mask = 0xffff;
  4145. cp->rx_cons_ptr =
  4146. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4147. cp->rx_cons = *cp->rx_cons_ptr;
  4148. }
  4149. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4150. {
  4151. struct cnic_local *cp = dev->cnic_priv;
  4152. struct bnx2x *bp = netdev_priv(dev->netdev);
  4153. u32 pfid = bp->pfid;
  4154. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4155. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4156. cp->kcq1.sw_prod_idx = 0;
  4157. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4158. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4159. cp->kcq1.hw_prod_idx_ptr =
  4160. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4161. cp->kcq1.status_idx_ptr =
  4162. &sb->sb.running_index[SM_RX_ID];
  4163. } else {
  4164. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4165. cp->kcq1.hw_prod_idx_ptr =
  4166. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4167. cp->kcq1.status_idx_ptr =
  4168. &sb->sb.running_index[SM_RX_ID];
  4169. }
  4170. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4171. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4172. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4173. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4174. cp->kcq2.sw_prod_idx = 0;
  4175. cp->kcq2.hw_prod_idx_ptr =
  4176. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4177. cp->kcq2.status_idx_ptr =
  4178. &sb->sb.running_index[SM_RX_ID];
  4179. }
  4180. }
  4181. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4182. {
  4183. struct cnic_local *cp = dev->cnic_priv;
  4184. struct bnx2x *bp = netdev_priv(dev->netdev);
  4185. struct cnic_eth_dev *ethdev = cp->ethdev;
  4186. int func, ret;
  4187. u32 pfid;
  4188. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4189. cp->func = bp->pf_num;
  4190. func = CNIC_FUNC(cp);
  4191. pfid = bp->pfid;
  4192. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4193. cp->iscsi_start_cid, 0);
  4194. if (ret)
  4195. return -ENOMEM;
  4196. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4197. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4198. cp->fcoe_start_cid, 0);
  4199. if (ret)
  4200. return -ENOMEM;
  4201. }
  4202. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4203. cnic_init_bnx2x_kcq(dev);
  4204. /* Only 1 EQ */
  4205. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4206. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4207. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4208. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4209. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4210. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4211. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4212. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4213. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4214. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4215. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4216. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4217. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4218. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4219. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4220. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4221. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4222. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4223. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4224. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4225. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4226. HC_INDEX_ISCSI_EQ_CONS);
  4227. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4228. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4229. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4230. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4231. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4232. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4233. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4234. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4235. cnic_setup_bnx2x_context(dev);
  4236. ret = cnic_init_bnx2x_irq(dev);
  4237. if (ret)
  4238. return ret;
  4239. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4240. return 0;
  4241. }
  4242. static void cnic_init_rings(struct cnic_dev *dev)
  4243. {
  4244. struct cnic_local *cp = dev->cnic_priv;
  4245. struct bnx2x *bp = netdev_priv(dev->netdev);
  4246. struct cnic_uio_dev *udev = cp->udev;
  4247. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4248. return;
  4249. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4250. cnic_init_bnx2_tx_ring(dev);
  4251. cnic_init_bnx2_rx_ring(dev);
  4252. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4253. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4254. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4255. u32 cid = cp->ethdev->iscsi_l2_cid;
  4256. u32 cl_qzone_id;
  4257. struct client_init_ramrod_data *data;
  4258. union l5cm_specific_data l5_data;
  4259. struct ustorm_eth_rx_producers rx_prods = {0};
  4260. u32 off, i, *cid_ptr;
  4261. rx_prods.bd_prod = 0;
  4262. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4263. barrier();
  4264. cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
  4265. off = BAR_USTRORM_INTMEM +
  4266. (BNX2X_CHIP_IS_E2_PLUS(bp) ?
  4267. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4268. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
  4269. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4270. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4271. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4272. data = udev->l2_buf;
  4273. cid_ptr = udev->l2_buf + 12;
  4274. memset(data, 0, sizeof(*data));
  4275. cnic_init_bnx2x_tx_ring(dev, data);
  4276. cnic_init_bnx2x_rx_ring(dev, data);
  4277. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4278. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4279. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4280. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4281. cid, ETH_CONNECTION_TYPE, &l5_data);
  4282. i = 0;
  4283. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4284. ++i < 10)
  4285. msleep(1);
  4286. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4287. netdev_err(dev->netdev,
  4288. "iSCSI CLIENT_SETUP did not complete\n");
  4289. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4290. cnic_ring_ctl(dev, cid, cli, 1);
  4291. *cid_ptr = cid >> 4;
  4292. *(cid_ptr + 1) = cid * bp->db_size;
  4293. *(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
  4294. }
  4295. }
  4296. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4297. {
  4298. struct cnic_local *cp = dev->cnic_priv;
  4299. struct cnic_uio_dev *udev = cp->udev;
  4300. void *rx_ring;
  4301. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4302. return;
  4303. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4304. cnic_shutdown_bnx2_rx_ring(dev);
  4305. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4306. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4307. u32 cid = cp->ethdev->iscsi_l2_cid;
  4308. union l5cm_specific_data l5_data;
  4309. int i;
  4310. cnic_ring_ctl(dev, cid, cli, 0);
  4311. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4312. l5_data.phy_address.lo = cli;
  4313. l5_data.phy_address.hi = 0;
  4314. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4315. cid, ETH_CONNECTION_TYPE, &l5_data);
  4316. i = 0;
  4317. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4318. ++i < 10)
  4319. msleep(1);
  4320. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4321. netdev_err(dev->netdev,
  4322. "iSCSI CLIENT_HALT did not complete\n");
  4323. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4324. memset(&l5_data, 0, sizeof(l5_data));
  4325. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4326. cid, NONE_CONNECTION_TYPE, &l5_data);
  4327. msleep(10);
  4328. }
  4329. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4330. rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
  4331. memset(rx_ring, 0, CNIC_PAGE_SIZE);
  4332. }
  4333. static int cnic_register_netdev(struct cnic_dev *dev)
  4334. {
  4335. struct cnic_local *cp = dev->cnic_priv;
  4336. struct cnic_eth_dev *ethdev = cp->ethdev;
  4337. int err;
  4338. if (!ethdev)
  4339. return -ENODEV;
  4340. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4341. return 0;
  4342. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4343. if (err)
  4344. netdev_err(dev->netdev, "register_cnic failed\n");
  4345. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4346. * can change after firmware is downloaded.
  4347. */
  4348. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4349. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4350. dev->max_iscsi_conn = 0;
  4351. return err;
  4352. }
  4353. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4354. {
  4355. struct cnic_local *cp = dev->cnic_priv;
  4356. struct cnic_eth_dev *ethdev = cp->ethdev;
  4357. if (!ethdev)
  4358. return;
  4359. ethdev->drv_unregister_cnic(dev->netdev);
  4360. }
  4361. static int cnic_start_hw(struct cnic_dev *dev)
  4362. {
  4363. struct cnic_local *cp = dev->cnic_priv;
  4364. struct cnic_eth_dev *ethdev = cp->ethdev;
  4365. int err;
  4366. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4367. return -EALREADY;
  4368. dev->regview = ethdev->io_base;
  4369. pci_dev_get(dev->pcidev);
  4370. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4371. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4372. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4373. err = cp->alloc_resc(dev);
  4374. if (err) {
  4375. netdev_err(dev->netdev, "allocate resource failure\n");
  4376. goto err1;
  4377. }
  4378. err = cp->start_hw(dev);
  4379. if (err)
  4380. goto err1;
  4381. err = cnic_cm_open(dev);
  4382. if (err)
  4383. goto err1;
  4384. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4385. cp->enable_int(dev);
  4386. return 0;
  4387. err1:
  4388. cp->free_resc(dev);
  4389. pci_dev_put(dev->pcidev);
  4390. return err;
  4391. }
  4392. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4393. {
  4394. cnic_disable_bnx2_int_sync(dev);
  4395. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4396. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4397. cnic_init_context(dev, KWQ_CID);
  4398. cnic_init_context(dev, KCQ_CID);
  4399. cnic_setup_5709_context(dev, 0);
  4400. cnic_free_irq(dev);
  4401. cnic_free_resc(dev);
  4402. }
  4403. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4404. {
  4405. struct cnic_local *cp = dev->cnic_priv;
  4406. struct bnx2x *bp = netdev_priv(dev->netdev);
  4407. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4408. u32 sb_id = cp->status_blk_num;
  4409. u32 idx_off, syn_off;
  4410. cnic_free_irq(dev);
  4411. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4412. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4413. (hc_index * sizeof(u16));
  4414. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4415. } else {
  4416. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4417. (hc_index * sizeof(u16));
  4418. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4419. }
  4420. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4421. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4422. idx_off, 0);
  4423. *cp->kcq1.hw_prod_idx_ptr = 0;
  4424. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4425. CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
  4426. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4427. cnic_free_resc(dev);
  4428. }
  4429. static void cnic_stop_hw(struct cnic_dev *dev)
  4430. {
  4431. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4432. struct cnic_local *cp = dev->cnic_priv;
  4433. int i = 0;
  4434. /* Need to wait for the ring shutdown event to complete
  4435. * before clearing the CNIC_UP flag.
  4436. */
  4437. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4438. msleep(100);
  4439. i++;
  4440. }
  4441. cnic_shutdown_rings(dev);
  4442. cp->stop_cm(dev);
  4443. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4444. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4445. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4446. synchronize_rcu();
  4447. cnic_cm_shutdown(dev);
  4448. cp->stop_hw(dev);
  4449. pci_dev_put(dev->pcidev);
  4450. }
  4451. }
  4452. static void cnic_free_dev(struct cnic_dev *dev)
  4453. {
  4454. int i = 0;
  4455. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4456. msleep(100);
  4457. i++;
  4458. }
  4459. if (atomic_read(&dev->ref_count) != 0)
  4460. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4461. netdev_info(dev->netdev, "Removed CNIC device\n");
  4462. dev_put(dev->netdev);
  4463. kfree(dev);
  4464. }
  4465. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4466. struct pci_dev *pdev)
  4467. {
  4468. struct cnic_dev *cdev;
  4469. struct cnic_local *cp;
  4470. int alloc_size;
  4471. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4472. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4473. if (cdev == NULL)
  4474. return NULL;
  4475. cdev->netdev = dev;
  4476. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4477. cdev->register_device = cnic_register_device;
  4478. cdev->unregister_device = cnic_unregister_device;
  4479. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4480. cp = cdev->cnic_priv;
  4481. cp->dev = cdev;
  4482. cp->l2_single_buf_size = 0x400;
  4483. cp->l2_rx_ring_size = 3;
  4484. spin_lock_init(&cp->cnic_ulp_lock);
  4485. netdev_info(dev, "Added CNIC device\n");
  4486. return cdev;
  4487. }
  4488. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4489. {
  4490. struct pci_dev *pdev;
  4491. struct cnic_dev *cdev;
  4492. struct cnic_local *cp;
  4493. struct bnx2 *bp = netdev_priv(dev);
  4494. struct cnic_eth_dev *ethdev = NULL;
  4495. if (bp->cnic_probe)
  4496. ethdev = (bp->cnic_probe)(dev);
  4497. if (!ethdev)
  4498. return NULL;
  4499. pdev = ethdev->pdev;
  4500. if (!pdev)
  4501. return NULL;
  4502. dev_hold(dev);
  4503. pci_dev_get(pdev);
  4504. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4505. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4506. (pdev->revision < 0x10)) {
  4507. pci_dev_put(pdev);
  4508. goto cnic_err;
  4509. }
  4510. pci_dev_put(pdev);
  4511. cdev = cnic_alloc_dev(dev, pdev);
  4512. if (cdev == NULL)
  4513. goto cnic_err;
  4514. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4515. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4516. cp = cdev->cnic_priv;
  4517. cp->ethdev = ethdev;
  4518. cdev->pcidev = pdev;
  4519. cp->chip_id = ethdev->chip_id;
  4520. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4521. cp->cnic_ops = &cnic_bnx2_ops;
  4522. cp->start_hw = cnic_start_bnx2_hw;
  4523. cp->stop_hw = cnic_stop_bnx2_hw;
  4524. cp->setup_pgtbl = cnic_setup_page_tbl;
  4525. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4526. cp->free_resc = cnic_free_resc;
  4527. cp->start_cm = cnic_cm_init_bnx2_hw;
  4528. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4529. cp->enable_int = cnic_enable_bnx2_int;
  4530. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4531. cp->close_conn = cnic_close_bnx2_conn;
  4532. return cdev;
  4533. cnic_err:
  4534. dev_put(dev);
  4535. return NULL;
  4536. }
  4537. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4538. {
  4539. struct pci_dev *pdev;
  4540. struct cnic_dev *cdev;
  4541. struct cnic_local *cp;
  4542. struct bnx2x *bp = netdev_priv(dev);
  4543. struct cnic_eth_dev *ethdev = NULL;
  4544. if (bp->cnic_probe)
  4545. ethdev = bp->cnic_probe(dev);
  4546. if (!ethdev)
  4547. return NULL;
  4548. pdev = ethdev->pdev;
  4549. if (!pdev)
  4550. return NULL;
  4551. dev_hold(dev);
  4552. cdev = cnic_alloc_dev(dev, pdev);
  4553. if (cdev == NULL) {
  4554. dev_put(dev);
  4555. return NULL;
  4556. }
  4557. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4558. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4559. cp = cdev->cnic_priv;
  4560. cp->ethdev = ethdev;
  4561. cdev->pcidev = pdev;
  4562. cp->chip_id = ethdev->chip_id;
  4563. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4564. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4565. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4566. if (CNIC_SUPPORTS_FCOE(bp)) {
  4567. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4568. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4569. }
  4570. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4571. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4572. memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
  4573. cp->cnic_ops = &cnic_bnx2x_ops;
  4574. cp->start_hw = cnic_start_bnx2x_hw;
  4575. cp->stop_hw = cnic_stop_bnx2x_hw;
  4576. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4577. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4578. cp->free_resc = cnic_free_resc;
  4579. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4580. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4581. cp->enable_int = cnic_enable_bnx2x_int;
  4582. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4583. if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
  4584. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4585. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4586. } else {
  4587. cp->ack_int = cnic_ack_bnx2x_msix;
  4588. cp->arm_int = cnic_arm_bnx2x_msix;
  4589. }
  4590. cp->close_conn = cnic_close_bnx2x_conn;
  4591. return cdev;
  4592. }
  4593. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4594. {
  4595. struct ethtool_drvinfo drvinfo;
  4596. struct cnic_dev *cdev = NULL;
  4597. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4598. memset(&drvinfo, 0, sizeof(drvinfo));
  4599. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4600. if (!strcmp(drvinfo.driver, "bnx2"))
  4601. cdev = init_bnx2_cnic(dev);
  4602. if (!strcmp(drvinfo.driver, "bnx2x"))
  4603. cdev = init_bnx2x_cnic(dev);
  4604. if (cdev) {
  4605. write_lock(&cnic_dev_lock);
  4606. list_add(&cdev->list, &cnic_dev_list);
  4607. write_unlock(&cnic_dev_lock);
  4608. }
  4609. }
  4610. return cdev;
  4611. }
  4612. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4613. u16 vlan_id)
  4614. {
  4615. int if_type;
  4616. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4617. struct cnic_ulp_ops *ulp_ops;
  4618. void *ctx;
  4619. mutex_lock(&cnic_lock);
  4620. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  4621. lockdep_is_held(&cnic_lock));
  4622. if (!ulp_ops || !ulp_ops->indicate_netevent) {
  4623. mutex_unlock(&cnic_lock);
  4624. continue;
  4625. }
  4626. ctx = cp->ulp_handle[if_type];
  4627. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4628. mutex_unlock(&cnic_lock);
  4629. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4630. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  4631. }
  4632. }
  4633. /* netdev event handler */
  4634. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4635. void *ptr)
  4636. {
  4637. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4638. struct cnic_dev *dev;
  4639. int new_dev = 0;
  4640. dev = cnic_from_netdev(netdev);
  4641. if (!dev && event == NETDEV_REGISTER) {
  4642. /* Check for the hot-plug device */
  4643. dev = is_cnic_dev(netdev);
  4644. if (dev) {
  4645. new_dev = 1;
  4646. cnic_hold(dev);
  4647. }
  4648. }
  4649. if (dev) {
  4650. struct cnic_local *cp = dev->cnic_priv;
  4651. if (new_dev)
  4652. cnic_ulp_init(dev);
  4653. else if (event == NETDEV_UNREGISTER)
  4654. cnic_ulp_exit(dev);
  4655. if (event == NETDEV_UP) {
  4656. if (cnic_register_netdev(dev) != 0) {
  4657. cnic_put(dev);
  4658. goto done;
  4659. }
  4660. if (!cnic_start_hw(dev))
  4661. cnic_ulp_start(dev);
  4662. }
  4663. cnic_rcv_netevent(cp, event, 0);
  4664. if (event == NETDEV_GOING_DOWN) {
  4665. cnic_ulp_stop(dev);
  4666. cnic_stop_hw(dev);
  4667. cnic_unregister_netdev(dev);
  4668. } else if (event == NETDEV_UNREGISTER) {
  4669. write_lock(&cnic_dev_lock);
  4670. list_del_init(&dev->list);
  4671. write_unlock(&cnic_dev_lock);
  4672. cnic_put(dev);
  4673. cnic_free_dev(dev);
  4674. goto done;
  4675. }
  4676. cnic_put(dev);
  4677. } else {
  4678. struct net_device *realdev;
  4679. u16 vid;
  4680. vid = cnic_get_vlan(netdev, &realdev);
  4681. if (realdev) {
  4682. dev = cnic_from_netdev(realdev);
  4683. if (dev) {
  4684. vid |= VLAN_TAG_PRESENT;
  4685. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4686. cnic_put(dev);
  4687. }
  4688. }
  4689. }
  4690. done:
  4691. return NOTIFY_DONE;
  4692. }
  4693. static struct notifier_block cnic_netdev_notifier = {
  4694. .notifier_call = cnic_netdev_event
  4695. };
  4696. static void cnic_release(void)
  4697. {
  4698. struct cnic_uio_dev *udev;
  4699. while (!list_empty(&cnic_udev_list)) {
  4700. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4701. list);
  4702. cnic_free_uio(udev);
  4703. }
  4704. }
  4705. static int __init cnic_init(void)
  4706. {
  4707. int rc = 0;
  4708. pr_info("%s", version);
  4709. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4710. if (rc) {
  4711. cnic_release();
  4712. return rc;
  4713. }
  4714. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4715. if (!cnic_wq) {
  4716. cnic_release();
  4717. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4718. return -ENOMEM;
  4719. }
  4720. return 0;
  4721. }
  4722. static void __exit cnic_exit(void)
  4723. {
  4724. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4725. cnic_release();
  4726. destroy_workqueue(cnic_wq);
  4727. }
  4728. module_init(cnic_init);
  4729. module_exit(cnic_exit);