atl1c_main.c 77 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803
  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.1-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static const struct pci_device_id atl1c_pci_tbl[] = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcomm Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u16 atl1c_pay_load_size[] = {
  63. 128, 256, 512, 1024, 2048, 4096,
  64. };
  65. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  66. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  67. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  68. {
  69. u32 mst_data, data;
  70. /* pclk sel could switch to 25M */
  71. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  72. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  73. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  74. /* WoL/PCIE related settings */
  75. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  76. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  77. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  78. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  79. } else { /* new dev set bit5 of MASTER */
  80. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  81. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  82. mst_data | MASTER_CTRL_WAKEN_25M);
  83. }
  84. /* aspm/PCIE setting only for l2cb 1.0 */
  85. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  86. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  87. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  88. L2CB1_PCIE_PHYMISC2_CDR_BW);
  89. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  90. L2CB1_PCIE_PHYMISC2_L0S_TH);
  91. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  92. /* extend L1 sync timer */
  93. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  94. data |= LINK_CTRL_EXT_SYNC;
  95. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  96. }
  97. /* l2cb 1.x & l1d 1.x */
  98. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  99. AT_READ_REG(hw, REG_PM_CTRL, &data);
  100. data |= PM_CTRL_L0S_BUFSRX_EN;
  101. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  102. /* clear vendor msg */
  103. AT_READ_REG(hw, REG_DMA_DBG, &data);
  104. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  105. }
  106. }
  107. /* FIXME: no need any more ? */
  108. /*
  109. * atl1c_init_pcie - init PCIE module
  110. */
  111. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  112. {
  113. u32 data;
  114. u32 pci_cmd;
  115. struct pci_dev *pdev = hw->adapter->pdev;
  116. int pos;
  117. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  118. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  119. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  120. PCI_COMMAND_IO);
  121. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  122. /*
  123. * Clear any PowerSaveing Settings
  124. */
  125. pci_enable_wake(pdev, PCI_D3hot, 0);
  126. pci_enable_wake(pdev, PCI_D3cold, 0);
  127. /* wol sts read-clear */
  128. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  129. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  130. /*
  131. * Mask some pcie error bits
  132. */
  133. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  134. if (pos) {
  135. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  136. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  137. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  138. }
  139. /* clear error status */
  140. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
  141. PCI_EXP_DEVSTA_NFED |
  142. PCI_EXP_DEVSTA_FED |
  143. PCI_EXP_DEVSTA_CED |
  144. PCI_EXP_DEVSTA_URD);
  145. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  146. data &= ~LTSSM_ID_EN_WRO;
  147. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  148. atl1c_pcie_patch(hw);
  149. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  150. atl1c_disable_l0s_l1(hw);
  151. msleep(5);
  152. }
  153. /**
  154. * atl1c_irq_enable - Enable default interrupt generation settings
  155. * @adapter: board private structure
  156. */
  157. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  158. {
  159. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  160. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  161. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  162. AT_WRITE_FLUSH(&adapter->hw);
  163. }
  164. }
  165. /**
  166. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  167. * @adapter: board private structure
  168. */
  169. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  170. {
  171. atomic_inc(&adapter->irq_sem);
  172. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  173. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  174. AT_WRITE_FLUSH(&adapter->hw);
  175. synchronize_irq(adapter->pdev->irq);
  176. }
  177. /**
  178. * atl1c_irq_reset - reset interrupt confiure on the NIC
  179. * @adapter: board private structure
  180. */
  181. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  182. {
  183. atomic_set(&adapter->irq_sem, 1);
  184. atl1c_irq_enable(adapter);
  185. }
  186. /*
  187. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  188. * of the idle status register until the device is actually idle
  189. */
  190. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  191. {
  192. int timeout;
  193. u32 data;
  194. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  195. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  196. if ((data & modu_ctrl) == 0)
  197. return 0;
  198. msleep(1);
  199. }
  200. return data;
  201. }
  202. /**
  203. * atl1c_phy_config - Timer Call-back
  204. * @data: pointer to netdev cast into an unsigned long
  205. */
  206. static void atl1c_phy_config(unsigned long data)
  207. {
  208. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  209. struct atl1c_hw *hw = &adapter->hw;
  210. unsigned long flags;
  211. spin_lock_irqsave(&adapter->mdio_lock, flags);
  212. atl1c_restart_autoneg(hw);
  213. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  214. }
  215. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  216. {
  217. WARN_ON(in_interrupt());
  218. atl1c_down(adapter);
  219. atl1c_up(adapter);
  220. clear_bit(__AT_RESETTING, &adapter->flags);
  221. }
  222. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  223. {
  224. struct atl1c_hw *hw = &adapter->hw;
  225. struct net_device *netdev = adapter->netdev;
  226. struct pci_dev *pdev = adapter->pdev;
  227. int err;
  228. unsigned long flags;
  229. u16 speed, duplex, phy_data;
  230. spin_lock_irqsave(&adapter->mdio_lock, flags);
  231. /* MII_BMSR must read twise */
  232. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  233. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  234. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  235. if ((phy_data & BMSR_LSTATUS) == 0) {
  236. /* link down */
  237. netif_carrier_off(netdev);
  238. hw->hibernate = true;
  239. if (atl1c_reset_mac(hw) != 0)
  240. if (netif_msg_hw(adapter))
  241. dev_warn(&pdev->dev, "reset mac failed\n");
  242. atl1c_set_aspm(hw, SPEED_0);
  243. atl1c_post_phy_linkchg(hw, SPEED_0);
  244. atl1c_reset_dma_ring(adapter);
  245. atl1c_configure(adapter);
  246. } else {
  247. /* Link Up */
  248. hw->hibernate = false;
  249. spin_lock_irqsave(&adapter->mdio_lock, flags);
  250. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  251. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  252. if (unlikely(err))
  253. return;
  254. /* link result is our setting */
  255. if (adapter->link_speed != speed ||
  256. adapter->link_duplex != duplex) {
  257. adapter->link_speed = speed;
  258. adapter->link_duplex = duplex;
  259. atl1c_set_aspm(hw, speed);
  260. atl1c_post_phy_linkchg(hw, speed);
  261. atl1c_start_mac(adapter);
  262. if (netif_msg_link(adapter))
  263. dev_info(&pdev->dev,
  264. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  265. atl1c_driver_name, netdev->name,
  266. adapter->link_speed,
  267. adapter->link_duplex == FULL_DUPLEX ?
  268. "Full Duplex" : "Half Duplex");
  269. }
  270. if (!netif_carrier_ok(netdev))
  271. netif_carrier_on(netdev);
  272. }
  273. }
  274. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  275. {
  276. struct net_device *netdev = adapter->netdev;
  277. struct pci_dev *pdev = adapter->pdev;
  278. u16 phy_data;
  279. u16 link_up;
  280. spin_lock(&adapter->mdio_lock);
  281. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  282. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  283. spin_unlock(&adapter->mdio_lock);
  284. link_up = phy_data & BMSR_LSTATUS;
  285. /* notify upper layer link down ASAP */
  286. if (!link_up) {
  287. if (netif_carrier_ok(netdev)) {
  288. /* old link state: Up */
  289. netif_carrier_off(netdev);
  290. if (netif_msg_link(adapter))
  291. dev_info(&pdev->dev,
  292. "%s: %s NIC Link is Down\n",
  293. atl1c_driver_name, netdev->name);
  294. adapter->link_speed = SPEED_0;
  295. }
  296. }
  297. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  298. schedule_work(&adapter->common_task);
  299. }
  300. static void atl1c_common_task(struct work_struct *work)
  301. {
  302. struct atl1c_adapter *adapter;
  303. struct net_device *netdev;
  304. adapter = container_of(work, struct atl1c_adapter, common_task);
  305. netdev = adapter->netdev;
  306. if (test_bit(__AT_DOWN, &adapter->flags))
  307. return;
  308. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  309. netif_device_detach(netdev);
  310. atl1c_down(adapter);
  311. atl1c_up(adapter);
  312. netif_device_attach(netdev);
  313. }
  314. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  315. &adapter->work_event)) {
  316. atl1c_irq_disable(adapter);
  317. atl1c_check_link_status(adapter);
  318. atl1c_irq_enable(adapter);
  319. }
  320. }
  321. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  322. {
  323. del_timer_sync(&adapter->phy_config_timer);
  324. }
  325. /**
  326. * atl1c_tx_timeout - Respond to a Tx Hang
  327. * @netdev: network interface device structure
  328. */
  329. static void atl1c_tx_timeout(struct net_device *netdev)
  330. {
  331. struct atl1c_adapter *adapter = netdev_priv(netdev);
  332. /* Do the reset outside of interrupt context */
  333. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  334. schedule_work(&adapter->common_task);
  335. }
  336. /**
  337. * atl1c_set_multi - Multicast and Promiscuous mode set
  338. * @netdev: network interface device structure
  339. *
  340. * The set_multi entry point is called whenever the multicast address
  341. * list or the network interface flags are updated. This routine is
  342. * responsible for configuring the hardware for proper multicast,
  343. * promiscuous mode, and all-multi behavior.
  344. */
  345. static void atl1c_set_multi(struct net_device *netdev)
  346. {
  347. struct atl1c_adapter *adapter = netdev_priv(netdev);
  348. struct atl1c_hw *hw = &adapter->hw;
  349. struct netdev_hw_addr *ha;
  350. u32 mac_ctrl_data;
  351. u32 hash_value;
  352. /* Check for Promiscuous and All Multicast modes */
  353. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  354. if (netdev->flags & IFF_PROMISC) {
  355. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  356. } else if (netdev->flags & IFF_ALLMULTI) {
  357. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  358. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  359. } else {
  360. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  361. }
  362. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  363. /* clear the old settings from the multicast hash table */
  364. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  365. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  366. /* comoute mc addresses' hash value ,and put it into hash table */
  367. netdev_for_each_mc_addr(ha, netdev) {
  368. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  369. atl1c_hash_set(hw, hash_value);
  370. }
  371. }
  372. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  373. {
  374. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  375. /* enable VLAN tag insert/strip */
  376. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  377. } else {
  378. /* disable VLAN tag insert/strip */
  379. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  380. }
  381. }
  382. static void atl1c_vlan_mode(struct net_device *netdev,
  383. netdev_features_t features)
  384. {
  385. struct atl1c_adapter *adapter = netdev_priv(netdev);
  386. struct pci_dev *pdev = adapter->pdev;
  387. u32 mac_ctrl_data = 0;
  388. if (netif_msg_pktdata(adapter))
  389. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  390. atl1c_irq_disable(adapter);
  391. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  392. __atl1c_vlan_mode(features, &mac_ctrl_data);
  393. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  394. atl1c_irq_enable(adapter);
  395. }
  396. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  397. {
  398. struct pci_dev *pdev = adapter->pdev;
  399. if (netif_msg_pktdata(adapter))
  400. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  401. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  402. }
  403. /**
  404. * atl1c_set_mac - Change the Ethernet Address of the NIC
  405. * @netdev: network interface device structure
  406. * @p: pointer to an address structure
  407. *
  408. * Returns 0 on success, negative on failure
  409. */
  410. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  411. {
  412. struct atl1c_adapter *adapter = netdev_priv(netdev);
  413. struct sockaddr *addr = p;
  414. if (!is_valid_ether_addr(addr->sa_data))
  415. return -EADDRNOTAVAIL;
  416. if (netif_running(netdev))
  417. return -EBUSY;
  418. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  419. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  420. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  421. return 0;
  422. }
  423. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  424. struct net_device *dev)
  425. {
  426. unsigned int head_size;
  427. int mtu = dev->mtu;
  428. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  429. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  430. head_size = SKB_DATA_ALIGN(adapter->rx_buffer_len + NET_SKB_PAD) +
  431. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  432. adapter->rx_frag_size = roundup_pow_of_two(head_size);
  433. }
  434. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  435. netdev_features_t features)
  436. {
  437. /*
  438. * Since there is no support for separate rx/tx vlan accel
  439. * enable/disable make sure tx flag is always in same state as rx.
  440. */
  441. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  442. features |= NETIF_F_HW_VLAN_CTAG_TX;
  443. else
  444. features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  445. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  446. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  447. return features;
  448. }
  449. static int atl1c_set_features(struct net_device *netdev,
  450. netdev_features_t features)
  451. {
  452. netdev_features_t changed = netdev->features ^ features;
  453. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  454. atl1c_vlan_mode(netdev, features);
  455. return 0;
  456. }
  457. /**
  458. * atl1c_change_mtu - Change the Maximum Transfer Unit
  459. * @netdev: network interface device structure
  460. * @new_mtu: new value for maximum frame size
  461. *
  462. * Returns 0 on success, negative on failure
  463. */
  464. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  465. {
  466. struct atl1c_adapter *adapter = netdev_priv(netdev);
  467. struct atl1c_hw *hw = &adapter->hw;
  468. int old_mtu = netdev->mtu;
  469. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  470. /* Fast Ethernet controller doesn't support jumbo packet */
  471. if (((hw->nic_type == athr_l2c ||
  472. hw->nic_type == athr_l2c_b ||
  473. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  474. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  475. max_frame > MAX_JUMBO_FRAME_SIZE) {
  476. if (netif_msg_link(adapter))
  477. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  478. return -EINVAL;
  479. }
  480. /* set MTU */
  481. if (old_mtu != new_mtu && netif_running(netdev)) {
  482. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  483. msleep(1);
  484. netdev->mtu = new_mtu;
  485. adapter->hw.max_frame_size = new_mtu;
  486. atl1c_set_rxbufsize(adapter, netdev);
  487. atl1c_down(adapter);
  488. netdev_update_features(netdev);
  489. atl1c_up(adapter);
  490. clear_bit(__AT_RESETTING, &adapter->flags);
  491. }
  492. return 0;
  493. }
  494. /*
  495. * caller should hold mdio_lock
  496. */
  497. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  498. {
  499. struct atl1c_adapter *adapter = netdev_priv(netdev);
  500. u16 result;
  501. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  502. return result;
  503. }
  504. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  505. int reg_num, int val)
  506. {
  507. struct atl1c_adapter *adapter = netdev_priv(netdev);
  508. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  509. }
  510. static int atl1c_mii_ioctl(struct net_device *netdev,
  511. struct ifreq *ifr, int cmd)
  512. {
  513. struct atl1c_adapter *adapter = netdev_priv(netdev);
  514. struct pci_dev *pdev = adapter->pdev;
  515. struct mii_ioctl_data *data = if_mii(ifr);
  516. unsigned long flags;
  517. int retval = 0;
  518. if (!netif_running(netdev))
  519. return -EINVAL;
  520. spin_lock_irqsave(&adapter->mdio_lock, flags);
  521. switch (cmd) {
  522. case SIOCGMIIPHY:
  523. data->phy_id = 0;
  524. break;
  525. case SIOCGMIIREG:
  526. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  527. &data->val_out)) {
  528. retval = -EIO;
  529. goto out;
  530. }
  531. break;
  532. case SIOCSMIIREG:
  533. if (data->reg_num & ~(0x1F)) {
  534. retval = -EFAULT;
  535. goto out;
  536. }
  537. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  538. data->reg_num, data->val_in);
  539. if (atl1c_write_phy_reg(&adapter->hw,
  540. data->reg_num, data->val_in)) {
  541. retval = -EIO;
  542. goto out;
  543. }
  544. break;
  545. default:
  546. retval = -EOPNOTSUPP;
  547. break;
  548. }
  549. out:
  550. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  551. return retval;
  552. }
  553. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  554. {
  555. switch (cmd) {
  556. case SIOCGMIIPHY:
  557. case SIOCGMIIREG:
  558. case SIOCSMIIREG:
  559. return atl1c_mii_ioctl(netdev, ifr, cmd);
  560. default:
  561. return -EOPNOTSUPP;
  562. }
  563. }
  564. /**
  565. * atl1c_alloc_queues - Allocate memory for all rings
  566. * @adapter: board private structure to initialize
  567. *
  568. */
  569. static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
  570. {
  571. return 0;
  572. }
  573. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  574. {
  575. switch (hw->device_id) {
  576. case PCI_DEVICE_ID_ATTANSIC_L2C:
  577. hw->nic_type = athr_l2c;
  578. break;
  579. case PCI_DEVICE_ID_ATTANSIC_L1C:
  580. hw->nic_type = athr_l1c;
  581. break;
  582. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  583. hw->nic_type = athr_l2c_b;
  584. break;
  585. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  586. hw->nic_type = athr_l2c_b2;
  587. break;
  588. case PCI_DEVICE_ID_ATHEROS_L1D:
  589. hw->nic_type = athr_l1d;
  590. break;
  591. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  592. hw->nic_type = athr_l1d_2;
  593. break;
  594. default:
  595. break;
  596. }
  597. }
  598. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  599. {
  600. u32 link_ctrl_data;
  601. atl1c_set_mac_type(hw);
  602. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  603. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  604. ATL1C_TXQ_MODE_ENHANCE;
  605. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  606. ATL1C_ASPM_L1_SUPPORT;
  607. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  608. if (hw->nic_type == athr_l1c ||
  609. hw->nic_type == athr_l1d ||
  610. hw->nic_type == athr_l1d_2)
  611. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  612. return 0;
  613. }
  614. struct atl1c_platform_patch {
  615. u16 pci_did;
  616. u8 pci_revid;
  617. u16 subsystem_vid;
  618. u16 subsystem_did;
  619. u32 patch_flag;
  620. #define ATL1C_LINK_PATCH 0x1
  621. };
  622. static const struct atl1c_platform_patch plats[] = {
  623. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  624. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  625. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  626. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  627. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  628. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  629. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  630. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  631. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  632. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  633. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  634. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  635. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  636. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  637. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  638. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  639. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  640. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  641. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  642. {0},
  643. };
  644. static void atl1c_patch_assign(struct atl1c_hw *hw)
  645. {
  646. struct pci_dev *pdev = hw->adapter->pdev;
  647. u32 misc_ctrl;
  648. int i = 0;
  649. hw->msi_lnkpatch = false;
  650. while (plats[i].pci_did != 0) {
  651. if (plats[i].pci_did == hw->device_id &&
  652. plats[i].pci_revid == hw->revision_id &&
  653. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  654. plats[i].subsystem_did == hw->subsystem_id) {
  655. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  656. hw->msi_lnkpatch = true;
  657. }
  658. i++;
  659. }
  660. if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
  661. hw->revision_id == L2CB_V21) {
  662. /* config access mode */
  663. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  664. REG_PCIE_DEV_MISC_CTRL);
  665. pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
  666. misc_ctrl &= ~0x100;
  667. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  668. REG_PCIE_DEV_MISC_CTRL);
  669. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
  670. }
  671. }
  672. /**
  673. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  674. * @adapter: board private structure to initialize
  675. *
  676. * atl1c_sw_init initializes the Adapter private data structure.
  677. * Fields are initialized based on PCI device information and
  678. * OS network device settings (MTU size).
  679. */
  680. static int atl1c_sw_init(struct atl1c_adapter *adapter)
  681. {
  682. struct atl1c_hw *hw = &adapter->hw;
  683. struct pci_dev *pdev = adapter->pdev;
  684. u32 revision;
  685. adapter->wol = 0;
  686. device_set_wakeup_enable(&pdev->dev, false);
  687. adapter->link_speed = SPEED_0;
  688. adapter->link_duplex = FULL_DUPLEX;
  689. adapter->tpd_ring[0].count = 1024;
  690. adapter->rfd_ring.count = 512;
  691. hw->vendor_id = pdev->vendor;
  692. hw->device_id = pdev->device;
  693. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  694. hw->subsystem_id = pdev->subsystem_device;
  695. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
  696. hw->revision_id = revision & 0xFF;
  697. /* before link up, we assume hibernate is true */
  698. hw->hibernate = true;
  699. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  700. if (atl1c_setup_mac_funcs(hw) != 0) {
  701. dev_err(&pdev->dev, "set mac function pointers failed\n");
  702. return -1;
  703. }
  704. atl1c_patch_assign(hw);
  705. hw->intr_mask = IMR_NORMAL_MASK;
  706. hw->phy_configured = false;
  707. hw->preamble_len = 7;
  708. hw->max_frame_size = adapter->netdev->mtu;
  709. hw->autoneg_advertised = ADVERTISED_Autoneg;
  710. hw->indirect_tab = 0xE4E4E4E4;
  711. hw->base_cpu = 0;
  712. hw->ict = 50000; /* 100ms */
  713. hw->smb_timer = 200000; /* 400ms */
  714. hw->rx_imt = 200;
  715. hw->tx_imt = 1000;
  716. hw->tpd_burst = 5;
  717. hw->rfd_burst = 8;
  718. hw->dma_order = atl1c_dma_ord_out;
  719. hw->dmar_block = atl1c_dma_req_1024;
  720. if (atl1c_alloc_queues(adapter)) {
  721. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  722. return -ENOMEM;
  723. }
  724. /* TODO */
  725. atl1c_set_rxbufsize(adapter, adapter->netdev);
  726. atomic_set(&adapter->irq_sem, 1);
  727. spin_lock_init(&adapter->mdio_lock);
  728. spin_lock_init(&adapter->tx_lock);
  729. set_bit(__AT_DOWN, &adapter->flags);
  730. return 0;
  731. }
  732. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  733. struct atl1c_buffer *buffer_info)
  734. {
  735. u16 pci_driection;
  736. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  737. return;
  738. if (buffer_info->dma) {
  739. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  740. pci_driection = PCI_DMA_FROMDEVICE;
  741. else
  742. pci_driection = PCI_DMA_TODEVICE;
  743. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  744. pci_unmap_single(pdev, buffer_info->dma,
  745. buffer_info->length, pci_driection);
  746. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  747. pci_unmap_page(pdev, buffer_info->dma,
  748. buffer_info->length, pci_driection);
  749. }
  750. if (buffer_info->skb)
  751. dev_consume_skb_any(buffer_info->skb);
  752. buffer_info->dma = 0;
  753. buffer_info->skb = NULL;
  754. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  755. }
  756. /**
  757. * atl1c_clean_tx_ring - Free Tx-skb
  758. * @adapter: board private structure
  759. */
  760. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  761. enum atl1c_trans_queue type)
  762. {
  763. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  764. struct atl1c_buffer *buffer_info;
  765. struct pci_dev *pdev = adapter->pdev;
  766. u16 index, ring_count;
  767. ring_count = tpd_ring->count;
  768. for (index = 0; index < ring_count; index++) {
  769. buffer_info = &tpd_ring->buffer_info[index];
  770. atl1c_clean_buffer(pdev, buffer_info);
  771. }
  772. /* Zero out Tx-buffers */
  773. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  774. ring_count);
  775. atomic_set(&tpd_ring->next_to_clean, 0);
  776. tpd_ring->next_to_use = 0;
  777. }
  778. /**
  779. * atl1c_clean_rx_ring - Free rx-reservation skbs
  780. * @adapter: board private structure
  781. */
  782. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  783. {
  784. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  785. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  786. struct atl1c_buffer *buffer_info;
  787. struct pci_dev *pdev = adapter->pdev;
  788. int j;
  789. for (j = 0; j < rfd_ring->count; j++) {
  790. buffer_info = &rfd_ring->buffer_info[j];
  791. atl1c_clean_buffer(pdev, buffer_info);
  792. }
  793. /* zero out the descriptor ring */
  794. memset(rfd_ring->desc, 0, rfd_ring->size);
  795. rfd_ring->next_to_clean = 0;
  796. rfd_ring->next_to_use = 0;
  797. rrd_ring->next_to_use = 0;
  798. rrd_ring->next_to_clean = 0;
  799. }
  800. /*
  801. * Read / Write Ptr Initialize:
  802. */
  803. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  804. {
  805. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  806. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  807. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  808. struct atl1c_buffer *buffer_info;
  809. int i, j;
  810. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  811. tpd_ring[i].next_to_use = 0;
  812. atomic_set(&tpd_ring[i].next_to_clean, 0);
  813. buffer_info = tpd_ring[i].buffer_info;
  814. for (j = 0; j < tpd_ring->count; j++)
  815. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  816. ATL1C_BUFFER_FREE);
  817. }
  818. rfd_ring->next_to_use = 0;
  819. rfd_ring->next_to_clean = 0;
  820. rrd_ring->next_to_use = 0;
  821. rrd_ring->next_to_clean = 0;
  822. for (j = 0; j < rfd_ring->count; j++) {
  823. buffer_info = &rfd_ring->buffer_info[j];
  824. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  825. }
  826. }
  827. /**
  828. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  829. * @adapter: board private structure
  830. *
  831. * Free all transmit software resources
  832. */
  833. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  834. {
  835. struct pci_dev *pdev = adapter->pdev;
  836. pci_free_consistent(pdev, adapter->ring_header.size,
  837. adapter->ring_header.desc,
  838. adapter->ring_header.dma);
  839. adapter->ring_header.desc = NULL;
  840. /* Note: just free tdp_ring.buffer_info,
  841. * it contain rfd_ring.buffer_info, do not double free */
  842. if (adapter->tpd_ring[0].buffer_info) {
  843. kfree(adapter->tpd_ring[0].buffer_info);
  844. adapter->tpd_ring[0].buffer_info = NULL;
  845. }
  846. if (adapter->rx_page) {
  847. put_page(adapter->rx_page);
  848. adapter->rx_page = NULL;
  849. }
  850. }
  851. /**
  852. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  853. * @adapter: board private structure
  854. *
  855. * Return 0 on success, negative on failure
  856. */
  857. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  858. {
  859. struct pci_dev *pdev = adapter->pdev;
  860. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  861. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  862. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  863. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  864. int size;
  865. int i;
  866. int count = 0;
  867. int rx_desc_count = 0;
  868. u32 offset = 0;
  869. rrd_ring->count = rfd_ring->count;
  870. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  871. tpd_ring[i].count = tpd_ring[0].count;
  872. /* 2 tpd queue, one high priority queue,
  873. * another normal priority queue */
  874. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  875. rfd_ring->count);
  876. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  877. if (unlikely(!tpd_ring->buffer_info))
  878. goto err_nomem;
  879. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  880. tpd_ring[i].buffer_info =
  881. (tpd_ring->buffer_info + count);
  882. count += tpd_ring[i].count;
  883. }
  884. rfd_ring->buffer_info =
  885. (tpd_ring->buffer_info + count);
  886. count += rfd_ring->count;
  887. rx_desc_count += rfd_ring->count;
  888. /*
  889. * real ring DMA buffer
  890. * each ring/block may need up to 8 bytes for alignment, hence the
  891. * additional bytes tacked onto the end.
  892. */
  893. ring_header->size = size =
  894. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  895. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  896. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  897. 8 * 4;
  898. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  899. &ring_header->dma);
  900. if (unlikely(!ring_header->desc)) {
  901. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  902. goto err_nomem;
  903. }
  904. memset(ring_header->desc, 0, ring_header->size);
  905. /* init TPD ring */
  906. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  907. offset = tpd_ring[0].dma - ring_header->dma;
  908. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  909. tpd_ring[i].dma = ring_header->dma + offset;
  910. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  911. tpd_ring[i].size =
  912. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  913. offset += roundup(tpd_ring[i].size, 8);
  914. }
  915. /* init RFD ring */
  916. rfd_ring->dma = ring_header->dma + offset;
  917. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  918. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  919. offset += roundup(rfd_ring->size, 8);
  920. /* init RRD ring */
  921. rrd_ring->dma = ring_header->dma + offset;
  922. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  923. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  924. rrd_ring->count;
  925. offset += roundup(rrd_ring->size, 8);
  926. return 0;
  927. err_nomem:
  928. kfree(tpd_ring->buffer_info);
  929. return -ENOMEM;
  930. }
  931. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  932. {
  933. struct atl1c_hw *hw = &adapter->hw;
  934. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  935. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  936. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  937. adapter->tpd_ring;
  938. /* TPD */
  939. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  940. (u32)((tpd_ring[atl1c_trans_normal].dma &
  941. AT_DMA_HI_ADDR_MASK) >> 32));
  942. /* just enable normal priority TX queue */
  943. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  944. (u32)(tpd_ring[atl1c_trans_normal].dma &
  945. AT_DMA_LO_ADDR_MASK));
  946. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  947. (u32)(tpd_ring[atl1c_trans_high].dma &
  948. AT_DMA_LO_ADDR_MASK));
  949. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  950. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  951. /* RFD */
  952. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  953. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  954. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  955. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  956. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  957. rfd_ring->count & RFD_RING_SIZE_MASK);
  958. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  959. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  960. /* RRD */
  961. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  962. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  963. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  964. (rrd_ring->count & RRD_RING_SIZE_MASK));
  965. if (hw->nic_type == athr_l2c_b) {
  966. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  967. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  968. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  969. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  970. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  971. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  972. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  973. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  974. }
  975. /* Load all of base address above */
  976. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  977. }
  978. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  979. {
  980. struct atl1c_hw *hw = &adapter->hw;
  981. int max_pay_load;
  982. u16 tx_offload_thresh;
  983. u32 txq_ctrl_data;
  984. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  985. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  986. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  987. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  988. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  989. /*
  990. * if BIOS had changed the dam-read-max-length to an invalid value,
  991. * restore it to default value
  992. */
  993. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  994. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  995. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  996. }
  997. txq_ctrl_data =
  998. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  999. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  1000. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  1001. }
  1002. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  1003. {
  1004. struct atl1c_hw *hw = &adapter->hw;
  1005. u32 rxq_ctrl_data;
  1006. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1007. RXQ_RFD_BURST_NUM_SHIFT;
  1008. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1009. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1010. /* aspm for gigabit */
  1011. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1012. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1013. ASPM_THRUPUT_LIMIT_100M);
  1014. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1015. }
  1016. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1017. {
  1018. struct atl1c_hw *hw = &adapter->hw;
  1019. u32 dma_ctrl_data;
  1020. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1021. DMA_CTRL_RREQ_PRI_DATA |
  1022. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1023. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1024. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1025. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1026. }
  1027. /*
  1028. * Stop the mac, transmit and receive units
  1029. * hw - Struct containing variables accessed by shared code
  1030. * return : 0 or idle status (if error)
  1031. */
  1032. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1033. {
  1034. u32 data;
  1035. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1036. data &= ~RXQ_CTRL_EN;
  1037. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1038. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1039. data &= ~TXQ_CTRL_EN;
  1040. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1041. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1042. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1043. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1044. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1045. return (int)atl1c_wait_until_idle(hw,
  1046. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1047. }
  1048. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1049. {
  1050. struct atl1c_hw *hw = &adapter->hw;
  1051. u32 mac, txq, rxq;
  1052. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1053. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1054. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1055. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1056. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1057. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1058. txq |= TXQ_CTRL_EN;
  1059. rxq |= RXQ_CTRL_EN;
  1060. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1061. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1062. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1063. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1064. MAC_CTRL_HASH_ALG_CRC32;
  1065. if (hw->mac_duplex)
  1066. mac |= MAC_CTRL_DUPLX;
  1067. else
  1068. mac &= ~MAC_CTRL_DUPLX;
  1069. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1070. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1071. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1072. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1073. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1074. }
  1075. /*
  1076. * Reset the transmit and receive units; mask and clear all interrupts.
  1077. * hw - Struct containing variables accessed by shared code
  1078. * return : 0 or idle status (if error)
  1079. */
  1080. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1081. {
  1082. struct atl1c_adapter *adapter = hw->adapter;
  1083. struct pci_dev *pdev = adapter->pdev;
  1084. u32 ctrl_data = 0;
  1085. atl1c_stop_mac(hw);
  1086. /*
  1087. * Issue Soft Reset to the MAC. This will reset the chip's
  1088. * transmit, receive, DMA. It will not effect
  1089. * the current PCI configuration. The global reset bit is self-
  1090. * clearing, and should clear within a microsecond.
  1091. */
  1092. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1093. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1094. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1095. AT_WRITE_FLUSH(hw);
  1096. msleep(10);
  1097. /* Wait at least 10ms for All module to be Idle */
  1098. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1099. dev_err(&pdev->dev,
  1100. "MAC state machine can't be idle since"
  1101. " disabled for 10ms second\n");
  1102. return -1;
  1103. }
  1104. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1105. /* driver control speed/duplex */
  1106. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1107. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1108. /* clk switch setting */
  1109. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1110. switch (hw->nic_type) {
  1111. case athr_l2c_b:
  1112. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1113. SERDES_MAC_CLK_SLOWDOWN);
  1114. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1115. break;
  1116. case athr_l2c_b2:
  1117. case athr_l1d_2:
  1118. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1119. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1120. break;
  1121. default:
  1122. break;
  1123. }
  1124. return 0;
  1125. }
  1126. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1127. {
  1128. u16 ctrl_flags = hw->ctrl_flags;
  1129. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1130. atl1c_set_aspm(hw, SPEED_0);
  1131. hw->ctrl_flags = ctrl_flags;
  1132. }
  1133. /*
  1134. * Set ASPM state.
  1135. * Enable/disable L0s/L1 depend on link state.
  1136. */
  1137. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1138. {
  1139. u32 pm_ctrl_data;
  1140. u32 link_l1_timer;
  1141. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1142. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1143. PM_CTRL_ASPM_L0S_EN |
  1144. PM_CTRL_MAC_ASPM_CHK);
  1145. /* L1 timer */
  1146. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1147. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1148. link_l1_timer =
  1149. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1150. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1151. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1152. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1153. } else {
  1154. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1155. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1156. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1157. link_l1_timer = 1;
  1158. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1159. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1160. }
  1161. /* L0S/L1 enable */
  1162. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1163. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1164. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1165. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1166. /* l2cb & l1d & l2cb2 & l1d2 */
  1167. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1168. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1169. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1170. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1171. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1172. PM_CTRL_SERDES_PD_EX_L1 |
  1173. PM_CTRL_CLK_SWH_L1;
  1174. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1175. PM_CTRL_SERDES_PLL_L1_EN |
  1176. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1177. PM_CTRL_SA_DLY_EN |
  1178. PM_CTRL_HOTRST);
  1179. /* disable l0s if link down or l2cb */
  1180. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1181. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1182. } else { /* l1c */
  1183. pm_ctrl_data =
  1184. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1185. if (link_speed != SPEED_0) {
  1186. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1187. PM_CTRL_SERDES_PLL_L1_EN |
  1188. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1189. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1190. PM_CTRL_CLK_SWH_L1 |
  1191. PM_CTRL_ASPM_L0S_EN |
  1192. PM_CTRL_ASPM_L1_EN);
  1193. } else { /* link down */
  1194. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1195. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1196. PM_CTRL_SERDES_PLL_L1_EN |
  1197. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1198. PM_CTRL_ASPM_L0S_EN);
  1199. }
  1200. }
  1201. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1202. return;
  1203. }
  1204. /**
  1205. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1206. * @adapter: board private structure
  1207. *
  1208. * Configure the Tx /Rx unit of the MAC after a reset.
  1209. */
  1210. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1211. {
  1212. struct atl1c_hw *hw = &adapter->hw;
  1213. u32 master_ctrl_data = 0;
  1214. u32 intr_modrt_data;
  1215. u32 data;
  1216. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1217. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1218. MASTER_CTRL_RX_ITIMER_EN |
  1219. MASTER_CTRL_INT_RDCLR);
  1220. /* clear interrupt status */
  1221. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1222. /* Clear any WOL status */
  1223. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1224. /* set Interrupt Clear Timer
  1225. * HW will enable self to assert interrupt event to system after
  1226. * waiting x-time for software to notify it accept interrupt.
  1227. */
  1228. data = CLK_GATING_EN_ALL;
  1229. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1230. if (hw->nic_type == athr_l2c_b)
  1231. data &= ~CLK_GATING_RXMAC_EN;
  1232. } else
  1233. data = 0;
  1234. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1235. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1236. hw->ict & INT_RETRIG_TIMER_MASK);
  1237. atl1c_configure_des_ring(adapter);
  1238. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1239. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1240. IRQ_MODRT_TX_TIMER_SHIFT;
  1241. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1242. IRQ_MODRT_RX_TIMER_SHIFT;
  1243. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1244. master_ctrl_data |=
  1245. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1246. }
  1247. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1248. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1249. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1250. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1251. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1252. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1253. /* set MTU */
  1254. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1255. VLAN_HLEN + ETH_FCS_LEN);
  1256. atl1c_configure_tx(adapter);
  1257. atl1c_configure_rx(adapter);
  1258. atl1c_configure_dma(adapter);
  1259. return 0;
  1260. }
  1261. static int atl1c_configure(struct atl1c_adapter *adapter)
  1262. {
  1263. struct net_device *netdev = adapter->netdev;
  1264. int num;
  1265. atl1c_init_ring_ptrs(adapter);
  1266. atl1c_set_multi(netdev);
  1267. atl1c_restore_vlan(adapter);
  1268. num = atl1c_alloc_rx_buffer(adapter);
  1269. if (unlikely(num == 0))
  1270. return -ENOMEM;
  1271. if (atl1c_configure_mac(adapter))
  1272. return -EIO;
  1273. return 0;
  1274. }
  1275. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1276. {
  1277. u16 hw_reg_addr = 0;
  1278. unsigned long *stats_item = NULL;
  1279. u32 data;
  1280. /* update rx status */
  1281. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1282. stats_item = &adapter->hw_stats.rx_ok;
  1283. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1284. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1285. *stats_item += data;
  1286. stats_item++;
  1287. hw_reg_addr += 4;
  1288. }
  1289. /* update tx status */
  1290. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1291. stats_item = &adapter->hw_stats.tx_ok;
  1292. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1293. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1294. *stats_item += data;
  1295. stats_item++;
  1296. hw_reg_addr += 4;
  1297. }
  1298. }
  1299. /**
  1300. * atl1c_get_stats - Get System Network Statistics
  1301. * @netdev: network interface device structure
  1302. *
  1303. * Returns the address of the device statistics structure.
  1304. * The statistics are actually updated from the timer callback.
  1305. */
  1306. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1307. {
  1308. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1309. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1310. struct net_device_stats *net_stats = &netdev->stats;
  1311. atl1c_update_hw_stats(adapter);
  1312. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1313. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1314. net_stats->multicast = hw_stats->rx_mcast;
  1315. net_stats->collisions = hw_stats->tx_1_col +
  1316. hw_stats->tx_2_col +
  1317. hw_stats->tx_late_col +
  1318. hw_stats->tx_abort_col;
  1319. net_stats->rx_errors = hw_stats->rx_frag +
  1320. hw_stats->rx_fcs_err +
  1321. hw_stats->rx_len_err +
  1322. hw_stats->rx_sz_ov +
  1323. hw_stats->rx_rrd_ov +
  1324. hw_stats->rx_align_err +
  1325. hw_stats->rx_rxf_ov;
  1326. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1327. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1328. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1329. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1330. net_stats->rx_dropped = hw_stats->rx_rrd_ov;
  1331. net_stats->tx_errors = hw_stats->tx_late_col +
  1332. hw_stats->tx_abort_col +
  1333. hw_stats->tx_underrun +
  1334. hw_stats->tx_trunc;
  1335. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1336. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1337. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1338. net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
  1339. net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
  1340. return net_stats;
  1341. }
  1342. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1343. {
  1344. u16 phy_data;
  1345. spin_lock(&adapter->mdio_lock);
  1346. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1347. spin_unlock(&adapter->mdio_lock);
  1348. }
  1349. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1350. enum atl1c_trans_queue type)
  1351. {
  1352. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1353. struct atl1c_buffer *buffer_info;
  1354. struct pci_dev *pdev = adapter->pdev;
  1355. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1356. u16 hw_next_to_clean;
  1357. u16 reg;
  1358. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1359. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1360. while (next_to_clean != hw_next_to_clean) {
  1361. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1362. atl1c_clean_buffer(pdev, buffer_info);
  1363. if (++next_to_clean == tpd_ring->count)
  1364. next_to_clean = 0;
  1365. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1366. }
  1367. if (netif_queue_stopped(adapter->netdev) &&
  1368. netif_carrier_ok(adapter->netdev)) {
  1369. netif_wake_queue(adapter->netdev);
  1370. }
  1371. return true;
  1372. }
  1373. /**
  1374. * atl1c_intr - Interrupt Handler
  1375. * @irq: interrupt number
  1376. * @data: pointer to a network interface device structure
  1377. */
  1378. static irqreturn_t atl1c_intr(int irq, void *data)
  1379. {
  1380. struct net_device *netdev = data;
  1381. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1382. struct pci_dev *pdev = adapter->pdev;
  1383. struct atl1c_hw *hw = &adapter->hw;
  1384. int max_ints = AT_MAX_INT_WORK;
  1385. int handled = IRQ_NONE;
  1386. u32 status;
  1387. u32 reg_data;
  1388. do {
  1389. AT_READ_REG(hw, REG_ISR, &reg_data);
  1390. status = reg_data & hw->intr_mask;
  1391. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1392. if (max_ints != AT_MAX_INT_WORK)
  1393. handled = IRQ_HANDLED;
  1394. break;
  1395. }
  1396. /* link event */
  1397. if (status & ISR_GPHY)
  1398. atl1c_clear_phy_int(adapter);
  1399. /* Ack ISR */
  1400. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1401. if (status & ISR_RX_PKT) {
  1402. if (likely(napi_schedule_prep(&adapter->napi))) {
  1403. hw->intr_mask &= ~ISR_RX_PKT;
  1404. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1405. __napi_schedule(&adapter->napi);
  1406. }
  1407. }
  1408. if (status & ISR_TX_PKT)
  1409. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1410. handled = IRQ_HANDLED;
  1411. /* check if PCIE PHY Link down */
  1412. if (status & ISR_ERROR) {
  1413. if (netif_msg_hw(adapter))
  1414. dev_err(&pdev->dev,
  1415. "atl1c hardware error (status = 0x%x)\n",
  1416. status & ISR_ERROR);
  1417. /* reset MAC */
  1418. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1419. schedule_work(&adapter->common_task);
  1420. return IRQ_HANDLED;
  1421. }
  1422. if (status & ISR_OVER)
  1423. if (netif_msg_intr(adapter))
  1424. dev_warn(&pdev->dev,
  1425. "TX/RX overflow (status = 0x%x)\n",
  1426. status & ISR_OVER);
  1427. /* link event */
  1428. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1429. netdev->stats.tx_carrier_errors++;
  1430. atl1c_link_chg_event(adapter);
  1431. break;
  1432. }
  1433. } while (--max_ints > 0);
  1434. /* re-enable Interrupt*/
  1435. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1436. return handled;
  1437. }
  1438. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1439. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1440. {
  1441. /*
  1442. * The pid field in RRS in not correct sometimes, so we
  1443. * cannot figure out if the packet is fragmented or not,
  1444. * so we tell the KERNEL CHECKSUM_NONE
  1445. */
  1446. skb_checksum_none_assert(skb);
  1447. }
  1448. static struct sk_buff *atl1c_alloc_skb(struct atl1c_adapter *adapter)
  1449. {
  1450. struct sk_buff *skb;
  1451. struct page *page;
  1452. if (adapter->rx_frag_size > PAGE_SIZE)
  1453. return netdev_alloc_skb(adapter->netdev,
  1454. adapter->rx_buffer_len);
  1455. page = adapter->rx_page;
  1456. if (!page) {
  1457. adapter->rx_page = page = alloc_page(GFP_ATOMIC);
  1458. if (unlikely(!page))
  1459. return NULL;
  1460. adapter->rx_page_offset = 0;
  1461. }
  1462. skb = build_skb(page_address(page) + adapter->rx_page_offset,
  1463. adapter->rx_frag_size);
  1464. if (likely(skb)) {
  1465. adapter->rx_page_offset += adapter->rx_frag_size;
  1466. if (adapter->rx_page_offset >= PAGE_SIZE)
  1467. adapter->rx_page = NULL;
  1468. else
  1469. get_page(page);
  1470. }
  1471. return skb;
  1472. }
  1473. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1474. {
  1475. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1476. struct pci_dev *pdev = adapter->pdev;
  1477. struct atl1c_buffer *buffer_info, *next_info;
  1478. struct sk_buff *skb;
  1479. void *vir_addr = NULL;
  1480. u16 num_alloc = 0;
  1481. u16 rfd_next_to_use, next_next;
  1482. struct atl1c_rx_free_desc *rfd_desc;
  1483. dma_addr_t mapping;
  1484. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1485. if (++next_next == rfd_ring->count)
  1486. next_next = 0;
  1487. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1488. next_info = &rfd_ring->buffer_info[next_next];
  1489. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1490. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1491. skb = atl1c_alloc_skb(adapter);
  1492. if (unlikely(!skb)) {
  1493. if (netif_msg_rx_err(adapter))
  1494. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1495. break;
  1496. }
  1497. /*
  1498. * Make buffer alignment 2 beyond a 16 byte boundary
  1499. * this will result in a 16 byte aligned IP header after
  1500. * the 14 byte MAC header is removed
  1501. */
  1502. vir_addr = skb->data;
  1503. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1504. buffer_info->skb = skb;
  1505. buffer_info->length = adapter->rx_buffer_len;
  1506. mapping = pci_map_single(pdev, vir_addr,
  1507. buffer_info->length,
  1508. PCI_DMA_FROMDEVICE);
  1509. if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
  1510. dev_kfree_skb(skb);
  1511. buffer_info->skb = NULL;
  1512. buffer_info->length = 0;
  1513. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  1514. netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
  1515. break;
  1516. }
  1517. buffer_info->dma = mapping;
  1518. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1519. ATL1C_PCIMAP_FROMDEVICE);
  1520. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1521. rfd_next_to_use = next_next;
  1522. if (++next_next == rfd_ring->count)
  1523. next_next = 0;
  1524. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1525. next_info = &rfd_ring->buffer_info[next_next];
  1526. num_alloc++;
  1527. }
  1528. if (num_alloc) {
  1529. /* TODO: update mailbox here */
  1530. wmb();
  1531. rfd_ring->next_to_use = rfd_next_to_use;
  1532. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1533. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1534. }
  1535. return num_alloc;
  1536. }
  1537. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1538. struct atl1c_recv_ret_status *rrs, u16 num)
  1539. {
  1540. u16 i;
  1541. /* the relationship between rrd and rfd is one map one */
  1542. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1543. rrd_ring->next_to_clean)) {
  1544. rrs->word3 &= ~RRS_RXD_UPDATED;
  1545. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1546. rrd_ring->next_to_clean = 0;
  1547. }
  1548. }
  1549. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1550. struct atl1c_recv_ret_status *rrs, u16 num)
  1551. {
  1552. u16 i;
  1553. u16 rfd_index;
  1554. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1555. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1556. RRS_RX_RFD_INDEX_MASK;
  1557. for (i = 0; i < num; i++) {
  1558. buffer_info[rfd_index].skb = NULL;
  1559. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1560. ATL1C_BUFFER_FREE);
  1561. if (++rfd_index == rfd_ring->count)
  1562. rfd_index = 0;
  1563. }
  1564. rfd_ring->next_to_clean = rfd_index;
  1565. }
  1566. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1567. int *work_done, int work_to_do)
  1568. {
  1569. u16 rfd_num, rfd_index;
  1570. u16 count = 0;
  1571. u16 length;
  1572. struct pci_dev *pdev = adapter->pdev;
  1573. struct net_device *netdev = adapter->netdev;
  1574. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1575. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1576. struct sk_buff *skb;
  1577. struct atl1c_recv_ret_status *rrs;
  1578. struct atl1c_buffer *buffer_info;
  1579. while (1) {
  1580. if (*work_done >= work_to_do)
  1581. break;
  1582. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1583. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1584. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1585. RRS_RX_RFD_CNT_MASK;
  1586. if (unlikely(rfd_num != 1))
  1587. /* TODO support mul rfd*/
  1588. if (netif_msg_rx_err(adapter))
  1589. dev_warn(&pdev->dev,
  1590. "Multi rfd not support yet!\n");
  1591. goto rrs_checked;
  1592. } else {
  1593. break;
  1594. }
  1595. rrs_checked:
  1596. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1597. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1598. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1599. if (netif_msg_rx_err(adapter))
  1600. dev_warn(&pdev->dev,
  1601. "wrong packet! rrs word3 is %x\n",
  1602. rrs->word3);
  1603. continue;
  1604. }
  1605. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1606. RRS_PKT_SIZE_MASK);
  1607. /* Good Receive */
  1608. if (likely(rfd_num == 1)) {
  1609. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1610. RRS_RX_RFD_INDEX_MASK;
  1611. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1612. pci_unmap_single(pdev, buffer_info->dma,
  1613. buffer_info->length, PCI_DMA_FROMDEVICE);
  1614. skb = buffer_info->skb;
  1615. } else {
  1616. /* TODO */
  1617. if (netif_msg_rx_err(adapter))
  1618. dev_warn(&pdev->dev,
  1619. "Multi rfd not support yet!\n");
  1620. break;
  1621. }
  1622. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1623. skb_put(skb, length - ETH_FCS_LEN);
  1624. skb->protocol = eth_type_trans(skb, netdev);
  1625. atl1c_rx_checksum(adapter, skb, rrs);
  1626. if (rrs->word3 & RRS_VLAN_INS) {
  1627. u16 vlan;
  1628. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1629. vlan = le16_to_cpu(vlan);
  1630. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
  1631. }
  1632. netif_receive_skb(skb);
  1633. (*work_done)++;
  1634. count++;
  1635. }
  1636. if (count)
  1637. atl1c_alloc_rx_buffer(adapter);
  1638. }
  1639. /**
  1640. * atl1c_clean - NAPI Rx polling callback
  1641. */
  1642. static int atl1c_clean(struct napi_struct *napi, int budget)
  1643. {
  1644. struct atl1c_adapter *adapter =
  1645. container_of(napi, struct atl1c_adapter, napi);
  1646. int work_done = 0;
  1647. /* Keep link state information with original netdev */
  1648. if (!netif_carrier_ok(adapter->netdev))
  1649. goto quit_polling;
  1650. /* just enable one RXQ */
  1651. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1652. if (work_done < budget) {
  1653. quit_polling:
  1654. napi_complete(napi);
  1655. adapter->hw.intr_mask |= ISR_RX_PKT;
  1656. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1657. }
  1658. return work_done;
  1659. }
  1660. #ifdef CONFIG_NET_POLL_CONTROLLER
  1661. /*
  1662. * Polling 'interrupt' - used by things like netconsole to send skbs
  1663. * without having to re-enable interrupts. It's not called while
  1664. * the interrupt routine is executing.
  1665. */
  1666. static void atl1c_netpoll(struct net_device *netdev)
  1667. {
  1668. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1669. disable_irq(adapter->pdev->irq);
  1670. atl1c_intr(adapter->pdev->irq, netdev);
  1671. enable_irq(adapter->pdev->irq);
  1672. }
  1673. #endif
  1674. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1675. {
  1676. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1677. u16 next_to_use = 0;
  1678. u16 next_to_clean = 0;
  1679. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1680. next_to_use = tpd_ring->next_to_use;
  1681. return (u16)(next_to_clean > next_to_use) ?
  1682. (next_to_clean - next_to_use - 1) :
  1683. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1684. }
  1685. /*
  1686. * get next usable tpd
  1687. * Note: should call atl1c_tdp_avail to make sure
  1688. * there is enough tpd to use
  1689. */
  1690. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1691. enum atl1c_trans_queue type)
  1692. {
  1693. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1694. struct atl1c_tpd_desc *tpd_desc;
  1695. u16 next_to_use = 0;
  1696. next_to_use = tpd_ring->next_to_use;
  1697. if (++tpd_ring->next_to_use == tpd_ring->count)
  1698. tpd_ring->next_to_use = 0;
  1699. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1700. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1701. return tpd_desc;
  1702. }
  1703. static struct atl1c_buffer *
  1704. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1705. {
  1706. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1707. return &tpd_ring->buffer_info[tpd -
  1708. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1709. }
  1710. /* Calculate the transmit packet descript needed*/
  1711. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1712. {
  1713. u16 tpd_req;
  1714. u16 proto_hdr_len = 0;
  1715. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1716. if (skb_is_gso(skb)) {
  1717. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1718. if (proto_hdr_len < skb_headlen(skb))
  1719. tpd_req++;
  1720. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1721. tpd_req++;
  1722. }
  1723. return tpd_req;
  1724. }
  1725. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1726. struct sk_buff *skb,
  1727. struct atl1c_tpd_desc **tpd,
  1728. enum atl1c_trans_queue type)
  1729. {
  1730. struct pci_dev *pdev = adapter->pdev;
  1731. unsigned short offload_type;
  1732. u8 hdr_len;
  1733. u32 real_len;
  1734. if (skb_is_gso(skb)) {
  1735. int err;
  1736. err = skb_cow_head(skb, 0);
  1737. if (err < 0)
  1738. return err;
  1739. offload_type = skb_shinfo(skb)->gso_type;
  1740. if (offload_type & SKB_GSO_TCPV4) {
  1741. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1742. + ntohs(ip_hdr(skb)->tot_len));
  1743. if (real_len < skb->len)
  1744. pskb_trim(skb, real_len);
  1745. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1746. if (unlikely(skb->len == hdr_len)) {
  1747. /* only xsum need */
  1748. if (netif_msg_tx_queued(adapter))
  1749. dev_warn(&pdev->dev,
  1750. "IPV4 tso with zero data??\n");
  1751. goto check_sum;
  1752. } else {
  1753. ip_hdr(skb)->check = 0;
  1754. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1755. ip_hdr(skb)->saddr,
  1756. ip_hdr(skb)->daddr,
  1757. 0, IPPROTO_TCP, 0);
  1758. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1759. }
  1760. }
  1761. if (offload_type & SKB_GSO_TCPV6) {
  1762. struct atl1c_tpd_ext_desc *etpd =
  1763. *(struct atl1c_tpd_ext_desc **)(tpd);
  1764. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1765. *tpd = atl1c_get_tpd(adapter, type);
  1766. ipv6_hdr(skb)->payload_len = 0;
  1767. /* check payload == 0 byte ? */
  1768. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1769. if (unlikely(skb->len == hdr_len)) {
  1770. /* only xsum need */
  1771. if (netif_msg_tx_queued(adapter))
  1772. dev_warn(&pdev->dev,
  1773. "IPV6 tso with zero data??\n");
  1774. goto check_sum;
  1775. } else
  1776. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1777. &ipv6_hdr(skb)->saddr,
  1778. &ipv6_hdr(skb)->daddr,
  1779. 0, IPPROTO_TCP, 0);
  1780. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1781. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1782. etpd->pkt_len = cpu_to_le32(skb->len);
  1783. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1784. }
  1785. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1786. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1787. TPD_TCPHDR_OFFSET_SHIFT;
  1788. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1789. TPD_MSS_SHIFT;
  1790. return 0;
  1791. }
  1792. check_sum:
  1793. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1794. u8 css, cso;
  1795. cso = skb_checksum_start_offset(skb);
  1796. if (unlikely(cso & 0x1)) {
  1797. if (netif_msg_tx_err(adapter))
  1798. dev_err(&adapter->pdev->dev,
  1799. "payload offset should not an event number\n");
  1800. return -1;
  1801. } else {
  1802. css = cso + skb->csum_offset;
  1803. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1804. TPD_PLOADOFFSET_SHIFT;
  1805. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1806. TPD_CCSUM_OFFSET_SHIFT;
  1807. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1808. }
  1809. }
  1810. return 0;
  1811. }
  1812. static void atl1c_tx_rollback(struct atl1c_adapter *adpt,
  1813. struct atl1c_tpd_desc *first_tpd,
  1814. enum atl1c_trans_queue type)
  1815. {
  1816. struct atl1c_tpd_ring *tpd_ring = &adpt->tpd_ring[type];
  1817. struct atl1c_buffer *buffer_info;
  1818. struct atl1c_tpd_desc *tpd;
  1819. u16 first_index, index;
  1820. first_index = first_tpd - (struct atl1c_tpd_desc *)tpd_ring->desc;
  1821. index = first_index;
  1822. while (index != tpd_ring->next_to_use) {
  1823. tpd = ATL1C_TPD_DESC(tpd_ring, index);
  1824. buffer_info = &tpd_ring->buffer_info[index];
  1825. atl1c_clean_buffer(adpt->pdev, buffer_info);
  1826. memset(tpd, 0, sizeof(struct atl1c_tpd_desc));
  1827. if (++index == tpd_ring->count)
  1828. index = 0;
  1829. }
  1830. tpd_ring->next_to_use = first_index;
  1831. }
  1832. static int atl1c_tx_map(struct atl1c_adapter *adapter,
  1833. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1834. enum atl1c_trans_queue type)
  1835. {
  1836. struct atl1c_tpd_desc *use_tpd = NULL;
  1837. struct atl1c_buffer *buffer_info = NULL;
  1838. u16 buf_len = skb_headlen(skb);
  1839. u16 map_len = 0;
  1840. u16 mapped_len = 0;
  1841. u16 hdr_len = 0;
  1842. u16 nr_frags;
  1843. u16 f;
  1844. int tso;
  1845. nr_frags = skb_shinfo(skb)->nr_frags;
  1846. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1847. if (tso) {
  1848. /* TSO */
  1849. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1850. use_tpd = tpd;
  1851. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1852. buffer_info->length = map_len;
  1853. buffer_info->dma = pci_map_single(adapter->pdev,
  1854. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1855. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1856. buffer_info->dma)))
  1857. goto err_dma;
  1858. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1859. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1860. ATL1C_PCIMAP_TODEVICE);
  1861. mapped_len += map_len;
  1862. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1863. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1864. }
  1865. if (mapped_len < buf_len) {
  1866. /* mapped_len == 0, means we should use the first tpd,
  1867. which is given by caller */
  1868. if (mapped_len == 0)
  1869. use_tpd = tpd;
  1870. else {
  1871. use_tpd = atl1c_get_tpd(adapter, type);
  1872. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1873. }
  1874. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1875. buffer_info->length = buf_len - mapped_len;
  1876. buffer_info->dma =
  1877. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1878. buffer_info->length, PCI_DMA_TODEVICE);
  1879. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1880. buffer_info->dma)))
  1881. goto err_dma;
  1882. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1883. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1884. ATL1C_PCIMAP_TODEVICE);
  1885. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1886. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1887. }
  1888. for (f = 0; f < nr_frags; f++) {
  1889. struct skb_frag_struct *frag;
  1890. frag = &skb_shinfo(skb)->frags[f];
  1891. use_tpd = atl1c_get_tpd(adapter, type);
  1892. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1893. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1894. buffer_info->length = skb_frag_size(frag);
  1895. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1896. frag, 0,
  1897. buffer_info->length,
  1898. DMA_TO_DEVICE);
  1899. if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma))
  1900. goto err_dma;
  1901. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1902. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1903. ATL1C_PCIMAP_TODEVICE);
  1904. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1905. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1906. }
  1907. /* The last tpd */
  1908. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1909. /* The last buffer info contain the skb address,
  1910. so it will be free after unmap */
  1911. buffer_info->skb = skb;
  1912. return 0;
  1913. err_dma:
  1914. buffer_info->dma = 0;
  1915. buffer_info->length = 0;
  1916. return -1;
  1917. }
  1918. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1919. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1920. {
  1921. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1922. u16 reg;
  1923. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1924. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1925. }
  1926. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1927. struct net_device *netdev)
  1928. {
  1929. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1930. unsigned long flags;
  1931. u16 tpd_req = 1;
  1932. struct atl1c_tpd_desc *tpd;
  1933. enum atl1c_trans_queue type = atl1c_trans_normal;
  1934. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1935. dev_kfree_skb_any(skb);
  1936. return NETDEV_TX_OK;
  1937. }
  1938. tpd_req = atl1c_cal_tpd_req(skb);
  1939. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1940. if (netif_msg_pktdata(adapter))
  1941. dev_info(&adapter->pdev->dev, "tx locked\n");
  1942. return NETDEV_TX_LOCKED;
  1943. }
  1944. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1945. /* no enough descriptor, just stop queue */
  1946. netif_stop_queue(netdev);
  1947. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1948. return NETDEV_TX_BUSY;
  1949. }
  1950. tpd = atl1c_get_tpd(adapter, type);
  1951. /* do TSO and check sum */
  1952. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1953. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1954. dev_kfree_skb_any(skb);
  1955. return NETDEV_TX_OK;
  1956. }
  1957. if (unlikely(skb_vlan_tag_present(skb))) {
  1958. u16 vlan = skb_vlan_tag_get(skb);
  1959. __le16 tag;
  1960. vlan = cpu_to_le16(vlan);
  1961. AT_VLAN_TO_TAG(vlan, tag);
  1962. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1963. tpd->vlan_tag = tag;
  1964. }
  1965. if (skb_network_offset(skb) != ETH_HLEN)
  1966. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1967. if (atl1c_tx_map(adapter, skb, tpd, type) < 0) {
  1968. netif_info(adapter, tx_done, adapter->netdev,
  1969. "tx-skb droppted due to dma error\n");
  1970. /* roll back tpd/buffer */
  1971. atl1c_tx_rollback(adapter, tpd, type);
  1972. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1973. dev_kfree_skb_any(skb);
  1974. } else {
  1975. atl1c_tx_queue(adapter, skb, tpd, type);
  1976. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1977. }
  1978. return NETDEV_TX_OK;
  1979. }
  1980. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1981. {
  1982. struct net_device *netdev = adapter->netdev;
  1983. free_irq(adapter->pdev->irq, netdev);
  1984. if (adapter->have_msi)
  1985. pci_disable_msi(adapter->pdev);
  1986. }
  1987. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1988. {
  1989. struct pci_dev *pdev = adapter->pdev;
  1990. struct net_device *netdev = adapter->netdev;
  1991. int flags = 0;
  1992. int err = 0;
  1993. adapter->have_msi = true;
  1994. err = pci_enable_msi(adapter->pdev);
  1995. if (err) {
  1996. if (netif_msg_ifup(adapter))
  1997. dev_err(&pdev->dev,
  1998. "Unable to allocate MSI interrupt Error: %d\n",
  1999. err);
  2000. adapter->have_msi = false;
  2001. }
  2002. if (!adapter->have_msi)
  2003. flags |= IRQF_SHARED;
  2004. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  2005. netdev->name, netdev);
  2006. if (err) {
  2007. if (netif_msg_ifup(adapter))
  2008. dev_err(&pdev->dev,
  2009. "Unable to allocate interrupt Error: %d\n",
  2010. err);
  2011. if (adapter->have_msi)
  2012. pci_disable_msi(adapter->pdev);
  2013. return err;
  2014. }
  2015. if (netif_msg_ifup(adapter))
  2016. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  2017. return err;
  2018. }
  2019. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  2020. {
  2021. /* release tx-pending skbs and reset tx/rx ring index */
  2022. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  2023. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  2024. atl1c_clean_rx_ring(adapter);
  2025. }
  2026. static int atl1c_up(struct atl1c_adapter *adapter)
  2027. {
  2028. struct net_device *netdev = adapter->netdev;
  2029. int err;
  2030. netif_carrier_off(netdev);
  2031. err = atl1c_configure(adapter);
  2032. if (unlikely(err))
  2033. goto err_up;
  2034. err = atl1c_request_irq(adapter);
  2035. if (unlikely(err))
  2036. goto err_up;
  2037. atl1c_check_link_status(adapter);
  2038. clear_bit(__AT_DOWN, &adapter->flags);
  2039. napi_enable(&adapter->napi);
  2040. atl1c_irq_enable(adapter);
  2041. netif_start_queue(netdev);
  2042. return err;
  2043. err_up:
  2044. atl1c_clean_rx_ring(adapter);
  2045. return err;
  2046. }
  2047. static void atl1c_down(struct atl1c_adapter *adapter)
  2048. {
  2049. struct net_device *netdev = adapter->netdev;
  2050. atl1c_del_timer(adapter);
  2051. adapter->work_event = 0; /* clear all event */
  2052. /* signal that we're down so the interrupt handler does not
  2053. * reschedule our watchdog timer */
  2054. set_bit(__AT_DOWN, &adapter->flags);
  2055. netif_carrier_off(netdev);
  2056. napi_disable(&adapter->napi);
  2057. atl1c_irq_disable(adapter);
  2058. atl1c_free_irq(adapter);
  2059. /* disable ASPM if device inactive */
  2060. atl1c_disable_l0s_l1(&adapter->hw);
  2061. /* reset MAC to disable all RX/TX */
  2062. atl1c_reset_mac(&adapter->hw);
  2063. msleep(1);
  2064. adapter->link_speed = SPEED_0;
  2065. adapter->link_duplex = -1;
  2066. atl1c_reset_dma_ring(adapter);
  2067. }
  2068. /**
  2069. * atl1c_open - Called when a network interface is made active
  2070. * @netdev: network interface device structure
  2071. *
  2072. * Returns 0 on success, negative value on failure
  2073. *
  2074. * The open entry point is called when a network interface is made
  2075. * active by the system (IFF_UP). At this point all resources needed
  2076. * for transmit and receive operations are allocated, the interrupt
  2077. * handler is registered with the OS, the watchdog timer is started,
  2078. * and the stack is notified that the interface is ready.
  2079. */
  2080. static int atl1c_open(struct net_device *netdev)
  2081. {
  2082. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2083. int err;
  2084. /* disallow open during test */
  2085. if (test_bit(__AT_TESTING, &adapter->flags))
  2086. return -EBUSY;
  2087. /* allocate rx/tx dma buffer & descriptors */
  2088. err = atl1c_setup_ring_resources(adapter);
  2089. if (unlikely(err))
  2090. return err;
  2091. err = atl1c_up(adapter);
  2092. if (unlikely(err))
  2093. goto err_up;
  2094. return 0;
  2095. err_up:
  2096. atl1c_free_irq(adapter);
  2097. atl1c_free_ring_resources(adapter);
  2098. atl1c_reset_mac(&adapter->hw);
  2099. return err;
  2100. }
  2101. /**
  2102. * atl1c_close - Disables a network interface
  2103. * @netdev: network interface device structure
  2104. *
  2105. * Returns 0, this is not allowed to fail
  2106. *
  2107. * The close entry point is called when an interface is de-activated
  2108. * by the OS. The hardware is still under the drivers control, but
  2109. * needs to be disabled. A global MAC reset is issued to stop the
  2110. * hardware, and all transmit and receive resources are freed.
  2111. */
  2112. static int atl1c_close(struct net_device *netdev)
  2113. {
  2114. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2115. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2116. set_bit(__AT_DOWN, &adapter->flags);
  2117. cancel_work_sync(&adapter->common_task);
  2118. atl1c_down(adapter);
  2119. atl1c_free_ring_resources(adapter);
  2120. return 0;
  2121. }
  2122. static int atl1c_suspend(struct device *dev)
  2123. {
  2124. struct pci_dev *pdev = to_pci_dev(dev);
  2125. struct net_device *netdev = pci_get_drvdata(pdev);
  2126. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2127. struct atl1c_hw *hw = &adapter->hw;
  2128. u32 wufc = adapter->wol;
  2129. atl1c_disable_l0s_l1(hw);
  2130. if (netif_running(netdev)) {
  2131. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2132. atl1c_down(adapter);
  2133. }
  2134. netif_device_detach(netdev);
  2135. if (wufc)
  2136. if (atl1c_phy_to_ps_link(hw) != 0)
  2137. dev_dbg(&pdev->dev, "phy power saving failed");
  2138. atl1c_power_saving(hw, wufc);
  2139. return 0;
  2140. }
  2141. #ifdef CONFIG_PM_SLEEP
  2142. static int atl1c_resume(struct device *dev)
  2143. {
  2144. struct pci_dev *pdev = to_pci_dev(dev);
  2145. struct net_device *netdev = pci_get_drvdata(pdev);
  2146. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2147. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2148. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2149. atl1c_phy_reset(&adapter->hw);
  2150. atl1c_reset_mac(&adapter->hw);
  2151. atl1c_phy_init(&adapter->hw);
  2152. #if 0
  2153. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2154. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2155. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2156. #endif
  2157. netif_device_attach(netdev);
  2158. if (netif_running(netdev))
  2159. atl1c_up(adapter);
  2160. return 0;
  2161. }
  2162. #endif
  2163. static void atl1c_shutdown(struct pci_dev *pdev)
  2164. {
  2165. struct net_device *netdev = pci_get_drvdata(pdev);
  2166. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2167. atl1c_suspend(&pdev->dev);
  2168. pci_wake_from_d3(pdev, adapter->wol);
  2169. pci_set_power_state(pdev, PCI_D3hot);
  2170. }
  2171. static const struct net_device_ops atl1c_netdev_ops = {
  2172. .ndo_open = atl1c_open,
  2173. .ndo_stop = atl1c_close,
  2174. .ndo_validate_addr = eth_validate_addr,
  2175. .ndo_start_xmit = atl1c_xmit_frame,
  2176. .ndo_set_mac_address = atl1c_set_mac_addr,
  2177. .ndo_set_rx_mode = atl1c_set_multi,
  2178. .ndo_change_mtu = atl1c_change_mtu,
  2179. .ndo_fix_features = atl1c_fix_features,
  2180. .ndo_set_features = atl1c_set_features,
  2181. .ndo_do_ioctl = atl1c_ioctl,
  2182. .ndo_tx_timeout = atl1c_tx_timeout,
  2183. .ndo_get_stats = atl1c_get_stats,
  2184. #ifdef CONFIG_NET_POLL_CONTROLLER
  2185. .ndo_poll_controller = atl1c_netpoll,
  2186. #endif
  2187. };
  2188. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2189. {
  2190. SET_NETDEV_DEV(netdev, &pdev->dev);
  2191. pci_set_drvdata(pdev, netdev);
  2192. netdev->netdev_ops = &atl1c_netdev_ops;
  2193. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2194. atl1c_set_ethtool_ops(netdev);
  2195. /* TODO: add when ready */
  2196. netdev->hw_features = NETIF_F_SG |
  2197. NETIF_F_HW_CSUM |
  2198. NETIF_F_HW_VLAN_CTAG_RX |
  2199. NETIF_F_TSO |
  2200. NETIF_F_TSO6;
  2201. netdev->features = netdev->hw_features |
  2202. NETIF_F_HW_VLAN_CTAG_TX;
  2203. return 0;
  2204. }
  2205. /**
  2206. * atl1c_probe - Device Initialization Routine
  2207. * @pdev: PCI device information struct
  2208. * @ent: entry in atl1c_pci_tbl
  2209. *
  2210. * Returns 0 on success, negative on failure
  2211. *
  2212. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2213. * The OS initialization, configuring of the adapter private structure,
  2214. * and a hardware reset occur.
  2215. */
  2216. static int atl1c_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2217. {
  2218. struct net_device *netdev;
  2219. struct atl1c_adapter *adapter;
  2220. static int cards_found;
  2221. int err = 0;
  2222. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2223. err = pci_enable_device_mem(pdev);
  2224. if (err) {
  2225. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2226. return err;
  2227. }
  2228. /*
  2229. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2230. * shared register for the high 32 bits, so only a single, aligned,
  2231. * 4 GB physical address range can be used at a time.
  2232. *
  2233. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2234. * worth. It is far easier to limit to 32-bit DMA than update
  2235. * various kernel subsystems to support the mechanics required by a
  2236. * fixed-high-32-bit system.
  2237. */
  2238. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2239. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2240. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2241. goto err_dma;
  2242. }
  2243. err = pci_request_regions(pdev, atl1c_driver_name);
  2244. if (err) {
  2245. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2246. goto err_pci_reg;
  2247. }
  2248. pci_set_master(pdev);
  2249. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2250. if (netdev == NULL) {
  2251. err = -ENOMEM;
  2252. goto err_alloc_etherdev;
  2253. }
  2254. err = atl1c_init_netdev(netdev, pdev);
  2255. if (err) {
  2256. dev_err(&pdev->dev, "init netdevice failed\n");
  2257. goto err_init_netdev;
  2258. }
  2259. adapter = netdev_priv(netdev);
  2260. adapter->bd_number = cards_found;
  2261. adapter->netdev = netdev;
  2262. adapter->pdev = pdev;
  2263. adapter->hw.adapter = adapter;
  2264. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2265. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2266. if (!adapter->hw.hw_addr) {
  2267. err = -EIO;
  2268. dev_err(&pdev->dev, "cannot map device registers\n");
  2269. goto err_ioremap;
  2270. }
  2271. /* init mii data */
  2272. adapter->mii.dev = netdev;
  2273. adapter->mii.mdio_read = atl1c_mdio_read;
  2274. adapter->mii.mdio_write = atl1c_mdio_write;
  2275. adapter->mii.phy_id_mask = 0x1f;
  2276. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2277. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2278. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2279. (unsigned long)adapter);
  2280. /* setup the private structure */
  2281. err = atl1c_sw_init(adapter);
  2282. if (err) {
  2283. dev_err(&pdev->dev, "net device private data init failed\n");
  2284. goto err_sw_init;
  2285. }
  2286. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2287. /* Init GPHY as early as possible due to power saving issue */
  2288. atl1c_phy_reset(&adapter->hw);
  2289. err = atl1c_reset_mac(&adapter->hw);
  2290. if (err) {
  2291. err = -EIO;
  2292. goto err_reset;
  2293. }
  2294. /* reset the controller to
  2295. * put the device in a known good starting state */
  2296. err = atl1c_phy_init(&adapter->hw);
  2297. if (err) {
  2298. err = -EIO;
  2299. goto err_reset;
  2300. }
  2301. if (atl1c_read_mac_addr(&adapter->hw)) {
  2302. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2303. netdev->addr_assign_type = NET_ADDR_RANDOM;
  2304. }
  2305. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2306. if (netif_msg_probe(adapter))
  2307. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2308. adapter->hw.mac_addr);
  2309. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2310. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2311. adapter->work_event = 0;
  2312. err = register_netdev(netdev);
  2313. if (err) {
  2314. dev_err(&pdev->dev, "register netdevice failed\n");
  2315. goto err_register;
  2316. }
  2317. if (netif_msg_probe(adapter))
  2318. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2319. cards_found++;
  2320. return 0;
  2321. err_reset:
  2322. err_register:
  2323. err_sw_init:
  2324. iounmap(adapter->hw.hw_addr);
  2325. err_init_netdev:
  2326. err_ioremap:
  2327. free_netdev(netdev);
  2328. err_alloc_etherdev:
  2329. pci_release_regions(pdev);
  2330. err_pci_reg:
  2331. err_dma:
  2332. pci_disable_device(pdev);
  2333. return err;
  2334. }
  2335. /**
  2336. * atl1c_remove - Device Removal Routine
  2337. * @pdev: PCI device information struct
  2338. *
  2339. * atl1c_remove is called by the PCI subsystem to alert the driver
  2340. * that it should release a PCI device. The could be caused by a
  2341. * Hot-Plug event, or because the driver is going to be removed from
  2342. * memory.
  2343. */
  2344. static void atl1c_remove(struct pci_dev *pdev)
  2345. {
  2346. struct net_device *netdev = pci_get_drvdata(pdev);
  2347. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2348. unregister_netdev(netdev);
  2349. /* restore permanent address */
  2350. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2351. atl1c_phy_disable(&adapter->hw);
  2352. iounmap(adapter->hw.hw_addr);
  2353. pci_release_regions(pdev);
  2354. pci_disable_device(pdev);
  2355. free_netdev(netdev);
  2356. }
  2357. /**
  2358. * atl1c_io_error_detected - called when PCI error is detected
  2359. * @pdev: Pointer to PCI device
  2360. * @state: The current pci connection state
  2361. *
  2362. * This function is called after a PCI bus error affecting
  2363. * this device has been detected.
  2364. */
  2365. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2366. pci_channel_state_t state)
  2367. {
  2368. struct net_device *netdev = pci_get_drvdata(pdev);
  2369. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2370. netif_device_detach(netdev);
  2371. if (state == pci_channel_io_perm_failure)
  2372. return PCI_ERS_RESULT_DISCONNECT;
  2373. if (netif_running(netdev))
  2374. atl1c_down(adapter);
  2375. pci_disable_device(pdev);
  2376. /* Request a slot slot reset. */
  2377. return PCI_ERS_RESULT_NEED_RESET;
  2378. }
  2379. /**
  2380. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2381. * @pdev: Pointer to PCI device
  2382. *
  2383. * Restart the card from scratch, as if from a cold-boot. Implementation
  2384. * resembles the first-half of the e1000_resume routine.
  2385. */
  2386. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2387. {
  2388. struct net_device *netdev = pci_get_drvdata(pdev);
  2389. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2390. if (pci_enable_device(pdev)) {
  2391. if (netif_msg_hw(adapter))
  2392. dev_err(&pdev->dev,
  2393. "Cannot re-enable PCI device after reset\n");
  2394. return PCI_ERS_RESULT_DISCONNECT;
  2395. }
  2396. pci_set_master(pdev);
  2397. pci_enable_wake(pdev, PCI_D3hot, 0);
  2398. pci_enable_wake(pdev, PCI_D3cold, 0);
  2399. atl1c_reset_mac(&adapter->hw);
  2400. return PCI_ERS_RESULT_RECOVERED;
  2401. }
  2402. /**
  2403. * atl1c_io_resume - called when traffic can start flowing again.
  2404. * @pdev: Pointer to PCI device
  2405. *
  2406. * This callback is called when the error recovery driver tells us that
  2407. * its OK to resume normal operation. Implementation resembles the
  2408. * second-half of the atl1c_resume routine.
  2409. */
  2410. static void atl1c_io_resume(struct pci_dev *pdev)
  2411. {
  2412. struct net_device *netdev = pci_get_drvdata(pdev);
  2413. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2414. if (netif_running(netdev)) {
  2415. if (atl1c_up(adapter)) {
  2416. if (netif_msg_hw(adapter))
  2417. dev_err(&pdev->dev,
  2418. "Cannot bring device back up after reset\n");
  2419. return;
  2420. }
  2421. }
  2422. netif_device_attach(netdev);
  2423. }
  2424. static const struct pci_error_handlers atl1c_err_handler = {
  2425. .error_detected = atl1c_io_error_detected,
  2426. .slot_reset = atl1c_io_slot_reset,
  2427. .resume = atl1c_io_resume,
  2428. };
  2429. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2430. static struct pci_driver atl1c_driver = {
  2431. .name = atl1c_driver_name,
  2432. .id_table = atl1c_pci_tbl,
  2433. .probe = atl1c_probe,
  2434. .remove = atl1c_remove,
  2435. .shutdown = atl1c_shutdown,
  2436. .err_handler = &atl1c_err_handler,
  2437. .driver.pm = &atl1c_pm_ops,
  2438. };
  2439. module_pci_driver(atl1c_driver);