coda-bit.c 57 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/log2.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-fh.h>
  25. #include <media/v4l2-mem2mem.h>
  26. #include <media/videobuf2-core.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include <media/videobuf2-vmalloc.h>
  29. #include "coda.h"
  30. #define CREATE_TRACE_POINTS
  31. #include "trace.h"
  32. #define CODA_PARA_BUF_SIZE (10 * 1024)
  33. #define CODA7_PS_BUF_SIZE 0x28000
  34. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  35. #define CODA_DEFAULT_GAMMA 4096
  36. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  37. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  38. static inline int coda_is_initialized(struct coda_dev *dev)
  39. {
  40. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  41. }
  42. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  43. {
  44. return coda_read(dev, CODA_REG_BIT_BUSY);
  45. }
  46. static int coda_wait_timeout(struct coda_dev *dev)
  47. {
  48. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  49. while (coda_isbusy(dev)) {
  50. if (time_after(jiffies, timeout))
  51. return -ETIMEDOUT;
  52. }
  53. return 0;
  54. }
  55. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  56. {
  57. struct coda_dev *dev = ctx->dev;
  58. if (dev->devtype->product == CODA_960 ||
  59. dev->devtype->product == CODA_7541) {
  60. /* Restore context related registers to CODA */
  61. coda_write(dev, ctx->bit_stream_param,
  62. CODA_REG_BIT_BIT_STREAM_PARAM);
  63. coda_write(dev, ctx->frm_dis_flg,
  64. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  65. coda_write(dev, ctx->frame_mem_ctrl,
  66. CODA_REG_BIT_FRAME_MEM_CTRL);
  67. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  68. }
  69. if (dev->devtype->product == CODA_960) {
  70. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  71. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  72. }
  73. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  74. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  75. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  76. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  77. trace_coda_bit_run(ctx, cmd);
  78. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  79. }
  80. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  81. {
  82. struct coda_dev *dev = ctx->dev;
  83. int ret;
  84. coda_command_async(ctx, cmd);
  85. ret = coda_wait_timeout(dev);
  86. trace_coda_bit_done(ctx);
  87. return ret;
  88. }
  89. int coda_hw_reset(struct coda_ctx *ctx)
  90. {
  91. struct coda_dev *dev = ctx->dev;
  92. unsigned long timeout;
  93. unsigned int idx;
  94. int ret;
  95. if (!dev->rstc)
  96. return -ENOENT;
  97. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  98. if (dev->devtype->product == CODA_960) {
  99. timeout = jiffies + msecs_to_jiffies(100);
  100. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  101. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  102. if (time_after(jiffies, timeout))
  103. return -ETIME;
  104. cpu_relax();
  105. }
  106. }
  107. ret = reset_control_reset(dev->rstc);
  108. if (ret < 0)
  109. return ret;
  110. if (dev->devtype->product == CODA_960)
  111. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  112. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  113. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  114. ret = coda_wait_timeout(dev);
  115. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  116. return ret;
  117. }
  118. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  119. {
  120. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  121. struct coda_dev *dev = ctx->dev;
  122. u32 rd_ptr;
  123. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  124. kfifo->out = (kfifo->in & ~kfifo->mask) |
  125. (rd_ptr - ctx->bitstream.paddr);
  126. if (kfifo->out > kfifo->in)
  127. kfifo->out -= kfifo->mask + 1;
  128. }
  129. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  130. {
  131. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  132. struct coda_dev *dev = ctx->dev;
  133. u32 rd_ptr, wr_ptr;
  134. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  135. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  136. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  137. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  138. }
  139. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  140. {
  141. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  142. struct coda_dev *dev = ctx->dev;
  143. u32 wr_ptr;
  144. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  145. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  146. }
  147. static int coda_bitstream_queue(struct coda_ctx *ctx,
  148. struct vb2_buffer *src_buf)
  149. {
  150. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  151. u32 n;
  152. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
  153. src_size);
  154. if (n < src_size)
  155. return -ENOSPC;
  156. src_buf->v4l2_buf.sequence = ctx->qsequence++;
  157. return 0;
  158. }
  159. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  160. struct vb2_buffer *src_buf)
  161. {
  162. int ret;
  163. if (coda_get_bitstream_payload(ctx) +
  164. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  165. return false;
  166. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  167. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  168. return true;
  169. }
  170. ret = coda_bitstream_queue(ctx, src_buf);
  171. if (ret < 0) {
  172. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  173. return false;
  174. }
  175. /* Sync read pointer to device */
  176. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  177. coda_kfifo_sync_to_device_write(ctx);
  178. ctx->hold = false;
  179. return true;
  180. }
  181. void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
  182. {
  183. struct vb2_buffer *src_buf;
  184. struct coda_buffer_meta *meta;
  185. u32 start;
  186. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  187. /*
  188. * Only queue a single JPEG into the bitstream buffer, except
  189. * to increase payload over 512 bytes or if in hold state.
  190. */
  191. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  192. (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
  193. break;
  194. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  195. /* Drop frames that do not start/end with a SOI/EOI markers */
  196. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  197. !coda_jpeg_check_buffer(ctx, src_buf)) {
  198. v4l2_err(&ctx->dev->v4l2_dev,
  199. "dropping invalid JPEG frame %d\n",
  200. ctx->qsequence);
  201. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  202. v4l2_m2m_buf_done(src_buf, streaming ?
  203. VB2_BUF_STATE_ERROR :
  204. VB2_BUF_STATE_QUEUED);
  205. continue;
  206. }
  207. /* Buffer start position */
  208. start = ctx->bitstream_fifo.kfifo.in &
  209. ctx->bitstream_fifo.kfifo.mask;
  210. if (coda_bitstream_try_queue(ctx, src_buf)) {
  211. /*
  212. * Source buffer is queued in the bitstream ringbuffer;
  213. * queue the timestamp and mark source buffer as done
  214. */
  215. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  216. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  217. if (meta) {
  218. meta->sequence = src_buf->v4l2_buf.sequence;
  219. meta->timecode = src_buf->v4l2_buf.timecode;
  220. meta->timestamp = src_buf->v4l2_buf.timestamp;
  221. meta->start = start;
  222. meta->end = ctx->bitstream_fifo.kfifo.in &
  223. ctx->bitstream_fifo.kfifo.mask;
  224. list_add_tail(&meta->list,
  225. &ctx->buffer_meta_list);
  226. trace_coda_bit_queue(ctx, src_buf, meta);
  227. }
  228. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  229. } else {
  230. break;
  231. }
  232. }
  233. }
  234. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  235. {
  236. struct coda_dev *dev = ctx->dev;
  237. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  238. /* If this context is currently running, update the hardware flag */
  239. if ((dev->devtype->product == CODA_960) &&
  240. coda_isbusy(dev) &&
  241. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  242. coda_write(dev, ctx->bit_stream_param,
  243. CODA_REG_BIT_BIT_STREAM_PARAM);
  244. }
  245. }
  246. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  247. {
  248. struct coda_dev *dev = ctx->dev;
  249. u32 *p = ctx->parabuf.vaddr;
  250. if (dev->devtype->product == CODA_DX6)
  251. p[index] = value;
  252. else
  253. p[index ^ 1] = value;
  254. }
  255. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  256. struct coda_aux_buf *buf, size_t size,
  257. const char *name)
  258. {
  259. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  260. }
  261. static void coda_free_framebuffers(struct coda_ctx *ctx)
  262. {
  263. int i;
  264. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  265. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  266. }
  267. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  268. struct coda_q_data *q_data, u32 fourcc)
  269. {
  270. struct coda_dev *dev = ctx->dev;
  271. int width, height;
  272. dma_addr_t paddr;
  273. int ysize;
  274. int ret;
  275. int i;
  276. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  277. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  278. width = round_up(q_data->width, 16);
  279. height = round_up(q_data->height, 16);
  280. } else {
  281. width = round_up(q_data->width, 8);
  282. height = q_data->height;
  283. }
  284. ysize = width * height;
  285. /* Allocate frame buffers */
  286. for (i = 0; i < ctx->num_internal_frames; i++) {
  287. size_t size;
  288. char *name;
  289. size = ysize + ysize / 2;
  290. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  291. dev->devtype->product != CODA_DX6)
  292. size += ysize / 4;
  293. name = kasprintf(GFP_KERNEL, "fb%d", i);
  294. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  295. size, name);
  296. kfree(name);
  297. if (ret < 0) {
  298. coda_free_framebuffers(ctx);
  299. return ret;
  300. }
  301. }
  302. /* Register frame buffers in the parameter buffer */
  303. for (i = 0; i < ctx->num_internal_frames; i++) {
  304. paddr = ctx->internal_frames[i].paddr;
  305. /* Start addresses of Y, Cb, Cr planes */
  306. coda_parabuf_write(ctx, i * 3 + 0, paddr);
  307. coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
  308. coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
  309. /* mvcol buffer for h.264 */
  310. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  311. dev->devtype->product != CODA_DX6)
  312. coda_parabuf_write(ctx, 96 + i,
  313. ctx->internal_frames[i].paddr +
  314. ysize + ysize/4 + ysize/4);
  315. }
  316. /* mvcol buffer for mpeg4 */
  317. if ((dev->devtype->product != CODA_DX6) &&
  318. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  319. coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
  320. ysize + ysize/4 + ysize/4);
  321. return 0;
  322. }
  323. static void coda_free_context_buffers(struct coda_ctx *ctx)
  324. {
  325. struct coda_dev *dev = ctx->dev;
  326. coda_free_aux_buf(dev, &ctx->slicebuf);
  327. coda_free_aux_buf(dev, &ctx->psbuf);
  328. if (dev->devtype->product != CODA_DX6)
  329. coda_free_aux_buf(dev, &ctx->workbuf);
  330. coda_free_aux_buf(dev, &ctx->parabuf);
  331. }
  332. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  333. struct coda_q_data *q_data)
  334. {
  335. struct coda_dev *dev = ctx->dev;
  336. size_t size;
  337. int ret;
  338. if (!ctx->parabuf.vaddr) {
  339. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  340. CODA_PARA_BUF_SIZE, "parabuf");
  341. if (ret < 0)
  342. return ret;
  343. }
  344. if (dev->devtype->product == CODA_DX6)
  345. return 0;
  346. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  347. /* worst case slice size */
  348. size = (DIV_ROUND_UP(q_data->width, 16) *
  349. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  350. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  351. "slicebuf");
  352. if (ret < 0)
  353. goto err;
  354. }
  355. if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
  356. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  357. CODA7_PS_BUF_SIZE, "psbuf");
  358. if (ret < 0)
  359. goto err;
  360. }
  361. if (!ctx->workbuf.vaddr) {
  362. size = dev->devtype->workbuf_size;
  363. if (dev->devtype->product == CODA_960 &&
  364. q_data->fourcc == V4L2_PIX_FMT_H264)
  365. size += CODA9_PS_SAVE_SIZE;
  366. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  367. "workbuf");
  368. if (ret < 0)
  369. goto err;
  370. }
  371. return 0;
  372. err:
  373. coda_free_context_buffers(ctx);
  374. return ret;
  375. }
  376. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  377. int header_code, u8 *header, int *size)
  378. {
  379. struct coda_dev *dev = ctx->dev;
  380. size_t bufsize;
  381. int ret;
  382. int i;
  383. if (dev->devtype->product == CODA_960)
  384. memset(vb2_plane_vaddr(buf, 0), 0, 64);
  385. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  386. CODA_CMD_ENC_HEADER_BB_START);
  387. bufsize = vb2_plane_size(buf, 0);
  388. if (dev->devtype->product == CODA_960)
  389. bufsize /= 1024;
  390. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  391. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  392. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  393. if (ret < 0) {
  394. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  395. return ret;
  396. }
  397. if (dev->devtype->product == CODA_960) {
  398. for (i = 63; i > 0; i--)
  399. if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
  400. break;
  401. *size = i + 1;
  402. } else {
  403. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  404. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  405. }
  406. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  407. return 0;
  408. }
  409. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  410. {
  411. phys_addr_t ret;
  412. size = round_up(size, 1024);
  413. if (size > iram->remaining)
  414. return 0;
  415. iram->remaining -= size;
  416. ret = iram->next_paddr;
  417. iram->next_paddr += size;
  418. return ret;
  419. }
  420. static void coda_setup_iram(struct coda_ctx *ctx)
  421. {
  422. struct coda_iram_info *iram_info = &ctx->iram_info;
  423. struct coda_dev *dev = ctx->dev;
  424. int w64, w128;
  425. int mb_width;
  426. int dbk_bits;
  427. int bit_bits;
  428. int ip_bits;
  429. memset(iram_info, 0, sizeof(*iram_info));
  430. iram_info->next_paddr = dev->iram.paddr;
  431. iram_info->remaining = dev->iram.size;
  432. if (!dev->iram.vaddr)
  433. return;
  434. switch (dev->devtype->product) {
  435. case CODA_7541:
  436. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  437. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  438. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  439. break;
  440. case CODA_960:
  441. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  442. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  443. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  444. break;
  445. default: /* CODA_DX6 */
  446. return;
  447. }
  448. if (ctx->inst_type == CODA_INST_ENCODER) {
  449. struct coda_q_data *q_data_src;
  450. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  451. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  452. w128 = mb_width * 128;
  453. w64 = mb_width * 64;
  454. /* Prioritize in case IRAM is too small for everything */
  455. if (dev->devtype->product == CODA_7541) {
  456. iram_info->search_ram_size = round_up(mb_width * 16 *
  457. 36 + 2048, 1024);
  458. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  459. iram_info->search_ram_size);
  460. if (!iram_info->search_ram_paddr) {
  461. pr_err("IRAM is smaller than the search ram size\n");
  462. goto out;
  463. }
  464. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  465. CODA7_USE_ME_ENABLE;
  466. }
  467. /* Only H.264BP and H.263P3 are considered */
  468. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  469. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  470. if (!iram_info->buf_dbk_c_use)
  471. goto out;
  472. iram_info->axi_sram_use |= dbk_bits;
  473. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  474. if (!iram_info->buf_bit_use)
  475. goto out;
  476. iram_info->axi_sram_use |= bit_bits;
  477. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  478. if (!iram_info->buf_ip_ac_dc_use)
  479. goto out;
  480. iram_info->axi_sram_use |= ip_bits;
  481. /* OVL and BTP disabled for encoder */
  482. } else if (ctx->inst_type == CODA_INST_DECODER) {
  483. struct coda_q_data *q_data_dst;
  484. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  485. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  486. w128 = mb_width * 128;
  487. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  488. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  489. if (!iram_info->buf_dbk_c_use)
  490. goto out;
  491. iram_info->axi_sram_use |= dbk_bits;
  492. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  493. if (!iram_info->buf_bit_use)
  494. goto out;
  495. iram_info->axi_sram_use |= bit_bits;
  496. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  497. if (!iram_info->buf_ip_ac_dc_use)
  498. goto out;
  499. iram_info->axi_sram_use |= ip_bits;
  500. /* OVL and BTP unused as there is no VC1 support yet */
  501. }
  502. out:
  503. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  504. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  505. "IRAM smaller than needed\n");
  506. if (dev->devtype->product == CODA_7541) {
  507. /* TODO - Enabling these causes picture errors on CODA7541 */
  508. if (ctx->inst_type == CODA_INST_DECODER) {
  509. /* fw 1.4.50 */
  510. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  511. CODA7_USE_IP_ENABLE);
  512. } else {
  513. /* fw 13.4.29 */
  514. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  515. CODA7_USE_HOST_DBK_ENABLE |
  516. CODA7_USE_IP_ENABLE |
  517. CODA7_USE_DBK_ENABLE);
  518. }
  519. }
  520. }
  521. static u32 coda_supported_firmwares[] = {
  522. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  523. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  524. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  525. };
  526. static bool coda_firmware_supported(u32 vernum)
  527. {
  528. int i;
  529. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  530. if (vernum == coda_supported_firmwares[i])
  531. return true;
  532. return false;
  533. }
  534. int coda_check_firmware(struct coda_dev *dev)
  535. {
  536. u16 product, major, minor, release;
  537. u32 data;
  538. int ret;
  539. ret = clk_prepare_enable(dev->clk_per);
  540. if (ret)
  541. goto err_clk_per;
  542. ret = clk_prepare_enable(dev->clk_ahb);
  543. if (ret)
  544. goto err_clk_ahb;
  545. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  546. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  547. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  548. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  549. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  550. if (coda_wait_timeout(dev)) {
  551. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  552. ret = -EIO;
  553. goto err_run_cmd;
  554. }
  555. if (dev->devtype->product == CODA_960) {
  556. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  557. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  558. data);
  559. }
  560. /* Check we are compatible with the loaded firmware */
  561. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  562. product = CODA_FIRMWARE_PRODUCT(data);
  563. major = CODA_FIRMWARE_MAJOR(data);
  564. minor = CODA_FIRMWARE_MINOR(data);
  565. release = CODA_FIRMWARE_RELEASE(data);
  566. clk_disable_unprepare(dev->clk_per);
  567. clk_disable_unprepare(dev->clk_ahb);
  568. if (product != dev->devtype->product) {
  569. v4l2_err(&dev->v4l2_dev,
  570. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  571. coda_product_name(dev->devtype->product),
  572. coda_product_name(product), major, minor, release);
  573. return -EINVAL;
  574. }
  575. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  576. coda_product_name(product));
  577. if (coda_firmware_supported(data)) {
  578. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  579. major, minor, release);
  580. } else {
  581. v4l2_warn(&dev->v4l2_dev,
  582. "Unsupported firmware version: %u.%u.%u\n",
  583. major, minor, release);
  584. }
  585. return 0;
  586. err_run_cmd:
  587. clk_disable_unprepare(dev->clk_ahb);
  588. err_clk_ahb:
  589. clk_disable_unprepare(dev->clk_per);
  590. err_clk_per:
  591. return ret;
  592. }
  593. /*
  594. * Encoder context operations
  595. */
  596. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  597. struct v4l2_requestbuffers *rb)
  598. {
  599. struct coda_q_data *q_data_src;
  600. int ret;
  601. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  602. return 0;
  603. if (rb->count) {
  604. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  605. ret = coda_alloc_context_buffers(ctx, q_data_src);
  606. if (ret < 0)
  607. return ret;
  608. } else {
  609. coda_free_context_buffers(ctx);
  610. }
  611. return 0;
  612. }
  613. static int coda_start_encoding(struct coda_ctx *ctx)
  614. {
  615. struct coda_dev *dev = ctx->dev;
  616. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  617. struct coda_q_data *q_data_src, *q_data_dst;
  618. u32 bitstream_buf, bitstream_size;
  619. struct vb2_buffer *buf;
  620. int gamma, ret, value;
  621. u32 dst_fourcc;
  622. int num_fb;
  623. u32 stride;
  624. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  625. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  626. dst_fourcc = q_data_dst->fourcc;
  627. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  628. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  629. bitstream_size = q_data_dst->sizeimage;
  630. if (!coda_is_initialized(dev)) {
  631. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  632. return -EFAULT;
  633. }
  634. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  635. if (!ctx->params.jpeg_qmat_tab[0])
  636. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  637. if (!ctx->params.jpeg_qmat_tab[1])
  638. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  639. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  640. }
  641. mutex_lock(&dev->coda_mutex);
  642. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  643. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  644. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  645. switch (dev->devtype->product) {
  646. case CODA_DX6:
  647. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  648. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  649. break;
  650. case CODA_960:
  651. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  652. /* fallthrough */
  653. case CODA_7541:
  654. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  655. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  656. break;
  657. }
  658. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  659. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  660. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  661. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  662. if (dev->devtype->product == CODA_DX6) {
  663. /* Configure the coda */
  664. coda_write(dev, dev->iram.paddr,
  665. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  666. }
  667. /* Could set rotation here if needed */
  668. value = 0;
  669. switch (dev->devtype->product) {
  670. case CODA_DX6:
  671. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  672. << CODADX6_PICWIDTH_OFFSET;
  673. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  674. << CODA_PICHEIGHT_OFFSET;
  675. break;
  676. case CODA_7541:
  677. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  678. value = (round_up(q_data_src->width, 16) &
  679. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  680. value |= (round_up(q_data_src->height, 16) &
  681. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  682. break;
  683. }
  684. /* fallthrough */
  685. case CODA_960:
  686. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  687. << CODA7_PICWIDTH_OFFSET;
  688. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  689. << CODA_PICHEIGHT_OFFSET;
  690. }
  691. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  692. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  693. ctx->params.framerate = 0;
  694. coda_write(dev, ctx->params.framerate,
  695. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  696. ctx->params.codec_mode = ctx->codec->mode;
  697. switch (dst_fourcc) {
  698. case V4L2_PIX_FMT_MPEG4:
  699. if (dev->devtype->product == CODA_960)
  700. coda_write(dev, CODA9_STD_MPEG4,
  701. CODA_CMD_ENC_SEQ_COD_STD);
  702. else
  703. coda_write(dev, CODA_STD_MPEG4,
  704. CODA_CMD_ENC_SEQ_COD_STD);
  705. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  706. break;
  707. case V4L2_PIX_FMT_H264:
  708. if (dev->devtype->product == CODA_960)
  709. coda_write(dev, CODA9_STD_H264,
  710. CODA_CMD_ENC_SEQ_COD_STD);
  711. else
  712. coda_write(dev, CODA_STD_H264,
  713. CODA_CMD_ENC_SEQ_COD_STD);
  714. if (ctx->params.h264_deblk_enabled) {
  715. value = ((ctx->params.h264_deblk_alpha &
  716. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  717. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  718. ((ctx->params.h264_deblk_beta &
  719. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  720. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  721. } else {
  722. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  723. }
  724. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  725. break;
  726. case V4L2_PIX_FMT_JPEG:
  727. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  728. coda_write(dev, ctx->params.jpeg_restart_interval,
  729. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  730. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  731. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  732. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  733. coda_jpeg_write_tables(ctx);
  734. break;
  735. default:
  736. v4l2_err(v4l2_dev,
  737. "dst format (0x%08x) invalid.\n", dst_fourcc);
  738. ret = -EINVAL;
  739. goto out;
  740. }
  741. /*
  742. * slice mode and GOP size registers are used for thumb size/offset
  743. * in JPEG mode
  744. */
  745. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  746. switch (ctx->params.slice_mode) {
  747. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  748. value = 0;
  749. break;
  750. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  751. value = (ctx->params.slice_max_mb &
  752. CODA_SLICING_SIZE_MASK)
  753. << CODA_SLICING_SIZE_OFFSET;
  754. value |= (1 & CODA_SLICING_UNIT_MASK)
  755. << CODA_SLICING_UNIT_OFFSET;
  756. value |= 1 & CODA_SLICING_MODE_MASK;
  757. break;
  758. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  759. value = (ctx->params.slice_max_bits &
  760. CODA_SLICING_SIZE_MASK)
  761. << CODA_SLICING_SIZE_OFFSET;
  762. value |= (0 & CODA_SLICING_UNIT_MASK)
  763. << CODA_SLICING_UNIT_OFFSET;
  764. value |= 1 & CODA_SLICING_MODE_MASK;
  765. break;
  766. }
  767. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  768. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  769. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  770. }
  771. if (ctx->params.bitrate) {
  772. /* Rate control enabled */
  773. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  774. << CODA_RATECONTROL_BITRATE_OFFSET;
  775. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  776. if (dev->devtype->product == CODA_960)
  777. value |= BIT(31); /* disable autoskip */
  778. } else {
  779. value = 0;
  780. }
  781. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  782. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  783. coda_write(dev, ctx->params.intra_refresh,
  784. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  785. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  786. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  787. value = 0;
  788. if (dev->devtype->product == CODA_960)
  789. gamma = CODA9_DEFAULT_GAMMA;
  790. else
  791. gamma = CODA_DEFAULT_GAMMA;
  792. if (gamma > 0) {
  793. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  794. CODA_CMD_ENC_SEQ_RC_GAMMA);
  795. }
  796. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  797. coda_write(dev,
  798. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  799. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  800. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  801. }
  802. if (dev->devtype->product == CODA_960) {
  803. if (ctx->params.h264_max_qp)
  804. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  805. if (CODA_DEFAULT_GAMMA > 0)
  806. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  807. } else {
  808. if (CODA_DEFAULT_GAMMA > 0) {
  809. if (dev->devtype->product == CODA_DX6)
  810. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  811. else
  812. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  813. }
  814. if (ctx->params.h264_min_qp)
  815. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  816. if (ctx->params.h264_max_qp)
  817. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  818. }
  819. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  820. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  821. coda_setup_iram(ctx);
  822. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  823. switch (dev->devtype->product) {
  824. case CODA_DX6:
  825. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  826. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  827. break;
  828. case CODA_7541:
  829. coda_write(dev, ctx->iram_info.search_ram_paddr,
  830. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  831. coda_write(dev, ctx->iram_info.search_ram_size,
  832. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  833. break;
  834. case CODA_960:
  835. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  836. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  837. }
  838. }
  839. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  840. if (ret < 0) {
  841. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  842. goto out;
  843. }
  844. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  845. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  846. ret = -EFAULT;
  847. goto out;
  848. }
  849. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  850. if (dev->devtype->product == CODA_960)
  851. ctx->num_internal_frames = 4;
  852. else
  853. ctx->num_internal_frames = 2;
  854. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  855. if (ret < 0) {
  856. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  857. goto out;
  858. }
  859. num_fb = 2;
  860. stride = q_data_src->bytesperline;
  861. } else {
  862. ctx->num_internal_frames = 0;
  863. num_fb = 0;
  864. stride = 0;
  865. }
  866. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  867. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  868. if (dev->devtype->product == CODA_7541) {
  869. coda_write(dev, q_data_src->bytesperline,
  870. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  871. }
  872. if (dev->devtype->product != CODA_DX6) {
  873. coda_write(dev, ctx->iram_info.buf_bit_use,
  874. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  875. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  876. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  877. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  878. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  879. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  880. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  881. coda_write(dev, ctx->iram_info.buf_ovl_use,
  882. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  883. if (dev->devtype->product == CODA_960) {
  884. coda_write(dev, ctx->iram_info.buf_btp_use,
  885. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  886. /* FIXME */
  887. coda_write(dev, ctx->internal_frames[2].paddr,
  888. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  889. coda_write(dev, ctx->internal_frames[3].paddr,
  890. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  891. }
  892. }
  893. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  894. if (ret < 0) {
  895. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  896. goto out;
  897. }
  898. /* Save stream headers */
  899. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  900. switch (dst_fourcc) {
  901. case V4L2_PIX_FMT_H264:
  902. /*
  903. * Get SPS in the first frame and copy it to an
  904. * intermediate buffer.
  905. */
  906. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  907. &ctx->vpu_header[0][0],
  908. &ctx->vpu_header_size[0]);
  909. if (ret < 0)
  910. goto out;
  911. /*
  912. * Get PPS in the first frame and copy it to an
  913. * intermediate buffer.
  914. */
  915. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  916. &ctx->vpu_header[1][0],
  917. &ctx->vpu_header_size[1]);
  918. if (ret < 0)
  919. goto out;
  920. /*
  921. * Length of H.264 headers is variable and thus it might not be
  922. * aligned for the coda to append the encoded frame. In that is
  923. * the case a filler NAL must be added to header 2.
  924. */
  925. ctx->vpu_header_size[2] = coda_h264_padding(
  926. (ctx->vpu_header_size[0] +
  927. ctx->vpu_header_size[1]),
  928. ctx->vpu_header[2]);
  929. break;
  930. case V4L2_PIX_FMT_MPEG4:
  931. /*
  932. * Get VOS in the first frame and copy it to an
  933. * intermediate buffer
  934. */
  935. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  936. &ctx->vpu_header[0][0],
  937. &ctx->vpu_header_size[0]);
  938. if (ret < 0)
  939. goto out;
  940. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  941. &ctx->vpu_header[1][0],
  942. &ctx->vpu_header_size[1]);
  943. if (ret < 0)
  944. goto out;
  945. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  946. &ctx->vpu_header[2][0],
  947. &ctx->vpu_header_size[2]);
  948. if (ret < 0)
  949. goto out;
  950. break;
  951. default:
  952. /* No more formats need to save headers at the moment */
  953. break;
  954. }
  955. out:
  956. mutex_unlock(&dev->coda_mutex);
  957. return ret;
  958. }
  959. static int coda_prepare_encode(struct coda_ctx *ctx)
  960. {
  961. struct coda_q_data *q_data_src, *q_data_dst;
  962. struct vb2_buffer *src_buf, *dst_buf;
  963. struct coda_dev *dev = ctx->dev;
  964. int force_ipicture;
  965. int quant_param = 0;
  966. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  967. u32 rot_mode = 0;
  968. u32 dst_fourcc;
  969. u32 reg;
  970. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  971. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  972. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  973. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  974. dst_fourcc = q_data_dst->fourcc;
  975. src_buf->v4l2_buf.sequence = ctx->osequence;
  976. dst_buf->v4l2_buf.sequence = ctx->osequence;
  977. ctx->osequence++;
  978. /*
  979. * Workaround coda firmware BUG that only marks the first
  980. * frame as IDR. This is a problem for some decoders that can't
  981. * recover when a frame is lost.
  982. */
  983. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  984. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  985. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  986. } else {
  987. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  988. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  989. }
  990. if (dev->devtype->product == CODA_960)
  991. coda_set_gdi_regs(ctx);
  992. /*
  993. * Copy headers at the beginning of the first frame for H.264 only.
  994. * In MPEG4 they are already copied by the coda.
  995. */
  996. if (src_buf->v4l2_buf.sequence == 0) {
  997. pic_stream_buffer_addr =
  998. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  999. ctx->vpu_header_size[0] +
  1000. ctx->vpu_header_size[1] +
  1001. ctx->vpu_header_size[2];
  1002. pic_stream_buffer_size = q_data_dst->sizeimage -
  1003. ctx->vpu_header_size[0] -
  1004. ctx->vpu_header_size[1] -
  1005. ctx->vpu_header_size[2];
  1006. memcpy(vb2_plane_vaddr(dst_buf, 0),
  1007. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1008. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  1009. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  1010. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  1011. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  1012. ctx->vpu_header_size[2]);
  1013. } else {
  1014. pic_stream_buffer_addr =
  1015. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  1016. pic_stream_buffer_size = q_data_dst->sizeimage;
  1017. }
  1018. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1019. force_ipicture = 1;
  1020. switch (dst_fourcc) {
  1021. case V4L2_PIX_FMT_H264:
  1022. quant_param = ctx->params.h264_intra_qp;
  1023. break;
  1024. case V4L2_PIX_FMT_MPEG4:
  1025. quant_param = ctx->params.mpeg4_intra_qp;
  1026. break;
  1027. case V4L2_PIX_FMT_JPEG:
  1028. quant_param = 30;
  1029. break;
  1030. default:
  1031. v4l2_warn(&ctx->dev->v4l2_dev,
  1032. "cannot set intra qp, fmt not supported\n");
  1033. break;
  1034. }
  1035. } else {
  1036. force_ipicture = 0;
  1037. switch (dst_fourcc) {
  1038. case V4L2_PIX_FMT_H264:
  1039. quant_param = ctx->params.h264_inter_qp;
  1040. break;
  1041. case V4L2_PIX_FMT_MPEG4:
  1042. quant_param = ctx->params.mpeg4_inter_qp;
  1043. break;
  1044. default:
  1045. v4l2_warn(&ctx->dev->v4l2_dev,
  1046. "cannot set inter qp, fmt not supported\n");
  1047. break;
  1048. }
  1049. }
  1050. /* submit */
  1051. if (ctx->params.rot_mode)
  1052. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1053. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1054. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1055. if (dev->devtype->product == CODA_960) {
  1056. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1057. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1058. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1059. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1060. } else {
  1061. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1062. }
  1063. coda_write_base(ctx, q_data_src, src_buf, reg);
  1064. coda_write(dev, force_ipicture << 1 & 0x2,
  1065. CODA_CMD_ENC_PIC_OPTION);
  1066. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1067. coda_write(dev, pic_stream_buffer_size / 1024,
  1068. CODA_CMD_ENC_PIC_BB_SIZE);
  1069. if (!ctx->streamon_out) {
  1070. /* After streamoff on the output side, set stream end flag */
  1071. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1072. coda_write(dev, ctx->bit_stream_param,
  1073. CODA_REG_BIT_BIT_STREAM_PARAM);
  1074. }
  1075. if (dev->devtype->product != CODA_DX6)
  1076. coda_write(dev, ctx->iram_info.axi_sram_use,
  1077. CODA7_REG_BIT_AXI_SRAM_USE);
  1078. trace_coda_enc_pic_run(ctx, src_buf);
  1079. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1080. return 0;
  1081. }
  1082. static void coda_finish_encode(struct coda_ctx *ctx)
  1083. {
  1084. struct vb2_buffer *src_buf, *dst_buf;
  1085. struct coda_dev *dev = ctx->dev;
  1086. u32 wr_ptr, start_ptr;
  1087. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1088. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1089. trace_coda_enc_pic_done(ctx, dst_buf);
  1090. /* Get results from the coda */
  1091. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1092. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1093. /* Calculate bytesused field */
  1094. if (dst_buf->v4l2_buf.sequence == 0) {
  1095. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1096. ctx->vpu_header_size[0] +
  1097. ctx->vpu_header_size[1] +
  1098. ctx->vpu_header_size[2]);
  1099. } else {
  1100. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1101. }
  1102. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1103. wr_ptr - start_ptr);
  1104. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1105. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1106. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1107. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1108. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1109. } else {
  1110. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1111. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1112. }
  1113. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1114. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1115. dst_buf->v4l2_buf.flags |=
  1116. src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1117. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1118. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1119. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1120. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1121. ctx->gopcounter--;
  1122. if (ctx->gopcounter < 0)
  1123. ctx->gopcounter = ctx->params.gop_size - 1;
  1124. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1125. "job finished: encoding frame (%d) (%s)\n",
  1126. dst_buf->v4l2_buf.sequence,
  1127. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1128. "KEYFRAME" : "PFRAME");
  1129. }
  1130. static void coda_seq_end_work(struct work_struct *work)
  1131. {
  1132. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1133. struct coda_dev *dev = ctx->dev;
  1134. mutex_lock(&ctx->buffer_mutex);
  1135. mutex_lock(&dev->coda_mutex);
  1136. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1137. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1138. __func__);
  1139. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1140. v4l2_err(&dev->v4l2_dev,
  1141. "CODA_COMMAND_SEQ_END failed\n");
  1142. }
  1143. kfifo_init(&ctx->bitstream_fifo,
  1144. ctx->bitstream.vaddr, ctx->bitstream.size);
  1145. coda_free_framebuffers(ctx);
  1146. mutex_unlock(&dev->coda_mutex);
  1147. mutex_unlock(&ctx->buffer_mutex);
  1148. }
  1149. static void coda_bit_release(struct coda_ctx *ctx)
  1150. {
  1151. mutex_lock(&ctx->buffer_mutex);
  1152. coda_free_framebuffers(ctx);
  1153. coda_free_context_buffers(ctx);
  1154. coda_free_bitstream_buffer(ctx);
  1155. mutex_unlock(&ctx->buffer_mutex);
  1156. }
  1157. const struct coda_context_ops coda_bit_encode_ops = {
  1158. .queue_init = coda_encoder_queue_init,
  1159. .reqbufs = coda_encoder_reqbufs,
  1160. .start_streaming = coda_start_encoding,
  1161. .prepare_run = coda_prepare_encode,
  1162. .finish_run = coda_finish_encode,
  1163. .seq_end_work = coda_seq_end_work,
  1164. .release = coda_bit_release,
  1165. };
  1166. /*
  1167. * Decoder context operations
  1168. */
  1169. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1170. struct coda_q_data *q_data)
  1171. {
  1172. if (ctx->bitstream.vaddr)
  1173. return 0;
  1174. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1175. ctx->bitstream.vaddr = dma_alloc_writecombine(
  1176. &ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1177. &ctx->bitstream.paddr, GFP_KERNEL);
  1178. if (!ctx->bitstream.vaddr) {
  1179. v4l2_err(&ctx->dev->v4l2_dev,
  1180. "failed to allocate bitstream ringbuffer");
  1181. return -ENOMEM;
  1182. }
  1183. kfifo_init(&ctx->bitstream_fifo,
  1184. ctx->bitstream.vaddr, ctx->bitstream.size);
  1185. return 0;
  1186. }
  1187. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1188. {
  1189. if (ctx->bitstream.vaddr == NULL)
  1190. return;
  1191. dma_free_writecombine(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1192. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1193. ctx->bitstream.vaddr = NULL;
  1194. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1195. }
  1196. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1197. struct v4l2_requestbuffers *rb)
  1198. {
  1199. struct coda_q_data *q_data_src;
  1200. int ret;
  1201. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1202. return 0;
  1203. if (rb->count) {
  1204. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1205. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1206. if (ret < 0)
  1207. return ret;
  1208. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1209. if (ret < 0) {
  1210. coda_free_context_buffers(ctx);
  1211. return ret;
  1212. }
  1213. } else {
  1214. coda_free_bitstream_buffer(ctx);
  1215. coda_free_context_buffers(ctx);
  1216. }
  1217. return 0;
  1218. }
  1219. static int __coda_start_decoding(struct coda_ctx *ctx)
  1220. {
  1221. struct coda_q_data *q_data_src, *q_data_dst;
  1222. u32 bitstream_buf, bitstream_size;
  1223. struct coda_dev *dev = ctx->dev;
  1224. int width, height;
  1225. u32 src_fourcc, dst_fourcc;
  1226. u32 val;
  1227. int ret;
  1228. /* Start decoding */
  1229. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1230. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1231. bitstream_buf = ctx->bitstream.paddr;
  1232. bitstream_size = ctx->bitstream.size;
  1233. src_fourcc = q_data_src->fourcc;
  1234. dst_fourcc = q_data_dst->fourcc;
  1235. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1236. /* Update coda bitstream read and write pointers from kfifo */
  1237. coda_kfifo_sync_to_device_full(ctx);
  1238. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  1239. if (dst_fourcc == V4L2_PIX_FMT_NV12)
  1240. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1241. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1242. ctx->display_idx = -1;
  1243. ctx->frm_dis_flg = 0;
  1244. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1245. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1246. CODA_REG_BIT_BIT_STREAM_PARAM);
  1247. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1248. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1249. val = 0;
  1250. if ((dev->devtype->product == CODA_7541) ||
  1251. (dev->devtype->product == CODA_960))
  1252. val |= CODA_REORDER_ENABLE;
  1253. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1254. val |= CODA_NO_INT_ENABLE;
  1255. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1256. ctx->params.codec_mode = ctx->codec->mode;
  1257. if (dev->devtype->product == CODA_960 &&
  1258. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1259. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1260. else
  1261. ctx->params.codec_mode_aux = 0;
  1262. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1263. if (dev->devtype->product == CODA_7541) {
  1264. coda_write(dev, ctx->psbuf.paddr,
  1265. CODA_CMD_DEC_SEQ_PS_BB_START);
  1266. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1267. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1268. }
  1269. if (dev->devtype->product == CODA_960) {
  1270. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1271. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1272. }
  1273. }
  1274. if (dev->devtype->product != CODA_960)
  1275. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1276. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1277. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1278. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1279. return -ETIMEDOUT;
  1280. }
  1281. /* Update kfifo out pointer from coda bitstream read pointer */
  1282. coda_kfifo_sync_from_device(ctx);
  1283. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1284. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1285. v4l2_err(&dev->v4l2_dev,
  1286. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1287. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1288. return -EAGAIN;
  1289. }
  1290. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1291. if (dev->devtype->product == CODA_DX6) {
  1292. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1293. height = val & CODADX6_PICHEIGHT_MASK;
  1294. } else {
  1295. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1296. height = val & CODA7_PICHEIGHT_MASK;
  1297. }
  1298. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1299. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1300. width, height, q_data_dst->bytesperline,
  1301. q_data_dst->height);
  1302. return -EINVAL;
  1303. }
  1304. width = round_up(width, 16);
  1305. height = round_up(height, 16);
  1306. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1307. __func__, ctx->idx, width, height);
  1308. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1309. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1310. v4l2_err(&dev->v4l2_dev,
  1311. "not enough framebuffers to decode (%d < %d)\n",
  1312. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1313. return -EINVAL;
  1314. }
  1315. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1316. u32 left_right;
  1317. u32 top_bottom;
  1318. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1319. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1320. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1321. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1322. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1323. (left_right & 0x3ff);
  1324. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1325. (top_bottom & 0x3ff);
  1326. }
  1327. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1328. if (ret < 0) {
  1329. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1330. return ret;
  1331. }
  1332. /* Tell the decoder how many frame buffers we allocated. */
  1333. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1334. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1335. if (dev->devtype->product != CODA_DX6) {
  1336. /* Set secondary AXI IRAM */
  1337. coda_setup_iram(ctx);
  1338. coda_write(dev, ctx->iram_info.buf_bit_use,
  1339. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1340. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1341. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1342. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1343. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1344. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1345. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1346. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1347. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1348. if (dev->devtype->product == CODA_960)
  1349. coda_write(dev, ctx->iram_info.buf_btp_use,
  1350. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1351. }
  1352. if (dev->devtype->product == CODA_960) {
  1353. int cbb_size, crb_size;
  1354. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1355. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  1356. coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  1357. if (dst_fourcc == V4L2_PIX_FMT_NV12) {
  1358. cbb_size = 0;
  1359. crb_size = 16;
  1360. } else {
  1361. cbb_size = 8;
  1362. crb_size = 8;
  1363. }
  1364. coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
  1365. 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  1366. cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
  1367. crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
  1368. CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  1369. }
  1370. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1371. coda_write(dev, ctx->slicebuf.paddr,
  1372. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1373. coda_write(dev, ctx->slicebuf.size / 1024,
  1374. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1375. }
  1376. if (dev->devtype->product == CODA_7541) {
  1377. int max_mb_x = 1920 / 16;
  1378. int max_mb_y = 1088 / 16;
  1379. int max_mb_num = max_mb_x * max_mb_y;
  1380. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1381. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1382. } else if (dev->devtype->product == CODA_960) {
  1383. int max_mb_x = 1920 / 16;
  1384. int max_mb_y = 1088 / 16;
  1385. int max_mb_num = max_mb_x * max_mb_y;
  1386. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1387. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1388. }
  1389. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1390. v4l2_err(&ctx->dev->v4l2_dev,
  1391. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1392. return -ETIMEDOUT;
  1393. }
  1394. return 0;
  1395. }
  1396. static int coda_start_decoding(struct coda_ctx *ctx)
  1397. {
  1398. struct coda_dev *dev = ctx->dev;
  1399. int ret;
  1400. mutex_lock(&dev->coda_mutex);
  1401. ret = __coda_start_decoding(ctx);
  1402. mutex_unlock(&dev->coda_mutex);
  1403. return ret;
  1404. }
  1405. static int coda_prepare_decode(struct coda_ctx *ctx)
  1406. {
  1407. struct vb2_buffer *dst_buf;
  1408. struct coda_dev *dev = ctx->dev;
  1409. struct coda_q_data *q_data_dst;
  1410. struct coda_buffer_meta *meta;
  1411. u32 reg_addr, reg_stride;
  1412. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1413. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1414. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1415. mutex_lock(&ctx->bitstream_mutex);
  1416. coda_fill_bitstream(ctx, true);
  1417. mutex_unlock(&ctx->bitstream_mutex);
  1418. if (coda_get_bitstream_payload(ctx) < 512 &&
  1419. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1420. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1421. "bitstream payload: %d, skipping\n",
  1422. coda_get_bitstream_payload(ctx));
  1423. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1424. return -EAGAIN;
  1425. }
  1426. /* Run coda_start_decoding (again) if not yet initialized */
  1427. if (!ctx->initialized) {
  1428. int ret = __coda_start_decoding(ctx);
  1429. if (ret < 0) {
  1430. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1431. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1432. return -EAGAIN;
  1433. } else {
  1434. ctx->initialized = 1;
  1435. }
  1436. }
  1437. if (dev->devtype->product == CODA_960)
  1438. coda_set_gdi_regs(ctx);
  1439. if (dev->devtype->product == CODA_960) {
  1440. /*
  1441. * The CODA960 seems to have an internal list of buffers with
  1442. * 64 entries that includes the registered frame buffers as
  1443. * well as the rotator buffer output.
  1444. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1445. */
  1446. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
  1447. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1448. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1449. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1450. } else {
  1451. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1452. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1453. }
  1454. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1455. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1456. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1457. CODA_CMD_DEC_PIC_ROT_MODE);
  1458. switch (dev->devtype->product) {
  1459. case CODA_DX6:
  1460. /* TBD */
  1461. case CODA_7541:
  1462. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1463. break;
  1464. case CODA_960:
  1465. /* 'hardcode to use interrupt disable mode'? */
  1466. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1467. break;
  1468. }
  1469. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1470. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1471. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1472. if (dev->devtype->product != CODA_DX6)
  1473. coda_write(dev, ctx->iram_info.axi_sram_use,
  1474. CODA7_REG_BIT_AXI_SRAM_USE);
  1475. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1476. struct coda_buffer_meta, list);
  1477. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1478. /* If this is the last buffer in the bitstream, add padding */
  1479. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1480. ctx->bitstream_fifo.kfifo.mask)) {
  1481. static unsigned char buf[512];
  1482. unsigned int pad;
  1483. /* Pad to multiple of 256 and then add 256 more */
  1484. pad = ((0 - meta->end) & 0xff) + 256;
  1485. memset(buf, 0xff, sizeof(buf));
  1486. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1487. }
  1488. }
  1489. coda_kfifo_sync_to_device_full(ctx);
  1490. /* Clear decode success flag */
  1491. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1492. trace_coda_dec_pic_run(ctx, meta);
  1493. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1494. return 0;
  1495. }
  1496. static void coda_finish_decode(struct coda_ctx *ctx)
  1497. {
  1498. struct coda_dev *dev = ctx->dev;
  1499. struct coda_q_data *q_data_src;
  1500. struct coda_q_data *q_data_dst;
  1501. struct vb2_buffer *dst_buf;
  1502. struct coda_buffer_meta *meta;
  1503. unsigned long payload;
  1504. int width, height;
  1505. int decoded_idx;
  1506. int display_idx;
  1507. u32 src_fourcc;
  1508. int success;
  1509. u32 err_mb;
  1510. u32 val;
  1511. /* Update kfifo out pointer from coda bitstream read pointer */
  1512. coda_kfifo_sync_from_device(ctx);
  1513. /*
  1514. * in stream-end mode, the read pointer can overshoot the write pointer
  1515. * by up to 512 bytes
  1516. */
  1517. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1518. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1519. kfifo_init(&ctx->bitstream_fifo,
  1520. ctx->bitstream.vaddr, ctx->bitstream.size);
  1521. }
  1522. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1523. src_fourcc = q_data_src->fourcc;
  1524. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1525. if (val != 1)
  1526. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1527. success = val & 0x1;
  1528. if (!success)
  1529. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1530. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1531. if (val & (1 << 3))
  1532. v4l2_err(&dev->v4l2_dev,
  1533. "insufficient PS buffer space (%d bytes)\n",
  1534. ctx->psbuf.size);
  1535. if (val & (1 << 2))
  1536. v4l2_err(&dev->v4l2_dev,
  1537. "insufficient slice buffer space (%d bytes)\n",
  1538. ctx->slicebuf.size);
  1539. }
  1540. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1541. width = (val >> 16) & 0xffff;
  1542. height = val & 0xffff;
  1543. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1544. /* frame crop information */
  1545. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1546. u32 left_right;
  1547. u32 top_bottom;
  1548. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1549. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1550. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1551. /* Keep current crop information */
  1552. } else {
  1553. struct v4l2_rect *rect = &q_data_dst->rect;
  1554. rect->left = left_right >> 16 & 0xffff;
  1555. rect->top = top_bottom >> 16 & 0xffff;
  1556. rect->width = width - rect->left -
  1557. (left_right & 0xffff);
  1558. rect->height = height - rect->top -
  1559. (top_bottom & 0xffff);
  1560. }
  1561. } else {
  1562. /* no cropping */
  1563. }
  1564. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1565. if (err_mb > 0)
  1566. v4l2_err(&dev->v4l2_dev,
  1567. "errors in %d macroblocks\n", err_mb);
  1568. if (dev->devtype->product == CODA_7541) {
  1569. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1570. if (val == 0) {
  1571. /* not enough bitstream data */
  1572. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1573. "prescan failed: %d\n", val);
  1574. ctx->hold = true;
  1575. return;
  1576. }
  1577. }
  1578. ctx->frm_dis_flg = coda_read(dev,
  1579. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1580. /*
  1581. * The previous display frame was copied out by the rotator,
  1582. * now it can be overwritten again
  1583. */
  1584. if (ctx->display_idx >= 0 &&
  1585. ctx->display_idx < ctx->num_internal_frames) {
  1586. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1587. coda_write(dev, ctx->frm_dis_flg,
  1588. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1589. }
  1590. /*
  1591. * The index of the last decoded frame, not necessarily in
  1592. * display order, and the index of the next display frame.
  1593. * The latter could have been decoded in a previous run.
  1594. */
  1595. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1596. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1597. if (decoded_idx == -1) {
  1598. /* no frame was decoded, but we might have a display frame */
  1599. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1600. ctx->sequence_offset++;
  1601. else if (ctx->display_idx < 0)
  1602. ctx->hold = true;
  1603. } else if (decoded_idx == -2) {
  1604. /* no frame was decoded, we still return remaining buffers */
  1605. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1606. v4l2_err(&dev->v4l2_dev,
  1607. "decoded frame index out of range: %d\n", decoded_idx);
  1608. } else {
  1609. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1610. val -= ctx->sequence_offset;
  1611. mutex_lock(&ctx->bitstream_mutex);
  1612. if (!list_empty(&ctx->buffer_meta_list)) {
  1613. meta = list_first_entry(&ctx->buffer_meta_list,
  1614. struct coda_buffer_meta, list);
  1615. list_del(&meta->list);
  1616. if (val != (meta->sequence & 0xffff)) {
  1617. v4l2_err(&dev->v4l2_dev,
  1618. "sequence number mismatch (%d(%d) != %d)\n",
  1619. val, ctx->sequence_offset,
  1620. meta->sequence);
  1621. }
  1622. ctx->frame_metas[decoded_idx] = *meta;
  1623. kfree(meta);
  1624. } else {
  1625. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1626. memset(&ctx->frame_metas[decoded_idx], 0,
  1627. sizeof(struct coda_buffer_meta));
  1628. ctx->frame_metas[decoded_idx].sequence = val;
  1629. ctx->sequence_offset++;
  1630. }
  1631. mutex_unlock(&ctx->bitstream_mutex);
  1632. trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
  1633. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1634. if (val == 0)
  1635. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1636. else if (val == 1)
  1637. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1638. else
  1639. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1640. ctx->frame_errors[decoded_idx] = err_mb;
  1641. }
  1642. if (display_idx == -1) {
  1643. /*
  1644. * no more frames to be decoded, but there could still
  1645. * be rotator output to dequeue
  1646. */
  1647. ctx->hold = true;
  1648. } else if (display_idx == -3) {
  1649. /* possibly prescan failure */
  1650. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1651. v4l2_err(&dev->v4l2_dev,
  1652. "presentation frame index out of range: %d\n",
  1653. display_idx);
  1654. }
  1655. /* If a frame was copied out, return it */
  1656. if (ctx->display_idx >= 0 &&
  1657. ctx->display_idx < ctx->num_internal_frames) {
  1658. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1659. dst_buf->v4l2_buf.sequence = ctx->osequence++;
  1660. dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1661. V4L2_BUF_FLAG_PFRAME |
  1662. V4L2_BUF_FLAG_BFRAME);
  1663. dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
  1664. meta = &ctx->frame_metas[ctx->display_idx];
  1665. dst_buf->v4l2_buf.timecode = meta->timecode;
  1666. dst_buf->v4l2_buf.timestamp = meta->timestamp;
  1667. trace_coda_dec_rot_done(ctx, meta, dst_buf);
  1668. switch (q_data_dst->fourcc) {
  1669. case V4L2_PIX_FMT_YUV420:
  1670. case V4L2_PIX_FMT_YVU420:
  1671. case V4L2_PIX_FMT_NV12:
  1672. default:
  1673. payload = width * height * 3 / 2;
  1674. break;
  1675. case V4L2_PIX_FMT_YUV422P:
  1676. payload = width * height * 2;
  1677. break;
  1678. }
  1679. vb2_set_plane_payload(dst_buf, 0, payload);
  1680. v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
  1681. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1682. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1683. "job finished: decoding frame (%d) (%s)\n",
  1684. dst_buf->v4l2_buf.sequence,
  1685. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1686. "KEYFRAME" : "PFRAME");
  1687. } else {
  1688. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1689. "job finished: no frame decoded\n");
  1690. }
  1691. /* The rotator will copy the current display frame next time */
  1692. ctx->display_idx = display_idx;
  1693. }
  1694. const struct coda_context_ops coda_bit_decode_ops = {
  1695. .queue_init = coda_decoder_queue_init,
  1696. .reqbufs = coda_decoder_reqbufs,
  1697. .start_streaming = coda_start_decoding,
  1698. .prepare_run = coda_prepare_decode,
  1699. .finish_run = coda_finish_decode,
  1700. .seq_end_work = coda_seq_end_work,
  1701. .release = coda_bit_release,
  1702. };
  1703. irqreturn_t coda_irq_handler(int irq, void *data)
  1704. {
  1705. struct coda_dev *dev = data;
  1706. struct coda_ctx *ctx;
  1707. /* read status register to attend the IRQ */
  1708. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1709. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1710. CODA_REG_BIT_INT_CLEAR);
  1711. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1712. if (ctx == NULL) {
  1713. v4l2_err(&dev->v4l2_dev,
  1714. "Instance released before the end of transaction\n");
  1715. mutex_unlock(&dev->coda_mutex);
  1716. return IRQ_HANDLED;
  1717. }
  1718. trace_coda_bit_done(ctx);
  1719. if (ctx->aborting) {
  1720. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1721. "task has been aborted\n");
  1722. }
  1723. if (coda_isbusy(ctx->dev)) {
  1724. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1725. "coda is still busy!!!!\n");
  1726. return IRQ_NONE;
  1727. }
  1728. complete(&ctx->completion);
  1729. return IRQ_HANDLED;
  1730. }