adv7180.c 36 KB

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  1. /*
  2. * adv7180.c Analog Devices ADV7180 video decoder driver
  3. * Copyright (c) 2009 Intel Corporation
  4. * Copyright (C) 2013 Cogent Embedded, Inc.
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/errno.h>
  23. #include <linux/kernel.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/i2c.h>
  26. #include <linux/slab.h>
  27. #include <media/v4l2-ioctl.h>
  28. #include <linux/videodev2.h>
  29. #include <media/v4l2-device.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include <linux/mutex.h>
  32. #include <linux/delay.h>
  33. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  34. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  35. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  36. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  37. #define ADV7180_STD_NTSC_J 0x4
  38. #define ADV7180_STD_NTSC_M 0x5
  39. #define ADV7180_STD_PAL60 0x6
  40. #define ADV7180_STD_NTSC_443 0x7
  41. #define ADV7180_STD_PAL_BG 0x8
  42. #define ADV7180_STD_PAL_N 0x9
  43. #define ADV7180_STD_PAL_M 0xa
  44. #define ADV7180_STD_PAL_M_PED 0xb
  45. #define ADV7180_STD_PAL_COMB_N 0xc
  46. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  47. #define ADV7180_STD_PAL_SECAM 0xe
  48. #define ADV7180_STD_PAL_SECAM_PED 0xf
  49. #define ADV7180_REG_INPUT_CONTROL 0x0000
  50. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  51. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  52. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  53. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  54. #define ADV7180_REG_AUTODETECT_ENABLE 0x07
  55. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  56. /* Contrast */
  57. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  58. #define ADV7180_CON_MIN 0
  59. #define ADV7180_CON_DEF 128
  60. #define ADV7180_CON_MAX 255
  61. /* Brightness*/
  62. #define ADV7180_REG_BRI 0x000a /*Signed */
  63. #define ADV7180_BRI_MIN -128
  64. #define ADV7180_BRI_DEF 0
  65. #define ADV7180_BRI_MAX 127
  66. /* Hue */
  67. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  68. #define ADV7180_HUE_MIN -127
  69. #define ADV7180_HUE_DEF 0
  70. #define ADV7180_HUE_MAX 128
  71. #define ADV7180_REG_CTRL 0x000e
  72. #define ADV7180_CTRL_IRQ_SPACE 0x20
  73. #define ADV7180_REG_PWR_MAN 0x0f
  74. #define ADV7180_PWR_MAN_ON 0x04
  75. #define ADV7180_PWR_MAN_OFF 0x24
  76. #define ADV7180_PWR_MAN_RES 0x80
  77. #define ADV7180_REG_STATUS1 0x0010
  78. #define ADV7180_STATUS1_IN_LOCK 0x01
  79. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  80. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  81. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  82. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  83. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  84. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  85. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  86. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  87. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  88. #define ADV7180_REG_IDENT 0x0011
  89. #define ADV7180_ID_7180 0x18
  90. #define ADV7180_REG_ICONF1 0x0040
  91. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  92. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  93. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  94. /* Saturation */
  95. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  96. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  97. #define ADV7180_SAT_MIN 0
  98. #define ADV7180_SAT_DEF 128
  99. #define ADV7180_SAT_MAX 255
  100. #define ADV7180_IRQ1_LOCK 0x01
  101. #define ADV7180_IRQ1_UNLOCK 0x02
  102. #define ADV7180_REG_ISR1 0x0042
  103. #define ADV7180_REG_ICR1 0x0043
  104. #define ADV7180_REG_IMR1 0x0044
  105. #define ADV7180_REG_IMR2 0x0048
  106. #define ADV7180_IRQ3_AD_CHANGE 0x08
  107. #define ADV7180_REG_ISR3 0x004A
  108. #define ADV7180_REG_ICR3 0x004B
  109. #define ADV7180_REG_IMR3 0x004C
  110. #define ADV7180_REG_IMR4 0x50
  111. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  112. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  113. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  114. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  115. #define ADV7180_REG_FLCONTROL 0x40e0
  116. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  117. #define ADV7180_CSI_REG_PWRDN 0x00
  118. #define ADV7180_CSI_PWRDN 0x80
  119. #define ADV7180_INPUT_CVBS_AIN1 0x00
  120. #define ADV7180_INPUT_CVBS_AIN2 0x01
  121. #define ADV7180_INPUT_CVBS_AIN3 0x02
  122. #define ADV7180_INPUT_CVBS_AIN4 0x03
  123. #define ADV7180_INPUT_CVBS_AIN5 0x04
  124. #define ADV7180_INPUT_CVBS_AIN6 0x05
  125. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  126. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  127. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  128. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  129. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  130. #define ADV7182_INPUT_CVBS_AIN1 0x00
  131. #define ADV7182_INPUT_CVBS_AIN2 0x01
  132. #define ADV7182_INPUT_CVBS_AIN3 0x02
  133. #define ADV7182_INPUT_CVBS_AIN4 0x03
  134. #define ADV7182_INPUT_CVBS_AIN5 0x04
  135. #define ADV7182_INPUT_CVBS_AIN6 0x05
  136. #define ADV7182_INPUT_CVBS_AIN7 0x06
  137. #define ADV7182_INPUT_CVBS_AIN8 0x07
  138. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  139. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  140. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  141. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  142. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  143. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  144. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  145. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  146. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  147. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  148. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  149. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  150. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  151. struct adv7180_state;
  152. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  153. #define ADV7180_FLAG_V2 BIT(1)
  154. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  155. #define ADV7180_FLAG_I2P BIT(3)
  156. struct adv7180_chip_info {
  157. unsigned int flags;
  158. unsigned int valid_input_mask;
  159. int (*set_std)(struct adv7180_state *st, unsigned int std);
  160. int (*select_input)(struct adv7180_state *st, unsigned int input);
  161. int (*init)(struct adv7180_state *state);
  162. };
  163. struct adv7180_state {
  164. struct v4l2_ctrl_handler ctrl_hdl;
  165. struct v4l2_subdev sd;
  166. struct media_pad pad;
  167. struct mutex mutex; /* mutual excl. when accessing chip */
  168. int irq;
  169. v4l2_std_id curr_norm;
  170. bool autodetect;
  171. bool powered;
  172. u8 input;
  173. struct i2c_client *client;
  174. unsigned int register_page;
  175. struct i2c_client *csi_client;
  176. struct i2c_client *vpp_client;
  177. const struct adv7180_chip_info *chip_info;
  178. enum v4l2_field field;
  179. };
  180. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  181. struct adv7180_state, \
  182. ctrl_hdl)->sd)
  183. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  184. {
  185. if (state->register_page != page) {
  186. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  187. page);
  188. state->register_page = page;
  189. }
  190. return 0;
  191. }
  192. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  193. unsigned int value)
  194. {
  195. lockdep_assert_held(&state->mutex);
  196. adv7180_select_page(state, reg >> 8);
  197. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  198. }
  199. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  200. {
  201. lockdep_assert_held(&state->mutex);
  202. adv7180_select_page(state, reg >> 8);
  203. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  204. }
  205. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  206. unsigned int value)
  207. {
  208. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  209. }
  210. static int adv7180_set_video_standard(struct adv7180_state *state,
  211. unsigned int std)
  212. {
  213. return state->chip_info->set_std(state, std);
  214. }
  215. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  216. unsigned int value)
  217. {
  218. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  219. }
  220. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  221. {
  222. /* in case V4L2_IN_ST_NO_SIGNAL */
  223. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  224. return V4L2_STD_UNKNOWN;
  225. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  226. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  227. return V4L2_STD_NTSC;
  228. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  229. return V4L2_STD_NTSC_443;
  230. case ADV7180_STATUS1_AUTOD_PAL_M:
  231. return V4L2_STD_PAL_M;
  232. case ADV7180_STATUS1_AUTOD_PAL_60:
  233. return V4L2_STD_PAL_60;
  234. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  235. return V4L2_STD_PAL;
  236. case ADV7180_STATUS1_AUTOD_SECAM:
  237. return V4L2_STD_SECAM;
  238. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  239. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  240. case ADV7180_STATUS1_AUTOD_SECAM_525:
  241. return V4L2_STD_SECAM;
  242. default:
  243. return V4L2_STD_UNKNOWN;
  244. }
  245. }
  246. static int v4l2_std_to_adv7180(v4l2_std_id std)
  247. {
  248. if (std == V4L2_STD_PAL_60)
  249. return ADV7180_STD_PAL60;
  250. if (std == V4L2_STD_NTSC_443)
  251. return ADV7180_STD_NTSC_443;
  252. if (std == V4L2_STD_PAL_N)
  253. return ADV7180_STD_PAL_N;
  254. if (std == V4L2_STD_PAL_M)
  255. return ADV7180_STD_PAL_M;
  256. if (std == V4L2_STD_PAL_Nc)
  257. return ADV7180_STD_PAL_COMB_N;
  258. if (std & V4L2_STD_PAL)
  259. return ADV7180_STD_PAL_BG;
  260. if (std & V4L2_STD_NTSC)
  261. return ADV7180_STD_NTSC_M;
  262. if (std & V4L2_STD_SECAM)
  263. return ADV7180_STD_PAL_SECAM;
  264. return -EINVAL;
  265. }
  266. static u32 adv7180_status_to_v4l2(u8 status1)
  267. {
  268. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  269. return V4L2_IN_ST_NO_SIGNAL;
  270. return 0;
  271. }
  272. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  273. v4l2_std_id *std)
  274. {
  275. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  276. if (status1 < 0)
  277. return status1;
  278. if (status)
  279. *status = adv7180_status_to_v4l2(status1);
  280. if (std)
  281. *std = adv7180_std_to_v4l2(status1);
  282. return 0;
  283. }
  284. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  285. {
  286. return container_of(sd, struct adv7180_state, sd);
  287. }
  288. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  289. {
  290. struct adv7180_state *state = to_state(sd);
  291. int err = mutex_lock_interruptible(&state->mutex);
  292. if (err)
  293. return err;
  294. /* when we are interrupt driven we know the state */
  295. if (!state->autodetect || state->irq > 0)
  296. *std = state->curr_norm;
  297. else
  298. err = __adv7180_status(state, NULL, std);
  299. mutex_unlock(&state->mutex);
  300. return err;
  301. }
  302. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  303. u32 output, u32 config)
  304. {
  305. struct adv7180_state *state = to_state(sd);
  306. int ret = mutex_lock_interruptible(&state->mutex);
  307. if (ret)
  308. return ret;
  309. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  310. ret = -EINVAL;
  311. goto out;
  312. }
  313. ret = state->chip_info->select_input(state, input);
  314. if (ret == 0)
  315. state->input = input;
  316. out:
  317. mutex_unlock(&state->mutex);
  318. return ret;
  319. }
  320. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  321. {
  322. struct adv7180_state *state = to_state(sd);
  323. int ret = mutex_lock_interruptible(&state->mutex);
  324. if (ret)
  325. return ret;
  326. ret = __adv7180_status(state, status, NULL);
  327. mutex_unlock(&state->mutex);
  328. return ret;
  329. }
  330. static int adv7180_program_std(struct adv7180_state *state)
  331. {
  332. int ret;
  333. if (state->autodetect) {
  334. ret = adv7180_set_video_standard(state,
  335. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  336. if (ret < 0)
  337. return ret;
  338. __adv7180_status(state, NULL, &state->curr_norm);
  339. } else {
  340. ret = v4l2_std_to_adv7180(state->curr_norm);
  341. if (ret < 0)
  342. return ret;
  343. ret = adv7180_set_video_standard(state, ret);
  344. if (ret < 0)
  345. return ret;
  346. }
  347. return 0;
  348. }
  349. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  350. {
  351. struct adv7180_state *state = to_state(sd);
  352. int ret = mutex_lock_interruptible(&state->mutex);
  353. if (ret)
  354. return ret;
  355. /* all standards -> autodetect */
  356. if (std == V4L2_STD_ALL) {
  357. state->autodetect = true;
  358. } else {
  359. /* Make sure we can support this std */
  360. ret = v4l2_std_to_adv7180(std);
  361. if (ret < 0)
  362. goto out;
  363. state->curr_norm = std;
  364. state->autodetect = false;
  365. }
  366. ret = adv7180_program_std(state);
  367. out:
  368. mutex_unlock(&state->mutex);
  369. return ret;
  370. }
  371. static int adv7180_set_power(struct adv7180_state *state, bool on)
  372. {
  373. u8 val;
  374. int ret;
  375. if (on)
  376. val = ADV7180_PWR_MAN_ON;
  377. else
  378. val = ADV7180_PWR_MAN_OFF;
  379. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  380. if (ret)
  381. return ret;
  382. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  383. if (on) {
  384. adv7180_csi_write(state, 0xDE, 0x02);
  385. adv7180_csi_write(state, 0xD2, 0xF7);
  386. adv7180_csi_write(state, 0xD8, 0x65);
  387. adv7180_csi_write(state, 0xE0, 0x09);
  388. adv7180_csi_write(state, 0x2C, 0x00);
  389. if (state->field == V4L2_FIELD_NONE)
  390. adv7180_csi_write(state, 0x1D, 0x80);
  391. adv7180_csi_write(state, 0x00, 0x00);
  392. } else {
  393. adv7180_csi_write(state, 0x00, 0x80);
  394. }
  395. }
  396. return 0;
  397. }
  398. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  399. {
  400. struct adv7180_state *state = to_state(sd);
  401. int ret;
  402. ret = mutex_lock_interruptible(&state->mutex);
  403. if (ret)
  404. return ret;
  405. ret = adv7180_set_power(state, on);
  406. if (ret == 0)
  407. state->powered = on;
  408. mutex_unlock(&state->mutex);
  409. return ret;
  410. }
  411. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  412. {
  413. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  414. struct adv7180_state *state = to_state(sd);
  415. int ret = mutex_lock_interruptible(&state->mutex);
  416. int val;
  417. if (ret)
  418. return ret;
  419. val = ctrl->val;
  420. switch (ctrl->id) {
  421. case V4L2_CID_BRIGHTNESS:
  422. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  423. break;
  424. case V4L2_CID_HUE:
  425. /*Hue is inverted according to HSL chart */
  426. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  427. break;
  428. case V4L2_CID_CONTRAST:
  429. ret = adv7180_write(state, ADV7180_REG_CON, val);
  430. break;
  431. case V4L2_CID_SATURATION:
  432. /*
  433. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  434. *Let's not confuse the user, everybody understands saturation
  435. */
  436. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  437. if (ret < 0)
  438. break;
  439. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  440. break;
  441. case V4L2_CID_ADV_FAST_SWITCH:
  442. if (ctrl->val) {
  443. /* ADI required write */
  444. adv7180_write(state, 0x80d9, 0x44);
  445. adv7180_write(state, ADV7180_REG_FLCONTROL,
  446. ADV7180_FLCONTROL_FL_ENABLE);
  447. } else {
  448. /* ADI required write */
  449. adv7180_write(state, 0x80d9, 0xc4);
  450. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  451. }
  452. break;
  453. default:
  454. ret = -EINVAL;
  455. }
  456. mutex_unlock(&state->mutex);
  457. return ret;
  458. }
  459. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  460. .s_ctrl = adv7180_s_ctrl,
  461. };
  462. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  463. .ops = &adv7180_ctrl_ops,
  464. .id = V4L2_CID_ADV_FAST_SWITCH,
  465. .name = "Fast Switching",
  466. .type = V4L2_CTRL_TYPE_BOOLEAN,
  467. .min = 0,
  468. .max = 1,
  469. .step = 1,
  470. };
  471. static int adv7180_init_controls(struct adv7180_state *state)
  472. {
  473. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  474. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  475. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  476. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  477. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  478. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  479. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  480. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  481. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  482. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  483. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  484. V4L2_CID_HUE, ADV7180_HUE_MIN,
  485. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  486. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  487. state->sd.ctrl_handler = &state->ctrl_hdl;
  488. if (state->ctrl_hdl.error) {
  489. int err = state->ctrl_hdl.error;
  490. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  491. return err;
  492. }
  493. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  494. return 0;
  495. }
  496. static void adv7180_exit_controls(struct adv7180_state *state)
  497. {
  498. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  499. }
  500. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  501. struct v4l2_subdev_pad_config *cfg,
  502. struct v4l2_subdev_mbus_code_enum *code)
  503. {
  504. if (code->index != 0)
  505. return -EINVAL;
  506. code->code = MEDIA_BUS_FMT_YUYV8_2X8;
  507. return 0;
  508. }
  509. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  510. struct v4l2_mbus_framefmt *fmt)
  511. {
  512. struct adv7180_state *state = to_state(sd);
  513. fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
  514. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  515. fmt->width = 720;
  516. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  517. return 0;
  518. }
  519. static int adv7180_set_field_mode(struct adv7180_state *state)
  520. {
  521. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  522. return 0;
  523. if (state->field == V4L2_FIELD_NONE) {
  524. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  525. adv7180_csi_write(state, 0x01, 0x20);
  526. adv7180_csi_write(state, 0x02, 0x28);
  527. adv7180_csi_write(state, 0x03, 0x38);
  528. adv7180_csi_write(state, 0x04, 0x30);
  529. adv7180_csi_write(state, 0x05, 0x30);
  530. adv7180_csi_write(state, 0x06, 0x80);
  531. adv7180_csi_write(state, 0x07, 0x70);
  532. adv7180_csi_write(state, 0x08, 0x50);
  533. }
  534. adv7180_vpp_write(state, 0xa3, 0x00);
  535. adv7180_vpp_write(state, 0x5b, 0x00);
  536. adv7180_vpp_write(state, 0x55, 0x80);
  537. } else {
  538. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  539. adv7180_csi_write(state, 0x01, 0x18);
  540. adv7180_csi_write(state, 0x02, 0x18);
  541. adv7180_csi_write(state, 0x03, 0x30);
  542. adv7180_csi_write(state, 0x04, 0x20);
  543. adv7180_csi_write(state, 0x05, 0x28);
  544. adv7180_csi_write(state, 0x06, 0x40);
  545. adv7180_csi_write(state, 0x07, 0x58);
  546. adv7180_csi_write(state, 0x08, 0x30);
  547. }
  548. adv7180_vpp_write(state, 0xa3, 0x70);
  549. adv7180_vpp_write(state, 0x5b, 0x80);
  550. adv7180_vpp_write(state, 0x55, 0x00);
  551. }
  552. return 0;
  553. }
  554. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  555. struct v4l2_subdev_pad_config *cfg,
  556. struct v4l2_subdev_format *format)
  557. {
  558. struct adv7180_state *state = to_state(sd);
  559. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  560. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  561. } else {
  562. adv7180_mbus_fmt(sd, &format->format);
  563. format->format.field = state->field;
  564. }
  565. return 0;
  566. }
  567. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  568. struct v4l2_subdev_pad_config *cfg,
  569. struct v4l2_subdev_format *format)
  570. {
  571. struct adv7180_state *state = to_state(sd);
  572. struct v4l2_mbus_framefmt *framefmt;
  573. switch (format->format.field) {
  574. case V4L2_FIELD_NONE:
  575. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  576. format->format.field = V4L2_FIELD_INTERLACED;
  577. break;
  578. default:
  579. format->format.field = V4L2_FIELD_INTERLACED;
  580. break;
  581. }
  582. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  583. framefmt = &format->format;
  584. if (state->field != format->format.field) {
  585. state->field = format->format.field;
  586. adv7180_set_power(state, false);
  587. adv7180_set_field_mode(state);
  588. adv7180_set_power(state, true);
  589. }
  590. } else {
  591. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  592. *framefmt = format->format;
  593. }
  594. return adv7180_mbus_fmt(sd, framefmt);
  595. }
  596. static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
  597. struct v4l2_mbus_config *cfg)
  598. {
  599. struct adv7180_state *state = to_state(sd);
  600. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  601. cfg->type = V4L2_MBUS_CSI2;
  602. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  603. V4L2_MBUS_CSI2_CHANNEL_0 |
  604. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  605. } else {
  606. /*
  607. * The ADV7180 sensor supports BT.601/656 output modes.
  608. * The BT.656 is default and not yet configurable by s/w.
  609. */
  610. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  611. V4L2_MBUS_DATA_ACTIVE_HIGH;
  612. cfg->type = V4L2_MBUS_BT656;
  613. }
  614. return 0;
  615. }
  616. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  617. .s_std = adv7180_s_std,
  618. .querystd = adv7180_querystd,
  619. .g_input_status = adv7180_g_input_status,
  620. .s_routing = adv7180_s_routing,
  621. .g_mbus_config = adv7180_g_mbus_config,
  622. };
  623. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  624. .s_power = adv7180_s_power,
  625. };
  626. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  627. .enum_mbus_code = adv7180_enum_mbus_code,
  628. .set_fmt = adv7180_set_pad_format,
  629. .get_fmt = adv7180_get_pad_format,
  630. };
  631. static const struct v4l2_subdev_ops adv7180_ops = {
  632. .core = &adv7180_core_ops,
  633. .video = &adv7180_video_ops,
  634. .pad = &adv7180_pad_ops,
  635. };
  636. static irqreturn_t adv7180_irq(int irq, void *devid)
  637. {
  638. struct adv7180_state *state = devid;
  639. u8 isr3;
  640. mutex_lock(&state->mutex);
  641. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  642. /* clear */
  643. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  644. if (isr3 & ADV7180_IRQ3_AD_CHANGE && state->autodetect)
  645. __adv7180_status(state, NULL, &state->curr_norm);
  646. mutex_unlock(&state->mutex);
  647. return IRQ_HANDLED;
  648. }
  649. static int adv7180_init(struct adv7180_state *state)
  650. {
  651. int ret;
  652. /* ITU-R BT.656-4 compatible */
  653. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  654. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  655. if (ret < 0)
  656. return ret;
  657. /* Manually set V bit end position in NTSC mode */
  658. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  659. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  660. }
  661. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  662. {
  663. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  664. (std << 4) | state->input);
  665. }
  666. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  667. {
  668. int ret;
  669. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  670. if (ret < 0)
  671. return ret;
  672. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  673. ret |= input;
  674. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  675. }
  676. static int adv7182_init(struct adv7180_state *state)
  677. {
  678. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  679. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  680. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  681. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  682. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  683. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  684. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  685. /* ADI recommended writes for improved video quality */
  686. adv7180_write(state, 0x0080, 0x51);
  687. adv7180_write(state, 0x0081, 0x51);
  688. adv7180_write(state, 0x0082, 0x68);
  689. }
  690. /* ADI required writes */
  691. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  692. adv7180_write(state, 0x0003, 0x4e);
  693. adv7180_write(state, 0x0004, 0x57);
  694. adv7180_write(state, 0x001d, 0xc0);
  695. } else {
  696. if (state->chip_info->flags & ADV7180_FLAG_V2)
  697. adv7180_write(state, 0x0004, 0x17);
  698. else
  699. adv7180_write(state, 0x0004, 0x07);
  700. adv7180_write(state, 0x0003, 0x0c);
  701. adv7180_write(state, 0x001d, 0x40);
  702. }
  703. adv7180_write(state, 0x0013, 0x00);
  704. return 0;
  705. }
  706. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  707. {
  708. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  709. }
  710. enum adv7182_input_type {
  711. ADV7182_INPUT_TYPE_CVBS,
  712. ADV7182_INPUT_TYPE_DIFF_CVBS,
  713. ADV7182_INPUT_TYPE_SVIDEO,
  714. ADV7182_INPUT_TYPE_YPBPR,
  715. };
  716. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  717. {
  718. switch (input) {
  719. case ADV7182_INPUT_CVBS_AIN1:
  720. case ADV7182_INPUT_CVBS_AIN2:
  721. case ADV7182_INPUT_CVBS_AIN3:
  722. case ADV7182_INPUT_CVBS_AIN4:
  723. case ADV7182_INPUT_CVBS_AIN5:
  724. case ADV7182_INPUT_CVBS_AIN6:
  725. case ADV7182_INPUT_CVBS_AIN7:
  726. case ADV7182_INPUT_CVBS_AIN8:
  727. return ADV7182_INPUT_TYPE_CVBS;
  728. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  729. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  730. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  731. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  732. return ADV7182_INPUT_TYPE_SVIDEO;
  733. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  734. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  735. return ADV7182_INPUT_TYPE_YPBPR;
  736. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  737. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  738. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  739. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  740. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  741. default: /* Will never happen */
  742. return 0;
  743. }
  744. }
  745. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  746. static unsigned int adv7182_lbias_settings[][3] = {
  747. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  748. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  749. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  750. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  751. };
  752. static unsigned int adv7280_lbias_settings[][3] = {
  753. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  754. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  755. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  756. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  757. };
  758. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  759. {
  760. enum adv7182_input_type input_type;
  761. unsigned int *lbias;
  762. unsigned int i;
  763. int ret;
  764. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  765. if (ret)
  766. return ret;
  767. /* Reset clamp circuitry - ADI recommended writes */
  768. adv7180_write(state, 0x809c, 0x00);
  769. adv7180_write(state, 0x809c, 0xff);
  770. input_type = adv7182_get_input_type(input);
  771. switch (input_type) {
  772. case ADV7182_INPUT_TYPE_CVBS:
  773. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  774. /* ADI recommends to use the SH1 filter */
  775. adv7180_write(state, 0x0017, 0x41);
  776. break;
  777. default:
  778. adv7180_write(state, 0x0017, 0x01);
  779. break;
  780. }
  781. if (state->chip_info->flags & ADV7180_FLAG_V2)
  782. lbias = adv7280_lbias_settings[input_type];
  783. else
  784. lbias = adv7182_lbias_settings[input_type];
  785. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  786. adv7180_write(state, 0x0052 + i, lbias[i]);
  787. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  788. /* ADI required writes to make differential CVBS work */
  789. adv7180_write(state, 0x005f, 0xa8);
  790. adv7180_write(state, 0x005a, 0x90);
  791. adv7180_write(state, 0x0060, 0xb0);
  792. adv7180_write(state, 0x80b6, 0x08);
  793. adv7180_write(state, 0x80c0, 0xa0);
  794. } else {
  795. adv7180_write(state, 0x005f, 0xf0);
  796. adv7180_write(state, 0x005a, 0xd0);
  797. adv7180_write(state, 0x0060, 0x10);
  798. adv7180_write(state, 0x80b6, 0x9c);
  799. adv7180_write(state, 0x80c0, 0x00);
  800. }
  801. return 0;
  802. }
  803. static const struct adv7180_chip_info adv7180_info = {
  804. .flags = ADV7180_FLAG_RESET_POWERED,
  805. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  806. * all inputs and let the card driver take care of validation
  807. */
  808. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  809. BIT(ADV7180_INPUT_CVBS_AIN2) |
  810. BIT(ADV7180_INPUT_CVBS_AIN3) |
  811. BIT(ADV7180_INPUT_CVBS_AIN4) |
  812. BIT(ADV7180_INPUT_CVBS_AIN5) |
  813. BIT(ADV7180_INPUT_CVBS_AIN6) |
  814. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  815. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  816. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  817. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  818. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  819. .init = adv7180_init,
  820. .set_std = adv7180_set_std,
  821. .select_input = adv7180_select_input,
  822. };
  823. static const struct adv7180_chip_info adv7182_info = {
  824. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  825. BIT(ADV7182_INPUT_CVBS_AIN2) |
  826. BIT(ADV7182_INPUT_CVBS_AIN3) |
  827. BIT(ADV7182_INPUT_CVBS_AIN4) |
  828. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  829. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  830. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  831. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  832. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  833. .init = adv7182_init,
  834. .set_std = adv7182_set_std,
  835. .select_input = adv7182_select_input,
  836. };
  837. static const struct adv7180_chip_info adv7280_info = {
  838. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  839. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  840. BIT(ADV7182_INPUT_CVBS_AIN2) |
  841. BIT(ADV7182_INPUT_CVBS_AIN3) |
  842. BIT(ADV7182_INPUT_CVBS_AIN4) |
  843. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  844. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  845. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  846. .init = adv7182_init,
  847. .set_std = adv7182_set_std,
  848. .select_input = adv7182_select_input,
  849. };
  850. static const struct adv7180_chip_info adv7280_m_info = {
  851. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  852. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  853. BIT(ADV7182_INPUT_CVBS_AIN2) |
  854. BIT(ADV7182_INPUT_CVBS_AIN3) |
  855. BIT(ADV7182_INPUT_CVBS_AIN4) |
  856. BIT(ADV7182_INPUT_CVBS_AIN5) |
  857. BIT(ADV7182_INPUT_CVBS_AIN6) |
  858. BIT(ADV7182_INPUT_CVBS_AIN7) |
  859. BIT(ADV7182_INPUT_CVBS_AIN8) |
  860. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  861. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  862. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  863. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  864. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  865. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  866. .init = adv7182_init,
  867. .set_std = adv7182_set_std,
  868. .select_input = adv7182_select_input,
  869. };
  870. static const struct adv7180_chip_info adv7281_info = {
  871. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  872. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  873. BIT(ADV7182_INPUT_CVBS_AIN2) |
  874. BIT(ADV7182_INPUT_CVBS_AIN7) |
  875. BIT(ADV7182_INPUT_CVBS_AIN8) |
  876. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  877. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  878. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  879. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  880. .init = adv7182_init,
  881. .set_std = adv7182_set_std,
  882. .select_input = adv7182_select_input,
  883. };
  884. static const struct adv7180_chip_info adv7281_m_info = {
  885. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  886. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  887. BIT(ADV7182_INPUT_CVBS_AIN2) |
  888. BIT(ADV7182_INPUT_CVBS_AIN3) |
  889. BIT(ADV7182_INPUT_CVBS_AIN4) |
  890. BIT(ADV7182_INPUT_CVBS_AIN7) |
  891. BIT(ADV7182_INPUT_CVBS_AIN8) |
  892. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  893. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  894. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  895. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  896. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  897. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  898. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  899. .init = adv7182_init,
  900. .set_std = adv7182_set_std,
  901. .select_input = adv7182_select_input,
  902. };
  903. static const struct adv7180_chip_info adv7281_ma_info = {
  904. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  905. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  906. BIT(ADV7182_INPUT_CVBS_AIN2) |
  907. BIT(ADV7182_INPUT_CVBS_AIN3) |
  908. BIT(ADV7182_INPUT_CVBS_AIN4) |
  909. BIT(ADV7182_INPUT_CVBS_AIN5) |
  910. BIT(ADV7182_INPUT_CVBS_AIN6) |
  911. BIT(ADV7182_INPUT_CVBS_AIN7) |
  912. BIT(ADV7182_INPUT_CVBS_AIN8) |
  913. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  914. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  915. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  916. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  917. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  918. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  919. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  920. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  921. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  922. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  923. .init = adv7182_init,
  924. .set_std = adv7182_set_std,
  925. .select_input = adv7182_select_input,
  926. };
  927. static const struct adv7180_chip_info adv7282_info = {
  928. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  929. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  930. BIT(ADV7182_INPUT_CVBS_AIN2) |
  931. BIT(ADV7182_INPUT_CVBS_AIN7) |
  932. BIT(ADV7182_INPUT_CVBS_AIN8) |
  933. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  934. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  935. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  936. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  937. .init = adv7182_init,
  938. .set_std = adv7182_set_std,
  939. .select_input = adv7182_select_input,
  940. };
  941. static const struct adv7180_chip_info adv7282_m_info = {
  942. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  943. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  944. BIT(ADV7182_INPUT_CVBS_AIN2) |
  945. BIT(ADV7182_INPUT_CVBS_AIN3) |
  946. BIT(ADV7182_INPUT_CVBS_AIN4) |
  947. BIT(ADV7182_INPUT_CVBS_AIN7) |
  948. BIT(ADV7182_INPUT_CVBS_AIN8) |
  949. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  950. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  951. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  952. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  953. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  954. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  955. .init = adv7182_init,
  956. .set_std = adv7182_set_std,
  957. .select_input = adv7182_select_input,
  958. };
  959. static int init_device(struct adv7180_state *state)
  960. {
  961. int ret;
  962. mutex_lock(&state->mutex);
  963. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  964. usleep_range(2000, 10000);
  965. ret = state->chip_info->init(state);
  966. if (ret)
  967. goto out_unlock;
  968. ret = adv7180_program_std(state);
  969. if (ret)
  970. goto out_unlock;
  971. adv7180_set_field_mode(state);
  972. /* register for interrupts */
  973. if (state->irq > 0) {
  974. /* config the Interrupt pin to be active low */
  975. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  976. ADV7180_ICONF1_ACTIVE_LOW |
  977. ADV7180_ICONF1_PSYNC_ONLY);
  978. if (ret < 0)
  979. goto out_unlock;
  980. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  981. if (ret < 0)
  982. goto out_unlock;
  983. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  984. if (ret < 0)
  985. goto out_unlock;
  986. /* enable AD change interrupts interrupts */
  987. ret = adv7180_write(state, ADV7180_REG_IMR3,
  988. ADV7180_IRQ3_AD_CHANGE);
  989. if (ret < 0)
  990. goto out_unlock;
  991. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  992. if (ret < 0)
  993. goto out_unlock;
  994. }
  995. out_unlock:
  996. mutex_unlock(&state->mutex);
  997. return ret;
  998. }
  999. static int adv7180_probe(struct i2c_client *client,
  1000. const struct i2c_device_id *id)
  1001. {
  1002. struct adv7180_state *state;
  1003. struct v4l2_subdev *sd;
  1004. int ret;
  1005. /* Check if the adapter supports the needed features */
  1006. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1007. return -EIO;
  1008. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1009. client->addr, client->adapter->name);
  1010. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1011. if (state == NULL)
  1012. return -ENOMEM;
  1013. state->client = client;
  1014. state->field = V4L2_FIELD_INTERLACED;
  1015. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1016. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1017. state->csi_client = i2c_new_dummy(client->adapter,
  1018. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1019. if (!state->csi_client)
  1020. return -ENOMEM;
  1021. }
  1022. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1023. state->vpp_client = i2c_new_dummy(client->adapter,
  1024. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1025. if (!state->vpp_client) {
  1026. ret = -ENOMEM;
  1027. goto err_unregister_csi_client;
  1028. }
  1029. }
  1030. state->irq = client->irq;
  1031. mutex_init(&state->mutex);
  1032. state->autodetect = true;
  1033. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1034. state->powered = true;
  1035. else
  1036. state->powered = false;
  1037. state->input = 0;
  1038. sd = &state->sd;
  1039. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1040. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
  1041. ret = adv7180_init_controls(state);
  1042. if (ret)
  1043. goto err_unregister_vpp_client;
  1044. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1045. sd->entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
  1046. ret = media_entity_init(&sd->entity, 1, &state->pad, 0);
  1047. if (ret)
  1048. goto err_free_ctrl;
  1049. ret = init_device(state);
  1050. if (ret)
  1051. goto err_media_entity_cleanup;
  1052. if (state->irq) {
  1053. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1054. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1055. KBUILD_MODNAME, state);
  1056. if (ret)
  1057. goto err_media_entity_cleanup;
  1058. }
  1059. ret = v4l2_async_register_subdev(sd);
  1060. if (ret)
  1061. goto err_free_irq;
  1062. return 0;
  1063. err_free_irq:
  1064. if (state->irq > 0)
  1065. free_irq(client->irq, state);
  1066. err_media_entity_cleanup:
  1067. media_entity_cleanup(&sd->entity);
  1068. err_free_ctrl:
  1069. adv7180_exit_controls(state);
  1070. err_unregister_vpp_client:
  1071. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1072. i2c_unregister_device(state->vpp_client);
  1073. err_unregister_csi_client:
  1074. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1075. i2c_unregister_device(state->csi_client);
  1076. mutex_destroy(&state->mutex);
  1077. return ret;
  1078. }
  1079. static int adv7180_remove(struct i2c_client *client)
  1080. {
  1081. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1082. struct adv7180_state *state = to_state(sd);
  1083. v4l2_async_unregister_subdev(sd);
  1084. if (state->irq > 0)
  1085. free_irq(client->irq, state);
  1086. media_entity_cleanup(&sd->entity);
  1087. adv7180_exit_controls(state);
  1088. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1089. i2c_unregister_device(state->vpp_client);
  1090. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1091. i2c_unregister_device(state->csi_client);
  1092. mutex_destroy(&state->mutex);
  1093. return 0;
  1094. }
  1095. static const struct i2c_device_id adv7180_id[] = {
  1096. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1097. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1098. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1099. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1100. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1101. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1102. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1103. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1104. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1105. {},
  1106. };
  1107. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1108. #ifdef CONFIG_PM_SLEEP
  1109. static int adv7180_suspend(struct device *dev)
  1110. {
  1111. struct i2c_client *client = to_i2c_client(dev);
  1112. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1113. struct adv7180_state *state = to_state(sd);
  1114. return adv7180_set_power(state, false);
  1115. }
  1116. static int adv7180_resume(struct device *dev)
  1117. {
  1118. struct i2c_client *client = to_i2c_client(dev);
  1119. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1120. struct adv7180_state *state = to_state(sd);
  1121. int ret;
  1122. ret = init_device(state);
  1123. if (ret < 0)
  1124. return ret;
  1125. ret = adv7180_set_power(state, state->powered);
  1126. if (ret)
  1127. return ret;
  1128. return 0;
  1129. }
  1130. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1131. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1132. #else
  1133. #define ADV7180_PM_OPS NULL
  1134. #endif
  1135. static struct i2c_driver adv7180_driver = {
  1136. .driver = {
  1137. .owner = THIS_MODULE,
  1138. .name = KBUILD_MODNAME,
  1139. .pm = ADV7180_PM_OPS,
  1140. },
  1141. .probe = adv7180_probe,
  1142. .remove = adv7180_remove,
  1143. .id_table = adv7180_id,
  1144. };
  1145. module_i2c_driver(adv7180_driver);
  1146. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1147. MODULE_AUTHOR("Mocean Laboratories");
  1148. MODULE_LICENSE("GPL v2");