ocrdma_verbs.c 84 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195
  1. /*******************************************************************
  2. * This file is part of the Emulex RoCE Device Driver for *
  3. * RoCE (RDMA over Converged Ethernet) adapters. *
  4. * Copyright (C) 2008-2012 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or *
  9. * modify it under the terms of version 2 of the GNU General *
  10. * Public License as published by the Free Software Foundation. *
  11. * This program is distributed in the hope that it will be useful. *
  12. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  13. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  14. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  15. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  17. * more details, a copy of which can be found in the file COPYING *
  18. * included with this package. *
  19. *
  20. * Contact Information:
  21. * linux-drivers@emulex.com
  22. *
  23. * Emulex
  24. * 3333 Susan Street
  25. * Costa Mesa, CA 92626
  26. *******************************************************************/
  27. #include <linux/dma-mapping.h>
  28. #include <rdma/ib_verbs.h>
  29. #include <rdma/ib_user_verbs.h>
  30. #include <rdma/iw_cm.h>
  31. #include <rdma/ib_umem.h>
  32. #include <rdma/ib_addr.h>
  33. #include "ocrdma.h"
  34. #include "ocrdma_hw.h"
  35. #include "ocrdma_verbs.h"
  36. #include "ocrdma_abi.h"
  37. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  38. {
  39. if (index > 1)
  40. return -EINVAL;
  41. *pkey = 0xffff;
  42. return 0;
  43. }
  44. int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
  45. int index, union ib_gid *sgid)
  46. {
  47. struct ocrdma_dev *dev;
  48. dev = get_ocrdma_dev(ibdev);
  49. memset(sgid, 0, sizeof(*sgid));
  50. if (index >= OCRDMA_MAX_SGID)
  51. return -EINVAL;
  52. memcpy(sgid, &dev->sgid_tbl[index], sizeof(*sgid));
  53. return 0;
  54. }
  55. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr)
  56. {
  57. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  58. memset(attr, 0, sizeof *attr);
  59. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  60. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  61. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  62. attr->max_mr_size = dev->attr.max_mr_size;
  63. attr->page_size_cap = 0xffff000;
  64. attr->vendor_id = dev->nic_info.pdev->vendor;
  65. attr->vendor_part_id = dev->nic_info.pdev->device;
  66. attr->hw_ver = dev->asic_id;
  67. attr->max_qp = dev->attr.max_qp;
  68. attr->max_ah = OCRDMA_MAX_AH;
  69. attr->max_qp_wr = dev->attr.max_wqe;
  70. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  71. IB_DEVICE_RC_RNR_NAK_GEN |
  72. IB_DEVICE_SHUTDOWN_PORT |
  73. IB_DEVICE_SYS_IMAGE_GUID |
  74. IB_DEVICE_LOCAL_DMA_LKEY |
  75. IB_DEVICE_MEM_MGT_EXTENSIONS;
  76. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge);
  77. attr->max_sge_rd = 0;
  78. attr->max_cq = dev->attr.max_cq;
  79. attr->max_cqe = dev->attr.max_cqe;
  80. attr->max_mr = dev->attr.max_mr;
  81. attr->max_mw = dev->attr.max_mw;
  82. attr->max_pd = dev->attr.max_pd;
  83. attr->atomic_cap = 0;
  84. attr->max_fmr = 0;
  85. attr->max_map_per_fmr = 0;
  86. attr->max_qp_rd_atom =
  87. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  88. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  89. attr->max_srq = dev->attr.max_srq;
  90. attr->max_srq_sge = dev->attr.max_srq_sge;
  91. attr->max_srq_wr = dev->attr.max_rqe;
  92. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  93. attr->max_fast_reg_page_list_len = dev->attr.max_pages_per_frmr;
  94. attr->max_pkeys = 1;
  95. return 0;
  96. }
  97. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  98. u8 *ib_speed, u8 *ib_width)
  99. {
  100. int status;
  101. u8 speed;
  102. status = ocrdma_mbx_get_link_speed(dev, &speed);
  103. if (status)
  104. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  105. switch (speed) {
  106. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  107. *ib_speed = IB_SPEED_SDR;
  108. *ib_width = IB_WIDTH_1X;
  109. break;
  110. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  111. *ib_speed = IB_SPEED_QDR;
  112. *ib_width = IB_WIDTH_1X;
  113. break;
  114. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  115. *ib_speed = IB_SPEED_DDR;
  116. *ib_width = IB_WIDTH_4X;
  117. break;
  118. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  119. *ib_speed = IB_SPEED_QDR;
  120. *ib_width = IB_WIDTH_4X;
  121. break;
  122. default:
  123. /* Unsupported */
  124. *ib_speed = IB_SPEED_SDR;
  125. *ib_width = IB_WIDTH_1X;
  126. }
  127. }
  128. int ocrdma_query_port(struct ib_device *ibdev,
  129. u8 port, struct ib_port_attr *props)
  130. {
  131. enum ib_port_state port_state;
  132. struct ocrdma_dev *dev;
  133. struct net_device *netdev;
  134. dev = get_ocrdma_dev(ibdev);
  135. if (port > 1) {
  136. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  137. dev->id, port);
  138. return -EINVAL;
  139. }
  140. netdev = dev->nic_info.netdev;
  141. if (netif_running(netdev) && netif_oper_up(netdev)) {
  142. port_state = IB_PORT_ACTIVE;
  143. props->phys_state = 5;
  144. } else {
  145. port_state = IB_PORT_DOWN;
  146. props->phys_state = 3;
  147. }
  148. props->max_mtu = IB_MTU_4096;
  149. props->active_mtu = iboe_get_mtu(netdev->mtu);
  150. props->lid = 0;
  151. props->lmc = 0;
  152. props->sm_lid = 0;
  153. props->sm_sl = 0;
  154. props->state = port_state;
  155. props->port_cap_flags =
  156. IB_PORT_CM_SUP |
  157. IB_PORT_REINIT_SUP |
  158. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP | IB_PORT_IP_BASED_GIDS;
  159. props->gid_tbl_len = OCRDMA_MAX_SGID;
  160. props->pkey_tbl_len = 1;
  161. props->bad_pkey_cntr = 0;
  162. props->qkey_viol_cntr = 0;
  163. get_link_speed_and_width(dev, &props->active_speed,
  164. &props->active_width);
  165. props->max_msg_sz = 0x80000000;
  166. props->max_vl_num = 4;
  167. return 0;
  168. }
  169. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  170. struct ib_port_modify *props)
  171. {
  172. struct ocrdma_dev *dev;
  173. dev = get_ocrdma_dev(ibdev);
  174. if (port > 1) {
  175. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  176. return -EINVAL;
  177. }
  178. return 0;
  179. }
  180. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  181. unsigned long len)
  182. {
  183. struct ocrdma_mm *mm;
  184. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  185. if (mm == NULL)
  186. return -ENOMEM;
  187. mm->key.phy_addr = phy_addr;
  188. mm->key.len = len;
  189. INIT_LIST_HEAD(&mm->entry);
  190. mutex_lock(&uctx->mm_list_lock);
  191. list_add_tail(&mm->entry, &uctx->mm_head);
  192. mutex_unlock(&uctx->mm_list_lock);
  193. return 0;
  194. }
  195. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  196. unsigned long len)
  197. {
  198. struct ocrdma_mm *mm, *tmp;
  199. mutex_lock(&uctx->mm_list_lock);
  200. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  201. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  202. continue;
  203. list_del(&mm->entry);
  204. kfree(mm);
  205. break;
  206. }
  207. mutex_unlock(&uctx->mm_list_lock);
  208. }
  209. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  210. unsigned long len)
  211. {
  212. bool found = false;
  213. struct ocrdma_mm *mm;
  214. mutex_lock(&uctx->mm_list_lock);
  215. list_for_each_entry(mm, &uctx->mm_head, entry) {
  216. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  217. continue;
  218. found = true;
  219. break;
  220. }
  221. mutex_unlock(&uctx->mm_list_lock);
  222. return found;
  223. }
  224. static u16 _ocrdma_pd_mgr_get_bitmap(struct ocrdma_dev *dev, bool dpp_pool)
  225. {
  226. u16 pd_bitmap_idx = 0;
  227. const unsigned long *pd_bitmap;
  228. if (dpp_pool) {
  229. pd_bitmap = dev->pd_mgr->pd_dpp_bitmap;
  230. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  231. dev->pd_mgr->max_dpp_pd);
  232. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_dpp_bitmap);
  233. dev->pd_mgr->pd_dpp_count++;
  234. if (dev->pd_mgr->pd_dpp_count > dev->pd_mgr->pd_dpp_thrsh)
  235. dev->pd_mgr->pd_dpp_thrsh = dev->pd_mgr->pd_dpp_count;
  236. } else {
  237. pd_bitmap = dev->pd_mgr->pd_norm_bitmap;
  238. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  239. dev->pd_mgr->max_normal_pd);
  240. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_norm_bitmap);
  241. dev->pd_mgr->pd_norm_count++;
  242. if (dev->pd_mgr->pd_norm_count > dev->pd_mgr->pd_norm_thrsh)
  243. dev->pd_mgr->pd_norm_thrsh = dev->pd_mgr->pd_norm_count;
  244. }
  245. return pd_bitmap_idx;
  246. }
  247. static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id,
  248. bool dpp_pool)
  249. {
  250. u16 pd_count;
  251. u16 pd_bit_index;
  252. pd_count = dpp_pool ? dev->pd_mgr->pd_dpp_count :
  253. dev->pd_mgr->pd_norm_count;
  254. if (pd_count == 0)
  255. return -EINVAL;
  256. if (dpp_pool) {
  257. pd_bit_index = pd_id - dev->pd_mgr->pd_dpp_start;
  258. if (pd_bit_index >= dev->pd_mgr->max_dpp_pd) {
  259. return -EINVAL;
  260. } else {
  261. __clear_bit(pd_bit_index, dev->pd_mgr->pd_dpp_bitmap);
  262. dev->pd_mgr->pd_dpp_count--;
  263. }
  264. } else {
  265. pd_bit_index = pd_id - dev->pd_mgr->pd_norm_start;
  266. if (pd_bit_index >= dev->pd_mgr->max_normal_pd) {
  267. return -EINVAL;
  268. } else {
  269. __clear_bit(pd_bit_index, dev->pd_mgr->pd_norm_bitmap);
  270. dev->pd_mgr->pd_norm_count--;
  271. }
  272. }
  273. return 0;
  274. }
  275. static u8 ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
  276. bool dpp_pool)
  277. {
  278. int status;
  279. mutex_lock(&dev->dev_lock);
  280. status = _ocrdma_pd_mgr_put_bitmap(dev, pd_id, dpp_pool);
  281. mutex_unlock(&dev->dev_lock);
  282. return status;
  283. }
  284. static int ocrdma_get_pd_num(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
  285. {
  286. u16 pd_idx = 0;
  287. int status = 0;
  288. mutex_lock(&dev->dev_lock);
  289. if (pd->dpp_enabled) {
  290. /* try allocating DPP PD, if not available then normal PD */
  291. if (dev->pd_mgr->pd_dpp_count < dev->pd_mgr->max_dpp_pd) {
  292. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, true);
  293. pd->id = dev->pd_mgr->pd_dpp_start + pd_idx;
  294. pd->dpp_page = dev->pd_mgr->dpp_page_index + pd_idx;
  295. } else if (dev->pd_mgr->pd_norm_count <
  296. dev->pd_mgr->max_normal_pd) {
  297. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  298. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  299. pd->dpp_enabled = false;
  300. } else {
  301. status = -EINVAL;
  302. }
  303. } else {
  304. if (dev->pd_mgr->pd_norm_count < dev->pd_mgr->max_normal_pd) {
  305. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  306. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  307. } else {
  308. status = -EINVAL;
  309. }
  310. }
  311. mutex_unlock(&dev->dev_lock);
  312. return status;
  313. }
  314. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  315. struct ocrdma_ucontext *uctx,
  316. struct ib_udata *udata)
  317. {
  318. struct ocrdma_pd *pd = NULL;
  319. int status = 0;
  320. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  321. if (!pd)
  322. return ERR_PTR(-ENOMEM);
  323. if (udata && uctx && dev->attr.max_dpp_pds) {
  324. pd->dpp_enabled =
  325. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  326. pd->num_dpp_qp =
  327. pd->dpp_enabled ? (dev->nic_info.db_page_size /
  328. dev->attr.wqe_size) : 0;
  329. }
  330. if (dev->pd_mgr->pd_prealloc_valid) {
  331. status = ocrdma_get_pd_num(dev, pd);
  332. return (status == 0) ? pd : ERR_PTR(status);
  333. }
  334. retry:
  335. status = ocrdma_mbx_alloc_pd(dev, pd);
  336. if (status) {
  337. if (pd->dpp_enabled) {
  338. pd->dpp_enabled = false;
  339. pd->num_dpp_qp = 0;
  340. goto retry;
  341. } else {
  342. kfree(pd);
  343. return ERR_PTR(status);
  344. }
  345. }
  346. return pd;
  347. }
  348. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  349. struct ocrdma_pd *pd)
  350. {
  351. return (uctx->cntxt_pd == pd ? true : false);
  352. }
  353. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  354. struct ocrdma_pd *pd)
  355. {
  356. int status = 0;
  357. if (dev->pd_mgr->pd_prealloc_valid)
  358. status = ocrdma_put_pd_num(dev, pd->id, pd->dpp_enabled);
  359. else
  360. status = ocrdma_mbx_dealloc_pd(dev, pd);
  361. kfree(pd);
  362. return status;
  363. }
  364. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  365. struct ocrdma_ucontext *uctx,
  366. struct ib_udata *udata)
  367. {
  368. int status = 0;
  369. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  370. if (IS_ERR(uctx->cntxt_pd)) {
  371. status = PTR_ERR(uctx->cntxt_pd);
  372. uctx->cntxt_pd = NULL;
  373. goto err;
  374. }
  375. uctx->cntxt_pd->uctx = uctx;
  376. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  377. err:
  378. return status;
  379. }
  380. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  381. {
  382. struct ocrdma_pd *pd = uctx->cntxt_pd;
  383. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  384. if (uctx->pd_in_use) {
  385. pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
  386. __func__, dev->id, pd->id);
  387. }
  388. uctx->cntxt_pd = NULL;
  389. (void)_ocrdma_dealloc_pd(dev, pd);
  390. return 0;
  391. }
  392. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  393. {
  394. struct ocrdma_pd *pd = NULL;
  395. mutex_lock(&uctx->mm_list_lock);
  396. if (!uctx->pd_in_use) {
  397. uctx->pd_in_use = true;
  398. pd = uctx->cntxt_pd;
  399. }
  400. mutex_unlock(&uctx->mm_list_lock);
  401. return pd;
  402. }
  403. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  404. {
  405. mutex_lock(&uctx->mm_list_lock);
  406. uctx->pd_in_use = false;
  407. mutex_unlock(&uctx->mm_list_lock);
  408. }
  409. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  410. struct ib_udata *udata)
  411. {
  412. int status;
  413. struct ocrdma_ucontext *ctx;
  414. struct ocrdma_alloc_ucontext_resp resp;
  415. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  416. struct pci_dev *pdev = dev->nic_info.pdev;
  417. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  418. if (!udata)
  419. return ERR_PTR(-EFAULT);
  420. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  421. if (!ctx)
  422. return ERR_PTR(-ENOMEM);
  423. INIT_LIST_HEAD(&ctx->mm_head);
  424. mutex_init(&ctx->mm_list_lock);
  425. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  426. &ctx->ah_tbl.pa, GFP_KERNEL);
  427. if (!ctx->ah_tbl.va) {
  428. kfree(ctx);
  429. return ERR_PTR(-ENOMEM);
  430. }
  431. memset(ctx->ah_tbl.va, 0, map_len);
  432. ctx->ah_tbl.len = map_len;
  433. memset(&resp, 0, sizeof(resp));
  434. resp.ah_tbl_len = ctx->ah_tbl.len;
  435. resp.ah_tbl_page = virt_to_phys(ctx->ah_tbl.va);
  436. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  437. if (status)
  438. goto map_err;
  439. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  440. if (status)
  441. goto pd_err;
  442. resp.dev_id = dev->id;
  443. resp.max_inline_data = dev->attr.max_inline_data;
  444. resp.wqe_size = dev->attr.wqe_size;
  445. resp.rqe_size = dev->attr.rqe_size;
  446. resp.dpp_wqe_size = dev->attr.wqe_size;
  447. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  448. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  449. if (status)
  450. goto cpy_err;
  451. return &ctx->ibucontext;
  452. cpy_err:
  453. pd_err:
  454. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  455. map_err:
  456. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  457. ctx->ah_tbl.pa);
  458. kfree(ctx);
  459. return ERR_PTR(status);
  460. }
  461. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  462. {
  463. int status = 0;
  464. struct ocrdma_mm *mm, *tmp;
  465. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  466. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  467. struct pci_dev *pdev = dev->nic_info.pdev;
  468. status = ocrdma_dealloc_ucontext_pd(uctx);
  469. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  470. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  471. uctx->ah_tbl.pa);
  472. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  473. list_del(&mm->entry);
  474. kfree(mm);
  475. }
  476. kfree(uctx);
  477. return status;
  478. }
  479. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  480. {
  481. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  482. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  483. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  484. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  485. unsigned long len = (vma->vm_end - vma->vm_start);
  486. int status = 0;
  487. bool found;
  488. if (vma->vm_start & (PAGE_SIZE - 1))
  489. return -EINVAL;
  490. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  491. if (!found)
  492. return -EINVAL;
  493. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  494. dev->nic_info.db_total_size)) &&
  495. (len <= dev->nic_info.db_page_size)) {
  496. if (vma->vm_flags & VM_READ)
  497. return -EPERM;
  498. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  499. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  500. len, vma->vm_page_prot);
  501. } else if (dev->nic_info.dpp_unmapped_len &&
  502. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  503. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  504. dev->nic_info.dpp_unmapped_len)) &&
  505. (len <= dev->nic_info.dpp_unmapped_len)) {
  506. if (vma->vm_flags & VM_READ)
  507. return -EPERM;
  508. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  509. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  510. len, vma->vm_page_prot);
  511. } else {
  512. status = remap_pfn_range(vma, vma->vm_start,
  513. vma->vm_pgoff, len, vma->vm_page_prot);
  514. }
  515. return status;
  516. }
  517. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  518. struct ib_ucontext *ib_ctx,
  519. struct ib_udata *udata)
  520. {
  521. int status;
  522. u64 db_page_addr;
  523. u64 dpp_page_addr = 0;
  524. u32 db_page_size;
  525. struct ocrdma_alloc_pd_uresp rsp;
  526. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  527. memset(&rsp, 0, sizeof(rsp));
  528. rsp.id = pd->id;
  529. rsp.dpp_enabled = pd->dpp_enabled;
  530. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  531. db_page_size = dev->nic_info.db_page_size;
  532. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  533. if (status)
  534. return status;
  535. if (pd->dpp_enabled) {
  536. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  537. (pd->id * PAGE_SIZE);
  538. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  539. PAGE_SIZE);
  540. if (status)
  541. goto dpp_map_err;
  542. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  543. rsp.dpp_page_addr_lo = dpp_page_addr;
  544. }
  545. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  546. if (status)
  547. goto ucopy_err;
  548. pd->uctx = uctx;
  549. return 0;
  550. ucopy_err:
  551. if (pd->dpp_enabled)
  552. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  553. dpp_map_err:
  554. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  555. return status;
  556. }
  557. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  558. struct ib_ucontext *context,
  559. struct ib_udata *udata)
  560. {
  561. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  562. struct ocrdma_pd *pd;
  563. struct ocrdma_ucontext *uctx = NULL;
  564. int status;
  565. u8 is_uctx_pd = false;
  566. if (udata && context) {
  567. uctx = get_ocrdma_ucontext(context);
  568. pd = ocrdma_get_ucontext_pd(uctx);
  569. if (pd) {
  570. is_uctx_pd = true;
  571. goto pd_mapping;
  572. }
  573. }
  574. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  575. if (IS_ERR(pd)) {
  576. status = PTR_ERR(pd);
  577. goto exit;
  578. }
  579. pd_mapping:
  580. if (udata && context) {
  581. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  582. if (status)
  583. goto err;
  584. }
  585. return &pd->ibpd;
  586. err:
  587. if (is_uctx_pd) {
  588. ocrdma_release_ucontext_pd(uctx);
  589. } else {
  590. status = _ocrdma_dealloc_pd(dev, pd);
  591. kfree(pd);
  592. }
  593. exit:
  594. return ERR_PTR(status);
  595. }
  596. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  597. {
  598. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  599. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  600. struct ocrdma_ucontext *uctx = NULL;
  601. int status = 0;
  602. u64 usr_db;
  603. uctx = pd->uctx;
  604. if (uctx) {
  605. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  606. (pd->id * PAGE_SIZE);
  607. if (pd->dpp_enabled)
  608. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  609. usr_db = ocrdma_get_db_addr(dev, pd->id);
  610. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  611. if (is_ucontext_pd(uctx, pd)) {
  612. ocrdma_release_ucontext_pd(uctx);
  613. return status;
  614. }
  615. }
  616. status = _ocrdma_dealloc_pd(dev, pd);
  617. return status;
  618. }
  619. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  620. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  621. {
  622. int status;
  623. mr->hwmr.fr_mr = 0;
  624. mr->hwmr.local_rd = 1;
  625. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  626. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  627. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  628. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  629. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  630. mr->hwmr.num_pbls = num_pbls;
  631. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  632. if (status)
  633. return status;
  634. mr->ibmr.lkey = mr->hwmr.lkey;
  635. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  636. mr->ibmr.rkey = mr->hwmr.lkey;
  637. return 0;
  638. }
  639. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  640. {
  641. int status;
  642. struct ocrdma_mr *mr;
  643. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  644. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  645. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  646. pr_err("%s err, invalid access rights\n", __func__);
  647. return ERR_PTR(-EINVAL);
  648. }
  649. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  650. if (!mr)
  651. return ERR_PTR(-ENOMEM);
  652. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  653. OCRDMA_ADDR_CHECK_DISABLE);
  654. if (status) {
  655. kfree(mr);
  656. return ERR_PTR(status);
  657. }
  658. return &mr->ibmr;
  659. }
  660. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  661. struct ocrdma_hw_mr *mr)
  662. {
  663. struct pci_dev *pdev = dev->nic_info.pdev;
  664. int i = 0;
  665. if (mr->pbl_table) {
  666. for (i = 0; i < mr->num_pbls; i++) {
  667. if (!mr->pbl_table[i].va)
  668. continue;
  669. dma_free_coherent(&pdev->dev, mr->pbl_size,
  670. mr->pbl_table[i].va,
  671. mr->pbl_table[i].pa);
  672. }
  673. kfree(mr->pbl_table);
  674. mr->pbl_table = NULL;
  675. }
  676. }
  677. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  678. u32 num_pbes)
  679. {
  680. u32 num_pbls = 0;
  681. u32 idx = 0;
  682. int status = 0;
  683. u32 pbl_size;
  684. do {
  685. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  686. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  687. status = -EFAULT;
  688. break;
  689. }
  690. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  691. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  692. idx++;
  693. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  694. mr->hwmr.num_pbes = num_pbes;
  695. mr->hwmr.num_pbls = num_pbls;
  696. mr->hwmr.pbl_size = pbl_size;
  697. return status;
  698. }
  699. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  700. {
  701. int status = 0;
  702. int i;
  703. u32 dma_len = mr->pbl_size;
  704. struct pci_dev *pdev = dev->nic_info.pdev;
  705. void *va;
  706. dma_addr_t pa;
  707. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  708. mr->num_pbls, GFP_KERNEL);
  709. if (!mr->pbl_table)
  710. return -ENOMEM;
  711. for (i = 0; i < mr->num_pbls; i++) {
  712. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  713. if (!va) {
  714. ocrdma_free_mr_pbl_tbl(dev, mr);
  715. status = -ENOMEM;
  716. break;
  717. }
  718. memset(va, 0, dma_len);
  719. mr->pbl_table[i].va = va;
  720. mr->pbl_table[i].pa = pa;
  721. }
  722. return status;
  723. }
  724. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  725. u32 num_pbes)
  726. {
  727. struct ocrdma_pbe *pbe;
  728. struct scatterlist *sg;
  729. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  730. struct ib_umem *umem = mr->umem;
  731. int shift, pg_cnt, pages, pbe_cnt, entry, total_num_pbes = 0;
  732. if (!mr->hwmr.num_pbes)
  733. return;
  734. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  735. pbe_cnt = 0;
  736. shift = ilog2(umem->page_size);
  737. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  738. pages = sg_dma_len(sg) >> shift;
  739. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  740. /* store the page address in pbe */
  741. pbe->pa_lo =
  742. cpu_to_le32(sg_dma_address
  743. (sg) +
  744. (umem->page_size * pg_cnt));
  745. pbe->pa_hi =
  746. cpu_to_le32(upper_32_bits
  747. ((sg_dma_address
  748. (sg) +
  749. umem->page_size * pg_cnt)));
  750. pbe_cnt += 1;
  751. total_num_pbes += 1;
  752. pbe++;
  753. /* if done building pbes, issue the mbx cmd. */
  754. if (total_num_pbes == num_pbes)
  755. return;
  756. /* if the given pbl is full storing the pbes,
  757. * move to next pbl.
  758. */
  759. if (pbe_cnt ==
  760. (mr->hwmr.pbl_size / sizeof(u64))) {
  761. pbl_tbl++;
  762. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  763. pbe_cnt = 0;
  764. }
  765. }
  766. }
  767. }
  768. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  769. u64 usr_addr, int acc, struct ib_udata *udata)
  770. {
  771. int status = -ENOMEM;
  772. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  773. struct ocrdma_mr *mr;
  774. struct ocrdma_pd *pd;
  775. u32 num_pbes;
  776. pd = get_ocrdma_pd(ibpd);
  777. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  778. return ERR_PTR(-EINVAL);
  779. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  780. if (!mr)
  781. return ERR_PTR(status);
  782. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  783. if (IS_ERR(mr->umem)) {
  784. status = -EFAULT;
  785. goto umem_err;
  786. }
  787. num_pbes = ib_umem_page_count(mr->umem);
  788. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  789. if (status)
  790. goto umem_err;
  791. mr->hwmr.pbe_size = mr->umem->page_size;
  792. mr->hwmr.fbo = ib_umem_offset(mr->umem);
  793. mr->hwmr.va = usr_addr;
  794. mr->hwmr.len = len;
  795. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  796. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  797. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  798. mr->hwmr.local_rd = 1;
  799. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  800. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  801. if (status)
  802. goto umem_err;
  803. build_user_pbes(dev, mr, num_pbes);
  804. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  805. if (status)
  806. goto mbx_err;
  807. mr->ibmr.lkey = mr->hwmr.lkey;
  808. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  809. mr->ibmr.rkey = mr->hwmr.lkey;
  810. return &mr->ibmr;
  811. mbx_err:
  812. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  813. umem_err:
  814. kfree(mr);
  815. return ERR_PTR(status);
  816. }
  817. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  818. {
  819. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  820. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  821. (void) ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  822. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  823. /* it could be user registered memory. */
  824. if (mr->umem)
  825. ib_umem_release(mr->umem);
  826. kfree(mr);
  827. /* Don't stop cleanup, in case FW is unresponsive */
  828. if (dev->mqe_ctx.fw_error_state) {
  829. pr_err("%s(%d) fw not responding.\n",
  830. __func__, dev->id);
  831. }
  832. return 0;
  833. }
  834. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  835. struct ib_udata *udata,
  836. struct ib_ucontext *ib_ctx)
  837. {
  838. int status;
  839. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  840. struct ocrdma_create_cq_uresp uresp;
  841. memset(&uresp, 0, sizeof(uresp));
  842. uresp.cq_id = cq->id;
  843. uresp.page_size = PAGE_ALIGN(cq->len);
  844. uresp.num_pages = 1;
  845. uresp.max_hw_cqe = cq->max_hw_cqe;
  846. uresp.page_addr[0] = virt_to_phys(cq->va);
  847. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  848. uresp.db_page_size = dev->nic_info.db_page_size;
  849. uresp.phase_change = cq->phase_change ? 1 : 0;
  850. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  851. if (status) {
  852. pr_err("%s(%d) copy error cqid=0x%x.\n",
  853. __func__, dev->id, cq->id);
  854. goto err;
  855. }
  856. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  857. if (status)
  858. goto err;
  859. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  860. if (status) {
  861. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  862. goto err;
  863. }
  864. cq->ucontext = uctx;
  865. err:
  866. return status;
  867. }
  868. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev, int entries, int vector,
  869. struct ib_ucontext *ib_ctx,
  870. struct ib_udata *udata)
  871. {
  872. struct ocrdma_cq *cq;
  873. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  874. struct ocrdma_ucontext *uctx = NULL;
  875. u16 pd_id = 0;
  876. int status;
  877. struct ocrdma_create_cq_ureq ureq;
  878. if (udata) {
  879. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  880. return ERR_PTR(-EFAULT);
  881. } else
  882. ureq.dpp_cq = 0;
  883. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  884. if (!cq)
  885. return ERR_PTR(-ENOMEM);
  886. spin_lock_init(&cq->cq_lock);
  887. spin_lock_init(&cq->comp_handler_lock);
  888. INIT_LIST_HEAD(&cq->sq_head);
  889. INIT_LIST_HEAD(&cq->rq_head);
  890. cq->first_arm = true;
  891. if (ib_ctx) {
  892. uctx = get_ocrdma_ucontext(ib_ctx);
  893. pd_id = uctx->cntxt_pd->id;
  894. }
  895. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  896. if (status) {
  897. kfree(cq);
  898. return ERR_PTR(status);
  899. }
  900. if (ib_ctx) {
  901. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  902. if (status)
  903. goto ctx_err;
  904. }
  905. cq->phase = OCRDMA_CQE_VALID;
  906. dev->cq_tbl[cq->id] = cq;
  907. return &cq->ibcq;
  908. ctx_err:
  909. ocrdma_mbx_destroy_cq(dev, cq);
  910. kfree(cq);
  911. return ERR_PTR(status);
  912. }
  913. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  914. struct ib_udata *udata)
  915. {
  916. int status = 0;
  917. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  918. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  919. status = -EINVAL;
  920. return status;
  921. }
  922. ibcq->cqe = new_cnt;
  923. return status;
  924. }
  925. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  926. {
  927. int cqe_cnt;
  928. int valid_count = 0;
  929. unsigned long flags;
  930. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  931. struct ocrdma_cqe *cqe = NULL;
  932. cqe = cq->va;
  933. cqe_cnt = cq->cqe_cnt;
  934. /* Last irq might have scheduled a polling thread
  935. * sync-up with it before hard flushing.
  936. */
  937. spin_lock_irqsave(&cq->cq_lock, flags);
  938. while (cqe_cnt) {
  939. if (is_cqe_valid(cq, cqe))
  940. valid_count++;
  941. cqe++;
  942. cqe_cnt--;
  943. }
  944. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  945. spin_unlock_irqrestore(&cq->cq_lock, flags);
  946. }
  947. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  948. {
  949. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  950. struct ocrdma_eq *eq = NULL;
  951. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  952. int pdid = 0;
  953. u32 irq, indx;
  954. dev->cq_tbl[cq->id] = NULL;
  955. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  956. if (indx == -EINVAL)
  957. BUG();
  958. eq = &dev->eq_tbl[indx];
  959. irq = ocrdma_get_irq(dev, eq);
  960. synchronize_irq(irq);
  961. ocrdma_flush_cq(cq);
  962. (void)ocrdma_mbx_destroy_cq(dev, cq);
  963. if (cq->ucontext) {
  964. pdid = cq->ucontext->cntxt_pd->id;
  965. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  966. PAGE_ALIGN(cq->len));
  967. ocrdma_del_mmap(cq->ucontext,
  968. ocrdma_get_db_addr(dev, pdid),
  969. dev->nic_info.db_page_size);
  970. }
  971. kfree(cq);
  972. return 0;
  973. }
  974. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  975. {
  976. int status = -EINVAL;
  977. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  978. dev->qp_tbl[qp->id] = qp;
  979. status = 0;
  980. }
  981. return status;
  982. }
  983. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  984. {
  985. dev->qp_tbl[qp->id] = NULL;
  986. }
  987. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  988. struct ib_qp_init_attr *attrs)
  989. {
  990. if ((attrs->qp_type != IB_QPT_GSI) &&
  991. (attrs->qp_type != IB_QPT_RC) &&
  992. (attrs->qp_type != IB_QPT_UC) &&
  993. (attrs->qp_type != IB_QPT_UD)) {
  994. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  995. __func__, dev->id, attrs->qp_type);
  996. return -EINVAL;
  997. }
  998. /* Skip the check for QP1 to support CM size of 128 */
  999. if ((attrs->qp_type != IB_QPT_GSI) &&
  1000. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  1001. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  1002. __func__, dev->id, attrs->cap.max_send_wr);
  1003. pr_err("%s(%d) supported send_wr=0x%x\n",
  1004. __func__, dev->id, dev->attr.max_wqe);
  1005. return -EINVAL;
  1006. }
  1007. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  1008. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  1009. __func__, dev->id, attrs->cap.max_recv_wr);
  1010. pr_err("%s(%d) supported recv_wr=0x%x\n",
  1011. __func__, dev->id, dev->attr.max_rqe);
  1012. return -EINVAL;
  1013. }
  1014. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  1015. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  1016. __func__, dev->id, attrs->cap.max_inline_data);
  1017. pr_err("%s(%d) supported inline data size=0x%x\n",
  1018. __func__, dev->id, dev->attr.max_inline_data);
  1019. return -EINVAL;
  1020. }
  1021. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  1022. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  1023. __func__, dev->id, attrs->cap.max_send_sge);
  1024. pr_err("%s(%d) supported send_sge=0x%x\n",
  1025. __func__, dev->id, dev->attr.max_send_sge);
  1026. return -EINVAL;
  1027. }
  1028. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  1029. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  1030. __func__, dev->id, attrs->cap.max_recv_sge);
  1031. pr_err("%s(%d) supported recv_sge=0x%x\n",
  1032. __func__, dev->id, dev->attr.max_recv_sge);
  1033. return -EINVAL;
  1034. }
  1035. /* unprivileged user space cannot create special QP */
  1036. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  1037. pr_err
  1038. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  1039. __func__, dev->id, attrs->qp_type);
  1040. return -EINVAL;
  1041. }
  1042. /* allow creating only one GSI type of QP */
  1043. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  1044. pr_err("%s(%d) GSI special QPs already created.\n",
  1045. __func__, dev->id);
  1046. return -EINVAL;
  1047. }
  1048. /* verify consumer QPs are not trying to use GSI QP's CQ */
  1049. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  1050. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  1051. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  1052. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  1053. __func__, dev->id);
  1054. return -EINVAL;
  1055. }
  1056. }
  1057. return 0;
  1058. }
  1059. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  1060. struct ib_udata *udata, int dpp_offset,
  1061. int dpp_credit_lmt, int srq)
  1062. {
  1063. int status = 0;
  1064. u64 usr_db;
  1065. struct ocrdma_create_qp_uresp uresp;
  1066. struct ocrdma_pd *pd = qp->pd;
  1067. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  1068. memset(&uresp, 0, sizeof(uresp));
  1069. usr_db = dev->nic_info.unmapped_db +
  1070. (pd->id * dev->nic_info.db_page_size);
  1071. uresp.qp_id = qp->id;
  1072. uresp.sq_dbid = qp->sq.dbid;
  1073. uresp.num_sq_pages = 1;
  1074. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  1075. uresp.sq_page_addr[0] = virt_to_phys(qp->sq.va);
  1076. uresp.num_wqe_allocated = qp->sq.max_cnt;
  1077. if (!srq) {
  1078. uresp.rq_dbid = qp->rq.dbid;
  1079. uresp.num_rq_pages = 1;
  1080. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  1081. uresp.rq_page_addr[0] = virt_to_phys(qp->rq.va);
  1082. uresp.num_rqe_allocated = qp->rq.max_cnt;
  1083. }
  1084. uresp.db_page_addr = usr_db;
  1085. uresp.db_page_size = dev->nic_info.db_page_size;
  1086. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  1087. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1088. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  1089. if (qp->dpp_enabled) {
  1090. uresp.dpp_credit = dpp_credit_lmt;
  1091. uresp.dpp_offset = dpp_offset;
  1092. }
  1093. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1094. if (status) {
  1095. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  1096. goto err;
  1097. }
  1098. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  1099. uresp.sq_page_size);
  1100. if (status)
  1101. goto err;
  1102. if (!srq) {
  1103. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1104. uresp.rq_page_size);
  1105. if (status)
  1106. goto rq_map_err;
  1107. }
  1108. return status;
  1109. rq_map_err:
  1110. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1111. err:
  1112. return status;
  1113. }
  1114. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1115. struct ocrdma_pd *pd)
  1116. {
  1117. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1118. qp->sq_db = dev->nic_info.db +
  1119. (pd->id * dev->nic_info.db_page_size) +
  1120. OCRDMA_DB_GEN2_SQ_OFFSET;
  1121. qp->rq_db = dev->nic_info.db +
  1122. (pd->id * dev->nic_info.db_page_size) +
  1123. OCRDMA_DB_GEN2_RQ_OFFSET;
  1124. } else {
  1125. qp->sq_db = dev->nic_info.db +
  1126. (pd->id * dev->nic_info.db_page_size) +
  1127. OCRDMA_DB_SQ_OFFSET;
  1128. qp->rq_db = dev->nic_info.db +
  1129. (pd->id * dev->nic_info.db_page_size) +
  1130. OCRDMA_DB_RQ_OFFSET;
  1131. }
  1132. }
  1133. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1134. {
  1135. qp->wqe_wr_id_tbl =
  1136. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1137. GFP_KERNEL);
  1138. if (qp->wqe_wr_id_tbl == NULL)
  1139. return -ENOMEM;
  1140. qp->rqe_wr_id_tbl =
  1141. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1142. if (qp->rqe_wr_id_tbl == NULL)
  1143. return -ENOMEM;
  1144. return 0;
  1145. }
  1146. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1147. struct ocrdma_pd *pd,
  1148. struct ib_qp_init_attr *attrs)
  1149. {
  1150. qp->pd = pd;
  1151. spin_lock_init(&qp->q_lock);
  1152. INIT_LIST_HEAD(&qp->sq_entry);
  1153. INIT_LIST_HEAD(&qp->rq_entry);
  1154. qp->qp_type = attrs->qp_type;
  1155. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1156. qp->max_inline_data = attrs->cap.max_inline_data;
  1157. qp->sq.max_sges = attrs->cap.max_send_sge;
  1158. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1159. qp->state = OCRDMA_QPS_RST;
  1160. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1161. }
  1162. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1163. struct ib_qp_init_attr *attrs)
  1164. {
  1165. if (attrs->qp_type == IB_QPT_GSI) {
  1166. dev->gsi_qp_created = 1;
  1167. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1168. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1169. }
  1170. }
  1171. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1172. struct ib_qp_init_attr *attrs,
  1173. struct ib_udata *udata)
  1174. {
  1175. int status;
  1176. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1177. struct ocrdma_qp *qp;
  1178. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1179. struct ocrdma_create_qp_ureq ureq;
  1180. u16 dpp_credit_lmt, dpp_offset;
  1181. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1182. if (status)
  1183. goto gen_err;
  1184. memset(&ureq, 0, sizeof(ureq));
  1185. if (udata) {
  1186. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1187. return ERR_PTR(-EFAULT);
  1188. }
  1189. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1190. if (!qp) {
  1191. status = -ENOMEM;
  1192. goto gen_err;
  1193. }
  1194. ocrdma_set_qp_init_params(qp, pd, attrs);
  1195. if (udata == NULL)
  1196. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1197. OCRDMA_QP_FAST_REG);
  1198. mutex_lock(&dev->dev_lock);
  1199. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1200. ureq.dpp_cq_id,
  1201. &dpp_offset, &dpp_credit_lmt);
  1202. if (status)
  1203. goto mbx_err;
  1204. /* user space QP's wr_id table are managed in library */
  1205. if (udata == NULL) {
  1206. status = ocrdma_alloc_wr_id_tbl(qp);
  1207. if (status)
  1208. goto map_err;
  1209. }
  1210. status = ocrdma_add_qpn_map(dev, qp);
  1211. if (status)
  1212. goto map_err;
  1213. ocrdma_set_qp_db(dev, qp, pd);
  1214. if (udata) {
  1215. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1216. dpp_credit_lmt,
  1217. (attrs->srq != NULL));
  1218. if (status)
  1219. goto cpy_err;
  1220. }
  1221. ocrdma_store_gsi_qp_cq(dev, attrs);
  1222. qp->ibqp.qp_num = qp->id;
  1223. mutex_unlock(&dev->dev_lock);
  1224. return &qp->ibqp;
  1225. cpy_err:
  1226. ocrdma_del_qpn_map(dev, qp);
  1227. map_err:
  1228. ocrdma_mbx_destroy_qp(dev, qp);
  1229. mbx_err:
  1230. mutex_unlock(&dev->dev_lock);
  1231. kfree(qp->wqe_wr_id_tbl);
  1232. kfree(qp->rqe_wr_id_tbl);
  1233. kfree(qp);
  1234. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1235. gen_err:
  1236. return ERR_PTR(status);
  1237. }
  1238. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1239. int attr_mask)
  1240. {
  1241. int status = 0;
  1242. struct ocrdma_qp *qp;
  1243. struct ocrdma_dev *dev;
  1244. enum ib_qp_state old_qps;
  1245. qp = get_ocrdma_qp(ibqp);
  1246. dev = get_ocrdma_dev(ibqp->device);
  1247. if (attr_mask & IB_QP_STATE)
  1248. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1249. /* if new and previous states are same hw doesn't need to
  1250. * know about it.
  1251. */
  1252. if (status < 0)
  1253. return status;
  1254. status = ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1255. return status;
  1256. }
  1257. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1258. int attr_mask, struct ib_udata *udata)
  1259. {
  1260. unsigned long flags;
  1261. int status = -EINVAL;
  1262. struct ocrdma_qp *qp;
  1263. struct ocrdma_dev *dev;
  1264. enum ib_qp_state old_qps, new_qps;
  1265. qp = get_ocrdma_qp(ibqp);
  1266. dev = get_ocrdma_dev(ibqp->device);
  1267. /* syncronize with multiple context trying to change, retrive qps */
  1268. mutex_lock(&dev->dev_lock);
  1269. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1270. spin_lock_irqsave(&qp->q_lock, flags);
  1271. old_qps = get_ibqp_state(qp->state);
  1272. if (attr_mask & IB_QP_STATE)
  1273. new_qps = attr->qp_state;
  1274. else
  1275. new_qps = old_qps;
  1276. spin_unlock_irqrestore(&qp->q_lock, flags);
  1277. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask,
  1278. IB_LINK_LAYER_ETHERNET)) {
  1279. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1280. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1281. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1282. old_qps, new_qps);
  1283. goto param_err;
  1284. }
  1285. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1286. if (status > 0)
  1287. status = 0;
  1288. param_err:
  1289. mutex_unlock(&dev->dev_lock);
  1290. return status;
  1291. }
  1292. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1293. {
  1294. switch (mtu) {
  1295. case 256:
  1296. return IB_MTU_256;
  1297. case 512:
  1298. return IB_MTU_512;
  1299. case 1024:
  1300. return IB_MTU_1024;
  1301. case 2048:
  1302. return IB_MTU_2048;
  1303. case 4096:
  1304. return IB_MTU_4096;
  1305. default:
  1306. return IB_MTU_1024;
  1307. }
  1308. }
  1309. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1310. {
  1311. int ib_qp_acc_flags = 0;
  1312. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1313. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1314. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1315. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1316. return ib_qp_acc_flags;
  1317. }
  1318. int ocrdma_query_qp(struct ib_qp *ibqp,
  1319. struct ib_qp_attr *qp_attr,
  1320. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1321. {
  1322. int status;
  1323. u32 qp_state;
  1324. struct ocrdma_qp_params params;
  1325. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1326. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1327. memset(&params, 0, sizeof(params));
  1328. mutex_lock(&dev->dev_lock);
  1329. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1330. mutex_unlock(&dev->dev_lock);
  1331. if (status)
  1332. goto mbx_err;
  1333. if (qp->qp_type == IB_QPT_UD)
  1334. qp_attr->qkey = params.qkey;
  1335. qp_attr->path_mtu =
  1336. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1337. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1338. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1339. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1340. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1341. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1342. qp_attr->dest_qp_num =
  1343. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1344. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1345. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1346. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1347. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1348. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1349. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1350. qp_init_attr->cap = qp_attr->cap;
  1351. memcpy(&qp_attr->ah_attr.grh.dgid, &params.dgid[0],
  1352. sizeof(params.dgid));
  1353. qp_attr->ah_attr.grh.flow_label = params.rnt_rc_sl_fl &
  1354. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK;
  1355. qp_attr->ah_attr.grh.sgid_index = qp->sgid_idx;
  1356. qp_attr->ah_attr.grh.hop_limit = (params.hop_lmt_rq_psn &
  1357. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1358. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT;
  1359. qp_attr->ah_attr.grh.traffic_class = (params.tclass_sq_psn &
  1360. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1361. OCRDMA_QP_PARAMS_TCLASS_SHIFT;
  1362. qp_attr->ah_attr.ah_flags = IB_AH_GRH;
  1363. qp_attr->ah_attr.port_num = 1;
  1364. qp_attr->ah_attr.sl = (params.rnt_rc_sl_fl &
  1365. OCRDMA_QP_PARAMS_SL_MASK) >>
  1366. OCRDMA_QP_PARAMS_SL_SHIFT;
  1367. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1368. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1369. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1370. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1371. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1372. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1373. qp_attr->retry_cnt =
  1374. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1375. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1376. qp_attr->min_rnr_timer = 0;
  1377. qp_attr->pkey_index = 0;
  1378. qp_attr->port_num = 1;
  1379. qp_attr->ah_attr.src_path_bits = 0;
  1380. qp_attr->ah_attr.static_rate = 0;
  1381. qp_attr->alt_pkey_index = 0;
  1382. qp_attr->alt_port_num = 0;
  1383. qp_attr->alt_timeout = 0;
  1384. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1385. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1386. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1387. qp_attr->qp_state = get_ibqp_state(qp_state);
  1388. qp_attr->cur_qp_state = qp_attr->qp_state;
  1389. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1390. qp_attr->max_dest_rd_atomic =
  1391. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1392. qp_attr->max_rd_atomic =
  1393. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1394. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1395. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1396. /* Sync driver QP state with FW */
  1397. ocrdma_qp_state_change(qp, qp_attr->qp_state, NULL);
  1398. mbx_err:
  1399. return status;
  1400. }
  1401. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, unsigned int idx)
  1402. {
  1403. unsigned int i = idx / 32;
  1404. u32 mask = (1U << (idx % 32));
  1405. srq->idx_bit_fields[i] ^= mask;
  1406. }
  1407. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1408. {
  1409. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1410. }
  1411. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1412. {
  1413. return (qp->sq.tail == qp->sq.head);
  1414. }
  1415. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1416. {
  1417. return (qp->rq.tail == qp->rq.head);
  1418. }
  1419. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1420. {
  1421. return q->va + (q->head * q->entry_size);
  1422. }
  1423. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1424. u32 idx)
  1425. {
  1426. return q->va + (idx * q->entry_size);
  1427. }
  1428. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1429. {
  1430. q->head = (q->head + 1) & q->max_wqe_idx;
  1431. }
  1432. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1433. {
  1434. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1435. }
  1436. /* discard the cqe for a given QP */
  1437. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1438. {
  1439. unsigned long cq_flags;
  1440. unsigned long flags;
  1441. int discard_cnt = 0;
  1442. u32 cur_getp, stop_getp;
  1443. struct ocrdma_cqe *cqe;
  1444. u32 qpn = 0, wqe_idx = 0;
  1445. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1446. /* traverse through the CQEs in the hw CQ,
  1447. * find the matching CQE for a given qp,
  1448. * mark the matching one discarded by clearing qpn.
  1449. * ring the doorbell in the poll_cq() as
  1450. * we don't complete out of order cqe.
  1451. */
  1452. cur_getp = cq->getp;
  1453. /* find upto when do we reap the cq. */
  1454. stop_getp = cur_getp;
  1455. do {
  1456. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1457. break;
  1458. cqe = cq->va + cur_getp;
  1459. /* if (a) done reaping whole hw cq, or
  1460. * (b) qp_xq becomes empty.
  1461. * then exit
  1462. */
  1463. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1464. /* if previously discarded cqe found, skip that too. */
  1465. /* check for matching qp */
  1466. if (qpn == 0 || qpn != qp->id)
  1467. goto skip_cqe;
  1468. if (is_cqe_for_sq(cqe)) {
  1469. ocrdma_hwq_inc_tail(&qp->sq);
  1470. } else {
  1471. if (qp->srq) {
  1472. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1473. OCRDMA_CQE_BUFTAG_SHIFT) &
  1474. qp->srq->rq.max_wqe_idx;
  1475. if (wqe_idx < 1)
  1476. BUG();
  1477. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1478. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1479. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1480. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1481. } else {
  1482. ocrdma_hwq_inc_tail(&qp->rq);
  1483. }
  1484. }
  1485. /* mark cqe discarded so that it is not picked up later
  1486. * in the poll_cq().
  1487. */
  1488. discard_cnt += 1;
  1489. cqe->cmn.qpn = 0;
  1490. skip_cqe:
  1491. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1492. } while (cur_getp != stop_getp);
  1493. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1494. }
  1495. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1496. {
  1497. int found = false;
  1498. unsigned long flags;
  1499. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1500. /* sync with any active CQ poll */
  1501. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1502. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1503. if (found)
  1504. list_del(&qp->sq_entry);
  1505. if (!qp->srq) {
  1506. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1507. if (found)
  1508. list_del(&qp->rq_entry);
  1509. }
  1510. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1511. }
  1512. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1513. {
  1514. struct ocrdma_pd *pd;
  1515. struct ocrdma_qp *qp;
  1516. struct ocrdma_dev *dev;
  1517. struct ib_qp_attr attrs;
  1518. int attr_mask;
  1519. unsigned long flags;
  1520. qp = get_ocrdma_qp(ibqp);
  1521. dev = get_ocrdma_dev(ibqp->device);
  1522. pd = qp->pd;
  1523. /* change the QP state to ERROR */
  1524. if (qp->state != OCRDMA_QPS_RST) {
  1525. attrs.qp_state = IB_QPS_ERR;
  1526. attr_mask = IB_QP_STATE;
  1527. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1528. }
  1529. /* ensure that CQEs for newly created QP (whose id may be same with
  1530. * one which just getting destroyed are same), dont get
  1531. * discarded until the old CQEs are discarded.
  1532. */
  1533. mutex_lock(&dev->dev_lock);
  1534. (void) ocrdma_mbx_destroy_qp(dev, qp);
  1535. /*
  1536. * acquire CQ lock while destroy is in progress, in order to
  1537. * protect against proessing in-flight CQEs for this QP.
  1538. */
  1539. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1540. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1541. spin_lock(&qp->rq_cq->cq_lock);
  1542. ocrdma_del_qpn_map(dev, qp);
  1543. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1544. spin_unlock(&qp->rq_cq->cq_lock);
  1545. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1546. if (!pd->uctx) {
  1547. ocrdma_discard_cqes(qp, qp->sq_cq);
  1548. ocrdma_discard_cqes(qp, qp->rq_cq);
  1549. }
  1550. mutex_unlock(&dev->dev_lock);
  1551. if (pd->uctx) {
  1552. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1553. PAGE_ALIGN(qp->sq.len));
  1554. if (!qp->srq)
  1555. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1556. PAGE_ALIGN(qp->rq.len));
  1557. }
  1558. ocrdma_del_flush_qp(qp);
  1559. kfree(qp->wqe_wr_id_tbl);
  1560. kfree(qp->rqe_wr_id_tbl);
  1561. kfree(qp);
  1562. return 0;
  1563. }
  1564. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1565. struct ib_udata *udata)
  1566. {
  1567. int status;
  1568. struct ocrdma_create_srq_uresp uresp;
  1569. memset(&uresp, 0, sizeof(uresp));
  1570. uresp.rq_dbid = srq->rq.dbid;
  1571. uresp.num_rq_pages = 1;
  1572. uresp.rq_page_addr[0] = virt_to_phys(srq->rq.va);
  1573. uresp.rq_page_size = srq->rq.len;
  1574. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1575. (srq->pd->id * dev->nic_info.db_page_size);
  1576. uresp.db_page_size = dev->nic_info.db_page_size;
  1577. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1578. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1579. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1580. uresp.db_shift = 24;
  1581. } else {
  1582. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1583. uresp.db_shift = 16;
  1584. }
  1585. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1586. if (status)
  1587. return status;
  1588. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1589. uresp.rq_page_size);
  1590. if (status)
  1591. return status;
  1592. return status;
  1593. }
  1594. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1595. struct ib_srq_init_attr *init_attr,
  1596. struct ib_udata *udata)
  1597. {
  1598. int status = -ENOMEM;
  1599. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1600. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1601. struct ocrdma_srq *srq;
  1602. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1603. return ERR_PTR(-EINVAL);
  1604. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1605. return ERR_PTR(-EINVAL);
  1606. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1607. if (!srq)
  1608. return ERR_PTR(status);
  1609. spin_lock_init(&srq->q_lock);
  1610. srq->pd = pd;
  1611. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1612. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1613. if (status)
  1614. goto err;
  1615. if (udata == NULL) {
  1616. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1617. GFP_KERNEL);
  1618. if (srq->rqe_wr_id_tbl == NULL)
  1619. goto arm_err;
  1620. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1621. (srq->rq.max_cnt % 32 ? 1 : 0);
  1622. srq->idx_bit_fields =
  1623. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1624. if (srq->idx_bit_fields == NULL)
  1625. goto arm_err;
  1626. memset(srq->idx_bit_fields, 0xff,
  1627. srq->bit_fields_len * sizeof(u32));
  1628. }
  1629. if (init_attr->attr.srq_limit) {
  1630. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1631. if (status)
  1632. goto arm_err;
  1633. }
  1634. if (udata) {
  1635. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1636. if (status)
  1637. goto arm_err;
  1638. }
  1639. return &srq->ibsrq;
  1640. arm_err:
  1641. ocrdma_mbx_destroy_srq(dev, srq);
  1642. err:
  1643. kfree(srq->rqe_wr_id_tbl);
  1644. kfree(srq->idx_bit_fields);
  1645. kfree(srq);
  1646. return ERR_PTR(status);
  1647. }
  1648. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1649. struct ib_srq_attr *srq_attr,
  1650. enum ib_srq_attr_mask srq_attr_mask,
  1651. struct ib_udata *udata)
  1652. {
  1653. int status = 0;
  1654. struct ocrdma_srq *srq;
  1655. srq = get_ocrdma_srq(ibsrq);
  1656. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1657. status = -EINVAL;
  1658. else
  1659. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1660. return status;
  1661. }
  1662. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1663. {
  1664. int status;
  1665. struct ocrdma_srq *srq;
  1666. srq = get_ocrdma_srq(ibsrq);
  1667. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1668. return status;
  1669. }
  1670. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1671. {
  1672. int status;
  1673. struct ocrdma_srq *srq;
  1674. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1675. srq = get_ocrdma_srq(ibsrq);
  1676. status = ocrdma_mbx_destroy_srq(dev, srq);
  1677. if (srq->pd->uctx)
  1678. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1679. PAGE_ALIGN(srq->rq.len));
  1680. kfree(srq->idx_bit_fields);
  1681. kfree(srq->rqe_wr_id_tbl);
  1682. kfree(srq);
  1683. return status;
  1684. }
  1685. /* unprivileged verbs and their support functions. */
  1686. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1687. struct ocrdma_hdr_wqe *hdr,
  1688. struct ib_send_wr *wr)
  1689. {
  1690. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1691. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1692. struct ocrdma_ah *ah = get_ocrdma_ah(wr->wr.ud.ah);
  1693. ud_hdr->rsvd_dest_qpn = wr->wr.ud.remote_qpn;
  1694. if (qp->qp_type == IB_QPT_GSI)
  1695. ud_hdr->qkey = qp->qkey;
  1696. else
  1697. ud_hdr->qkey = wr->wr.ud.remote_qkey;
  1698. ud_hdr->rsvd_ahid = ah->id;
  1699. if (ah->av->valid & OCRDMA_AV_VLAN_VALID)
  1700. hdr->cw |= (OCRDMA_FLAG_AH_VLAN_PR << OCRDMA_WQE_FLAGS_SHIFT);
  1701. }
  1702. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1703. struct ocrdma_sge *sge, int num_sge,
  1704. struct ib_sge *sg_list)
  1705. {
  1706. int i;
  1707. for (i = 0; i < num_sge; i++) {
  1708. sge[i].lrkey = sg_list[i].lkey;
  1709. sge[i].addr_lo = sg_list[i].addr;
  1710. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1711. sge[i].len = sg_list[i].length;
  1712. hdr->total_len += sg_list[i].length;
  1713. }
  1714. if (num_sge == 0)
  1715. memset(sge, 0, sizeof(*sge));
  1716. }
  1717. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1718. {
  1719. uint32_t total_len = 0, i;
  1720. for (i = 0; i < num_sge; i++)
  1721. total_len += sg_list[i].length;
  1722. return total_len;
  1723. }
  1724. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1725. struct ocrdma_hdr_wqe *hdr,
  1726. struct ocrdma_sge *sge,
  1727. struct ib_send_wr *wr, u32 wqe_size)
  1728. {
  1729. int i;
  1730. char *dpp_addr;
  1731. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1732. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1733. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1734. pr_err("%s() supported_len=0x%x,\n"
  1735. " unsupported len req=0x%x\n", __func__,
  1736. qp->max_inline_data, hdr->total_len);
  1737. return -EINVAL;
  1738. }
  1739. dpp_addr = (char *)sge;
  1740. for (i = 0; i < wr->num_sge; i++) {
  1741. memcpy(dpp_addr,
  1742. (void *)(unsigned long)wr->sg_list[i].addr,
  1743. wr->sg_list[i].length);
  1744. dpp_addr += wr->sg_list[i].length;
  1745. }
  1746. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1747. if (0 == hdr->total_len)
  1748. wqe_size += sizeof(struct ocrdma_sge);
  1749. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1750. } else {
  1751. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1752. if (wr->num_sge)
  1753. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1754. else
  1755. wqe_size += sizeof(struct ocrdma_sge);
  1756. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1757. }
  1758. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1759. return 0;
  1760. }
  1761. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1762. struct ib_send_wr *wr)
  1763. {
  1764. int status;
  1765. struct ocrdma_sge *sge;
  1766. u32 wqe_size = sizeof(*hdr);
  1767. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1768. ocrdma_build_ud_hdr(qp, hdr, wr);
  1769. sge = (struct ocrdma_sge *)(hdr + 2);
  1770. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1771. } else {
  1772. sge = (struct ocrdma_sge *)(hdr + 1);
  1773. }
  1774. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1775. return status;
  1776. }
  1777. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1778. struct ib_send_wr *wr)
  1779. {
  1780. int status;
  1781. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1782. struct ocrdma_sge *sge = ext_rw + 1;
  1783. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1784. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1785. if (status)
  1786. return status;
  1787. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1788. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1789. ext_rw->lrkey = wr->wr.rdma.rkey;
  1790. ext_rw->len = hdr->total_len;
  1791. return 0;
  1792. }
  1793. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1794. struct ib_send_wr *wr)
  1795. {
  1796. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1797. struct ocrdma_sge *sge = ext_rw + 1;
  1798. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1799. sizeof(struct ocrdma_hdr_wqe);
  1800. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1801. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1802. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1803. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1804. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1805. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1806. ext_rw->lrkey = wr->wr.rdma.rkey;
  1807. ext_rw->len = hdr->total_len;
  1808. }
  1809. static void build_frmr_pbes(struct ib_send_wr *wr, struct ocrdma_pbl *pbl_tbl,
  1810. struct ocrdma_hw_mr *hwmr)
  1811. {
  1812. int i;
  1813. u64 buf_addr = 0;
  1814. int num_pbes;
  1815. struct ocrdma_pbe *pbe;
  1816. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1817. num_pbes = 0;
  1818. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  1819. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  1820. /* number of pbes can be more for one OS buf, when
  1821. * buffers are of different sizes.
  1822. * split the ib_buf to one or more pbes.
  1823. */
  1824. buf_addr = wr->wr.fast_reg.page_list->page_list[i];
  1825. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1826. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1827. num_pbes += 1;
  1828. pbe++;
  1829. /* if the pbl is full storing the pbes,
  1830. * move to next pbl.
  1831. */
  1832. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  1833. pbl_tbl++;
  1834. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1835. }
  1836. }
  1837. return;
  1838. }
  1839. static int get_encoded_page_size(int pg_sz)
  1840. {
  1841. /* Max size is 256M 4096 << 16 */
  1842. int i = 0;
  1843. for (; i < 17; i++)
  1844. if (pg_sz == (4096 << i))
  1845. break;
  1846. return i;
  1847. }
  1848. static int ocrdma_build_fr(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1849. struct ib_send_wr *wr)
  1850. {
  1851. u64 fbo;
  1852. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1853. struct ocrdma_mr *mr;
  1854. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1855. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1856. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1857. if (wr->wr.fast_reg.page_list_len > dev->attr.max_pages_per_frmr)
  1858. return -EINVAL;
  1859. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1860. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1861. if (wr->wr.fast_reg.page_list_len == 0)
  1862. BUG();
  1863. if (wr->wr.fast_reg.access_flags & IB_ACCESS_LOCAL_WRITE)
  1864. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1865. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_WRITE)
  1866. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1867. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_READ)
  1868. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1869. hdr->lkey = wr->wr.fast_reg.rkey;
  1870. hdr->total_len = wr->wr.fast_reg.length;
  1871. fbo = wr->wr.fast_reg.iova_start -
  1872. (wr->wr.fast_reg.page_list->page_list[0] & PAGE_MASK);
  1873. fast_reg->va_hi = upper_32_bits(wr->wr.fast_reg.iova_start);
  1874. fast_reg->va_lo = (u32) (wr->wr.fast_reg.iova_start & 0xffffffff);
  1875. fast_reg->fbo_hi = upper_32_bits(fbo);
  1876. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1877. fast_reg->num_sges = wr->wr.fast_reg.page_list_len;
  1878. fast_reg->size_sge =
  1879. get_encoded_page_size(1 << wr->wr.fast_reg.page_shift);
  1880. mr = (struct ocrdma_mr *) (unsigned long)
  1881. dev->stag_arr[(hdr->lkey >> 8) & (OCRDMA_MAX_STAG - 1)];
  1882. build_frmr_pbes(wr, mr->hwmr.pbl_table, &mr->hwmr);
  1883. return 0;
  1884. }
  1885. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1886. {
  1887. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1888. iowrite32(val, qp->sq_db);
  1889. }
  1890. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1891. struct ib_send_wr **bad_wr)
  1892. {
  1893. int status = 0;
  1894. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1895. struct ocrdma_hdr_wqe *hdr;
  1896. unsigned long flags;
  1897. spin_lock_irqsave(&qp->q_lock, flags);
  1898. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1899. spin_unlock_irqrestore(&qp->q_lock, flags);
  1900. *bad_wr = wr;
  1901. return -EINVAL;
  1902. }
  1903. while (wr) {
  1904. if (qp->qp_type == IB_QPT_UD &&
  1905. (wr->opcode != IB_WR_SEND &&
  1906. wr->opcode != IB_WR_SEND_WITH_IMM)) {
  1907. *bad_wr = wr;
  1908. status = -EINVAL;
  1909. break;
  1910. }
  1911. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1912. wr->num_sge > qp->sq.max_sges) {
  1913. *bad_wr = wr;
  1914. status = -ENOMEM;
  1915. break;
  1916. }
  1917. hdr = ocrdma_hwq_head(&qp->sq);
  1918. hdr->cw = 0;
  1919. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1920. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1921. if (wr->send_flags & IB_SEND_FENCE)
  1922. hdr->cw |=
  1923. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1924. if (wr->send_flags & IB_SEND_SOLICITED)
  1925. hdr->cw |=
  1926. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1927. hdr->total_len = 0;
  1928. switch (wr->opcode) {
  1929. case IB_WR_SEND_WITH_IMM:
  1930. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1931. hdr->immdt = ntohl(wr->ex.imm_data);
  1932. case IB_WR_SEND:
  1933. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1934. ocrdma_build_send(qp, hdr, wr);
  1935. break;
  1936. case IB_WR_SEND_WITH_INV:
  1937. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1938. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1939. hdr->lkey = wr->ex.invalidate_rkey;
  1940. status = ocrdma_build_send(qp, hdr, wr);
  1941. break;
  1942. case IB_WR_RDMA_WRITE_WITH_IMM:
  1943. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1944. hdr->immdt = ntohl(wr->ex.imm_data);
  1945. case IB_WR_RDMA_WRITE:
  1946. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1947. status = ocrdma_build_write(qp, hdr, wr);
  1948. break;
  1949. case IB_WR_RDMA_READ:
  1950. ocrdma_build_read(qp, hdr, wr);
  1951. break;
  1952. case IB_WR_LOCAL_INV:
  1953. hdr->cw |=
  1954. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1955. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1956. sizeof(struct ocrdma_sge)) /
  1957. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1958. hdr->lkey = wr->ex.invalidate_rkey;
  1959. break;
  1960. case IB_WR_FAST_REG_MR:
  1961. status = ocrdma_build_fr(qp, hdr, wr);
  1962. break;
  1963. default:
  1964. status = -EINVAL;
  1965. break;
  1966. }
  1967. if (status) {
  1968. *bad_wr = wr;
  1969. break;
  1970. }
  1971. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1972. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  1973. else
  1974. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  1975. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  1976. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  1977. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  1978. /* make sure wqe is written before adapter can access it */
  1979. wmb();
  1980. /* inform hw to start processing it */
  1981. ocrdma_ring_sq_db(qp);
  1982. /* update pointer, counter for next wr */
  1983. ocrdma_hwq_inc_head(&qp->sq);
  1984. wr = wr->next;
  1985. }
  1986. spin_unlock_irqrestore(&qp->q_lock, flags);
  1987. return status;
  1988. }
  1989. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  1990. {
  1991. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  1992. iowrite32(val, qp->rq_db);
  1993. }
  1994. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  1995. u16 tag)
  1996. {
  1997. u32 wqe_size = 0;
  1998. struct ocrdma_sge *sge;
  1999. if (wr->num_sge)
  2000. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  2001. else
  2002. wqe_size = sizeof(*sge) + sizeof(*rqe);
  2003. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  2004. OCRDMA_WQE_SIZE_SHIFT);
  2005. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  2006. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  2007. rqe->total_len = 0;
  2008. rqe->rsvd_tag = tag;
  2009. sge = (struct ocrdma_sge *)(rqe + 1);
  2010. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  2011. ocrdma_cpu_to_le32(rqe, wqe_size);
  2012. }
  2013. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  2014. struct ib_recv_wr **bad_wr)
  2015. {
  2016. int status = 0;
  2017. unsigned long flags;
  2018. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  2019. struct ocrdma_hdr_wqe *rqe;
  2020. spin_lock_irqsave(&qp->q_lock, flags);
  2021. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  2022. spin_unlock_irqrestore(&qp->q_lock, flags);
  2023. *bad_wr = wr;
  2024. return -EINVAL;
  2025. }
  2026. while (wr) {
  2027. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  2028. wr->num_sge > qp->rq.max_sges) {
  2029. *bad_wr = wr;
  2030. status = -ENOMEM;
  2031. break;
  2032. }
  2033. rqe = ocrdma_hwq_head(&qp->rq);
  2034. ocrdma_build_rqe(rqe, wr, 0);
  2035. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  2036. /* make sure rqe is written before adapter can access it */
  2037. wmb();
  2038. /* inform hw to start processing it */
  2039. ocrdma_ring_rq_db(qp);
  2040. /* update pointer, counter for next wr */
  2041. ocrdma_hwq_inc_head(&qp->rq);
  2042. wr = wr->next;
  2043. }
  2044. spin_unlock_irqrestore(&qp->q_lock, flags);
  2045. return status;
  2046. }
  2047. /* cqe for srq's rqe can potentially arrive out of order.
  2048. * index gives the entry in the shadow table where to store
  2049. * the wr_id. tag/index is returned in cqe to reference back
  2050. * for a given rqe.
  2051. */
  2052. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  2053. {
  2054. int row = 0;
  2055. int indx = 0;
  2056. for (row = 0; row < srq->bit_fields_len; row++) {
  2057. if (srq->idx_bit_fields[row]) {
  2058. indx = ffs(srq->idx_bit_fields[row]);
  2059. indx = (row * 32) + (indx - 1);
  2060. if (indx >= srq->rq.max_cnt)
  2061. BUG();
  2062. ocrdma_srq_toggle_bit(srq, indx);
  2063. break;
  2064. }
  2065. }
  2066. if (row == srq->bit_fields_len)
  2067. BUG();
  2068. return indx + 1; /* Use from index 1 */
  2069. }
  2070. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  2071. {
  2072. u32 val = srq->rq.dbid | (1 << 16);
  2073. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  2074. }
  2075. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  2076. struct ib_recv_wr **bad_wr)
  2077. {
  2078. int status = 0;
  2079. unsigned long flags;
  2080. struct ocrdma_srq *srq;
  2081. struct ocrdma_hdr_wqe *rqe;
  2082. u16 tag;
  2083. srq = get_ocrdma_srq(ibsrq);
  2084. spin_lock_irqsave(&srq->q_lock, flags);
  2085. while (wr) {
  2086. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  2087. wr->num_sge > srq->rq.max_sges) {
  2088. status = -ENOMEM;
  2089. *bad_wr = wr;
  2090. break;
  2091. }
  2092. tag = ocrdma_srq_get_idx(srq);
  2093. rqe = ocrdma_hwq_head(&srq->rq);
  2094. ocrdma_build_rqe(rqe, wr, tag);
  2095. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  2096. /* make sure rqe is written before adapter can perform DMA */
  2097. wmb();
  2098. /* inform hw to start processing it */
  2099. ocrdma_ring_srq_db(srq);
  2100. /* update pointer, counter for next wr */
  2101. ocrdma_hwq_inc_head(&srq->rq);
  2102. wr = wr->next;
  2103. }
  2104. spin_unlock_irqrestore(&srq->q_lock, flags);
  2105. return status;
  2106. }
  2107. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  2108. {
  2109. enum ib_wc_status ibwc_status;
  2110. switch (status) {
  2111. case OCRDMA_CQE_GENERAL_ERR:
  2112. ibwc_status = IB_WC_GENERAL_ERR;
  2113. break;
  2114. case OCRDMA_CQE_LOC_LEN_ERR:
  2115. ibwc_status = IB_WC_LOC_LEN_ERR;
  2116. break;
  2117. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2118. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2119. break;
  2120. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2121. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2122. break;
  2123. case OCRDMA_CQE_LOC_PROT_ERR:
  2124. ibwc_status = IB_WC_LOC_PROT_ERR;
  2125. break;
  2126. case OCRDMA_CQE_WR_FLUSH_ERR:
  2127. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2128. break;
  2129. case OCRDMA_CQE_MW_BIND_ERR:
  2130. ibwc_status = IB_WC_MW_BIND_ERR;
  2131. break;
  2132. case OCRDMA_CQE_BAD_RESP_ERR:
  2133. ibwc_status = IB_WC_BAD_RESP_ERR;
  2134. break;
  2135. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2136. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2137. break;
  2138. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2139. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2140. break;
  2141. case OCRDMA_CQE_REM_ACCESS_ERR:
  2142. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2143. break;
  2144. case OCRDMA_CQE_REM_OP_ERR:
  2145. ibwc_status = IB_WC_REM_OP_ERR;
  2146. break;
  2147. case OCRDMA_CQE_RETRY_EXC_ERR:
  2148. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2149. break;
  2150. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2151. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2152. break;
  2153. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2154. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2155. break;
  2156. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2157. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2158. break;
  2159. case OCRDMA_CQE_REM_ABORT_ERR:
  2160. ibwc_status = IB_WC_REM_ABORT_ERR;
  2161. break;
  2162. case OCRDMA_CQE_INV_EECN_ERR:
  2163. ibwc_status = IB_WC_INV_EECN_ERR;
  2164. break;
  2165. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2166. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2167. break;
  2168. case OCRDMA_CQE_FATAL_ERR:
  2169. ibwc_status = IB_WC_FATAL_ERR;
  2170. break;
  2171. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2172. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2173. break;
  2174. default:
  2175. ibwc_status = IB_WC_GENERAL_ERR;
  2176. break;
  2177. }
  2178. return ibwc_status;
  2179. }
  2180. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2181. u32 wqe_idx)
  2182. {
  2183. struct ocrdma_hdr_wqe *hdr;
  2184. struct ocrdma_sge *rw;
  2185. int opcode;
  2186. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2187. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2188. /* Undo the hdr->cw swap */
  2189. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2190. switch (opcode) {
  2191. case OCRDMA_WRITE:
  2192. ibwc->opcode = IB_WC_RDMA_WRITE;
  2193. break;
  2194. case OCRDMA_READ:
  2195. rw = (struct ocrdma_sge *)(hdr + 1);
  2196. ibwc->opcode = IB_WC_RDMA_READ;
  2197. ibwc->byte_len = rw->len;
  2198. break;
  2199. case OCRDMA_SEND:
  2200. ibwc->opcode = IB_WC_SEND;
  2201. break;
  2202. case OCRDMA_FR_MR:
  2203. ibwc->opcode = IB_WC_FAST_REG_MR;
  2204. break;
  2205. case OCRDMA_LKEY_INV:
  2206. ibwc->opcode = IB_WC_LOCAL_INV;
  2207. break;
  2208. default:
  2209. ibwc->status = IB_WC_GENERAL_ERR;
  2210. pr_err("%s() invalid opcode received = 0x%x\n",
  2211. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2212. break;
  2213. }
  2214. }
  2215. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2216. struct ocrdma_cqe *cqe)
  2217. {
  2218. if (is_cqe_for_sq(cqe)) {
  2219. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2220. cqe->flags_status_srcqpn) &
  2221. ~OCRDMA_CQE_STATUS_MASK);
  2222. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2223. cqe->flags_status_srcqpn) |
  2224. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2225. OCRDMA_CQE_STATUS_SHIFT));
  2226. } else {
  2227. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2228. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2229. cqe->flags_status_srcqpn) &
  2230. ~OCRDMA_CQE_UD_STATUS_MASK);
  2231. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2232. cqe->flags_status_srcqpn) |
  2233. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2234. OCRDMA_CQE_UD_STATUS_SHIFT));
  2235. } else {
  2236. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2237. cqe->flags_status_srcqpn) &
  2238. ~OCRDMA_CQE_STATUS_MASK);
  2239. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2240. cqe->flags_status_srcqpn) |
  2241. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2242. OCRDMA_CQE_STATUS_SHIFT));
  2243. }
  2244. }
  2245. }
  2246. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2247. struct ocrdma_qp *qp, int status)
  2248. {
  2249. bool expand = false;
  2250. ibwc->byte_len = 0;
  2251. ibwc->qp = &qp->ibqp;
  2252. ibwc->status = ocrdma_to_ibwc_err(status);
  2253. ocrdma_flush_qp(qp);
  2254. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2255. /* if wqe/rqe pending for which cqe needs to be returned,
  2256. * trigger inflating it.
  2257. */
  2258. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2259. expand = true;
  2260. ocrdma_set_cqe_status_flushed(qp, cqe);
  2261. }
  2262. return expand;
  2263. }
  2264. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2265. struct ocrdma_qp *qp, int status)
  2266. {
  2267. ibwc->opcode = IB_WC_RECV;
  2268. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2269. ocrdma_hwq_inc_tail(&qp->rq);
  2270. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2271. }
  2272. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2273. struct ocrdma_qp *qp, int status)
  2274. {
  2275. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2276. ocrdma_hwq_inc_tail(&qp->sq);
  2277. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2278. }
  2279. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2280. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2281. bool *polled, bool *stop)
  2282. {
  2283. bool expand;
  2284. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2285. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2286. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2287. if (status < OCRDMA_MAX_CQE_ERR)
  2288. atomic_inc(&dev->cqe_err_stats[status]);
  2289. /* when hw sq is empty, but rq is not empty, so we continue
  2290. * to keep the cqe in order to get the cq event again.
  2291. */
  2292. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2293. /* when cq for rq and sq is same, it is safe to return
  2294. * flush cqe for RQEs.
  2295. */
  2296. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2297. *polled = true;
  2298. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2299. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2300. } else {
  2301. /* stop processing further cqe as this cqe is used for
  2302. * triggering cq event on buddy cq of RQ.
  2303. * When QP is destroyed, this cqe will be removed
  2304. * from the cq's hardware q.
  2305. */
  2306. *polled = false;
  2307. *stop = true;
  2308. expand = false;
  2309. }
  2310. } else if (is_hw_sq_empty(qp)) {
  2311. /* Do nothing */
  2312. expand = false;
  2313. *polled = false;
  2314. *stop = false;
  2315. } else {
  2316. *polled = true;
  2317. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2318. }
  2319. return expand;
  2320. }
  2321. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2322. struct ocrdma_cqe *cqe,
  2323. struct ib_wc *ibwc, bool *polled)
  2324. {
  2325. bool expand = false;
  2326. int tail = qp->sq.tail;
  2327. u32 wqe_idx;
  2328. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2329. *polled = false; /* WC cannot be consumed yet */
  2330. } else {
  2331. ibwc->status = IB_WC_SUCCESS;
  2332. ibwc->wc_flags = 0;
  2333. ibwc->qp = &qp->ibqp;
  2334. ocrdma_update_wc(qp, ibwc, tail);
  2335. *polled = true;
  2336. }
  2337. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2338. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2339. if (tail != wqe_idx)
  2340. expand = true; /* Coalesced CQE can't be consumed yet */
  2341. ocrdma_hwq_inc_tail(&qp->sq);
  2342. return expand;
  2343. }
  2344. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2345. struct ib_wc *ibwc, bool *polled, bool *stop)
  2346. {
  2347. int status;
  2348. bool expand;
  2349. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2350. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2351. if (status == OCRDMA_CQE_SUCCESS)
  2352. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2353. else
  2354. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2355. return expand;
  2356. }
  2357. static int ocrdma_update_ud_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe)
  2358. {
  2359. int status;
  2360. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2361. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2362. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2363. OCRDMA_CQE_SRCQP_MASK;
  2364. ibwc->pkey_index = le32_to_cpu(cqe->ud.rxlen_pkey) &
  2365. OCRDMA_CQE_PKEY_MASK;
  2366. ibwc->wc_flags = IB_WC_GRH;
  2367. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2368. OCRDMA_CQE_UD_XFER_LEN_SHIFT);
  2369. return status;
  2370. }
  2371. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2372. struct ocrdma_cqe *cqe,
  2373. struct ocrdma_qp *qp)
  2374. {
  2375. unsigned long flags;
  2376. struct ocrdma_srq *srq;
  2377. u32 wqe_idx;
  2378. srq = get_ocrdma_srq(qp->ibqp.srq);
  2379. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2380. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2381. if (wqe_idx < 1)
  2382. BUG();
  2383. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2384. spin_lock_irqsave(&srq->q_lock, flags);
  2385. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2386. spin_unlock_irqrestore(&srq->q_lock, flags);
  2387. ocrdma_hwq_inc_tail(&srq->rq);
  2388. }
  2389. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2390. struct ib_wc *ibwc, bool *polled, bool *stop,
  2391. int status)
  2392. {
  2393. bool expand;
  2394. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2395. if (status < OCRDMA_MAX_CQE_ERR)
  2396. atomic_inc(&dev->cqe_err_stats[status]);
  2397. /* when hw_rq is empty, but wq is not empty, so continue
  2398. * to keep the cqe to get the cq event again.
  2399. */
  2400. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2401. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2402. *polled = true;
  2403. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2404. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2405. } else {
  2406. *polled = false;
  2407. *stop = true;
  2408. expand = false;
  2409. }
  2410. } else if (is_hw_rq_empty(qp)) {
  2411. /* Do nothing */
  2412. expand = false;
  2413. *polled = false;
  2414. *stop = false;
  2415. } else {
  2416. *polled = true;
  2417. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2418. }
  2419. return expand;
  2420. }
  2421. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2422. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2423. {
  2424. ibwc->opcode = IB_WC_RECV;
  2425. ibwc->qp = &qp->ibqp;
  2426. ibwc->status = IB_WC_SUCCESS;
  2427. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2428. ocrdma_update_ud_rcqe(ibwc, cqe);
  2429. else
  2430. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2431. if (is_cqe_imm(cqe)) {
  2432. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2433. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2434. } else if (is_cqe_wr_imm(cqe)) {
  2435. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2436. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2437. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2438. } else if (is_cqe_invalidated(cqe)) {
  2439. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2440. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2441. }
  2442. if (qp->ibqp.srq) {
  2443. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2444. } else {
  2445. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2446. ocrdma_hwq_inc_tail(&qp->rq);
  2447. }
  2448. }
  2449. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2450. struct ib_wc *ibwc, bool *polled, bool *stop)
  2451. {
  2452. int status;
  2453. bool expand = false;
  2454. ibwc->wc_flags = 0;
  2455. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2456. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2457. OCRDMA_CQE_UD_STATUS_MASK) >>
  2458. OCRDMA_CQE_UD_STATUS_SHIFT;
  2459. } else {
  2460. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2461. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2462. }
  2463. if (status == OCRDMA_CQE_SUCCESS) {
  2464. *polled = true;
  2465. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2466. } else {
  2467. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2468. status);
  2469. }
  2470. return expand;
  2471. }
  2472. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2473. u16 cur_getp)
  2474. {
  2475. if (cq->phase_change) {
  2476. if (cur_getp == 0)
  2477. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2478. } else {
  2479. /* clear valid bit */
  2480. cqe->flags_status_srcqpn = 0;
  2481. }
  2482. }
  2483. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2484. struct ib_wc *ibwc)
  2485. {
  2486. u16 qpn = 0;
  2487. int i = 0;
  2488. bool expand = false;
  2489. int polled_hw_cqes = 0;
  2490. struct ocrdma_qp *qp = NULL;
  2491. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2492. struct ocrdma_cqe *cqe;
  2493. u16 cur_getp; bool polled = false; bool stop = false;
  2494. cur_getp = cq->getp;
  2495. while (num_entries) {
  2496. cqe = cq->va + cur_getp;
  2497. /* check whether valid cqe or not */
  2498. if (!is_cqe_valid(cq, cqe))
  2499. break;
  2500. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2501. /* ignore discarded cqe */
  2502. if (qpn == 0)
  2503. goto skip_cqe;
  2504. qp = dev->qp_tbl[qpn];
  2505. BUG_ON(qp == NULL);
  2506. if (is_cqe_for_sq(cqe)) {
  2507. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2508. &stop);
  2509. } else {
  2510. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2511. &stop);
  2512. }
  2513. if (expand)
  2514. goto expand_cqe;
  2515. if (stop)
  2516. goto stop_cqe;
  2517. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2518. cqe->cmn.qpn = 0;
  2519. skip_cqe:
  2520. polled_hw_cqes += 1;
  2521. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2522. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2523. expand_cqe:
  2524. if (polled) {
  2525. num_entries -= 1;
  2526. i += 1;
  2527. ibwc = ibwc + 1;
  2528. polled = false;
  2529. }
  2530. }
  2531. stop_cqe:
  2532. cq->getp = cur_getp;
  2533. if (cq->deferred_arm) {
  2534. ocrdma_ring_cq_db(dev, cq->id, true, cq->deferred_sol,
  2535. polled_hw_cqes);
  2536. cq->deferred_arm = false;
  2537. cq->deferred_sol = false;
  2538. } else {
  2539. /* We need to pop the CQE. No need to arm */
  2540. ocrdma_ring_cq_db(dev, cq->id, false, cq->deferred_sol,
  2541. polled_hw_cqes);
  2542. cq->deferred_sol = false;
  2543. }
  2544. return i;
  2545. }
  2546. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2547. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2548. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2549. {
  2550. int err_cqes = 0;
  2551. while (num_entries) {
  2552. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2553. break;
  2554. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2555. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2556. ocrdma_hwq_inc_tail(&qp->sq);
  2557. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2558. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2559. ocrdma_hwq_inc_tail(&qp->rq);
  2560. } else {
  2561. return err_cqes;
  2562. }
  2563. ibwc->byte_len = 0;
  2564. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2565. ibwc = ibwc + 1;
  2566. err_cqes += 1;
  2567. num_entries -= 1;
  2568. }
  2569. return err_cqes;
  2570. }
  2571. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2572. {
  2573. int cqes_to_poll = num_entries;
  2574. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2575. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2576. int num_os_cqe = 0, err_cqes = 0;
  2577. struct ocrdma_qp *qp;
  2578. unsigned long flags;
  2579. /* poll cqes from adapter CQ */
  2580. spin_lock_irqsave(&cq->cq_lock, flags);
  2581. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2582. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2583. cqes_to_poll -= num_os_cqe;
  2584. if (cqes_to_poll) {
  2585. wc = wc + num_os_cqe;
  2586. /* adapter returns single error cqe when qp moves to
  2587. * error state. So insert error cqes with wc_status as
  2588. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2589. * respectively which uses this CQ.
  2590. */
  2591. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2592. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2593. if (cqes_to_poll == 0)
  2594. break;
  2595. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2596. cqes_to_poll -= err_cqes;
  2597. num_os_cqe += err_cqes;
  2598. wc = wc + err_cqes;
  2599. }
  2600. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2601. }
  2602. return num_os_cqe;
  2603. }
  2604. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2605. {
  2606. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2607. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2608. u16 cq_id;
  2609. unsigned long flags;
  2610. bool arm_needed = false, sol_needed = false;
  2611. cq_id = cq->id;
  2612. spin_lock_irqsave(&cq->cq_lock, flags);
  2613. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2614. arm_needed = true;
  2615. if (cq_flags & IB_CQ_SOLICITED)
  2616. sol_needed = true;
  2617. if (cq->first_arm) {
  2618. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2619. cq->first_arm = false;
  2620. }
  2621. cq->deferred_arm = true;
  2622. cq->deferred_sol = sol_needed;
  2623. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2624. return 0;
  2625. }
  2626. struct ib_mr *ocrdma_alloc_frmr(struct ib_pd *ibpd, int max_page_list_len)
  2627. {
  2628. int status;
  2629. struct ocrdma_mr *mr;
  2630. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2631. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2632. if (max_page_list_len > dev->attr.max_pages_per_frmr)
  2633. return ERR_PTR(-EINVAL);
  2634. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2635. if (!mr)
  2636. return ERR_PTR(-ENOMEM);
  2637. status = ocrdma_get_pbl_info(dev, mr, max_page_list_len);
  2638. if (status)
  2639. goto pbl_err;
  2640. mr->hwmr.fr_mr = 1;
  2641. mr->hwmr.remote_rd = 0;
  2642. mr->hwmr.remote_wr = 0;
  2643. mr->hwmr.local_rd = 0;
  2644. mr->hwmr.local_wr = 0;
  2645. mr->hwmr.mw_bind = 0;
  2646. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2647. if (status)
  2648. goto pbl_err;
  2649. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2650. if (status)
  2651. goto mbx_err;
  2652. mr->ibmr.rkey = mr->hwmr.lkey;
  2653. mr->ibmr.lkey = mr->hwmr.lkey;
  2654. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2655. (unsigned long) mr;
  2656. return &mr->ibmr;
  2657. mbx_err:
  2658. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2659. pbl_err:
  2660. kfree(mr);
  2661. return ERR_PTR(-ENOMEM);
  2662. }
  2663. struct ib_fast_reg_page_list *ocrdma_alloc_frmr_page_list(struct ib_device
  2664. *ibdev,
  2665. int page_list_len)
  2666. {
  2667. struct ib_fast_reg_page_list *frmr_list;
  2668. int size;
  2669. size = sizeof(*frmr_list) + (page_list_len * sizeof(u64));
  2670. frmr_list = kzalloc(size, GFP_KERNEL);
  2671. if (!frmr_list)
  2672. return ERR_PTR(-ENOMEM);
  2673. frmr_list->page_list = (u64 *)(frmr_list + 1);
  2674. return frmr_list;
  2675. }
  2676. void ocrdma_free_frmr_page_list(struct ib_fast_reg_page_list *page_list)
  2677. {
  2678. kfree(page_list);
  2679. }
  2680. #define MAX_KERNEL_PBE_SIZE 65536
  2681. static inline int count_kernel_pbes(struct ib_phys_buf *buf_list,
  2682. int buf_cnt, u32 *pbe_size)
  2683. {
  2684. u64 total_size = 0;
  2685. u64 buf_size = 0;
  2686. int i;
  2687. *pbe_size = roundup(buf_list[0].size, PAGE_SIZE);
  2688. *pbe_size = roundup_pow_of_two(*pbe_size);
  2689. /* find the smallest PBE size that we can have */
  2690. for (i = 0; i < buf_cnt; i++) {
  2691. /* first addr may not be page aligned, so ignore checking */
  2692. if ((i != 0) && ((buf_list[i].addr & ~PAGE_MASK) ||
  2693. (buf_list[i].size & ~PAGE_MASK))) {
  2694. return 0;
  2695. }
  2696. /* if configured PBE size is greater then the chosen one,
  2697. * reduce the PBE size.
  2698. */
  2699. buf_size = roundup(buf_list[i].size, PAGE_SIZE);
  2700. /* pbe_size has to be even multiple of 4K 1,2,4,8...*/
  2701. buf_size = roundup_pow_of_two(buf_size);
  2702. if (*pbe_size > buf_size)
  2703. *pbe_size = buf_size;
  2704. total_size += buf_size;
  2705. }
  2706. *pbe_size = *pbe_size > MAX_KERNEL_PBE_SIZE ?
  2707. (MAX_KERNEL_PBE_SIZE) : (*pbe_size);
  2708. /* num_pbes = total_size / (*pbe_size); this is implemented below. */
  2709. return total_size >> ilog2(*pbe_size);
  2710. }
  2711. static void build_kernel_pbes(struct ib_phys_buf *buf_list, int ib_buf_cnt,
  2712. u32 pbe_size, struct ocrdma_pbl *pbl_tbl,
  2713. struct ocrdma_hw_mr *hwmr)
  2714. {
  2715. int i;
  2716. int idx;
  2717. int pbes_per_buf = 0;
  2718. u64 buf_addr = 0;
  2719. int num_pbes;
  2720. struct ocrdma_pbe *pbe;
  2721. int total_num_pbes = 0;
  2722. if (!hwmr->num_pbes)
  2723. return;
  2724. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2725. num_pbes = 0;
  2726. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  2727. for (i = 0; i < ib_buf_cnt; i++) {
  2728. buf_addr = buf_list[i].addr;
  2729. pbes_per_buf =
  2730. roundup_pow_of_two(roundup(buf_list[i].size, PAGE_SIZE)) /
  2731. pbe_size;
  2732. hwmr->len += buf_list[i].size;
  2733. /* number of pbes can be more for one OS buf, when
  2734. * buffers are of different sizes.
  2735. * split the ib_buf to one or more pbes.
  2736. */
  2737. for (idx = 0; idx < pbes_per_buf; idx++) {
  2738. /* we program always page aligned addresses,
  2739. * first unaligned address is taken care by fbo.
  2740. */
  2741. if (i == 0) {
  2742. /* for non zero fbo, assign the
  2743. * start of the page.
  2744. */
  2745. pbe->pa_lo =
  2746. cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  2747. pbe->pa_hi =
  2748. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2749. } else {
  2750. pbe->pa_lo =
  2751. cpu_to_le32((u32) (buf_addr & 0xffffffff));
  2752. pbe->pa_hi =
  2753. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2754. }
  2755. buf_addr += pbe_size;
  2756. num_pbes += 1;
  2757. total_num_pbes += 1;
  2758. pbe++;
  2759. if (total_num_pbes == hwmr->num_pbes)
  2760. goto mr_tbl_done;
  2761. /* if the pbl is full storing the pbes,
  2762. * move to next pbl.
  2763. */
  2764. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  2765. pbl_tbl++;
  2766. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2767. num_pbes = 0;
  2768. }
  2769. }
  2770. }
  2771. mr_tbl_done:
  2772. return;
  2773. }
  2774. struct ib_mr *ocrdma_reg_kernel_mr(struct ib_pd *ibpd,
  2775. struct ib_phys_buf *buf_list,
  2776. int buf_cnt, int acc, u64 *iova_start)
  2777. {
  2778. int status = -ENOMEM;
  2779. struct ocrdma_mr *mr;
  2780. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2781. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2782. u32 num_pbes;
  2783. u32 pbe_size = 0;
  2784. if ((acc & IB_ACCESS_REMOTE_WRITE) && !(acc & IB_ACCESS_LOCAL_WRITE))
  2785. return ERR_PTR(-EINVAL);
  2786. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2787. if (!mr)
  2788. return ERR_PTR(status);
  2789. num_pbes = count_kernel_pbes(buf_list, buf_cnt, &pbe_size);
  2790. if (num_pbes == 0) {
  2791. status = -EINVAL;
  2792. goto pbl_err;
  2793. }
  2794. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  2795. if (status)
  2796. goto pbl_err;
  2797. mr->hwmr.pbe_size = pbe_size;
  2798. mr->hwmr.fbo = *iova_start - (buf_list[0].addr & PAGE_MASK);
  2799. mr->hwmr.va = *iova_start;
  2800. mr->hwmr.local_rd = 1;
  2801. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  2802. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  2803. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  2804. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  2805. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  2806. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2807. if (status)
  2808. goto pbl_err;
  2809. build_kernel_pbes(buf_list, buf_cnt, pbe_size, mr->hwmr.pbl_table,
  2810. &mr->hwmr);
  2811. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  2812. if (status)
  2813. goto mbx_err;
  2814. mr->ibmr.lkey = mr->hwmr.lkey;
  2815. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  2816. mr->ibmr.rkey = mr->hwmr.lkey;
  2817. return &mr->ibmr;
  2818. mbx_err:
  2819. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2820. pbl_err:
  2821. kfree(mr);
  2822. return ERR_PTR(status);
  2823. }