odp.c 23 KB

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  1. /*
  2. * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <rdma/ib_umem.h>
  33. #include <rdma/ib_umem_odp.h>
  34. #include "mlx5_ib.h"
  35. #define MAX_PREFETCH_LEN (4*1024*1024U)
  36. /* Timeout in ms to wait for an active mmu notifier to complete when handling
  37. * a pagefault. */
  38. #define MMU_NOTIFIER_TIMEOUT 1000
  39. struct workqueue_struct *mlx5_ib_page_fault_wq;
  40. void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
  41. unsigned long end)
  42. {
  43. struct mlx5_ib_mr *mr;
  44. const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT / sizeof(u64)) - 1;
  45. u64 idx = 0, blk_start_idx = 0;
  46. int in_block = 0;
  47. u64 addr;
  48. if (!umem || !umem->odp_data) {
  49. pr_err("invalidation called on NULL umem or non-ODP umem\n");
  50. return;
  51. }
  52. mr = umem->odp_data->private;
  53. if (!mr || !mr->ibmr.pd)
  54. return;
  55. start = max_t(u64, ib_umem_start(umem), start);
  56. end = min_t(u64, ib_umem_end(umem), end);
  57. /*
  58. * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
  59. * while we are doing the invalidation, no page fault will attempt to
  60. * overwrite the same MTTs. Concurent invalidations might race us,
  61. * but they will write 0s as well, so no difference in the end result.
  62. */
  63. for (addr = start; addr < end; addr += (u64)umem->page_size) {
  64. idx = (addr - ib_umem_start(umem)) / PAGE_SIZE;
  65. /*
  66. * Strive to write the MTTs in chunks, but avoid overwriting
  67. * non-existing MTTs. The huristic here can be improved to
  68. * estimate the cost of another UMR vs. the cost of bigger
  69. * UMR.
  70. */
  71. if (umem->odp_data->dma_list[idx] &
  72. (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
  73. if (!in_block) {
  74. blk_start_idx = idx;
  75. in_block = 1;
  76. }
  77. } else {
  78. u64 umr_offset = idx & umr_block_mask;
  79. if (in_block && umr_offset == 0) {
  80. mlx5_ib_update_mtt(mr, blk_start_idx,
  81. idx - blk_start_idx, 1);
  82. in_block = 0;
  83. }
  84. }
  85. }
  86. if (in_block)
  87. mlx5_ib_update_mtt(mr, blk_start_idx, idx - blk_start_idx + 1,
  88. 1);
  89. /*
  90. * We are now sure that the device will not access the
  91. * memory. We can safely unmap it, and mark it as dirty if
  92. * needed.
  93. */
  94. ib_umem_odp_unmap_dma_pages(umem, start, end);
  95. }
  96. #define COPY_ODP_BIT_MLX_TO_IB(reg, ib_caps, field_name, bit_name) do { \
  97. if (be32_to_cpu(reg.field_name) & MLX5_ODP_SUPPORT_##bit_name) \
  98. ib_caps->field_name |= IB_ODP_SUPPORT_##bit_name; \
  99. } while (0)
  100. int mlx5_ib_internal_query_odp_caps(struct mlx5_ib_dev *dev)
  101. {
  102. int err;
  103. struct mlx5_odp_caps hw_caps;
  104. struct ib_odp_caps *caps = &dev->odp_caps;
  105. memset(caps, 0, sizeof(*caps));
  106. if (!(dev->mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_ON_DMND_PG))
  107. return 0;
  108. err = mlx5_query_odp_caps(dev->mdev, &hw_caps);
  109. if (err)
  110. goto out;
  111. caps->general_caps = IB_ODP_SUPPORT;
  112. COPY_ODP_BIT_MLX_TO_IB(hw_caps, caps, per_transport_caps.ud_odp_caps,
  113. SEND);
  114. COPY_ODP_BIT_MLX_TO_IB(hw_caps, caps, per_transport_caps.rc_odp_caps,
  115. SEND);
  116. COPY_ODP_BIT_MLX_TO_IB(hw_caps, caps, per_transport_caps.rc_odp_caps,
  117. RECV);
  118. COPY_ODP_BIT_MLX_TO_IB(hw_caps, caps, per_transport_caps.rc_odp_caps,
  119. WRITE);
  120. COPY_ODP_BIT_MLX_TO_IB(hw_caps, caps, per_transport_caps.rc_odp_caps,
  121. READ);
  122. out:
  123. return err;
  124. }
  125. static struct mlx5_ib_mr *mlx5_ib_odp_find_mr_lkey(struct mlx5_ib_dev *dev,
  126. u32 key)
  127. {
  128. u32 base_key = mlx5_base_mkey(key);
  129. struct mlx5_core_mr *mmr = __mlx5_mr_lookup(dev->mdev, base_key);
  130. struct mlx5_ib_mr *mr = container_of(mmr, struct mlx5_ib_mr, mmr);
  131. if (!mmr || mmr->key != key || !mr->live)
  132. return NULL;
  133. return container_of(mmr, struct mlx5_ib_mr, mmr);
  134. }
  135. static void mlx5_ib_page_fault_resume(struct mlx5_ib_qp *qp,
  136. struct mlx5_ib_pfault *pfault,
  137. int error) {
  138. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  139. int ret = mlx5_core_page_fault_resume(dev->mdev, qp->mqp.qpn,
  140. pfault->mpfault.flags,
  141. error);
  142. if (ret)
  143. pr_err("Failed to resolve the page fault on QP 0x%x\n",
  144. qp->mqp.qpn);
  145. }
  146. /*
  147. * Handle a single data segment in a page-fault WQE.
  148. *
  149. * Returns number of pages retrieved on success. The caller will continue to
  150. * the next data segment.
  151. * Can return the following error codes:
  152. * -EAGAIN to designate a temporary error. The caller will abort handling the
  153. * page fault and resolve it.
  154. * -EFAULT when there's an error mapping the requested pages. The caller will
  155. * abort the page fault handling and possibly move the QP to an error state.
  156. * On other errors the QP should also be closed with an error.
  157. */
  158. static int pagefault_single_data_segment(struct mlx5_ib_qp *qp,
  159. struct mlx5_ib_pfault *pfault,
  160. u32 key, u64 io_virt, size_t bcnt,
  161. u32 *bytes_mapped)
  162. {
  163. struct mlx5_ib_dev *mib_dev = to_mdev(qp->ibqp.pd->device);
  164. int srcu_key;
  165. unsigned int current_seq;
  166. u64 start_idx;
  167. int npages = 0, ret = 0;
  168. struct mlx5_ib_mr *mr;
  169. u64 access_mask = ODP_READ_ALLOWED_BIT;
  170. srcu_key = srcu_read_lock(&mib_dev->mr_srcu);
  171. mr = mlx5_ib_odp_find_mr_lkey(mib_dev, key);
  172. /*
  173. * If we didn't find the MR, it means the MR was closed while we were
  174. * handling the ODP event. In this case we return -EFAULT so that the
  175. * QP will be closed.
  176. */
  177. if (!mr || !mr->ibmr.pd) {
  178. pr_err("Failed to find relevant mr for lkey=0x%06x, probably the MR was destroyed\n",
  179. key);
  180. ret = -EFAULT;
  181. goto srcu_unlock;
  182. }
  183. if (!mr->umem->odp_data) {
  184. pr_debug("skipping non ODP MR (lkey=0x%06x) in page fault handler.\n",
  185. key);
  186. if (bytes_mapped)
  187. *bytes_mapped +=
  188. (bcnt - pfault->mpfault.bytes_committed);
  189. goto srcu_unlock;
  190. }
  191. if (mr->ibmr.pd != qp->ibqp.pd) {
  192. pr_err("Page-fault with different PDs for QP and MR.\n");
  193. ret = -EFAULT;
  194. goto srcu_unlock;
  195. }
  196. current_seq = ACCESS_ONCE(mr->umem->odp_data->notifiers_seq);
  197. /*
  198. * Ensure the sequence number is valid for some time before we call
  199. * gup.
  200. */
  201. smp_rmb();
  202. /*
  203. * Avoid branches - this code will perform correctly
  204. * in all iterations (in iteration 2 and above,
  205. * bytes_committed == 0).
  206. */
  207. io_virt += pfault->mpfault.bytes_committed;
  208. bcnt -= pfault->mpfault.bytes_committed;
  209. start_idx = (io_virt - (mr->mmr.iova & PAGE_MASK)) >> PAGE_SHIFT;
  210. if (mr->umem->writable)
  211. access_mask |= ODP_WRITE_ALLOWED_BIT;
  212. npages = ib_umem_odp_map_dma_pages(mr->umem, io_virt, bcnt,
  213. access_mask, current_seq);
  214. if (npages < 0) {
  215. ret = npages;
  216. goto srcu_unlock;
  217. }
  218. if (npages > 0) {
  219. mutex_lock(&mr->umem->odp_data->umem_mutex);
  220. if (!ib_umem_mmu_notifier_retry(mr->umem, current_seq)) {
  221. /*
  222. * No need to check whether the MTTs really belong to
  223. * this MR, since ib_umem_odp_map_dma_pages already
  224. * checks this.
  225. */
  226. ret = mlx5_ib_update_mtt(mr, start_idx, npages, 0);
  227. } else {
  228. ret = -EAGAIN;
  229. }
  230. mutex_unlock(&mr->umem->odp_data->umem_mutex);
  231. if (ret < 0) {
  232. if (ret != -EAGAIN)
  233. pr_err("Failed to update mkey page tables\n");
  234. goto srcu_unlock;
  235. }
  236. if (bytes_mapped) {
  237. u32 new_mappings = npages * PAGE_SIZE -
  238. (io_virt - round_down(io_virt, PAGE_SIZE));
  239. *bytes_mapped += min_t(u32, new_mappings, bcnt);
  240. }
  241. }
  242. srcu_unlock:
  243. if (ret == -EAGAIN) {
  244. if (!mr->umem->odp_data->dying) {
  245. struct ib_umem_odp *odp_data = mr->umem->odp_data;
  246. unsigned long timeout =
  247. msecs_to_jiffies(MMU_NOTIFIER_TIMEOUT);
  248. if (!wait_for_completion_timeout(
  249. &odp_data->notifier_completion,
  250. timeout)) {
  251. pr_warn("timeout waiting for mmu notifier completion\n");
  252. }
  253. } else {
  254. /* The MR is being killed, kill the QP as well. */
  255. ret = -EFAULT;
  256. }
  257. }
  258. srcu_read_unlock(&mib_dev->mr_srcu, srcu_key);
  259. pfault->mpfault.bytes_committed = 0;
  260. return ret ? ret : npages;
  261. }
  262. /**
  263. * Parse a series of data segments for page fault handling.
  264. *
  265. * @qp the QP on which the fault occurred.
  266. * @pfault contains page fault information.
  267. * @wqe points at the first data segment in the WQE.
  268. * @wqe_end points after the end of the WQE.
  269. * @bytes_mapped receives the number of bytes that the function was able to
  270. * map. This allows the caller to decide intelligently whether
  271. * enough memory was mapped to resolve the page fault
  272. * successfully (e.g. enough for the next MTU, or the entire
  273. * WQE).
  274. * @total_wqe_bytes receives the total data size of this WQE in bytes (minus
  275. * the committed bytes).
  276. *
  277. * Returns the number of pages loaded if positive, zero for an empty WQE, or a
  278. * negative error code.
  279. */
  280. static int pagefault_data_segments(struct mlx5_ib_qp *qp,
  281. struct mlx5_ib_pfault *pfault, void *wqe,
  282. void *wqe_end, u32 *bytes_mapped,
  283. u32 *total_wqe_bytes, int receive_queue)
  284. {
  285. int ret = 0, npages = 0;
  286. u64 io_virt;
  287. u32 key;
  288. u32 byte_count;
  289. size_t bcnt;
  290. int inline_segment;
  291. /* Skip SRQ next-WQE segment. */
  292. if (receive_queue && qp->ibqp.srq)
  293. wqe += sizeof(struct mlx5_wqe_srq_next_seg);
  294. if (bytes_mapped)
  295. *bytes_mapped = 0;
  296. if (total_wqe_bytes)
  297. *total_wqe_bytes = 0;
  298. while (wqe < wqe_end) {
  299. struct mlx5_wqe_data_seg *dseg = wqe;
  300. io_virt = be64_to_cpu(dseg->addr);
  301. key = be32_to_cpu(dseg->lkey);
  302. byte_count = be32_to_cpu(dseg->byte_count);
  303. inline_segment = !!(byte_count & MLX5_INLINE_SEG);
  304. bcnt = byte_count & ~MLX5_INLINE_SEG;
  305. if (inline_segment) {
  306. bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
  307. wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
  308. 16);
  309. } else {
  310. wqe += sizeof(*dseg);
  311. }
  312. /* receive WQE end of sg list. */
  313. if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
  314. io_virt == 0)
  315. break;
  316. if (!inline_segment && total_wqe_bytes) {
  317. *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
  318. pfault->mpfault.bytes_committed);
  319. }
  320. /* A zero length data segment designates a length of 2GB. */
  321. if (bcnt == 0)
  322. bcnt = 1U << 31;
  323. if (inline_segment || bcnt <= pfault->mpfault.bytes_committed) {
  324. pfault->mpfault.bytes_committed -=
  325. min_t(size_t, bcnt,
  326. pfault->mpfault.bytes_committed);
  327. continue;
  328. }
  329. ret = pagefault_single_data_segment(qp, pfault, key, io_virt,
  330. bcnt, bytes_mapped);
  331. if (ret < 0)
  332. break;
  333. npages += ret;
  334. }
  335. return ret < 0 ? ret : npages;
  336. }
  337. /*
  338. * Parse initiator WQE. Advances the wqe pointer to point at the
  339. * scatter-gather list, and set wqe_end to the end of the WQE.
  340. */
  341. static int mlx5_ib_mr_initiator_pfault_handler(
  342. struct mlx5_ib_qp *qp, struct mlx5_ib_pfault *pfault,
  343. void **wqe, void **wqe_end, int wqe_length)
  344. {
  345. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  346. struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
  347. u16 wqe_index = pfault->mpfault.wqe.wqe_index;
  348. unsigned ds, opcode;
  349. #if defined(DEBUG)
  350. u32 ctrl_wqe_index, ctrl_qpn;
  351. #endif
  352. ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
  353. if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
  354. mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
  355. ds, wqe_length);
  356. return -EFAULT;
  357. }
  358. if (ds == 0) {
  359. mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
  360. wqe_index, qp->mqp.qpn);
  361. return -EFAULT;
  362. }
  363. #if defined(DEBUG)
  364. ctrl_wqe_index = (be32_to_cpu(ctrl->opmod_idx_opcode) &
  365. MLX5_WQE_CTRL_WQE_INDEX_MASK) >>
  366. MLX5_WQE_CTRL_WQE_INDEX_SHIFT;
  367. if (wqe_index != ctrl_wqe_index) {
  368. mlx5_ib_err(dev, "Got WQE with invalid wqe_index. wqe_index=0x%x, qpn=0x%x ctrl->wqe_index=0x%x\n",
  369. wqe_index, qp->mqp.qpn,
  370. ctrl_wqe_index);
  371. return -EFAULT;
  372. }
  373. ctrl_qpn = (be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_QPN_MASK) >>
  374. MLX5_WQE_CTRL_QPN_SHIFT;
  375. if (qp->mqp.qpn != ctrl_qpn) {
  376. mlx5_ib_err(dev, "Got WQE with incorrect QP number. wqe_index=0x%x, qpn=0x%x ctrl->qpn=0x%x\n",
  377. wqe_index, qp->mqp.qpn,
  378. ctrl_qpn);
  379. return -EFAULT;
  380. }
  381. #endif /* DEBUG */
  382. *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
  383. *wqe += sizeof(*ctrl);
  384. opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
  385. MLX5_WQE_CTRL_OPCODE_MASK;
  386. switch (qp->ibqp.qp_type) {
  387. case IB_QPT_RC:
  388. switch (opcode) {
  389. case MLX5_OPCODE_SEND:
  390. case MLX5_OPCODE_SEND_IMM:
  391. case MLX5_OPCODE_SEND_INVAL:
  392. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  393. IB_ODP_SUPPORT_SEND))
  394. goto invalid_transport_or_opcode;
  395. break;
  396. case MLX5_OPCODE_RDMA_WRITE:
  397. case MLX5_OPCODE_RDMA_WRITE_IMM:
  398. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  399. IB_ODP_SUPPORT_WRITE))
  400. goto invalid_transport_or_opcode;
  401. *wqe += sizeof(struct mlx5_wqe_raddr_seg);
  402. break;
  403. case MLX5_OPCODE_RDMA_READ:
  404. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  405. IB_ODP_SUPPORT_READ))
  406. goto invalid_transport_or_opcode;
  407. *wqe += sizeof(struct mlx5_wqe_raddr_seg);
  408. break;
  409. default:
  410. goto invalid_transport_or_opcode;
  411. }
  412. break;
  413. case IB_QPT_UD:
  414. switch (opcode) {
  415. case MLX5_OPCODE_SEND:
  416. case MLX5_OPCODE_SEND_IMM:
  417. if (!(dev->odp_caps.per_transport_caps.ud_odp_caps &
  418. IB_ODP_SUPPORT_SEND))
  419. goto invalid_transport_or_opcode;
  420. *wqe += sizeof(struct mlx5_wqe_datagram_seg);
  421. break;
  422. default:
  423. goto invalid_transport_or_opcode;
  424. }
  425. break;
  426. default:
  427. invalid_transport_or_opcode:
  428. mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode or transport. transport: 0x%x opcode: 0x%x.\n",
  429. qp->ibqp.qp_type, opcode);
  430. return -EFAULT;
  431. }
  432. return 0;
  433. }
  434. /*
  435. * Parse responder WQE. Advances the wqe pointer to point at the
  436. * scatter-gather list, and set wqe_end to the end of the WQE.
  437. */
  438. static int mlx5_ib_mr_responder_pfault_handler(
  439. struct mlx5_ib_qp *qp, struct mlx5_ib_pfault *pfault,
  440. void **wqe, void **wqe_end, int wqe_length)
  441. {
  442. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  443. struct mlx5_ib_wq *wq = &qp->rq;
  444. int wqe_size = 1 << wq->wqe_shift;
  445. if (qp->ibqp.srq) {
  446. mlx5_ib_err(dev, "ODP fault on SRQ is not supported\n");
  447. return -EFAULT;
  448. }
  449. if (qp->wq_sig) {
  450. mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
  451. return -EFAULT;
  452. }
  453. if (wqe_size > wqe_length) {
  454. mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
  455. return -EFAULT;
  456. }
  457. switch (qp->ibqp.qp_type) {
  458. case IB_QPT_RC:
  459. if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
  460. IB_ODP_SUPPORT_RECV))
  461. goto invalid_transport_or_opcode;
  462. break;
  463. default:
  464. invalid_transport_or_opcode:
  465. mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport. transport: 0x%x\n",
  466. qp->ibqp.qp_type);
  467. return -EFAULT;
  468. }
  469. *wqe_end = *wqe + wqe_size;
  470. return 0;
  471. }
  472. static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_qp *qp,
  473. struct mlx5_ib_pfault *pfault)
  474. {
  475. struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.pd->device);
  476. int ret;
  477. void *wqe, *wqe_end;
  478. u32 bytes_mapped, total_wqe_bytes;
  479. char *buffer = NULL;
  480. int resume_with_error = 0;
  481. u16 wqe_index = pfault->mpfault.wqe.wqe_index;
  482. int requestor = pfault->mpfault.flags & MLX5_PFAULT_REQUESTOR;
  483. buffer = (char *)__get_free_page(GFP_KERNEL);
  484. if (!buffer) {
  485. mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
  486. resume_with_error = 1;
  487. goto resolve_page_fault;
  488. }
  489. ret = mlx5_ib_read_user_wqe(qp, requestor, wqe_index, buffer,
  490. PAGE_SIZE);
  491. if (ret < 0) {
  492. mlx5_ib_err(dev, "Failed reading a WQE following page fault, error=%x, wqe_index=%x, qpn=%x\n",
  493. -ret, wqe_index, qp->mqp.qpn);
  494. resume_with_error = 1;
  495. goto resolve_page_fault;
  496. }
  497. wqe = buffer;
  498. if (requestor)
  499. ret = mlx5_ib_mr_initiator_pfault_handler(qp, pfault, &wqe,
  500. &wqe_end, ret);
  501. else
  502. ret = mlx5_ib_mr_responder_pfault_handler(qp, pfault, &wqe,
  503. &wqe_end, ret);
  504. if (ret < 0) {
  505. resume_with_error = 1;
  506. goto resolve_page_fault;
  507. }
  508. if (wqe >= wqe_end) {
  509. mlx5_ib_err(dev, "ODP fault on invalid WQE.\n");
  510. resume_with_error = 1;
  511. goto resolve_page_fault;
  512. }
  513. ret = pagefault_data_segments(qp, pfault, wqe, wqe_end, &bytes_mapped,
  514. &total_wqe_bytes, !requestor);
  515. if (ret == -EAGAIN) {
  516. goto resolve_page_fault;
  517. } else if (ret < 0 || total_wqe_bytes > bytes_mapped) {
  518. mlx5_ib_err(dev, "Error getting user pages for page fault. Error: 0x%x\n",
  519. -ret);
  520. resume_with_error = 1;
  521. goto resolve_page_fault;
  522. }
  523. resolve_page_fault:
  524. mlx5_ib_page_fault_resume(qp, pfault, resume_with_error);
  525. mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, flags: 0x%x\n",
  526. qp->mqp.qpn, resume_with_error, pfault->mpfault.flags);
  527. free_page((unsigned long)buffer);
  528. }
  529. static int pages_in_range(u64 address, u32 length)
  530. {
  531. return (ALIGN(address + length, PAGE_SIZE) -
  532. (address & PAGE_MASK)) >> PAGE_SHIFT;
  533. }
  534. static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_qp *qp,
  535. struct mlx5_ib_pfault *pfault)
  536. {
  537. struct mlx5_pagefault *mpfault = &pfault->mpfault;
  538. u64 address;
  539. u32 length;
  540. u32 prefetch_len = mpfault->bytes_committed;
  541. int prefetch_activated = 0;
  542. u32 rkey = mpfault->rdma.r_key;
  543. int ret;
  544. /* The RDMA responder handler handles the page fault in two parts.
  545. * First it brings the necessary pages for the current packet
  546. * (and uses the pfault context), and then (after resuming the QP)
  547. * prefetches more pages. The second operation cannot use the pfault
  548. * context and therefore uses the dummy_pfault context allocated on
  549. * the stack */
  550. struct mlx5_ib_pfault dummy_pfault = {};
  551. dummy_pfault.mpfault.bytes_committed = 0;
  552. mpfault->rdma.rdma_va += mpfault->bytes_committed;
  553. mpfault->rdma.rdma_op_len -= min(mpfault->bytes_committed,
  554. mpfault->rdma.rdma_op_len);
  555. mpfault->bytes_committed = 0;
  556. address = mpfault->rdma.rdma_va;
  557. length = mpfault->rdma.rdma_op_len;
  558. /* For some operations, the hardware cannot tell the exact message
  559. * length, and in those cases it reports zero. Use prefetch
  560. * logic. */
  561. if (length == 0) {
  562. prefetch_activated = 1;
  563. length = mpfault->rdma.packet_size;
  564. prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
  565. }
  566. ret = pagefault_single_data_segment(qp, pfault, rkey, address, length,
  567. NULL);
  568. if (ret == -EAGAIN) {
  569. /* We're racing with an invalidation, don't prefetch */
  570. prefetch_activated = 0;
  571. } else if (ret < 0 || pages_in_range(address, length) > ret) {
  572. mlx5_ib_page_fault_resume(qp, pfault, 1);
  573. return;
  574. }
  575. mlx5_ib_page_fault_resume(qp, pfault, 0);
  576. /* At this point, there might be a new pagefault already arriving in
  577. * the eq, switch to the dummy pagefault for the rest of the
  578. * processing. We're still OK with the objects being alive as the
  579. * work-queue is being fenced. */
  580. if (prefetch_activated) {
  581. ret = pagefault_single_data_segment(qp, &dummy_pfault, rkey,
  582. address,
  583. prefetch_len,
  584. NULL);
  585. if (ret < 0) {
  586. pr_warn("Prefetch failed (ret = %d, prefetch_activated = %d) for QPN %d, address: 0x%.16llx, length = 0x%.16x\n",
  587. ret, prefetch_activated,
  588. qp->ibqp.qp_num, address, prefetch_len);
  589. }
  590. }
  591. }
  592. void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
  593. struct mlx5_ib_pfault *pfault)
  594. {
  595. u8 event_subtype = pfault->mpfault.event_subtype;
  596. switch (event_subtype) {
  597. case MLX5_PFAULT_SUBTYPE_WQE:
  598. mlx5_ib_mr_wqe_pfault_handler(qp, pfault);
  599. break;
  600. case MLX5_PFAULT_SUBTYPE_RDMA:
  601. mlx5_ib_mr_rdma_pfault_handler(qp, pfault);
  602. break;
  603. default:
  604. pr_warn("Invalid page fault event subtype: 0x%x\n",
  605. event_subtype);
  606. mlx5_ib_page_fault_resume(qp, pfault, 1);
  607. break;
  608. }
  609. }
  610. static void mlx5_ib_qp_pfault_action(struct work_struct *work)
  611. {
  612. struct mlx5_ib_pfault *pfault = container_of(work,
  613. struct mlx5_ib_pfault,
  614. work);
  615. enum mlx5_ib_pagefault_context context =
  616. mlx5_ib_get_pagefault_context(&pfault->mpfault);
  617. struct mlx5_ib_qp *qp = container_of(pfault, struct mlx5_ib_qp,
  618. pagefaults[context]);
  619. mlx5_ib_mr_pfault_handler(qp, pfault);
  620. }
  621. void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp)
  622. {
  623. unsigned long flags;
  624. spin_lock_irqsave(&qp->disable_page_faults_lock, flags);
  625. qp->disable_page_faults = 1;
  626. spin_unlock_irqrestore(&qp->disable_page_faults_lock, flags);
  627. /*
  628. * Note that at this point, we are guarenteed that no more
  629. * work queue elements will be posted to the work queue with
  630. * the QP we are closing.
  631. */
  632. flush_workqueue(mlx5_ib_page_fault_wq);
  633. }
  634. void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp)
  635. {
  636. unsigned long flags;
  637. spin_lock_irqsave(&qp->disable_page_faults_lock, flags);
  638. qp->disable_page_faults = 0;
  639. spin_unlock_irqrestore(&qp->disable_page_faults_lock, flags);
  640. }
  641. static void mlx5_ib_pfault_handler(struct mlx5_core_qp *qp,
  642. struct mlx5_pagefault *pfault)
  643. {
  644. /*
  645. * Note that we will only get one fault event per QP per context
  646. * (responder/initiator, read/write), until we resolve the page fault
  647. * with the mlx5_ib_page_fault_resume command. Since this function is
  648. * called from within the work element, there is no risk of missing
  649. * events.
  650. */
  651. struct mlx5_ib_qp *mibqp = to_mibqp(qp);
  652. enum mlx5_ib_pagefault_context context =
  653. mlx5_ib_get_pagefault_context(pfault);
  654. struct mlx5_ib_pfault *qp_pfault = &mibqp->pagefaults[context];
  655. qp_pfault->mpfault = *pfault;
  656. /* No need to stop interrupts here since we are in an interrupt */
  657. spin_lock(&mibqp->disable_page_faults_lock);
  658. if (!mibqp->disable_page_faults)
  659. queue_work(mlx5_ib_page_fault_wq, &qp_pfault->work);
  660. spin_unlock(&mibqp->disable_page_faults_lock);
  661. }
  662. void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp)
  663. {
  664. int i;
  665. qp->disable_page_faults = 1;
  666. spin_lock_init(&qp->disable_page_faults_lock);
  667. qp->mqp.pfault_handler = mlx5_ib_pfault_handler;
  668. for (i = 0; i < MLX5_IB_PAGEFAULT_CONTEXTS; ++i)
  669. INIT_WORK(&qp->pagefaults[i].work, mlx5_ib_qp_pfault_action);
  670. }
  671. int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev)
  672. {
  673. int ret;
  674. ret = init_srcu_struct(&ibdev->mr_srcu);
  675. if (ret)
  676. return ret;
  677. return 0;
  678. }
  679. void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev)
  680. {
  681. cleanup_srcu_struct(&ibdev->mr_srcu);
  682. }
  683. int __init mlx5_ib_odp_init(void)
  684. {
  685. mlx5_ib_page_fault_wq =
  686. create_singlethread_workqueue("mlx5_ib_page_faults");
  687. if (!mlx5_ib_page_fault_wq)
  688. return -ENOMEM;
  689. return 0;
  690. }
  691. void mlx5_ib_odp_cleanup(void)
  692. {
  693. destroy_workqueue(mlx5_ib_page_fault_wq);
  694. }