device.c 43 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. MODULE_VERSION(DRV_VERSION);
  44. static int allow_db_fc_on_t5;
  45. module_param(allow_db_fc_on_t5, int, 0644);
  46. MODULE_PARM_DESC(allow_db_fc_on_t5,
  47. "Allow DB Flow Control on T5 (default = 0)");
  48. static int allow_db_coalescing_on_t5;
  49. module_param(allow_db_coalescing_on_t5, int, 0644);
  50. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  51. "Allow DB Coalescing on T5 (default = 0)");
  52. int c4iw_wr_log = 0;
  53. module_param(c4iw_wr_log, int, 0444);
  54. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  55. static int c4iw_wr_log_size_order = 12;
  56. module_param(c4iw_wr_log_size_order, int, 0444);
  57. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  58. "Number of entries (log2) in the work request timing log.");
  59. struct uld_ctx {
  60. struct list_head entry;
  61. struct cxgb4_lld_info lldi;
  62. struct c4iw_dev *dev;
  63. };
  64. static LIST_HEAD(uld_ctx_list);
  65. static DEFINE_MUTEX(dev_mutex);
  66. #define DB_FC_RESUME_SIZE 64
  67. #define DB_FC_RESUME_DELAY 1
  68. #define DB_FC_DRAIN_THRESH 0
  69. static struct dentry *c4iw_debugfs_root;
  70. struct c4iw_debugfs_data {
  71. struct c4iw_dev *devp;
  72. char *buf;
  73. int bufsize;
  74. int pos;
  75. };
  76. /* registered cxgb4 netlink callbacks */
  77. static struct ibnl_client_cbs c4iw_nl_cb_table[] = {
  78. [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
  79. [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
  80. [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},
  81. [RDMA_NL_IWPM_HANDLE_ERR] = {.dump = iwpm_mapping_error_cb},
  82. [RDMA_NL_IWPM_REMOTE_INFO] = {.dump = iwpm_remote_info_cb},
  83. [RDMA_NL_IWPM_MAPINFO] = {.dump = iwpm_mapping_info_cb},
  84. [RDMA_NL_IWPM_MAPINFO_NUM] = {.dump = iwpm_ack_mapping_info_cb}
  85. };
  86. static int count_idrs(int id, void *p, void *data)
  87. {
  88. int *countp = data;
  89. *countp = *countp + 1;
  90. return 0;
  91. }
  92. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  93. loff_t *ppos)
  94. {
  95. struct c4iw_debugfs_data *d = file->private_data;
  96. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  97. }
  98. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  99. {
  100. struct wr_log_entry le;
  101. int idx;
  102. if (!wq->rdev->wr_log)
  103. return;
  104. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  105. (wq->rdev->wr_log_size - 1);
  106. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  107. getnstimeofday(&le.poll_host_ts);
  108. le.valid = 1;
  109. le.cqe_sge_ts = CQE_TS(cqe);
  110. if (SQ_TYPE(cqe)) {
  111. le.qid = wq->sq.qid;
  112. le.opcode = CQE_OPCODE(cqe);
  113. le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
  114. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  115. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  116. } else {
  117. le.qid = wq->rq.qid;
  118. le.opcode = FW_RI_RECEIVE;
  119. le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
  120. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  121. le.wr_id = CQE_WRID_MSN(cqe);
  122. }
  123. wq->rdev->wr_log[idx] = le;
  124. }
  125. static int wr_log_show(struct seq_file *seq, void *v)
  126. {
  127. struct c4iw_dev *dev = seq->private;
  128. struct timespec prev_ts = {0, 0};
  129. struct wr_log_entry *lep;
  130. int prev_ts_set = 0;
  131. int idx, end;
  132. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  133. idx = atomic_read(&dev->rdev.wr_log_idx) &
  134. (dev->rdev.wr_log_size - 1);
  135. end = idx - 1;
  136. if (end < 0)
  137. end = dev->rdev.wr_log_size - 1;
  138. lep = &dev->rdev.wr_log[idx];
  139. while (idx != end) {
  140. if (lep->valid) {
  141. if (!prev_ts_set) {
  142. prev_ts_set = 1;
  143. prev_ts = lep->poll_host_ts;
  144. }
  145. seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
  146. "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
  147. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  148. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  149. "cqe_poll_delta_ns %llu\n",
  150. idx,
  151. timespec_sub(lep->poll_host_ts,
  152. prev_ts).tv_sec,
  153. timespec_sub(lep->poll_host_ts,
  154. prev_ts).tv_nsec,
  155. lep->qid, lep->opcode,
  156. lep->opcode == FW_RI_RECEIVE ?
  157. "msn" : "wrid",
  158. lep->wr_id,
  159. timespec_sub(lep->poll_host_ts,
  160. lep->post_host_ts).tv_sec,
  161. timespec_sub(lep->poll_host_ts,
  162. lep->post_host_ts).tv_nsec,
  163. lep->post_sge_ts, lep->cqe_sge_ts,
  164. lep->poll_sge_ts,
  165. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  166. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  167. prev_ts = lep->poll_host_ts;
  168. }
  169. idx++;
  170. if (idx > (dev->rdev.wr_log_size - 1))
  171. idx = 0;
  172. lep = &dev->rdev.wr_log[idx];
  173. }
  174. #undef ts2ns
  175. return 0;
  176. }
  177. static int wr_log_open(struct inode *inode, struct file *file)
  178. {
  179. return single_open(file, wr_log_show, inode->i_private);
  180. }
  181. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  182. size_t count, loff_t *pos)
  183. {
  184. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  185. int i;
  186. if (dev->rdev.wr_log)
  187. for (i = 0; i < dev->rdev.wr_log_size; i++)
  188. dev->rdev.wr_log[i].valid = 0;
  189. return count;
  190. }
  191. static const struct file_operations wr_log_debugfs_fops = {
  192. .owner = THIS_MODULE,
  193. .open = wr_log_open,
  194. .release = single_release,
  195. .read = seq_read,
  196. .llseek = seq_lseek,
  197. .write = wr_log_clear,
  198. };
  199. static int dump_qp(int id, void *p, void *data)
  200. {
  201. struct c4iw_qp *qp = p;
  202. struct c4iw_debugfs_data *qpd = data;
  203. int space;
  204. int cc;
  205. if (id != qp->wq.sq.qid)
  206. return 0;
  207. space = qpd->bufsize - qpd->pos - 1;
  208. if (space == 0)
  209. return 1;
  210. if (qp->ep) {
  211. if (qp->ep->com.local_addr.ss_family == AF_INET) {
  212. struct sockaddr_in *lsin = (struct sockaddr_in *)
  213. &qp->ep->com.local_addr;
  214. struct sockaddr_in *rsin = (struct sockaddr_in *)
  215. &qp->ep->com.remote_addr;
  216. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  217. &qp->ep->com.mapped_local_addr;
  218. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  219. &qp->ep->com.mapped_remote_addr;
  220. cc = snprintf(qpd->buf + qpd->pos, space,
  221. "rc qp sq id %u rq id %u state %u "
  222. "onchip %u ep tid %u state %u "
  223. "%pI4:%u/%u->%pI4:%u/%u\n",
  224. qp->wq.sq.qid, qp->wq.rq.qid,
  225. (int)qp->attr.state,
  226. qp->wq.sq.flags & T4_SQ_ONCHIP,
  227. qp->ep->hwtid, (int)qp->ep->com.state,
  228. &lsin->sin_addr, ntohs(lsin->sin_port),
  229. ntohs(mapped_lsin->sin_port),
  230. &rsin->sin_addr, ntohs(rsin->sin_port),
  231. ntohs(mapped_rsin->sin_port));
  232. } else {
  233. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  234. &qp->ep->com.local_addr;
  235. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  236. &qp->ep->com.remote_addr;
  237. struct sockaddr_in6 *mapped_lsin6 =
  238. (struct sockaddr_in6 *)
  239. &qp->ep->com.mapped_local_addr;
  240. struct sockaddr_in6 *mapped_rsin6 =
  241. (struct sockaddr_in6 *)
  242. &qp->ep->com.mapped_remote_addr;
  243. cc = snprintf(qpd->buf + qpd->pos, space,
  244. "rc qp sq id %u rq id %u state %u "
  245. "onchip %u ep tid %u state %u "
  246. "%pI6:%u/%u->%pI6:%u/%u\n",
  247. qp->wq.sq.qid, qp->wq.rq.qid,
  248. (int)qp->attr.state,
  249. qp->wq.sq.flags & T4_SQ_ONCHIP,
  250. qp->ep->hwtid, (int)qp->ep->com.state,
  251. &lsin6->sin6_addr,
  252. ntohs(lsin6->sin6_port),
  253. ntohs(mapped_lsin6->sin6_port),
  254. &rsin6->sin6_addr,
  255. ntohs(rsin6->sin6_port),
  256. ntohs(mapped_rsin6->sin6_port));
  257. }
  258. } else
  259. cc = snprintf(qpd->buf + qpd->pos, space,
  260. "qp sq id %u rq id %u state %u onchip %u\n",
  261. qp->wq.sq.qid, qp->wq.rq.qid,
  262. (int)qp->attr.state,
  263. qp->wq.sq.flags & T4_SQ_ONCHIP);
  264. if (cc < space)
  265. qpd->pos += cc;
  266. return 0;
  267. }
  268. static int qp_release(struct inode *inode, struct file *file)
  269. {
  270. struct c4iw_debugfs_data *qpd = file->private_data;
  271. if (!qpd) {
  272. printk(KERN_INFO "%s null qpd?\n", __func__);
  273. return 0;
  274. }
  275. vfree(qpd->buf);
  276. kfree(qpd);
  277. return 0;
  278. }
  279. static int qp_open(struct inode *inode, struct file *file)
  280. {
  281. struct c4iw_debugfs_data *qpd;
  282. int ret = 0;
  283. int count = 1;
  284. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  285. if (!qpd) {
  286. ret = -ENOMEM;
  287. goto out;
  288. }
  289. qpd->devp = inode->i_private;
  290. qpd->pos = 0;
  291. spin_lock_irq(&qpd->devp->lock);
  292. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  293. spin_unlock_irq(&qpd->devp->lock);
  294. qpd->bufsize = count * 128;
  295. qpd->buf = vmalloc(qpd->bufsize);
  296. if (!qpd->buf) {
  297. ret = -ENOMEM;
  298. goto err1;
  299. }
  300. spin_lock_irq(&qpd->devp->lock);
  301. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  302. spin_unlock_irq(&qpd->devp->lock);
  303. qpd->buf[qpd->pos++] = 0;
  304. file->private_data = qpd;
  305. goto out;
  306. err1:
  307. kfree(qpd);
  308. out:
  309. return ret;
  310. }
  311. static const struct file_operations qp_debugfs_fops = {
  312. .owner = THIS_MODULE,
  313. .open = qp_open,
  314. .release = qp_release,
  315. .read = debugfs_read,
  316. .llseek = default_llseek,
  317. };
  318. static int dump_stag(int id, void *p, void *data)
  319. {
  320. struct c4iw_debugfs_data *stagd = data;
  321. int space;
  322. int cc;
  323. struct fw_ri_tpte tpte;
  324. int ret;
  325. space = stagd->bufsize - stagd->pos - 1;
  326. if (space == 0)
  327. return 1;
  328. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  329. (__be32 *)&tpte);
  330. if (ret) {
  331. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  332. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  333. return ret;
  334. }
  335. cc = snprintf(stagd->buf + stagd->pos, space,
  336. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  337. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  338. (u32)id<<8,
  339. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  340. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  341. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  342. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  343. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  344. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  345. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  346. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  347. if (cc < space)
  348. stagd->pos += cc;
  349. return 0;
  350. }
  351. static int stag_release(struct inode *inode, struct file *file)
  352. {
  353. struct c4iw_debugfs_data *stagd = file->private_data;
  354. if (!stagd) {
  355. printk(KERN_INFO "%s null stagd?\n", __func__);
  356. return 0;
  357. }
  358. vfree(stagd->buf);
  359. kfree(stagd);
  360. return 0;
  361. }
  362. static int stag_open(struct inode *inode, struct file *file)
  363. {
  364. struct c4iw_debugfs_data *stagd;
  365. int ret = 0;
  366. int count = 1;
  367. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  368. if (!stagd) {
  369. ret = -ENOMEM;
  370. goto out;
  371. }
  372. stagd->devp = inode->i_private;
  373. stagd->pos = 0;
  374. spin_lock_irq(&stagd->devp->lock);
  375. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  376. spin_unlock_irq(&stagd->devp->lock);
  377. stagd->bufsize = count * 256;
  378. stagd->buf = vmalloc(stagd->bufsize);
  379. if (!stagd->buf) {
  380. ret = -ENOMEM;
  381. goto err1;
  382. }
  383. spin_lock_irq(&stagd->devp->lock);
  384. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  385. spin_unlock_irq(&stagd->devp->lock);
  386. stagd->buf[stagd->pos++] = 0;
  387. file->private_data = stagd;
  388. goto out;
  389. err1:
  390. kfree(stagd);
  391. out:
  392. return ret;
  393. }
  394. static const struct file_operations stag_debugfs_fops = {
  395. .owner = THIS_MODULE,
  396. .open = stag_open,
  397. .release = stag_release,
  398. .read = debugfs_read,
  399. .llseek = default_llseek,
  400. };
  401. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  402. static int stats_show(struct seq_file *seq, void *v)
  403. {
  404. struct c4iw_dev *dev = seq->private;
  405. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  406. "Max", "Fail");
  407. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  408. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  409. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  410. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  411. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  412. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  413. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  414. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  415. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  416. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  417. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  418. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  419. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  420. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  421. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  422. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  423. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  424. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  425. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  426. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  427. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  428. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  429. db_state_str[dev->db_state],
  430. dev->rdev.stats.db_state_transitions,
  431. dev->rdev.stats.db_fc_interruptions);
  432. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  433. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  434. dev->rdev.stats.act_ofld_conn_fails);
  435. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  436. dev->rdev.stats.pas_ofld_conn_fails);
  437. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  438. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  439. return 0;
  440. }
  441. static int stats_open(struct inode *inode, struct file *file)
  442. {
  443. return single_open(file, stats_show, inode->i_private);
  444. }
  445. static ssize_t stats_clear(struct file *file, const char __user *buf,
  446. size_t count, loff_t *pos)
  447. {
  448. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  449. mutex_lock(&dev->rdev.stats.lock);
  450. dev->rdev.stats.pd.max = 0;
  451. dev->rdev.stats.pd.fail = 0;
  452. dev->rdev.stats.qid.max = 0;
  453. dev->rdev.stats.qid.fail = 0;
  454. dev->rdev.stats.stag.max = 0;
  455. dev->rdev.stats.stag.fail = 0;
  456. dev->rdev.stats.pbl.max = 0;
  457. dev->rdev.stats.pbl.fail = 0;
  458. dev->rdev.stats.rqt.max = 0;
  459. dev->rdev.stats.rqt.fail = 0;
  460. dev->rdev.stats.ocqp.max = 0;
  461. dev->rdev.stats.ocqp.fail = 0;
  462. dev->rdev.stats.db_full = 0;
  463. dev->rdev.stats.db_empty = 0;
  464. dev->rdev.stats.db_drop = 0;
  465. dev->rdev.stats.db_state_transitions = 0;
  466. dev->rdev.stats.tcam_full = 0;
  467. dev->rdev.stats.act_ofld_conn_fails = 0;
  468. dev->rdev.stats.pas_ofld_conn_fails = 0;
  469. mutex_unlock(&dev->rdev.stats.lock);
  470. return count;
  471. }
  472. static const struct file_operations stats_debugfs_fops = {
  473. .owner = THIS_MODULE,
  474. .open = stats_open,
  475. .release = single_release,
  476. .read = seq_read,
  477. .llseek = seq_lseek,
  478. .write = stats_clear,
  479. };
  480. static int dump_ep(int id, void *p, void *data)
  481. {
  482. struct c4iw_ep *ep = p;
  483. struct c4iw_debugfs_data *epd = data;
  484. int space;
  485. int cc;
  486. space = epd->bufsize - epd->pos - 1;
  487. if (space == 0)
  488. return 1;
  489. if (ep->com.local_addr.ss_family == AF_INET) {
  490. struct sockaddr_in *lsin = (struct sockaddr_in *)
  491. &ep->com.local_addr;
  492. struct sockaddr_in *rsin = (struct sockaddr_in *)
  493. &ep->com.remote_addr;
  494. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  495. &ep->com.mapped_local_addr;
  496. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  497. &ep->com.mapped_remote_addr;
  498. cc = snprintf(epd->buf + epd->pos, space,
  499. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  500. "history 0x%lx hwtid %d atid %d "
  501. "conn_na %u abort_na %u "
  502. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  503. ep, ep->com.cm_id, ep->com.qp,
  504. (int)ep->com.state, ep->com.flags,
  505. ep->com.history, ep->hwtid, ep->atid,
  506. ep->stats.connect_neg_adv,
  507. ep->stats.abort_neg_adv,
  508. &lsin->sin_addr, ntohs(lsin->sin_port),
  509. ntohs(mapped_lsin->sin_port),
  510. &rsin->sin_addr, ntohs(rsin->sin_port),
  511. ntohs(mapped_rsin->sin_port));
  512. } else {
  513. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  514. &ep->com.local_addr;
  515. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  516. &ep->com.remote_addr;
  517. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  518. &ep->com.mapped_local_addr;
  519. struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *)
  520. &ep->com.mapped_remote_addr;
  521. cc = snprintf(epd->buf + epd->pos, space,
  522. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  523. "history 0x%lx hwtid %d atid %d "
  524. "conn_na %u abort_na %u "
  525. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  526. ep, ep->com.cm_id, ep->com.qp,
  527. (int)ep->com.state, ep->com.flags,
  528. ep->com.history, ep->hwtid, ep->atid,
  529. ep->stats.connect_neg_adv,
  530. ep->stats.abort_neg_adv,
  531. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  532. ntohs(mapped_lsin6->sin6_port),
  533. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  534. ntohs(mapped_rsin6->sin6_port));
  535. }
  536. if (cc < space)
  537. epd->pos += cc;
  538. return 0;
  539. }
  540. static int dump_listen_ep(int id, void *p, void *data)
  541. {
  542. struct c4iw_listen_ep *ep = p;
  543. struct c4iw_debugfs_data *epd = data;
  544. int space;
  545. int cc;
  546. space = epd->bufsize - epd->pos - 1;
  547. if (space == 0)
  548. return 1;
  549. if (ep->com.local_addr.ss_family == AF_INET) {
  550. struct sockaddr_in *lsin = (struct sockaddr_in *)
  551. &ep->com.local_addr;
  552. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  553. &ep->com.mapped_local_addr;
  554. cc = snprintf(epd->buf + epd->pos, space,
  555. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  556. "backlog %d %pI4:%d/%d\n",
  557. ep, ep->com.cm_id, (int)ep->com.state,
  558. ep->com.flags, ep->stid, ep->backlog,
  559. &lsin->sin_addr, ntohs(lsin->sin_port),
  560. ntohs(mapped_lsin->sin_port));
  561. } else {
  562. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  563. &ep->com.local_addr;
  564. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  565. &ep->com.mapped_local_addr;
  566. cc = snprintf(epd->buf + epd->pos, space,
  567. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  568. "backlog %d %pI6:%d/%d\n",
  569. ep, ep->com.cm_id, (int)ep->com.state,
  570. ep->com.flags, ep->stid, ep->backlog,
  571. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  572. ntohs(mapped_lsin6->sin6_port));
  573. }
  574. if (cc < space)
  575. epd->pos += cc;
  576. return 0;
  577. }
  578. static int ep_release(struct inode *inode, struct file *file)
  579. {
  580. struct c4iw_debugfs_data *epd = file->private_data;
  581. if (!epd) {
  582. pr_info("%s null qpd?\n", __func__);
  583. return 0;
  584. }
  585. vfree(epd->buf);
  586. kfree(epd);
  587. return 0;
  588. }
  589. static int ep_open(struct inode *inode, struct file *file)
  590. {
  591. struct c4iw_debugfs_data *epd;
  592. int ret = 0;
  593. int count = 1;
  594. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  595. if (!epd) {
  596. ret = -ENOMEM;
  597. goto out;
  598. }
  599. epd->devp = inode->i_private;
  600. epd->pos = 0;
  601. spin_lock_irq(&epd->devp->lock);
  602. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  603. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  604. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  605. spin_unlock_irq(&epd->devp->lock);
  606. epd->bufsize = count * 240;
  607. epd->buf = vmalloc(epd->bufsize);
  608. if (!epd->buf) {
  609. ret = -ENOMEM;
  610. goto err1;
  611. }
  612. spin_lock_irq(&epd->devp->lock);
  613. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  614. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  615. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  616. spin_unlock_irq(&epd->devp->lock);
  617. file->private_data = epd;
  618. goto out;
  619. err1:
  620. kfree(epd);
  621. out:
  622. return ret;
  623. }
  624. static const struct file_operations ep_debugfs_fops = {
  625. .owner = THIS_MODULE,
  626. .open = ep_open,
  627. .release = ep_release,
  628. .read = debugfs_read,
  629. };
  630. static int setup_debugfs(struct c4iw_dev *devp)
  631. {
  632. if (!devp->debugfs_root)
  633. return -1;
  634. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  635. (void *)devp, &qp_debugfs_fops, 4096);
  636. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  637. (void *)devp, &stag_debugfs_fops, 4096);
  638. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  639. (void *)devp, &stats_debugfs_fops, 4096);
  640. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  641. (void *)devp, &ep_debugfs_fops, 4096);
  642. if (c4iw_wr_log)
  643. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  644. (void *)devp, &wr_log_debugfs_fops, 4096);
  645. return 0;
  646. }
  647. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  648. struct c4iw_dev_ucontext *uctx)
  649. {
  650. struct list_head *pos, *nxt;
  651. struct c4iw_qid_list *entry;
  652. mutex_lock(&uctx->lock);
  653. list_for_each_safe(pos, nxt, &uctx->qpids) {
  654. entry = list_entry(pos, struct c4iw_qid_list, entry);
  655. list_del_init(&entry->entry);
  656. if (!(entry->qid & rdev->qpmask)) {
  657. c4iw_put_resource(&rdev->resource.qid_table,
  658. entry->qid);
  659. mutex_lock(&rdev->stats.lock);
  660. rdev->stats.qid.cur -= rdev->qpmask + 1;
  661. mutex_unlock(&rdev->stats.lock);
  662. }
  663. kfree(entry);
  664. }
  665. list_for_each_safe(pos, nxt, &uctx->qpids) {
  666. entry = list_entry(pos, struct c4iw_qid_list, entry);
  667. list_del_init(&entry->entry);
  668. kfree(entry);
  669. }
  670. mutex_unlock(&uctx->lock);
  671. }
  672. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  673. struct c4iw_dev_ucontext *uctx)
  674. {
  675. INIT_LIST_HEAD(&uctx->qpids);
  676. INIT_LIST_HEAD(&uctx->cqids);
  677. mutex_init(&uctx->lock);
  678. }
  679. /* Caller takes care of locking if needed */
  680. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  681. {
  682. int err;
  683. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  684. /*
  685. * This implementation assumes udb_density == ucq_density! Eventually
  686. * we might need to support this but for now fail the open. Also the
  687. * cqid and qpid range must match for now.
  688. */
  689. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  690. pr_err(MOD "%s: unsupported udb/ucq densities %u/%u\n",
  691. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  692. rdev->lldi.ucq_density);
  693. err = -EINVAL;
  694. goto err1;
  695. }
  696. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  697. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  698. pr_err(MOD "%s: unsupported qp and cq id ranges "
  699. "qp start %u size %u cq start %u size %u\n",
  700. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  701. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  702. rdev->lldi.vr->cq.size);
  703. err = -EINVAL;
  704. goto err1;
  705. }
  706. /*
  707. * qpshift is the number of bits to shift the qpid left in order
  708. * to get the correct address of the doorbell for that qp.
  709. */
  710. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  711. rdev->qpmask = rdev->lldi.udb_density - 1;
  712. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  713. rdev->cqmask = rdev->lldi.ucq_density - 1;
  714. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  715. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  716. "qp qid start %u size %u cq qid start %u size %u\n",
  717. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  718. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  719. rdev->lldi.vr->pbl.start,
  720. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  721. rdev->lldi.vr->rq.size,
  722. rdev->lldi.vr->qp.start,
  723. rdev->lldi.vr->qp.size,
  724. rdev->lldi.vr->cq.start,
  725. rdev->lldi.vr->cq.size);
  726. PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
  727. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  728. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  729. (void *)pci_resource_start(rdev->lldi.pdev, 2),
  730. rdev->lldi.db_reg,
  731. rdev->lldi.gts_reg,
  732. rdev->qpshift, rdev->qpmask,
  733. rdev->cqshift, rdev->cqmask);
  734. if (c4iw_num_stags(rdev) == 0) {
  735. err = -EINVAL;
  736. goto err1;
  737. }
  738. rdev->stats.pd.total = T4_MAX_NUM_PD;
  739. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  740. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  741. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  742. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  743. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  744. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  745. if (err) {
  746. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  747. goto err1;
  748. }
  749. err = c4iw_pblpool_create(rdev);
  750. if (err) {
  751. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  752. goto err2;
  753. }
  754. err = c4iw_rqtpool_create(rdev);
  755. if (err) {
  756. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  757. goto err3;
  758. }
  759. err = c4iw_ocqp_pool_create(rdev);
  760. if (err) {
  761. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  762. goto err4;
  763. }
  764. rdev->status_page = (struct t4_dev_status_page *)
  765. __get_free_page(GFP_KERNEL);
  766. if (!rdev->status_page) {
  767. pr_err(MOD "error allocating status page\n");
  768. goto err4;
  769. }
  770. if (c4iw_wr_log) {
  771. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  772. sizeof(*rdev->wr_log), GFP_KERNEL);
  773. if (rdev->wr_log) {
  774. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  775. atomic_set(&rdev->wr_log_idx, 0);
  776. } else {
  777. pr_err(MOD "error allocating wr_log. Logging disabled\n");
  778. }
  779. }
  780. rdev->status_page->db_off = 0;
  781. return 0;
  782. err4:
  783. c4iw_rqtpool_destroy(rdev);
  784. err3:
  785. c4iw_pblpool_destroy(rdev);
  786. err2:
  787. c4iw_destroy_resource(&rdev->resource);
  788. err1:
  789. return err;
  790. }
  791. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  792. {
  793. kfree(rdev->wr_log);
  794. free_page((unsigned long)rdev->status_page);
  795. c4iw_pblpool_destroy(rdev);
  796. c4iw_rqtpool_destroy(rdev);
  797. c4iw_destroy_resource(&rdev->resource);
  798. }
  799. static void c4iw_dealloc(struct uld_ctx *ctx)
  800. {
  801. c4iw_rdev_close(&ctx->dev->rdev);
  802. idr_destroy(&ctx->dev->cqidr);
  803. idr_destroy(&ctx->dev->qpidr);
  804. idr_destroy(&ctx->dev->mmidr);
  805. idr_destroy(&ctx->dev->hwtid_idr);
  806. idr_destroy(&ctx->dev->stid_idr);
  807. idr_destroy(&ctx->dev->atid_idr);
  808. if (ctx->dev->rdev.bar2_kva)
  809. iounmap(ctx->dev->rdev.bar2_kva);
  810. if (ctx->dev->rdev.oc_mw_kva)
  811. iounmap(ctx->dev->rdev.oc_mw_kva);
  812. ib_dealloc_device(&ctx->dev->ibdev);
  813. ctx->dev = NULL;
  814. }
  815. static void c4iw_remove(struct uld_ctx *ctx)
  816. {
  817. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  818. c4iw_unregister_device(ctx->dev);
  819. c4iw_dealloc(ctx);
  820. }
  821. static int rdma_supported(const struct cxgb4_lld_info *infop)
  822. {
  823. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  824. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  825. infop->vr->cq.size > 0;
  826. }
  827. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  828. {
  829. struct c4iw_dev *devp;
  830. int ret;
  831. if (!rdma_supported(infop)) {
  832. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  833. pci_name(infop->pdev));
  834. return ERR_PTR(-ENOSYS);
  835. }
  836. if (!ocqp_supported(infop))
  837. pr_info("%s: On-Chip Queues not supported on this device.\n",
  838. pci_name(infop->pdev));
  839. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  840. if (!devp) {
  841. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  842. return ERR_PTR(-ENOMEM);
  843. }
  844. devp->rdev.lldi = *infop;
  845. /* init various hw-queue params based on lld info */
  846. PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  847. __func__, devp->rdev.lldi.sge_ingpadboundary,
  848. devp->rdev.lldi.sge_egrstatuspagesize);
  849. devp->rdev.hw_queue.t4_eq_status_entries =
  850. devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
  851. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  852. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  853. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  854. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  855. devp->rdev.hw_queue.t4_max_sq_size =
  856. devp->rdev.hw_queue.t4_max_eq_size -
  857. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  858. devp->rdev.hw_queue.t4_max_qp_depth =
  859. devp->rdev.hw_queue.t4_max_rq_size;
  860. devp->rdev.hw_queue.t4_max_cq_depth =
  861. devp->rdev.hw_queue.t4_max_iq_size - 2;
  862. devp->rdev.hw_queue.t4_stat_len =
  863. devp->rdev.lldi.sge_egrstatuspagesize;
  864. /*
  865. * For T5 devices, we map all of BAR2 with WC.
  866. * For T4 devices with onchip qp mem, we map only that part
  867. * of BAR2 with WC.
  868. */
  869. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  870. if (is_t5(devp->rdev.lldi.adapter_type)) {
  871. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  872. pci_resource_len(devp->rdev.lldi.pdev, 2));
  873. if (!devp->rdev.bar2_kva) {
  874. pr_err(MOD "Unable to ioremap BAR2\n");
  875. ib_dealloc_device(&devp->ibdev);
  876. return ERR_PTR(-EINVAL);
  877. }
  878. } else if (ocqp_supported(infop)) {
  879. devp->rdev.oc_mw_pa =
  880. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  881. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  882. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  883. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  884. devp->rdev.lldi.vr->ocq.size);
  885. if (!devp->rdev.oc_mw_kva) {
  886. pr_err(MOD "Unable to ioremap onchip mem\n");
  887. ib_dealloc_device(&devp->ibdev);
  888. return ERR_PTR(-EINVAL);
  889. }
  890. }
  891. PDBG(KERN_INFO MOD "ocq memory: "
  892. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  893. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  894. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  895. ret = c4iw_rdev_open(&devp->rdev);
  896. if (ret) {
  897. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  898. ib_dealloc_device(&devp->ibdev);
  899. return ERR_PTR(ret);
  900. }
  901. idr_init(&devp->cqidr);
  902. idr_init(&devp->qpidr);
  903. idr_init(&devp->mmidr);
  904. idr_init(&devp->hwtid_idr);
  905. idr_init(&devp->stid_idr);
  906. idr_init(&devp->atid_idr);
  907. spin_lock_init(&devp->lock);
  908. mutex_init(&devp->rdev.stats.lock);
  909. mutex_init(&devp->db_mutex);
  910. INIT_LIST_HEAD(&devp->db_fc_list);
  911. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  912. if (c4iw_debugfs_root) {
  913. devp->debugfs_root = debugfs_create_dir(
  914. pci_name(devp->rdev.lldi.pdev),
  915. c4iw_debugfs_root);
  916. setup_debugfs(devp);
  917. }
  918. return devp;
  919. }
  920. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  921. {
  922. struct uld_ctx *ctx;
  923. static int vers_printed;
  924. int i;
  925. if (!vers_printed++)
  926. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  927. DRV_VERSION);
  928. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  929. if (!ctx) {
  930. ctx = ERR_PTR(-ENOMEM);
  931. goto out;
  932. }
  933. ctx->lldi = *infop;
  934. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  935. __func__, pci_name(ctx->lldi.pdev),
  936. ctx->lldi.nchan, ctx->lldi.nrxq,
  937. ctx->lldi.ntxq, ctx->lldi.nports);
  938. mutex_lock(&dev_mutex);
  939. list_add_tail(&ctx->entry, &uld_ctx_list);
  940. mutex_unlock(&dev_mutex);
  941. for (i = 0; i < ctx->lldi.nrxq; i++)
  942. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  943. out:
  944. return ctx;
  945. }
  946. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  947. const __be64 *rsp,
  948. u32 pktshift)
  949. {
  950. struct sk_buff *skb;
  951. /*
  952. * Allocate space for cpl_pass_accept_req which will be synthesized by
  953. * driver. Once the driver synthesizes the request the skb will go
  954. * through the regular cpl_pass_accept_req processing.
  955. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  956. * cpl_rx_pkt.
  957. */
  958. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  959. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  960. if (unlikely(!skb))
  961. return NULL;
  962. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  963. sizeof(struct rss_header) - pktshift);
  964. /*
  965. * This skb will contain:
  966. * rss_header from the rspq descriptor (1 flit)
  967. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  968. * space for the difference between the size of an
  969. * rx_pkt and pass_accept_req cpl (1 flit)
  970. * the packet data from the gl
  971. */
  972. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  973. sizeof(struct rss_header));
  974. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  975. sizeof(struct cpl_pass_accept_req),
  976. gl->va + pktshift,
  977. gl->tot_len - pktshift);
  978. return skb;
  979. }
  980. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  981. const __be64 *rsp)
  982. {
  983. unsigned int opcode = *(u8 *)rsp;
  984. struct sk_buff *skb;
  985. if (opcode != CPL_RX_PKT)
  986. goto out;
  987. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  988. if (skb == NULL)
  989. goto out;
  990. if (c4iw_handlers[opcode] == NULL) {
  991. pr_info("%s no handler opcode 0x%x...\n", __func__,
  992. opcode);
  993. kfree_skb(skb);
  994. goto out;
  995. }
  996. c4iw_handlers[opcode](dev, skb);
  997. return 1;
  998. out:
  999. return 0;
  1000. }
  1001. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1002. const struct pkt_gl *gl)
  1003. {
  1004. struct uld_ctx *ctx = handle;
  1005. struct c4iw_dev *dev = ctx->dev;
  1006. struct sk_buff *skb;
  1007. u8 opcode;
  1008. if (gl == NULL) {
  1009. /* omit RSS and rsp_ctrl at end of descriptor */
  1010. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1011. skb = alloc_skb(256, GFP_ATOMIC);
  1012. if (!skb)
  1013. goto nomem;
  1014. __skb_put(skb, len);
  1015. skb_copy_to_linear_data(skb, &rsp[1], len);
  1016. } else if (gl == CXGB4_MSG_AN) {
  1017. const struct rsp_ctrl *rc = (void *)rsp;
  1018. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1019. c4iw_ev_handler(dev, qid);
  1020. return 0;
  1021. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1022. if (recv_rx_pkt(dev, gl, rsp))
  1023. return 0;
  1024. pr_info("%s: unexpected FL contents at %p, " \
  1025. "RSS %#llx, FL %#llx, len %u\n",
  1026. pci_name(ctx->lldi.pdev), gl->va,
  1027. (unsigned long long)be64_to_cpu(*rsp),
  1028. (unsigned long long)be64_to_cpu(
  1029. *(__force __be64 *)gl->va),
  1030. gl->tot_len);
  1031. return 0;
  1032. } else {
  1033. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1034. if (unlikely(!skb))
  1035. goto nomem;
  1036. }
  1037. opcode = *(u8 *)rsp;
  1038. if (c4iw_handlers[opcode]) {
  1039. c4iw_handlers[opcode](dev, skb);
  1040. } else {
  1041. pr_info("%s no handler opcode 0x%x...\n", __func__,
  1042. opcode);
  1043. kfree_skb(skb);
  1044. }
  1045. return 0;
  1046. nomem:
  1047. return -1;
  1048. }
  1049. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1050. {
  1051. struct uld_ctx *ctx = handle;
  1052. PDBG("%s new_state %u\n", __func__, new_state);
  1053. switch (new_state) {
  1054. case CXGB4_STATE_UP:
  1055. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  1056. if (!ctx->dev) {
  1057. int ret;
  1058. ctx->dev = c4iw_alloc(&ctx->lldi);
  1059. if (IS_ERR(ctx->dev)) {
  1060. printk(KERN_ERR MOD
  1061. "%s: initialization failed: %ld\n",
  1062. pci_name(ctx->lldi.pdev),
  1063. PTR_ERR(ctx->dev));
  1064. ctx->dev = NULL;
  1065. break;
  1066. }
  1067. ret = c4iw_register_device(ctx->dev);
  1068. if (ret) {
  1069. printk(KERN_ERR MOD
  1070. "%s: RDMA registration failed: %d\n",
  1071. pci_name(ctx->lldi.pdev), ret);
  1072. c4iw_dealloc(ctx);
  1073. }
  1074. }
  1075. break;
  1076. case CXGB4_STATE_DOWN:
  1077. printk(KERN_INFO MOD "%s: Down\n",
  1078. pci_name(ctx->lldi.pdev));
  1079. if (ctx->dev)
  1080. c4iw_remove(ctx);
  1081. break;
  1082. case CXGB4_STATE_START_RECOVERY:
  1083. printk(KERN_INFO MOD "%s: Fatal Error\n",
  1084. pci_name(ctx->lldi.pdev));
  1085. if (ctx->dev) {
  1086. struct ib_event event;
  1087. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1088. memset(&event, 0, sizeof event);
  1089. event.event = IB_EVENT_DEVICE_FATAL;
  1090. event.device = &ctx->dev->ibdev;
  1091. ib_dispatch_event(&event);
  1092. c4iw_remove(ctx);
  1093. }
  1094. break;
  1095. case CXGB4_STATE_DETACH:
  1096. printk(KERN_INFO MOD "%s: Detach\n",
  1097. pci_name(ctx->lldi.pdev));
  1098. if (ctx->dev)
  1099. c4iw_remove(ctx);
  1100. break;
  1101. }
  1102. return 0;
  1103. }
  1104. static int disable_qp_db(int id, void *p, void *data)
  1105. {
  1106. struct c4iw_qp *qp = p;
  1107. t4_disable_wq_db(&qp->wq);
  1108. return 0;
  1109. }
  1110. static void stop_queues(struct uld_ctx *ctx)
  1111. {
  1112. unsigned long flags;
  1113. spin_lock_irqsave(&ctx->dev->lock, flags);
  1114. ctx->dev->rdev.stats.db_state_transitions++;
  1115. ctx->dev->db_state = STOPPED;
  1116. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1117. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1118. else
  1119. ctx->dev->rdev.status_page->db_off = 1;
  1120. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1121. }
  1122. static int enable_qp_db(int id, void *p, void *data)
  1123. {
  1124. struct c4iw_qp *qp = p;
  1125. t4_enable_wq_db(&qp->wq);
  1126. return 0;
  1127. }
  1128. static void resume_rc_qp(struct c4iw_qp *qp)
  1129. {
  1130. spin_lock(&qp->lock);
  1131. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc,
  1132. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  1133. qp->wq.sq.wq_pidx_inc = 0;
  1134. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc,
  1135. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  1136. qp->wq.rq.wq_pidx_inc = 0;
  1137. spin_unlock(&qp->lock);
  1138. }
  1139. static void resume_a_chunk(struct uld_ctx *ctx)
  1140. {
  1141. int i;
  1142. struct c4iw_qp *qp;
  1143. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1144. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1145. db_fc_entry);
  1146. list_del_init(&qp->db_fc_entry);
  1147. resume_rc_qp(qp);
  1148. if (list_empty(&ctx->dev->db_fc_list))
  1149. break;
  1150. }
  1151. }
  1152. static void resume_queues(struct uld_ctx *ctx)
  1153. {
  1154. spin_lock_irq(&ctx->dev->lock);
  1155. if (ctx->dev->db_state != STOPPED)
  1156. goto out;
  1157. ctx->dev->db_state = FLOW_CONTROL;
  1158. while (1) {
  1159. if (list_empty(&ctx->dev->db_fc_list)) {
  1160. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1161. ctx->dev->db_state = NORMAL;
  1162. ctx->dev->rdev.stats.db_state_transitions++;
  1163. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1164. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1165. NULL);
  1166. } else {
  1167. ctx->dev->rdev.status_page->db_off = 0;
  1168. }
  1169. break;
  1170. } else {
  1171. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1172. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1173. DB_FC_DRAIN_THRESH)) {
  1174. resume_a_chunk(ctx);
  1175. }
  1176. if (!list_empty(&ctx->dev->db_fc_list)) {
  1177. spin_unlock_irq(&ctx->dev->lock);
  1178. if (DB_FC_RESUME_DELAY) {
  1179. set_current_state(TASK_UNINTERRUPTIBLE);
  1180. schedule_timeout(DB_FC_RESUME_DELAY);
  1181. }
  1182. spin_lock_irq(&ctx->dev->lock);
  1183. if (ctx->dev->db_state != FLOW_CONTROL)
  1184. break;
  1185. }
  1186. }
  1187. }
  1188. out:
  1189. if (ctx->dev->db_state != NORMAL)
  1190. ctx->dev->rdev.stats.db_fc_interruptions++;
  1191. spin_unlock_irq(&ctx->dev->lock);
  1192. }
  1193. struct qp_list {
  1194. unsigned idx;
  1195. struct c4iw_qp **qps;
  1196. };
  1197. static int add_and_ref_qp(int id, void *p, void *data)
  1198. {
  1199. struct qp_list *qp_listp = data;
  1200. struct c4iw_qp *qp = p;
  1201. c4iw_qp_add_ref(&qp->ibqp);
  1202. qp_listp->qps[qp_listp->idx++] = qp;
  1203. return 0;
  1204. }
  1205. static int count_qps(int id, void *p, void *data)
  1206. {
  1207. unsigned *countp = data;
  1208. (*countp)++;
  1209. return 0;
  1210. }
  1211. static void deref_qps(struct qp_list *qp_list)
  1212. {
  1213. int idx;
  1214. for (idx = 0; idx < qp_list->idx; idx++)
  1215. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1216. }
  1217. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1218. {
  1219. int idx;
  1220. int ret;
  1221. for (idx = 0; idx < qp_list->idx; idx++) {
  1222. struct c4iw_qp *qp = qp_list->qps[idx];
  1223. spin_lock_irq(&qp->rhp->lock);
  1224. spin_lock(&qp->lock);
  1225. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1226. qp->wq.sq.qid,
  1227. t4_sq_host_wq_pidx(&qp->wq),
  1228. t4_sq_wq_size(&qp->wq));
  1229. if (ret) {
  1230. pr_err(MOD "%s: Fatal error - "
  1231. "DB overflow recovery failed - "
  1232. "error syncing SQ qid %u\n",
  1233. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1234. spin_unlock(&qp->lock);
  1235. spin_unlock_irq(&qp->rhp->lock);
  1236. return;
  1237. }
  1238. qp->wq.sq.wq_pidx_inc = 0;
  1239. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1240. qp->wq.rq.qid,
  1241. t4_rq_host_wq_pidx(&qp->wq),
  1242. t4_rq_wq_size(&qp->wq));
  1243. if (ret) {
  1244. pr_err(MOD "%s: Fatal error - "
  1245. "DB overflow recovery failed - "
  1246. "error syncing RQ qid %u\n",
  1247. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1248. spin_unlock(&qp->lock);
  1249. spin_unlock_irq(&qp->rhp->lock);
  1250. return;
  1251. }
  1252. qp->wq.rq.wq_pidx_inc = 0;
  1253. spin_unlock(&qp->lock);
  1254. spin_unlock_irq(&qp->rhp->lock);
  1255. /* Wait for the dbfifo to drain */
  1256. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1257. set_current_state(TASK_UNINTERRUPTIBLE);
  1258. schedule_timeout(usecs_to_jiffies(10));
  1259. }
  1260. }
  1261. }
  1262. static void recover_queues(struct uld_ctx *ctx)
  1263. {
  1264. int count = 0;
  1265. struct qp_list qp_list;
  1266. int ret;
  1267. /* slow everybody down */
  1268. set_current_state(TASK_UNINTERRUPTIBLE);
  1269. schedule_timeout(usecs_to_jiffies(1000));
  1270. /* flush the SGE contexts */
  1271. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1272. if (ret) {
  1273. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1274. pci_name(ctx->lldi.pdev));
  1275. return;
  1276. }
  1277. /* Count active queues so we can build a list of queues to recover */
  1278. spin_lock_irq(&ctx->dev->lock);
  1279. WARN_ON(ctx->dev->db_state != STOPPED);
  1280. ctx->dev->db_state = RECOVERY;
  1281. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1282. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1283. if (!qp_list.qps) {
  1284. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1285. pci_name(ctx->lldi.pdev));
  1286. spin_unlock_irq(&ctx->dev->lock);
  1287. return;
  1288. }
  1289. qp_list.idx = 0;
  1290. /* add and ref each qp so it doesn't get freed */
  1291. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1292. spin_unlock_irq(&ctx->dev->lock);
  1293. /* now traverse the list in a safe context to recover the db state*/
  1294. recover_lost_dbs(ctx, &qp_list);
  1295. /* we're almost done! deref the qps and clean up */
  1296. deref_qps(&qp_list);
  1297. kfree(qp_list.qps);
  1298. spin_lock_irq(&ctx->dev->lock);
  1299. WARN_ON(ctx->dev->db_state != RECOVERY);
  1300. ctx->dev->db_state = STOPPED;
  1301. spin_unlock_irq(&ctx->dev->lock);
  1302. }
  1303. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1304. {
  1305. struct uld_ctx *ctx = handle;
  1306. switch (control) {
  1307. case CXGB4_CONTROL_DB_FULL:
  1308. stop_queues(ctx);
  1309. ctx->dev->rdev.stats.db_full++;
  1310. break;
  1311. case CXGB4_CONTROL_DB_EMPTY:
  1312. resume_queues(ctx);
  1313. mutex_lock(&ctx->dev->rdev.stats.lock);
  1314. ctx->dev->rdev.stats.db_empty++;
  1315. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1316. break;
  1317. case CXGB4_CONTROL_DB_DROP:
  1318. recover_queues(ctx);
  1319. mutex_lock(&ctx->dev->rdev.stats.lock);
  1320. ctx->dev->rdev.stats.db_drop++;
  1321. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1322. break;
  1323. default:
  1324. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  1325. pci_name(ctx->lldi.pdev), control);
  1326. break;
  1327. }
  1328. return 0;
  1329. }
  1330. static struct cxgb4_uld_info c4iw_uld_info = {
  1331. .name = DRV_NAME,
  1332. .add = c4iw_uld_add,
  1333. .rx_handler = c4iw_uld_rx_handler,
  1334. .state_change = c4iw_uld_state_change,
  1335. .control = c4iw_uld_control,
  1336. };
  1337. static int __init c4iw_init_module(void)
  1338. {
  1339. int err;
  1340. err = c4iw_cm_init();
  1341. if (err)
  1342. return err;
  1343. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1344. if (!c4iw_debugfs_root)
  1345. printk(KERN_WARNING MOD
  1346. "could not create debugfs entry, continuing\n");
  1347. if (ibnl_add_client(RDMA_NL_C4IW, RDMA_NL_IWPM_NUM_OPS,
  1348. c4iw_nl_cb_table))
  1349. pr_err("%s[%u]: Failed to add netlink callback\n"
  1350. , __func__, __LINE__);
  1351. err = iwpm_init(RDMA_NL_C4IW);
  1352. if (err) {
  1353. pr_err("port mapper initialization failed with %d\n", err);
  1354. ibnl_remove_client(RDMA_NL_C4IW);
  1355. c4iw_cm_term();
  1356. debugfs_remove_recursive(c4iw_debugfs_root);
  1357. return err;
  1358. }
  1359. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1360. return 0;
  1361. }
  1362. static void __exit c4iw_exit_module(void)
  1363. {
  1364. struct uld_ctx *ctx, *tmp;
  1365. mutex_lock(&dev_mutex);
  1366. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1367. if (ctx->dev)
  1368. c4iw_remove(ctx);
  1369. kfree(ctx);
  1370. }
  1371. mutex_unlock(&dev_mutex);
  1372. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1373. iwpm_exit(RDMA_NL_C4IW);
  1374. ibnl_remove_client(RDMA_NL_C4IW);
  1375. c4iw_cm_term();
  1376. debugfs_remove_recursive(c4iw_debugfs_root);
  1377. }
  1378. module_init(c4iw_init_module);
  1379. module_exit(c4iw_exit_module);