vmwgfx_irq.c 8.6 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include <drm/drmP.h>
  28. #include "vmwgfx_drv.h"
  29. #define VMW_FENCE_WRAP (1 << 24)
  30. irqreturn_t vmw_irq_handler(int irq, void *arg)
  31. {
  32. struct drm_device *dev = (struct drm_device *)arg;
  33. struct vmw_private *dev_priv = vmw_priv(dev);
  34. uint32_t status, masked_status;
  35. spin_lock(&dev_priv->irq_lock);
  36. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  37. masked_status = status & dev_priv->irq_mask;
  38. spin_unlock(&dev_priv->irq_lock);
  39. if (likely(status))
  40. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  41. if (!masked_status)
  42. return IRQ_NONE;
  43. if (masked_status & (SVGA_IRQFLAG_ANY_FENCE |
  44. SVGA_IRQFLAG_FENCE_GOAL)) {
  45. vmw_fences_update(dev_priv->fman);
  46. wake_up_all(&dev_priv->fence_queue);
  47. }
  48. if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
  49. wake_up_all(&dev_priv->fifo_queue);
  50. return IRQ_HANDLED;
  51. }
  52. static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
  53. {
  54. return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
  55. }
  56. void vmw_update_seqno(struct vmw_private *dev_priv,
  57. struct vmw_fifo_state *fifo_state)
  58. {
  59. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  60. uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
  61. if (dev_priv->last_read_seqno != seqno) {
  62. dev_priv->last_read_seqno = seqno;
  63. vmw_marker_pull(&fifo_state->marker_queue, seqno);
  64. vmw_fences_update(dev_priv->fman);
  65. }
  66. }
  67. bool vmw_seqno_passed(struct vmw_private *dev_priv,
  68. uint32_t seqno)
  69. {
  70. struct vmw_fifo_state *fifo_state;
  71. bool ret;
  72. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  73. return true;
  74. fifo_state = &dev_priv->fifo;
  75. vmw_update_seqno(dev_priv, fifo_state);
  76. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  77. return true;
  78. if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
  79. vmw_fifo_idle(dev_priv, seqno))
  80. return true;
  81. /**
  82. * Then check if the seqno is higher than what we've actually
  83. * emitted. Then the fence is stale and signaled.
  84. */
  85. ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
  86. > VMW_FENCE_WRAP);
  87. return ret;
  88. }
  89. int vmw_fallback_wait(struct vmw_private *dev_priv,
  90. bool lazy,
  91. bool fifo_idle,
  92. uint32_t seqno,
  93. bool interruptible,
  94. unsigned long timeout)
  95. {
  96. struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  97. uint32_t count = 0;
  98. uint32_t signal_seq;
  99. int ret;
  100. unsigned long end_jiffies = jiffies + timeout;
  101. bool (*wait_condition)(struct vmw_private *, uint32_t);
  102. DEFINE_WAIT(__wait);
  103. wait_condition = (fifo_idle) ? &vmw_fifo_idle :
  104. &vmw_seqno_passed;
  105. /**
  106. * Block command submission while waiting for idle.
  107. */
  108. if (fifo_idle)
  109. down_read(&fifo_state->rwsem);
  110. signal_seq = atomic_read(&dev_priv->marker_seq);
  111. ret = 0;
  112. for (;;) {
  113. prepare_to_wait(&dev_priv->fence_queue, &__wait,
  114. (interruptible) ?
  115. TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  116. if (wait_condition(dev_priv, seqno))
  117. break;
  118. if (time_after_eq(jiffies, end_jiffies)) {
  119. DRM_ERROR("SVGA device lockup.\n");
  120. break;
  121. }
  122. if (lazy)
  123. schedule_timeout(1);
  124. else if ((++count & 0x0F) == 0) {
  125. /**
  126. * FIXME: Use schedule_hr_timeout here for
  127. * newer kernels and lower CPU utilization.
  128. */
  129. __set_current_state(TASK_RUNNING);
  130. schedule();
  131. __set_current_state((interruptible) ?
  132. TASK_INTERRUPTIBLE :
  133. TASK_UNINTERRUPTIBLE);
  134. }
  135. if (interruptible && signal_pending(current)) {
  136. ret = -ERESTARTSYS;
  137. break;
  138. }
  139. }
  140. finish_wait(&dev_priv->fence_queue, &__wait);
  141. if (ret == 0 && fifo_idle) {
  142. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  143. iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
  144. }
  145. wake_up_all(&dev_priv->fence_queue);
  146. if (fifo_idle)
  147. up_read(&fifo_state->rwsem);
  148. return ret;
  149. }
  150. void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
  151. {
  152. spin_lock(&dev_priv->waiter_lock);
  153. if (dev_priv->fence_queue_waiters++ == 0) {
  154. unsigned long irq_flags;
  155. spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  156. outl(SVGA_IRQFLAG_ANY_FENCE,
  157. dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  158. dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE;
  159. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  160. spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  161. }
  162. spin_unlock(&dev_priv->waiter_lock);
  163. }
  164. void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
  165. {
  166. spin_lock(&dev_priv->waiter_lock);
  167. if (--dev_priv->fence_queue_waiters == 0) {
  168. unsigned long irq_flags;
  169. spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  170. dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE;
  171. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  172. spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  173. }
  174. spin_unlock(&dev_priv->waiter_lock);
  175. }
  176. void vmw_goal_waiter_add(struct vmw_private *dev_priv)
  177. {
  178. spin_lock(&dev_priv->waiter_lock);
  179. if (dev_priv->goal_queue_waiters++ == 0) {
  180. unsigned long irq_flags;
  181. spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  182. outl(SVGA_IRQFLAG_FENCE_GOAL,
  183. dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  184. dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL;
  185. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  186. spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  187. }
  188. spin_unlock(&dev_priv->waiter_lock);
  189. }
  190. void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
  191. {
  192. spin_lock(&dev_priv->waiter_lock);
  193. if (--dev_priv->goal_queue_waiters == 0) {
  194. unsigned long irq_flags;
  195. spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  196. dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL;
  197. vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  198. spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  199. }
  200. spin_unlock(&dev_priv->waiter_lock);
  201. }
  202. int vmw_wait_seqno(struct vmw_private *dev_priv,
  203. bool lazy, uint32_t seqno,
  204. bool interruptible, unsigned long timeout)
  205. {
  206. long ret;
  207. struct vmw_fifo_state *fifo = &dev_priv->fifo;
  208. if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  209. return 0;
  210. if (likely(vmw_seqno_passed(dev_priv, seqno)))
  211. return 0;
  212. vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
  213. if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
  214. return vmw_fallback_wait(dev_priv, lazy, true, seqno,
  215. interruptible, timeout);
  216. if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  217. return vmw_fallback_wait(dev_priv, lazy, false, seqno,
  218. interruptible, timeout);
  219. vmw_seqno_waiter_add(dev_priv);
  220. if (interruptible)
  221. ret = wait_event_interruptible_timeout
  222. (dev_priv->fence_queue,
  223. vmw_seqno_passed(dev_priv, seqno),
  224. timeout);
  225. else
  226. ret = wait_event_timeout
  227. (dev_priv->fence_queue,
  228. vmw_seqno_passed(dev_priv, seqno),
  229. timeout);
  230. vmw_seqno_waiter_remove(dev_priv);
  231. if (unlikely(ret == 0))
  232. ret = -EBUSY;
  233. else if (likely(ret > 0))
  234. ret = 0;
  235. return ret;
  236. }
  237. void vmw_irq_preinstall(struct drm_device *dev)
  238. {
  239. struct vmw_private *dev_priv = vmw_priv(dev);
  240. uint32_t status;
  241. if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  242. return;
  243. spin_lock_init(&dev_priv->irq_lock);
  244. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  245. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  246. }
  247. int vmw_irq_postinstall(struct drm_device *dev)
  248. {
  249. return 0;
  250. }
  251. void vmw_irq_uninstall(struct drm_device *dev)
  252. {
  253. struct vmw_private *dev_priv = vmw_priv(dev);
  254. uint32_t status;
  255. if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  256. return;
  257. vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
  258. status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  259. outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  260. }