omap_drv.c 18 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "omap_drv.h"
  20. #include "drm_crtc_helper.h"
  21. #include "drm_fb_helper.h"
  22. #include "omap_dmm_tiler.h"
  23. #define DRIVER_NAME MODULE_NAME
  24. #define DRIVER_DESC "OMAP DRM"
  25. #define DRIVER_DATE "20110917"
  26. #define DRIVER_MAJOR 1
  27. #define DRIVER_MINOR 0
  28. #define DRIVER_PATCHLEVEL 0
  29. static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
  30. MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
  31. module_param(num_crtc, int, 0600);
  32. /*
  33. * mode config funcs
  34. */
  35. /* Notes about mapping DSS and DRM entities:
  36. * CRTC: overlay
  37. * encoder: manager.. with some extension to allow one primary CRTC
  38. * and zero or more video CRTC's to be mapped to one encoder?
  39. * connector: dssdev.. manager can be attached/detached from different
  40. * devices
  41. */
  42. static void omap_fb_output_poll_changed(struct drm_device *dev)
  43. {
  44. struct omap_drm_private *priv = dev->dev_private;
  45. DBG("dev=%p", dev);
  46. if (priv->fbdev)
  47. drm_fb_helper_hotplug_event(priv->fbdev);
  48. }
  49. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  50. .fb_create = omap_framebuffer_create,
  51. .output_poll_changed = omap_fb_output_poll_changed,
  52. };
  53. static int get_connector_type(struct omap_dss_device *dssdev)
  54. {
  55. switch (dssdev->type) {
  56. case OMAP_DISPLAY_TYPE_HDMI:
  57. return DRM_MODE_CONNECTOR_HDMIA;
  58. case OMAP_DISPLAY_TYPE_DVI:
  59. return DRM_MODE_CONNECTOR_DVID;
  60. default:
  61. return DRM_MODE_CONNECTOR_Unknown;
  62. }
  63. }
  64. static bool channel_used(struct drm_device *dev, enum omap_channel channel)
  65. {
  66. struct omap_drm_private *priv = dev->dev_private;
  67. int i;
  68. for (i = 0; i < priv->num_crtcs; i++) {
  69. struct drm_crtc *crtc = priv->crtcs[i];
  70. if (omap_crtc_channel(crtc) == channel)
  71. return true;
  72. }
  73. return false;
  74. }
  75. static void omap_disconnect_dssdevs(void)
  76. {
  77. struct omap_dss_device *dssdev = NULL;
  78. for_each_dss_dev(dssdev)
  79. dssdev->driver->disconnect(dssdev);
  80. }
  81. static int omap_connect_dssdevs(void)
  82. {
  83. int r;
  84. struct omap_dss_device *dssdev = NULL;
  85. bool no_displays = true;
  86. for_each_dss_dev(dssdev) {
  87. r = dssdev->driver->connect(dssdev);
  88. if (r == -EPROBE_DEFER) {
  89. omap_dss_put_device(dssdev);
  90. goto cleanup;
  91. } else if (r) {
  92. dev_warn(dssdev->dev, "could not connect display: %s\n",
  93. dssdev->name);
  94. } else {
  95. no_displays = false;
  96. }
  97. }
  98. if (no_displays)
  99. return -EPROBE_DEFER;
  100. return 0;
  101. cleanup:
  102. /*
  103. * if we are deferring probe, we disconnect the devices we previously
  104. * connected
  105. */
  106. omap_disconnect_dssdevs();
  107. return r;
  108. }
  109. static int omap_modeset_create_crtc(struct drm_device *dev, int id,
  110. enum omap_channel channel)
  111. {
  112. struct omap_drm_private *priv = dev->dev_private;
  113. struct drm_plane *plane;
  114. struct drm_crtc *crtc;
  115. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY);
  116. if (IS_ERR(plane))
  117. return PTR_ERR(plane);
  118. crtc = omap_crtc_init(dev, plane, channel, id);
  119. BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
  120. priv->crtcs[id] = crtc;
  121. priv->num_crtcs++;
  122. priv->planes[id] = plane;
  123. priv->num_planes++;
  124. return 0;
  125. }
  126. static int omap_modeset_init(struct drm_device *dev)
  127. {
  128. struct omap_drm_private *priv = dev->dev_private;
  129. struct omap_dss_device *dssdev = NULL;
  130. int num_ovls = dss_feat_get_num_ovls();
  131. int num_mgrs = dss_feat_get_num_mgrs();
  132. int num_crtcs;
  133. int i, id = 0;
  134. int ret;
  135. drm_mode_config_init(dev);
  136. omap_drm_irq_install(dev);
  137. /*
  138. * We usually don't want to create a CRTC for each manager, at least
  139. * not until we have a way to expose private planes to userspace.
  140. * Otherwise there would not be enough video pipes left for drm planes.
  141. * We use the num_crtc argument to limit the number of crtcs we create.
  142. */
  143. num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
  144. dssdev = NULL;
  145. for_each_dss_dev(dssdev) {
  146. struct drm_connector *connector;
  147. struct drm_encoder *encoder;
  148. enum omap_channel channel;
  149. struct omap_overlay_manager *mgr;
  150. if (!omapdss_device_is_connected(dssdev))
  151. continue;
  152. encoder = omap_encoder_init(dev, dssdev);
  153. if (!encoder) {
  154. dev_err(dev->dev, "could not create encoder: %s\n",
  155. dssdev->name);
  156. return -ENOMEM;
  157. }
  158. connector = omap_connector_init(dev,
  159. get_connector_type(dssdev), dssdev, encoder);
  160. if (!connector) {
  161. dev_err(dev->dev, "could not create connector: %s\n",
  162. dssdev->name);
  163. return -ENOMEM;
  164. }
  165. BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
  166. BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
  167. priv->encoders[priv->num_encoders++] = encoder;
  168. priv->connectors[priv->num_connectors++] = connector;
  169. drm_mode_connector_attach_encoder(connector, encoder);
  170. /*
  171. * if we have reached the limit of the crtcs we are allowed to
  172. * create, let's not try to look for a crtc for this
  173. * panel/encoder and onwards, we will, of course, populate the
  174. * the possible_crtcs field for all the encoders with the final
  175. * set of crtcs we create
  176. */
  177. if (id == num_crtcs)
  178. continue;
  179. /*
  180. * get the recommended DISPC channel for this encoder. For now,
  181. * we only try to get create a crtc out of the recommended, the
  182. * other possible channels to which the encoder can connect are
  183. * not considered.
  184. */
  185. mgr = omapdss_find_mgr_from_display(dssdev);
  186. channel = mgr->id;
  187. /*
  188. * if this channel hasn't already been taken by a previously
  189. * allocated crtc, we create a new crtc for it
  190. */
  191. if (!channel_used(dev, channel)) {
  192. ret = omap_modeset_create_crtc(dev, id, channel);
  193. if (ret < 0) {
  194. dev_err(dev->dev,
  195. "could not create CRTC (channel %u)\n",
  196. channel);
  197. return ret;
  198. }
  199. id++;
  200. }
  201. }
  202. /*
  203. * we have allocated crtcs according to the need of the panels/encoders,
  204. * adding more crtcs here if needed
  205. */
  206. for (; id < num_crtcs; id++) {
  207. /* find a free manager for this crtc */
  208. for (i = 0; i < num_mgrs; i++) {
  209. if (!channel_used(dev, i))
  210. break;
  211. }
  212. if (i == num_mgrs) {
  213. /* this shouldn't really happen */
  214. dev_err(dev->dev, "no managers left for crtc\n");
  215. return -ENOMEM;
  216. }
  217. ret = omap_modeset_create_crtc(dev, id, i);
  218. if (ret < 0) {
  219. dev_err(dev->dev,
  220. "could not create CRTC (channel %u)\n", i);
  221. return ret;
  222. }
  223. }
  224. /*
  225. * Create normal planes for the remaining overlays:
  226. */
  227. for (; id < num_ovls; id++) {
  228. struct drm_plane *plane;
  229. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY);
  230. if (IS_ERR(plane))
  231. return PTR_ERR(plane);
  232. BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
  233. priv->planes[priv->num_planes++] = plane;
  234. }
  235. for (i = 0; i < priv->num_encoders; i++) {
  236. struct drm_encoder *encoder = priv->encoders[i];
  237. struct omap_dss_device *dssdev =
  238. omap_encoder_get_dssdev(encoder);
  239. struct omap_dss_device *output;
  240. output = omapdss_find_output_from_display(dssdev);
  241. /* figure out which crtc's we can connect the encoder to: */
  242. encoder->possible_crtcs = 0;
  243. for (id = 0; id < priv->num_crtcs; id++) {
  244. struct drm_crtc *crtc = priv->crtcs[id];
  245. enum omap_channel crtc_channel;
  246. crtc_channel = omap_crtc_channel(crtc);
  247. if (output->dispc_channel == crtc_channel) {
  248. encoder->possible_crtcs |= (1 << id);
  249. break;
  250. }
  251. }
  252. omap_dss_put_device(output);
  253. }
  254. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  255. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  256. priv->num_connectors);
  257. dev->mode_config.min_width = 32;
  258. dev->mode_config.min_height = 32;
  259. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  260. * to fill in these limits properly on different OMAP generations..
  261. */
  262. dev->mode_config.max_width = 2048;
  263. dev->mode_config.max_height = 2048;
  264. dev->mode_config.funcs = &omap_mode_config_funcs;
  265. return 0;
  266. }
  267. static void omap_modeset_free(struct drm_device *dev)
  268. {
  269. drm_mode_config_cleanup(dev);
  270. }
  271. /*
  272. * drm ioctl funcs
  273. */
  274. static int ioctl_get_param(struct drm_device *dev, void *data,
  275. struct drm_file *file_priv)
  276. {
  277. struct omap_drm_private *priv = dev->dev_private;
  278. struct drm_omap_param *args = data;
  279. DBG("%p: param=%llu", dev, args->param);
  280. switch (args->param) {
  281. case OMAP_PARAM_CHIPSET_ID:
  282. args->value = priv->omaprev;
  283. break;
  284. default:
  285. DBG("unknown parameter %lld", args->param);
  286. return -EINVAL;
  287. }
  288. return 0;
  289. }
  290. static int ioctl_set_param(struct drm_device *dev, void *data,
  291. struct drm_file *file_priv)
  292. {
  293. struct drm_omap_param *args = data;
  294. switch (args->param) {
  295. default:
  296. DBG("unknown parameter %lld", args->param);
  297. return -EINVAL;
  298. }
  299. return 0;
  300. }
  301. static int ioctl_gem_new(struct drm_device *dev, void *data,
  302. struct drm_file *file_priv)
  303. {
  304. struct drm_omap_gem_new *args = data;
  305. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  306. args->size.bytes, args->flags);
  307. return omap_gem_new_handle(dev, file_priv, args->size,
  308. args->flags, &args->handle);
  309. }
  310. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  311. struct drm_file *file_priv)
  312. {
  313. struct drm_omap_gem_cpu_prep *args = data;
  314. struct drm_gem_object *obj;
  315. int ret;
  316. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  317. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  318. if (!obj)
  319. return -ENOENT;
  320. ret = omap_gem_op_sync(obj, args->op);
  321. if (!ret)
  322. ret = omap_gem_op_start(obj, args->op);
  323. drm_gem_object_unreference_unlocked(obj);
  324. return ret;
  325. }
  326. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  327. struct drm_file *file_priv)
  328. {
  329. struct drm_omap_gem_cpu_fini *args = data;
  330. struct drm_gem_object *obj;
  331. int ret;
  332. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  333. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  334. if (!obj)
  335. return -ENOENT;
  336. /* XXX flushy, flushy */
  337. ret = 0;
  338. if (!ret)
  339. ret = omap_gem_op_finish(obj, args->op);
  340. drm_gem_object_unreference_unlocked(obj);
  341. return ret;
  342. }
  343. static int ioctl_gem_info(struct drm_device *dev, void *data,
  344. struct drm_file *file_priv)
  345. {
  346. struct drm_omap_gem_info *args = data;
  347. struct drm_gem_object *obj;
  348. int ret = 0;
  349. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  350. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  351. if (!obj)
  352. return -ENOENT;
  353. args->size = omap_gem_mmap_size(obj);
  354. args->offset = omap_gem_mmap_offset(obj);
  355. drm_gem_object_unreference_unlocked(obj);
  356. return ret;
  357. }
  358. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  359. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH),
  360. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  361. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH),
  362. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  363. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  364. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH),
  365. };
  366. /*
  367. * drm driver funcs
  368. */
  369. /**
  370. * load - setup chip and create an initial config
  371. * @dev: DRM device
  372. * @flags: startup flags
  373. *
  374. * The driver load routine has to do several things:
  375. * - initialize the memory manager
  376. * - allocate initial config memory
  377. * - setup the DRM framebuffer with the allocated memory
  378. */
  379. static int dev_load(struct drm_device *dev, unsigned long flags)
  380. {
  381. struct omap_drm_platform_data *pdata = dev->dev->platform_data;
  382. struct omap_drm_private *priv;
  383. int ret;
  384. DBG("load: dev=%p", dev);
  385. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  386. if (!priv)
  387. return -ENOMEM;
  388. priv->omaprev = pdata->omaprev;
  389. dev->dev_private = priv;
  390. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  391. spin_lock_init(&priv->list_lock);
  392. INIT_LIST_HEAD(&priv->obj_list);
  393. omap_gem_init(dev);
  394. ret = omap_modeset_init(dev);
  395. if (ret) {
  396. dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  397. dev->dev_private = NULL;
  398. kfree(priv);
  399. return ret;
  400. }
  401. ret = drm_vblank_init(dev, priv->num_crtcs);
  402. if (ret)
  403. dev_warn(dev->dev, "could not init vblank\n");
  404. priv->fbdev = omap_fbdev_init(dev);
  405. if (!priv->fbdev) {
  406. dev_warn(dev->dev, "omap_fbdev_init failed\n");
  407. /* well, limp along without an fbdev.. maybe X11 will work? */
  408. }
  409. /* store off drm_device for use in pm ops */
  410. dev_set_drvdata(dev->dev, dev);
  411. drm_kms_helper_poll_init(dev);
  412. return 0;
  413. }
  414. static int dev_unload(struct drm_device *dev)
  415. {
  416. struct omap_drm_private *priv = dev->dev_private;
  417. int i;
  418. DBG("unload: dev=%p", dev);
  419. drm_kms_helper_poll_fini(dev);
  420. if (priv->fbdev)
  421. omap_fbdev_free(dev);
  422. /* flush crtcs so the fbs get released */
  423. for (i = 0; i < priv->num_crtcs; i++)
  424. omap_crtc_flush(priv->crtcs[i]);
  425. omap_modeset_free(dev);
  426. omap_gem_deinit(dev);
  427. destroy_workqueue(priv->wq);
  428. drm_vblank_cleanup(dev);
  429. omap_drm_irq_uninstall(dev);
  430. kfree(dev->dev_private);
  431. dev->dev_private = NULL;
  432. dev_set_drvdata(dev->dev, NULL);
  433. return 0;
  434. }
  435. static int dev_open(struct drm_device *dev, struct drm_file *file)
  436. {
  437. file->driver_priv = NULL;
  438. DBG("open: dev=%p, file=%p", dev, file);
  439. return 0;
  440. }
  441. /**
  442. * lastclose - clean up after all DRM clients have exited
  443. * @dev: DRM device
  444. *
  445. * Take care of cleaning up after all DRM clients have exited. In the
  446. * mode setting case, we want to restore the kernel's initial mode (just
  447. * in case the last client left us in a bad state).
  448. */
  449. static void dev_lastclose(struct drm_device *dev)
  450. {
  451. int i;
  452. /* we don't support vga-switcheroo.. so just make sure the fbdev
  453. * mode is active
  454. */
  455. struct omap_drm_private *priv = dev->dev_private;
  456. int ret;
  457. DBG("lastclose: dev=%p", dev);
  458. if (priv->rotation_prop) {
  459. /* need to restore default rotation state.. not sure
  460. * if there is a cleaner way to restore properties to
  461. * default state? Maybe a flag that properties should
  462. * automatically be restored to default state on
  463. * lastclose?
  464. */
  465. for (i = 0; i < priv->num_crtcs; i++) {
  466. drm_object_property_set_value(&priv->crtcs[i]->base,
  467. priv->rotation_prop, 0);
  468. }
  469. for (i = 0; i < priv->num_planes; i++) {
  470. drm_object_property_set_value(&priv->planes[i]->base,
  471. priv->rotation_prop, 0);
  472. }
  473. }
  474. if (priv->fbdev) {
  475. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  476. if (ret)
  477. DBG("failed to restore crtc mode");
  478. }
  479. }
  480. static void dev_preclose(struct drm_device *dev, struct drm_file *file)
  481. {
  482. DBG("preclose: dev=%p", dev);
  483. }
  484. static void dev_postclose(struct drm_device *dev, struct drm_file *file)
  485. {
  486. DBG("postclose: dev=%p, file=%p", dev, file);
  487. }
  488. static const struct vm_operations_struct omap_gem_vm_ops = {
  489. .fault = omap_gem_fault,
  490. .open = drm_gem_vm_open,
  491. .close = drm_gem_vm_close,
  492. };
  493. static const struct file_operations omapdriver_fops = {
  494. .owner = THIS_MODULE,
  495. .open = drm_open,
  496. .unlocked_ioctl = drm_ioctl,
  497. .release = drm_release,
  498. .mmap = omap_gem_mmap,
  499. .poll = drm_poll,
  500. .read = drm_read,
  501. .llseek = noop_llseek,
  502. };
  503. static struct drm_driver omap_drm_driver = {
  504. .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM
  505. | DRIVER_PRIME,
  506. .load = dev_load,
  507. .unload = dev_unload,
  508. .open = dev_open,
  509. .lastclose = dev_lastclose,
  510. .preclose = dev_preclose,
  511. .postclose = dev_postclose,
  512. .set_busid = drm_platform_set_busid,
  513. .get_vblank_counter = drm_vblank_count,
  514. .enable_vblank = omap_irq_enable_vblank,
  515. .disable_vblank = omap_irq_disable_vblank,
  516. .irq_preinstall = omap_irq_preinstall,
  517. .irq_postinstall = omap_irq_postinstall,
  518. .irq_uninstall = omap_irq_uninstall,
  519. .irq_handler = omap_irq_handler,
  520. #ifdef CONFIG_DEBUG_FS
  521. .debugfs_init = omap_debugfs_init,
  522. .debugfs_cleanup = omap_debugfs_cleanup,
  523. #endif
  524. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  525. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  526. .gem_prime_export = omap_gem_prime_export,
  527. .gem_prime_import = omap_gem_prime_import,
  528. .gem_free_object = omap_gem_free_object,
  529. .gem_vm_ops = &omap_gem_vm_ops,
  530. .dumb_create = omap_gem_dumb_create,
  531. .dumb_map_offset = omap_gem_dumb_map_offset,
  532. .dumb_destroy = drm_gem_dumb_destroy,
  533. .ioctls = ioctls,
  534. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  535. .fops = &omapdriver_fops,
  536. .name = DRIVER_NAME,
  537. .desc = DRIVER_DESC,
  538. .date = DRIVER_DATE,
  539. .major = DRIVER_MAJOR,
  540. .minor = DRIVER_MINOR,
  541. .patchlevel = DRIVER_PATCHLEVEL,
  542. };
  543. static int pdev_probe(struct platform_device *device)
  544. {
  545. int r;
  546. if (omapdss_is_initialized() == false)
  547. return -EPROBE_DEFER;
  548. omap_crtc_pre_init();
  549. r = omap_connect_dssdevs();
  550. if (r) {
  551. omap_crtc_pre_uninit();
  552. return r;
  553. }
  554. DBG("%s", device->name);
  555. return drm_platform_init(&omap_drm_driver, device);
  556. }
  557. static int pdev_remove(struct platform_device *device)
  558. {
  559. DBG("");
  560. drm_put_dev(platform_get_drvdata(device));
  561. omap_disconnect_dssdevs();
  562. omap_crtc_pre_uninit();
  563. return 0;
  564. }
  565. #ifdef CONFIG_PM_SLEEP
  566. static int omap_drm_suspend(struct device *dev)
  567. {
  568. struct drm_device *drm_dev = dev_get_drvdata(dev);
  569. drm_kms_helper_poll_disable(drm_dev);
  570. return 0;
  571. }
  572. static int omap_drm_resume(struct device *dev)
  573. {
  574. struct drm_device *drm_dev = dev_get_drvdata(dev);
  575. drm_kms_helper_poll_enable(drm_dev);
  576. return omap_gem_resume(dev);
  577. }
  578. #endif
  579. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  580. static struct platform_driver pdev = {
  581. .driver = {
  582. .name = DRIVER_NAME,
  583. .pm = &omapdrm_pm_ops,
  584. },
  585. .probe = pdev_probe,
  586. .remove = pdev_remove,
  587. };
  588. static int __init omap_drm_init(void)
  589. {
  590. int r;
  591. DBG("init");
  592. r = platform_driver_register(&omap_dmm_driver);
  593. if (r) {
  594. pr_err("DMM driver registration failed\n");
  595. return r;
  596. }
  597. r = platform_driver_register(&pdev);
  598. if (r) {
  599. pr_err("omapdrm driver registration failed\n");
  600. platform_driver_unregister(&omap_dmm_driver);
  601. return r;
  602. }
  603. return 0;
  604. }
  605. static void __exit omap_drm_fini(void)
  606. {
  607. DBG("fini");
  608. platform_driver_unregister(&pdev);
  609. platform_driver_unregister(&omap_dmm_driver);
  610. }
  611. /* need late_initcall() so we load after dss_driver's are loaded */
  612. late_initcall(omap_drm_init);
  613. module_exit(omap_drm_fini);
  614. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  615. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  616. MODULE_ALIAS("platform:" DRIVER_NAME);
  617. MODULE_LICENSE("GPL v2");