nouveau_platform.c 6.0 KB

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  1. /*
  2. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20. * DEALINGS IN THE SOFTWARE.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/module.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/of.h>
  27. #include <linux/reset.h>
  28. #include <linux/regulator/consumer.h>
  29. #include <linux/iommu.h>
  30. #include <soc/tegra/fuse.h>
  31. #include <soc/tegra/pmc.h>
  32. #include "nouveau_drm.h"
  33. #include "nouveau_platform.h"
  34. static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu)
  35. {
  36. int err;
  37. err = regulator_enable(gpu->vdd);
  38. if (err)
  39. goto err_power;
  40. err = clk_prepare_enable(gpu->clk);
  41. if (err)
  42. goto err_clk;
  43. err = clk_prepare_enable(gpu->clk_pwr);
  44. if (err)
  45. goto err_clk_pwr;
  46. clk_set_rate(gpu->clk_pwr, 204000000);
  47. udelay(10);
  48. reset_control_assert(gpu->rst);
  49. udelay(10);
  50. err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
  51. if (err)
  52. goto err_clamp;
  53. udelay(10);
  54. reset_control_deassert(gpu->rst);
  55. udelay(10);
  56. return 0;
  57. err_clamp:
  58. clk_disable_unprepare(gpu->clk_pwr);
  59. err_clk_pwr:
  60. clk_disable_unprepare(gpu->clk);
  61. err_clk:
  62. regulator_disable(gpu->vdd);
  63. err_power:
  64. return err;
  65. }
  66. static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
  67. {
  68. int err;
  69. reset_control_assert(gpu->rst);
  70. udelay(10);
  71. clk_disable_unprepare(gpu->clk_pwr);
  72. clk_disable_unprepare(gpu->clk);
  73. udelay(10);
  74. err = regulator_disable(gpu->vdd);
  75. if (err)
  76. return err;
  77. return 0;
  78. }
  79. static void nouveau_platform_probe_iommu(struct device *dev,
  80. struct nouveau_platform_gpu *gpu)
  81. {
  82. int err;
  83. unsigned long pgsize_bitmap;
  84. mutex_init(&gpu->iommu.mutex);
  85. if (iommu_present(&platform_bus_type)) {
  86. gpu->iommu.domain = iommu_domain_alloc(&platform_bus_type);
  87. if (IS_ERR(gpu->iommu.domain))
  88. goto error;
  89. /*
  90. * A IOMMU is only usable if it supports page sizes smaller
  91. * or equal to the system's PAGE_SIZE, with a preference if
  92. * both are equal.
  93. */
  94. pgsize_bitmap = gpu->iommu.domain->ops->pgsize_bitmap;
  95. if (pgsize_bitmap & PAGE_SIZE) {
  96. gpu->iommu.pgshift = PAGE_SHIFT;
  97. } else {
  98. gpu->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
  99. if (gpu->iommu.pgshift == 0) {
  100. dev_warn(dev, "unsupported IOMMU page size\n");
  101. goto free_domain;
  102. }
  103. gpu->iommu.pgshift -= 1;
  104. }
  105. err = iommu_attach_device(gpu->iommu.domain, dev);
  106. if (err)
  107. goto free_domain;
  108. err = nvkm_mm_init(&gpu->iommu._mm, 0,
  109. (1ULL << 40) >> gpu->iommu.pgshift, 1);
  110. if (err)
  111. goto detach_device;
  112. gpu->iommu.mm = &gpu->iommu._mm;
  113. }
  114. return;
  115. detach_device:
  116. iommu_detach_device(gpu->iommu.domain, dev);
  117. free_domain:
  118. iommu_domain_free(gpu->iommu.domain);
  119. error:
  120. gpu->iommu.domain = NULL;
  121. gpu->iommu.pgshift = 0;
  122. dev_err(dev, "cannot initialize IOMMU MM\n");
  123. }
  124. static void nouveau_platform_remove_iommu(struct device *dev,
  125. struct nouveau_platform_gpu *gpu)
  126. {
  127. if (gpu->iommu.domain) {
  128. nvkm_mm_fini(&gpu->iommu._mm);
  129. iommu_detach_device(gpu->iommu.domain, dev);
  130. iommu_domain_free(gpu->iommu.domain);
  131. }
  132. }
  133. static int nouveau_platform_probe(struct platform_device *pdev)
  134. {
  135. struct nouveau_platform_gpu *gpu;
  136. struct nouveau_platform_device *device;
  137. struct drm_device *drm;
  138. int err;
  139. gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL);
  140. if (!gpu)
  141. return -ENOMEM;
  142. gpu->vdd = devm_regulator_get(&pdev->dev, "vdd");
  143. if (IS_ERR(gpu->vdd))
  144. return PTR_ERR(gpu->vdd);
  145. gpu->rst = devm_reset_control_get(&pdev->dev, "gpu");
  146. if (IS_ERR(gpu->rst))
  147. return PTR_ERR(gpu->rst);
  148. gpu->clk = devm_clk_get(&pdev->dev, "gpu");
  149. if (IS_ERR(gpu->clk))
  150. return PTR_ERR(gpu->clk);
  151. gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
  152. if (IS_ERR(gpu->clk_pwr))
  153. return PTR_ERR(gpu->clk_pwr);
  154. nouveau_platform_probe_iommu(&pdev->dev, gpu);
  155. err = nouveau_platform_power_up(gpu);
  156. if (err)
  157. return err;
  158. drm = nouveau_platform_device_create(pdev, &device);
  159. if (IS_ERR(drm)) {
  160. err = PTR_ERR(drm);
  161. goto power_down;
  162. }
  163. device->gpu = gpu;
  164. device->gpu_speedo = tegra_sku_info.gpu_speedo_value;
  165. err = drm_dev_register(drm, 0);
  166. if (err < 0)
  167. goto err_unref;
  168. return 0;
  169. err_unref:
  170. drm_dev_unref(drm);
  171. power_down:
  172. nouveau_platform_power_down(gpu);
  173. nouveau_platform_remove_iommu(&pdev->dev, gpu);
  174. return err;
  175. }
  176. static int nouveau_platform_remove(struct platform_device *pdev)
  177. {
  178. struct drm_device *drm_dev = platform_get_drvdata(pdev);
  179. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  180. struct nvkm_device *device = nvxx_device(&drm->device);
  181. struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
  182. int err;
  183. nouveau_drm_device_remove(drm_dev);
  184. err = nouveau_platform_power_down(gpu);
  185. nouveau_platform_remove_iommu(&pdev->dev, gpu);
  186. return err;
  187. }
  188. #if IS_ENABLED(CONFIG_OF)
  189. static const struct of_device_id nouveau_platform_match[] = {
  190. { .compatible = "nvidia,gk20a" },
  191. { }
  192. };
  193. MODULE_DEVICE_TABLE(of, nouveau_platform_match);
  194. #endif
  195. struct platform_driver nouveau_platform_driver = {
  196. .driver = {
  197. .name = "nouveau",
  198. .of_match_table = of_match_ptr(nouveau_platform_match),
  199. },
  200. .probe = nouveau_platform_probe,
  201. .remove = nouveau_platform_remove,
  202. };