nouveau_drm.c 29 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/console.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/vga_switcheroo.h>
  29. #include "drmP.h"
  30. #include "drm_crtc_helper.h"
  31. #include <core/device.h>
  32. #include <core/gpuobj.h>
  33. #include <core/option.h>
  34. #include "nouveau_drm.h"
  35. #include "nouveau_dma.h"
  36. #include "nouveau_ttm.h"
  37. #include "nouveau_gem.h"
  38. #include "nouveau_agp.h"
  39. #include "nouveau_vga.h"
  40. #include "nouveau_sysfs.h"
  41. #include "nouveau_hwmon.h"
  42. #include "nouveau_acpi.h"
  43. #include "nouveau_bios.h"
  44. #include "nouveau_ioctl.h"
  45. #include "nouveau_abi16.h"
  46. #include "nouveau_fbcon.h"
  47. #include "nouveau_fence.h"
  48. #include "nouveau_debugfs.h"
  49. #include "nouveau_usif.h"
  50. #include "nouveau_connector.h"
  51. #include "nouveau_platform.h"
  52. MODULE_PARM_DESC(config, "option string to pass to driver core");
  53. static char *nouveau_config;
  54. module_param_named(config, nouveau_config, charp, 0400);
  55. MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  56. static char *nouveau_debug;
  57. module_param_named(debug, nouveau_debug, charp, 0400);
  58. MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  59. static int nouveau_noaccel = 0;
  60. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  61. MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  62. "0 = disabled, 1 = enabled, 2 = headless)");
  63. int nouveau_modeset = -1;
  64. module_param_named(modeset, nouveau_modeset, int, 0400);
  65. MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  66. int nouveau_runtime_pm = -1;
  67. module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  68. static struct drm_driver driver_stub;
  69. static struct drm_driver driver_pci;
  70. static struct drm_driver driver_platform;
  71. static u64
  72. nouveau_pci_name(struct pci_dev *pdev)
  73. {
  74. u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
  75. name |= pdev->bus->number << 16;
  76. name |= PCI_SLOT(pdev->devfn) << 8;
  77. return name | PCI_FUNC(pdev->devfn);
  78. }
  79. static u64
  80. nouveau_platform_name(struct platform_device *platformdev)
  81. {
  82. return platformdev->id;
  83. }
  84. static u64
  85. nouveau_name(struct drm_device *dev)
  86. {
  87. if (dev->pdev)
  88. return nouveau_pci_name(dev->pdev);
  89. else
  90. return nouveau_platform_name(dev->platformdev);
  91. }
  92. static int
  93. nouveau_cli_create(u64 name, const char *sname,
  94. int size, void **pcli)
  95. {
  96. struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
  97. if (cli) {
  98. int ret = nvif_client_init(NULL, NULL, sname, name,
  99. nouveau_config, nouveau_debug,
  100. &cli->base);
  101. if (ret == 0) {
  102. mutex_init(&cli->mutex);
  103. usif_client_init(cli);
  104. }
  105. return ret;
  106. }
  107. return -ENOMEM;
  108. }
  109. static void
  110. nouveau_cli_destroy(struct nouveau_cli *cli)
  111. {
  112. nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
  113. nvif_client_fini(&cli->base);
  114. usif_client_fini(cli);
  115. }
  116. static void
  117. nouveau_accel_fini(struct nouveau_drm *drm)
  118. {
  119. nouveau_channel_del(&drm->channel);
  120. nvif_object_fini(&drm->ntfy);
  121. nvkm_gpuobj_ref(NULL, &drm->notify);
  122. nvif_object_fini(&drm->nvsw);
  123. nouveau_channel_del(&drm->cechan);
  124. nvif_object_fini(&drm->ttm.copy);
  125. if (drm->fence)
  126. nouveau_fence(drm)->dtor(drm);
  127. }
  128. static void
  129. nouveau_accel_init(struct nouveau_drm *drm)
  130. {
  131. struct nvif_device *device = &drm->device;
  132. u32 arg0, arg1;
  133. u32 sclass[16];
  134. int ret, i;
  135. if (nouveau_noaccel)
  136. return;
  137. /* initialise synchronisation routines */
  138. /*XXX: this is crap, but the fence/channel stuff is a little
  139. * backwards in some places. this will be fixed.
  140. */
  141. ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass));
  142. if (ret < 0)
  143. return;
  144. for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) {
  145. switch (sclass[i]) {
  146. case NV03_CHANNEL_DMA:
  147. ret = nv04_fence_create(drm);
  148. break;
  149. case NV10_CHANNEL_DMA:
  150. ret = nv10_fence_create(drm);
  151. break;
  152. case NV17_CHANNEL_DMA:
  153. case NV40_CHANNEL_DMA:
  154. ret = nv17_fence_create(drm);
  155. break;
  156. case NV50_CHANNEL_GPFIFO:
  157. ret = nv50_fence_create(drm);
  158. break;
  159. case G82_CHANNEL_GPFIFO:
  160. ret = nv84_fence_create(drm);
  161. break;
  162. case FERMI_CHANNEL_GPFIFO:
  163. case KEPLER_CHANNEL_GPFIFO_A:
  164. case MAXWELL_CHANNEL_GPFIFO_A:
  165. ret = nvc0_fence_create(drm);
  166. break;
  167. default:
  168. break;
  169. }
  170. }
  171. if (ret) {
  172. NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
  173. nouveau_accel_fini(drm);
  174. return;
  175. }
  176. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  177. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
  178. KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0|
  179. KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1,
  180. 0, &drm->cechan);
  181. if (ret)
  182. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  183. arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR;
  184. arg1 = 1;
  185. } else
  186. if (device->info.chipset >= 0xa3 &&
  187. device->info.chipset != 0xaa &&
  188. device->info.chipset != 0xac) {
  189. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
  190. NvDmaFB, NvDmaTT, &drm->cechan);
  191. if (ret)
  192. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  193. arg0 = NvDmaFB;
  194. arg1 = NvDmaTT;
  195. } else {
  196. arg0 = NvDmaFB;
  197. arg1 = NvDmaTT;
  198. }
  199. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1,
  200. &drm->channel);
  201. if (ret) {
  202. NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
  203. nouveau_accel_fini(drm);
  204. return;
  205. }
  206. ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
  207. nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
  208. if (ret == 0) {
  209. struct nvkm_sw_chan *swch;
  210. ret = RING_SPACE(drm->channel, 2);
  211. if (ret == 0) {
  212. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  213. BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
  214. OUT_RING (drm->channel, NVDRM_NVSW);
  215. } else
  216. if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
  217. BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
  218. OUT_RING (drm->channel, 0x001f0000);
  219. }
  220. }
  221. swch = (void *)nvxx_object(&drm->nvsw)->parent;
  222. swch->flip = nouveau_flip_complete;
  223. swch->flip_data = drm->channel;
  224. }
  225. if (ret) {
  226. NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
  227. nouveau_accel_fini(drm);
  228. return;
  229. }
  230. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  231. ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
  232. 0, 0, &drm->notify);
  233. if (ret) {
  234. NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
  235. nouveau_accel_fini(drm);
  236. return;
  237. }
  238. ret = nvif_object_init(drm->channel->object, NULL, NvNotify0,
  239. NV_DMA_IN_MEMORY,
  240. &(struct nv_dma_v0) {
  241. .target = NV_DMA_V0_TARGET_VRAM,
  242. .access = NV_DMA_V0_ACCESS_RDWR,
  243. .start = drm->notify->addr,
  244. .limit = drm->notify->addr + 31
  245. }, sizeof(struct nv_dma_v0),
  246. &drm->ntfy);
  247. if (ret) {
  248. nouveau_accel_fini(drm);
  249. return;
  250. }
  251. }
  252. nouveau_bo_move_init(drm);
  253. }
  254. static int nouveau_drm_probe(struct pci_dev *pdev,
  255. const struct pci_device_id *pent)
  256. {
  257. struct nvkm_device *device;
  258. struct apertures_struct *aper;
  259. bool boot = false;
  260. int ret;
  261. /* remove conflicting drivers (vesafb, efifb etc) */
  262. aper = alloc_apertures(3);
  263. if (!aper)
  264. return -ENOMEM;
  265. aper->ranges[0].base = pci_resource_start(pdev, 1);
  266. aper->ranges[0].size = pci_resource_len(pdev, 1);
  267. aper->count = 1;
  268. if (pci_resource_len(pdev, 2)) {
  269. aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
  270. aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
  271. aper->count++;
  272. }
  273. if (pci_resource_len(pdev, 3)) {
  274. aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
  275. aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
  276. aper->count++;
  277. }
  278. #ifdef CONFIG_X86
  279. boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  280. #endif
  281. if (nouveau_modeset != 2)
  282. remove_conflicting_framebuffers(aper, "nouveaufb", boot);
  283. kfree(aper);
  284. ret = nvkm_device_create(pdev, NVKM_BUS_PCI,
  285. nouveau_pci_name(pdev), pci_name(pdev),
  286. nouveau_config, nouveau_debug, &device);
  287. if (ret)
  288. return ret;
  289. pci_set_master(pdev);
  290. ret = drm_get_pci_dev(pdev, pent, &driver_pci);
  291. if (ret) {
  292. nvkm_object_ref(NULL, (struct nvkm_object **)&device);
  293. return ret;
  294. }
  295. return 0;
  296. }
  297. #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
  298. static void
  299. nouveau_get_hdmi_dev(struct nouveau_drm *drm)
  300. {
  301. struct pci_dev *pdev = drm->dev->pdev;
  302. if (!pdev) {
  303. DRM_INFO("not a PCI device; no HDMI\n");
  304. drm->hdmi_device = NULL;
  305. return;
  306. }
  307. /* subfunction one is a hdmi audio device? */
  308. drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
  309. PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
  310. if (!drm->hdmi_device) {
  311. NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
  312. return;
  313. }
  314. if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
  315. NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
  316. pci_dev_put(drm->hdmi_device);
  317. drm->hdmi_device = NULL;
  318. return;
  319. }
  320. }
  321. static int
  322. nouveau_drm_load(struct drm_device *dev, unsigned long flags)
  323. {
  324. struct pci_dev *pdev = dev->pdev;
  325. struct nouveau_drm *drm;
  326. int ret;
  327. ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm),
  328. (void **)&drm);
  329. if (ret)
  330. return ret;
  331. dev->dev_private = drm;
  332. drm->dev = dev;
  333. nvxx_client(&drm->client.base)->debug =
  334. nvkm_dbgopt(nouveau_debug, "DRM");
  335. INIT_LIST_HEAD(&drm->clients);
  336. spin_lock_init(&drm->tile.lock);
  337. nouveau_get_hdmi_dev(drm);
  338. /* make sure AGP controller is in a consistent state before we
  339. * (possibly) execute vbios init tables (see nouveau_agp.h)
  340. */
  341. if (pdev && drm_pci_device_is_agp(dev) && dev->agp) {
  342. const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY |
  343. NV_DEVICE_V0_DISABLE_MMIO;
  344. /* dummy device object, doesn't init anything, but allows
  345. * agp code access to registers
  346. */
  347. ret = nvif_device_init(&drm->client.base.base, NULL,
  348. NVDRM_DEVICE, NV_DEVICE,
  349. &(struct nv_device_v0) {
  350. .device = ~0,
  351. .disable = ~enables,
  352. .debug0 = ~0,
  353. }, sizeof(struct nv_device_v0),
  354. &drm->device);
  355. if (ret)
  356. goto fail_device;
  357. nouveau_agp_reset(drm);
  358. nvif_device_fini(&drm->device);
  359. }
  360. ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE,
  361. NV_DEVICE,
  362. &(struct nv_device_v0) {
  363. .device = ~0,
  364. .disable = 0,
  365. .debug0 = 0,
  366. }, sizeof(struct nv_device_v0),
  367. &drm->device);
  368. if (ret)
  369. goto fail_device;
  370. dev->irq_enabled = true;
  371. /* workaround an odd issue on nvc1 by disabling the device's
  372. * nosnoop capability. hopefully won't cause issues until a
  373. * better fix is found - assuming there is one...
  374. */
  375. if (drm->device.info.chipset == 0xc1)
  376. nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000);
  377. nouveau_vga_init(drm);
  378. nouveau_agp_init(drm);
  379. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  380. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  381. 0x1000, &drm->client.vm);
  382. if (ret)
  383. goto fail_device;
  384. nvxx_client(&drm->client.base)->vm = drm->client.vm;
  385. }
  386. ret = nouveau_ttm_init(drm);
  387. if (ret)
  388. goto fail_ttm;
  389. ret = nouveau_bios_init(dev);
  390. if (ret)
  391. goto fail_bios;
  392. ret = nouveau_display_create(dev);
  393. if (ret)
  394. goto fail_dispctor;
  395. if (dev->mode_config.num_crtc) {
  396. ret = nouveau_display_init(dev);
  397. if (ret)
  398. goto fail_dispinit;
  399. }
  400. nouveau_sysfs_init(dev);
  401. nouveau_hwmon_init(dev);
  402. nouveau_accel_init(drm);
  403. nouveau_fbcon_init(dev);
  404. if (nouveau_runtime_pm != 0) {
  405. pm_runtime_use_autosuspend(dev->dev);
  406. pm_runtime_set_autosuspend_delay(dev->dev, 5000);
  407. pm_runtime_set_active(dev->dev);
  408. pm_runtime_allow(dev->dev);
  409. pm_runtime_mark_last_busy(dev->dev);
  410. pm_runtime_put(dev->dev);
  411. }
  412. return 0;
  413. fail_dispinit:
  414. nouveau_display_destroy(dev);
  415. fail_dispctor:
  416. nouveau_bios_takedown(dev);
  417. fail_bios:
  418. nouveau_ttm_fini(drm);
  419. fail_ttm:
  420. nouveau_agp_fini(drm);
  421. nouveau_vga_fini(drm);
  422. fail_device:
  423. nvif_device_fini(&drm->device);
  424. nouveau_cli_destroy(&drm->client);
  425. return ret;
  426. }
  427. static int
  428. nouveau_drm_unload(struct drm_device *dev)
  429. {
  430. struct nouveau_drm *drm = nouveau_drm(dev);
  431. pm_runtime_get_sync(dev->dev);
  432. nouveau_fbcon_fini(dev);
  433. nouveau_accel_fini(drm);
  434. nouveau_hwmon_fini(dev);
  435. nouveau_sysfs_fini(dev);
  436. if (dev->mode_config.num_crtc)
  437. nouveau_display_fini(dev);
  438. nouveau_display_destroy(dev);
  439. nouveau_bios_takedown(dev);
  440. nouveau_ttm_fini(drm);
  441. nouveau_agp_fini(drm);
  442. nouveau_vga_fini(drm);
  443. nvif_device_fini(&drm->device);
  444. if (drm->hdmi_device)
  445. pci_dev_put(drm->hdmi_device);
  446. nouveau_cli_destroy(&drm->client);
  447. return 0;
  448. }
  449. void
  450. nouveau_drm_device_remove(struct drm_device *dev)
  451. {
  452. struct nouveau_drm *drm = nouveau_drm(dev);
  453. struct nvkm_client *client;
  454. struct nvkm_object *device;
  455. dev->irq_enabled = false;
  456. client = nvxx_client(&drm->client.base);
  457. device = client->device;
  458. drm_put_dev(dev);
  459. nvkm_object_ref(NULL, &device);
  460. nvkm_object_debug();
  461. }
  462. static void
  463. nouveau_drm_remove(struct pci_dev *pdev)
  464. {
  465. struct drm_device *dev = pci_get_drvdata(pdev);
  466. nouveau_drm_device_remove(dev);
  467. }
  468. static int
  469. nouveau_do_suspend(struct drm_device *dev, bool runtime)
  470. {
  471. struct nouveau_drm *drm = nouveau_drm(dev);
  472. struct nouveau_cli *cli;
  473. int ret;
  474. if (dev->mode_config.num_crtc) {
  475. NV_INFO(drm, "suspending console...\n");
  476. nouveau_fbcon_set_suspend(dev, 1);
  477. NV_INFO(drm, "suspending display...\n");
  478. ret = nouveau_display_suspend(dev, runtime);
  479. if (ret)
  480. return ret;
  481. }
  482. NV_INFO(drm, "evicting buffers...\n");
  483. ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  484. NV_INFO(drm, "waiting for kernel channels to go idle...\n");
  485. if (drm->cechan) {
  486. ret = nouveau_channel_idle(drm->cechan);
  487. if (ret)
  488. goto fail_display;
  489. }
  490. if (drm->channel) {
  491. ret = nouveau_channel_idle(drm->channel);
  492. if (ret)
  493. goto fail_display;
  494. }
  495. NV_INFO(drm, "suspending client object trees...\n");
  496. if (drm->fence && nouveau_fence(drm)->suspend) {
  497. if (!nouveau_fence(drm)->suspend(drm)) {
  498. ret = -ENOMEM;
  499. goto fail_display;
  500. }
  501. }
  502. list_for_each_entry(cli, &drm->clients, head) {
  503. ret = nvif_client_suspend(&cli->base);
  504. if (ret)
  505. goto fail_client;
  506. }
  507. NV_INFO(drm, "suspending kernel object tree...\n");
  508. ret = nvif_client_suspend(&drm->client.base);
  509. if (ret)
  510. goto fail_client;
  511. nouveau_agp_fini(drm);
  512. return 0;
  513. fail_client:
  514. list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
  515. nvif_client_resume(&cli->base);
  516. }
  517. if (drm->fence && nouveau_fence(drm)->resume)
  518. nouveau_fence(drm)->resume(drm);
  519. fail_display:
  520. if (dev->mode_config.num_crtc) {
  521. NV_INFO(drm, "resuming display...\n");
  522. nouveau_display_resume(dev, runtime);
  523. }
  524. return ret;
  525. }
  526. static int
  527. nouveau_do_resume(struct drm_device *dev, bool runtime)
  528. {
  529. struct nouveau_drm *drm = nouveau_drm(dev);
  530. struct nouveau_cli *cli;
  531. NV_INFO(drm, "re-enabling device...\n");
  532. nouveau_agp_reset(drm);
  533. NV_INFO(drm, "resuming kernel object tree...\n");
  534. nvif_client_resume(&drm->client.base);
  535. nouveau_agp_init(drm);
  536. NV_INFO(drm, "resuming client object trees...\n");
  537. if (drm->fence && nouveau_fence(drm)->resume)
  538. nouveau_fence(drm)->resume(drm);
  539. list_for_each_entry(cli, &drm->clients, head) {
  540. nvif_client_resume(&cli->base);
  541. }
  542. nouveau_run_vbios_init(dev);
  543. if (dev->mode_config.num_crtc) {
  544. NV_INFO(drm, "resuming display...\n");
  545. nouveau_display_resume(dev, runtime);
  546. NV_INFO(drm, "resuming console...\n");
  547. nouveau_fbcon_set_suspend(dev, 0);
  548. }
  549. return 0;
  550. }
  551. int
  552. nouveau_pmops_suspend(struct device *dev)
  553. {
  554. struct pci_dev *pdev = to_pci_dev(dev);
  555. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  556. int ret;
  557. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  558. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  559. return 0;
  560. ret = nouveau_do_suspend(drm_dev, false);
  561. if (ret)
  562. return ret;
  563. pci_save_state(pdev);
  564. pci_disable_device(pdev);
  565. pci_set_power_state(pdev, PCI_D3hot);
  566. return 0;
  567. }
  568. int
  569. nouveau_pmops_resume(struct device *dev)
  570. {
  571. struct pci_dev *pdev = to_pci_dev(dev);
  572. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  573. int ret;
  574. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  575. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  576. return 0;
  577. pci_set_power_state(pdev, PCI_D0);
  578. pci_restore_state(pdev);
  579. ret = pci_enable_device(pdev);
  580. if (ret)
  581. return ret;
  582. pci_set_master(pdev);
  583. return nouveau_do_resume(drm_dev, false);
  584. }
  585. static int
  586. nouveau_pmops_freeze(struct device *dev)
  587. {
  588. struct pci_dev *pdev = to_pci_dev(dev);
  589. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  590. return nouveau_do_suspend(drm_dev, false);
  591. }
  592. static int
  593. nouveau_pmops_thaw(struct device *dev)
  594. {
  595. struct pci_dev *pdev = to_pci_dev(dev);
  596. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  597. return nouveau_do_resume(drm_dev, false);
  598. }
  599. static int
  600. nouveau_pmops_runtime_suspend(struct device *dev)
  601. {
  602. struct pci_dev *pdev = to_pci_dev(dev);
  603. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  604. int ret;
  605. if (nouveau_runtime_pm == 0) {
  606. pm_runtime_forbid(dev);
  607. return -EBUSY;
  608. }
  609. /* are we optimus enabled? */
  610. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  611. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  612. pm_runtime_forbid(dev);
  613. return -EBUSY;
  614. }
  615. nv_debug_level(SILENT);
  616. drm_kms_helper_poll_disable(drm_dev);
  617. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  618. nouveau_switcheroo_optimus_dsm();
  619. ret = nouveau_do_suspend(drm_dev, true);
  620. pci_save_state(pdev);
  621. pci_disable_device(pdev);
  622. pci_ignore_hotplug(pdev);
  623. pci_set_power_state(pdev, PCI_D3cold);
  624. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  625. return ret;
  626. }
  627. static int
  628. nouveau_pmops_runtime_resume(struct device *dev)
  629. {
  630. struct pci_dev *pdev = to_pci_dev(dev);
  631. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  632. struct nvif_device *device = &nouveau_drm(drm_dev)->device;
  633. int ret;
  634. if (nouveau_runtime_pm == 0)
  635. return -EINVAL;
  636. pci_set_power_state(pdev, PCI_D0);
  637. pci_restore_state(pdev);
  638. ret = pci_enable_device(pdev);
  639. if (ret)
  640. return ret;
  641. pci_set_master(pdev);
  642. ret = nouveau_do_resume(drm_dev, true);
  643. drm_kms_helper_poll_enable(drm_dev);
  644. /* do magic */
  645. nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
  646. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  647. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  648. nv_debug_level(NORMAL);
  649. return ret;
  650. }
  651. static int
  652. nouveau_pmops_runtime_idle(struct device *dev)
  653. {
  654. struct pci_dev *pdev = to_pci_dev(dev);
  655. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  656. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  657. struct drm_crtc *crtc;
  658. if (nouveau_runtime_pm == 0) {
  659. pm_runtime_forbid(dev);
  660. return -EBUSY;
  661. }
  662. /* are we optimus enabled? */
  663. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  664. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  665. pm_runtime_forbid(dev);
  666. return -EBUSY;
  667. }
  668. /* if we have a hdmi audio device - make sure it has a driver loaded */
  669. if (drm->hdmi_device) {
  670. if (!drm->hdmi_device->driver) {
  671. DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
  672. pm_runtime_mark_last_busy(dev);
  673. return -EBUSY;
  674. }
  675. }
  676. list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
  677. if (crtc->enabled) {
  678. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  679. return -EBUSY;
  680. }
  681. }
  682. pm_runtime_mark_last_busy(dev);
  683. pm_runtime_autosuspend(dev);
  684. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  685. return 1;
  686. }
  687. static int
  688. nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
  689. {
  690. struct nouveau_drm *drm = nouveau_drm(dev);
  691. struct nouveau_cli *cli;
  692. char name[32], tmpname[TASK_COMM_LEN];
  693. int ret;
  694. /* need to bring up power immediately if opening device */
  695. ret = pm_runtime_get_sync(dev->dev);
  696. if (ret < 0 && ret != -EACCES)
  697. return ret;
  698. get_task_comm(tmpname, current);
  699. snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
  700. ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli),
  701. (void **)&cli);
  702. if (ret)
  703. goto out_suspend;
  704. cli->base.super = false;
  705. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  706. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  707. 0x1000, &cli->vm);
  708. if (ret) {
  709. nouveau_cli_destroy(cli);
  710. goto out_suspend;
  711. }
  712. nvxx_client(&cli->base)->vm = cli->vm;
  713. }
  714. fpriv->driver_priv = cli;
  715. mutex_lock(&drm->client.mutex);
  716. list_add(&cli->head, &drm->clients);
  717. mutex_unlock(&drm->client.mutex);
  718. out_suspend:
  719. pm_runtime_mark_last_busy(dev->dev);
  720. pm_runtime_put_autosuspend(dev->dev);
  721. return ret;
  722. }
  723. static void
  724. nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
  725. {
  726. struct nouveau_cli *cli = nouveau_cli(fpriv);
  727. struct nouveau_drm *drm = nouveau_drm(dev);
  728. pm_runtime_get_sync(dev->dev);
  729. if (cli->abi16)
  730. nouveau_abi16_fini(cli->abi16);
  731. mutex_lock(&drm->client.mutex);
  732. list_del(&cli->head);
  733. mutex_unlock(&drm->client.mutex);
  734. }
  735. static void
  736. nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
  737. {
  738. struct nouveau_cli *cli = nouveau_cli(fpriv);
  739. nouveau_cli_destroy(cli);
  740. pm_runtime_mark_last_busy(dev->dev);
  741. pm_runtime_put_autosuspend(dev->dev);
  742. }
  743. static const struct drm_ioctl_desc
  744. nouveau_ioctls[] = {
  745. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  746. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  747. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  748. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  749. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  750. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  751. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  752. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  753. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  754. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  755. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  756. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  757. };
  758. long
  759. nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  760. {
  761. struct drm_file *filp = file->private_data;
  762. struct drm_device *dev = filp->minor->dev;
  763. long ret;
  764. ret = pm_runtime_get_sync(dev->dev);
  765. if (ret < 0 && ret != -EACCES)
  766. return ret;
  767. switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
  768. case DRM_NOUVEAU_NVIF:
  769. ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
  770. break;
  771. default:
  772. ret = drm_ioctl(file, cmd, arg);
  773. break;
  774. }
  775. pm_runtime_mark_last_busy(dev->dev);
  776. pm_runtime_put_autosuspend(dev->dev);
  777. return ret;
  778. }
  779. static const struct file_operations
  780. nouveau_driver_fops = {
  781. .owner = THIS_MODULE,
  782. .open = drm_open,
  783. .release = drm_release,
  784. .unlocked_ioctl = nouveau_drm_ioctl,
  785. .mmap = nouveau_ttm_mmap,
  786. .poll = drm_poll,
  787. .read = drm_read,
  788. #if defined(CONFIG_COMPAT)
  789. .compat_ioctl = nouveau_compat_ioctl,
  790. #endif
  791. .llseek = noop_llseek,
  792. };
  793. static struct drm_driver
  794. driver_stub = {
  795. .driver_features =
  796. DRIVER_USE_AGP |
  797. DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
  798. .load = nouveau_drm_load,
  799. .unload = nouveau_drm_unload,
  800. .open = nouveau_drm_open,
  801. .preclose = nouveau_drm_preclose,
  802. .postclose = nouveau_drm_postclose,
  803. .lastclose = nouveau_vga_lastclose,
  804. #if defined(CONFIG_DEBUG_FS)
  805. .debugfs_init = nouveau_debugfs_init,
  806. .debugfs_cleanup = nouveau_debugfs_takedown,
  807. #endif
  808. .get_vblank_counter = drm_vblank_count,
  809. .enable_vblank = nouveau_display_vblank_enable,
  810. .disable_vblank = nouveau_display_vblank_disable,
  811. .get_scanout_position = nouveau_display_scanoutpos,
  812. .get_vblank_timestamp = nouveau_display_vblstamp,
  813. .ioctls = nouveau_ioctls,
  814. .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
  815. .fops = &nouveau_driver_fops,
  816. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  817. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  818. .gem_prime_export = drm_gem_prime_export,
  819. .gem_prime_import = drm_gem_prime_import,
  820. .gem_prime_pin = nouveau_gem_prime_pin,
  821. .gem_prime_res_obj = nouveau_gem_prime_res_obj,
  822. .gem_prime_unpin = nouveau_gem_prime_unpin,
  823. .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
  824. .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
  825. .gem_prime_vmap = nouveau_gem_prime_vmap,
  826. .gem_prime_vunmap = nouveau_gem_prime_vunmap,
  827. .gem_free_object = nouveau_gem_object_del,
  828. .gem_open_object = nouveau_gem_object_open,
  829. .gem_close_object = nouveau_gem_object_close,
  830. .dumb_create = nouveau_display_dumb_create,
  831. .dumb_map_offset = nouveau_display_dumb_map_offset,
  832. .dumb_destroy = drm_gem_dumb_destroy,
  833. .name = DRIVER_NAME,
  834. .desc = DRIVER_DESC,
  835. #ifdef GIT_REVISION
  836. .date = GIT_REVISION,
  837. #else
  838. .date = DRIVER_DATE,
  839. #endif
  840. .major = DRIVER_MAJOR,
  841. .minor = DRIVER_MINOR,
  842. .patchlevel = DRIVER_PATCHLEVEL,
  843. };
  844. static struct pci_device_id
  845. nouveau_drm_pci_table[] = {
  846. {
  847. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  848. .class = PCI_BASE_CLASS_DISPLAY << 16,
  849. .class_mask = 0xff << 16,
  850. },
  851. {
  852. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  853. .class = PCI_BASE_CLASS_DISPLAY << 16,
  854. .class_mask = 0xff << 16,
  855. },
  856. {}
  857. };
  858. static void nouveau_display_options(void)
  859. {
  860. DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
  861. DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
  862. DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
  863. DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
  864. DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
  865. DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
  866. DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
  867. DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
  868. DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
  869. DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
  870. DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
  871. DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate);
  872. }
  873. static const struct dev_pm_ops nouveau_pm_ops = {
  874. .suspend = nouveau_pmops_suspend,
  875. .resume = nouveau_pmops_resume,
  876. .freeze = nouveau_pmops_freeze,
  877. .thaw = nouveau_pmops_thaw,
  878. .poweroff = nouveau_pmops_freeze,
  879. .restore = nouveau_pmops_resume,
  880. .runtime_suspend = nouveau_pmops_runtime_suspend,
  881. .runtime_resume = nouveau_pmops_runtime_resume,
  882. .runtime_idle = nouveau_pmops_runtime_idle,
  883. };
  884. static struct pci_driver
  885. nouveau_drm_pci_driver = {
  886. .name = "nouveau",
  887. .id_table = nouveau_drm_pci_table,
  888. .probe = nouveau_drm_probe,
  889. .remove = nouveau_drm_remove,
  890. .driver.pm = &nouveau_pm_ops,
  891. };
  892. struct drm_device *
  893. nouveau_platform_device_create_(struct platform_device *pdev, int size,
  894. void **pobject)
  895. {
  896. struct drm_device *drm;
  897. int err;
  898. err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM,
  899. nouveau_platform_name(pdev),
  900. dev_name(&pdev->dev), nouveau_config,
  901. nouveau_debug, size, pobject);
  902. if (err)
  903. return ERR_PTR(err);
  904. drm = drm_dev_alloc(&driver_platform, &pdev->dev);
  905. if (!drm) {
  906. err = -ENOMEM;
  907. goto err_free;
  908. }
  909. err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev));
  910. if (err < 0)
  911. goto err_free;
  912. drm->platformdev = pdev;
  913. platform_set_drvdata(pdev, drm);
  914. return drm;
  915. err_free:
  916. nvkm_object_ref(NULL, (struct nvkm_object **)pobject);
  917. return ERR_PTR(err);
  918. }
  919. static int __init
  920. nouveau_drm_init(void)
  921. {
  922. driver_pci = driver_stub;
  923. driver_pci.set_busid = drm_pci_set_busid;
  924. driver_platform = driver_stub;
  925. driver_platform.set_busid = drm_platform_set_busid;
  926. nouveau_display_options();
  927. if (nouveau_modeset == -1) {
  928. #ifdef CONFIG_VGA_CONSOLE
  929. if (vgacon_text_force())
  930. nouveau_modeset = 0;
  931. #endif
  932. }
  933. if (!nouveau_modeset)
  934. return 0;
  935. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  936. platform_driver_register(&nouveau_platform_driver);
  937. #endif
  938. nouveau_register_dsm_handler();
  939. return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
  940. }
  941. static void __exit
  942. nouveau_drm_exit(void)
  943. {
  944. if (!nouveau_modeset)
  945. return;
  946. drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
  947. nouveau_unregister_dsm_handler();
  948. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  949. platform_driver_unregister(&nouveau_platform_driver);
  950. #endif
  951. }
  952. module_init(nouveau_drm_init);
  953. module_exit(nouveau_drm_exit);
  954. MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
  955. MODULE_AUTHOR(DRIVER_AUTHOR);
  956. MODULE_DESCRIPTION(DRIVER_DESC);
  957. MODULE_LICENSE("GPL and additional rights");