exynos_drm_g2d.c 37 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  3. * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundationr
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/slab.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/dma-attrs.h>
  20. #include <linux/of.h>
  21. #include <drm/drmP.h>
  22. #include <drm/exynos_drm.h>
  23. #include "exynos_drm_drv.h"
  24. #include "exynos_drm_g2d.h"
  25. #include "exynos_drm_gem.h"
  26. #include "exynos_drm_iommu.h"
  27. #define G2D_HW_MAJOR_VER 4
  28. #define G2D_HW_MINOR_VER 1
  29. /* vaild register range set from user: 0x0104 ~ 0x0880 */
  30. #define G2D_VALID_START 0x0104
  31. #define G2D_VALID_END 0x0880
  32. /* general registers */
  33. #define G2D_SOFT_RESET 0x0000
  34. #define G2D_INTEN 0x0004
  35. #define G2D_INTC_PEND 0x000C
  36. #define G2D_DMA_SFR_BASE_ADDR 0x0080
  37. #define G2D_DMA_COMMAND 0x0084
  38. #define G2D_DMA_STATUS 0x008C
  39. #define G2D_DMA_HOLD_CMD 0x0090
  40. /* command registers */
  41. #define G2D_BITBLT_START 0x0100
  42. /* registers for base address */
  43. #define G2D_SRC_BASE_ADDR 0x0304
  44. #define G2D_SRC_COLOR_MODE 0x030C
  45. #define G2D_SRC_LEFT_TOP 0x0310
  46. #define G2D_SRC_RIGHT_BOTTOM 0x0314
  47. #define G2D_SRC_PLANE2_BASE_ADDR 0x0318
  48. #define G2D_DST_BASE_ADDR 0x0404
  49. #define G2D_DST_COLOR_MODE 0x040C
  50. #define G2D_DST_LEFT_TOP 0x0410
  51. #define G2D_DST_RIGHT_BOTTOM 0x0414
  52. #define G2D_DST_PLANE2_BASE_ADDR 0x0418
  53. #define G2D_PAT_BASE_ADDR 0x0500
  54. #define G2D_MSK_BASE_ADDR 0x0520
  55. /* G2D_SOFT_RESET */
  56. #define G2D_SFRCLEAR (1 << 1)
  57. #define G2D_R (1 << 0)
  58. /* G2D_INTEN */
  59. #define G2D_INTEN_ACF (1 << 3)
  60. #define G2D_INTEN_UCF (1 << 2)
  61. #define G2D_INTEN_GCF (1 << 1)
  62. #define G2D_INTEN_SCF (1 << 0)
  63. /* G2D_INTC_PEND */
  64. #define G2D_INTP_ACMD_FIN (1 << 3)
  65. #define G2D_INTP_UCMD_FIN (1 << 2)
  66. #define G2D_INTP_GCMD_FIN (1 << 1)
  67. #define G2D_INTP_SCMD_FIN (1 << 0)
  68. /* G2D_DMA_COMMAND */
  69. #define G2D_DMA_HALT (1 << 2)
  70. #define G2D_DMA_CONTINUE (1 << 1)
  71. #define G2D_DMA_START (1 << 0)
  72. /* G2D_DMA_STATUS */
  73. #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17)
  74. #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1)
  75. #define G2D_DMA_DONE (1 << 0)
  76. #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17
  77. /* G2D_DMA_HOLD_CMD */
  78. #define G2D_USER_HOLD (1 << 2)
  79. #define G2D_LIST_HOLD (1 << 1)
  80. #define G2D_BITBLT_HOLD (1 << 0)
  81. /* G2D_BITBLT_START */
  82. #define G2D_START_CASESEL (1 << 2)
  83. #define G2D_START_NHOLT (1 << 1)
  84. #define G2D_START_BITBLT (1 << 0)
  85. /* buffer color format */
  86. #define G2D_FMT_XRGB8888 0
  87. #define G2D_FMT_ARGB8888 1
  88. #define G2D_FMT_RGB565 2
  89. #define G2D_FMT_XRGB1555 3
  90. #define G2D_FMT_ARGB1555 4
  91. #define G2D_FMT_XRGB4444 5
  92. #define G2D_FMT_ARGB4444 6
  93. #define G2D_FMT_PACKED_RGB888 7
  94. #define G2D_FMT_A8 11
  95. #define G2D_FMT_L8 12
  96. /* buffer valid length */
  97. #define G2D_LEN_MIN 1
  98. #define G2D_LEN_MAX 8000
  99. #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4)
  100. #define G2D_CMDLIST_NUM 64
  101. #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM)
  102. #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2)
  103. /* maximum buffer pool size of userptr is 64MB as default */
  104. #define MAX_POOL (64 * 1024 * 1024)
  105. enum {
  106. BUF_TYPE_GEM = 1,
  107. BUF_TYPE_USERPTR,
  108. };
  109. enum g2d_reg_type {
  110. REG_TYPE_NONE = -1,
  111. REG_TYPE_SRC,
  112. REG_TYPE_SRC_PLANE2,
  113. REG_TYPE_DST,
  114. REG_TYPE_DST_PLANE2,
  115. REG_TYPE_PAT,
  116. REG_TYPE_MSK,
  117. MAX_REG_TYPE_NR
  118. };
  119. /* cmdlist data structure */
  120. struct g2d_cmdlist {
  121. u32 head;
  122. unsigned long data[G2D_CMDLIST_DATA_NUM];
  123. u32 last; /* last data offset */
  124. };
  125. /*
  126. * A structure of buffer description
  127. *
  128. * @format: color format
  129. * @left_x: the x coordinates of left top corner
  130. * @top_y: the y coordinates of left top corner
  131. * @right_x: the x coordinates of right bottom corner
  132. * @bottom_y: the y coordinates of right bottom corner
  133. *
  134. */
  135. struct g2d_buf_desc {
  136. unsigned int format;
  137. unsigned int left_x;
  138. unsigned int top_y;
  139. unsigned int right_x;
  140. unsigned int bottom_y;
  141. };
  142. /*
  143. * A structure of buffer information
  144. *
  145. * @map_nr: manages the number of mapped buffers
  146. * @reg_types: stores regitster type in the order of requested command
  147. * @handles: stores buffer handle in its reg_type position
  148. * @types: stores buffer type in its reg_type position
  149. * @descs: stores buffer description in its reg_type position
  150. *
  151. */
  152. struct g2d_buf_info {
  153. unsigned int map_nr;
  154. enum g2d_reg_type reg_types[MAX_REG_TYPE_NR];
  155. unsigned long handles[MAX_REG_TYPE_NR];
  156. unsigned int types[MAX_REG_TYPE_NR];
  157. struct g2d_buf_desc descs[MAX_REG_TYPE_NR];
  158. };
  159. struct drm_exynos_pending_g2d_event {
  160. struct drm_pending_event base;
  161. struct drm_exynos_g2d_event event;
  162. };
  163. struct g2d_cmdlist_userptr {
  164. struct list_head list;
  165. dma_addr_t dma_addr;
  166. unsigned long userptr;
  167. unsigned long size;
  168. struct page **pages;
  169. unsigned int npages;
  170. struct sg_table *sgt;
  171. struct vm_area_struct *vma;
  172. atomic_t refcount;
  173. bool in_pool;
  174. bool out_of_list;
  175. };
  176. struct g2d_cmdlist_node {
  177. struct list_head list;
  178. struct g2d_cmdlist *cmdlist;
  179. dma_addr_t dma_addr;
  180. struct g2d_buf_info buf_info;
  181. struct drm_exynos_pending_g2d_event *event;
  182. };
  183. struct g2d_runqueue_node {
  184. struct list_head list;
  185. struct list_head run_cmdlist;
  186. struct list_head event_list;
  187. struct drm_file *filp;
  188. pid_t pid;
  189. struct completion complete;
  190. int async;
  191. };
  192. struct g2d_data {
  193. struct device *dev;
  194. struct clk *gate_clk;
  195. void __iomem *regs;
  196. int irq;
  197. struct workqueue_struct *g2d_workq;
  198. struct work_struct runqueue_work;
  199. struct exynos_drm_subdrv subdrv;
  200. bool suspended;
  201. /* cmdlist */
  202. struct g2d_cmdlist_node *cmdlist_node;
  203. struct list_head free_cmdlist;
  204. struct mutex cmdlist_mutex;
  205. dma_addr_t cmdlist_pool;
  206. void *cmdlist_pool_virt;
  207. struct dma_attrs cmdlist_dma_attrs;
  208. /* runqueue*/
  209. struct g2d_runqueue_node *runqueue_node;
  210. struct list_head runqueue;
  211. struct mutex runqueue_mutex;
  212. struct kmem_cache *runqueue_slab;
  213. unsigned long current_pool;
  214. unsigned long max_pool;
  215. };
  216. static int g2d_init_cmdlist(struct g2d_data *g2d)
  217. {
  218. struct device *dev = g2d->dev;
  219. struct g2d_cmdlist_node *node = g2d->cmdlist_node;
  220. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  221. int nr;
  222. int ret;
  223. struct g2d_buf_info *buf_info;
  224. init_dma_attrs(&g2d->cmdlist_dma_attrs);
  225. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &g2d->cmdlist_dma_attrs);
  226. g2d->cmdlist_pool_virt = dma_alloc_attrs(subdrv->drm_dev->dev,
  227. G2D_CMDLIST_POOL_SIZE,
  228. &g2d->cmdlist_pool, GFP_KERNEL,
  229. &g2d->cmdlist_dma_attrs);
  230. if (!g2d->cmdlist_pool_virt) {
  231. dev_err(dev, "failed to allocate dma memory\n");
  232. return -ENOMEM;
  233. }
  234. node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
  235. if (!node) {
  236. dev_err(dev, "failed to allocate memory\n");
  237. ret = -ENOMEM;
  238. goto err;
  239. }
  240. for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) {
  241. unsigned int i;
  242. node[nr].cmdlist =
  243. g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE;
  244. node[nr].dma_addr =
  245. g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE;
  246. buf_info = &node[nr].buf_info;
  247. for (i = 0; i < MAX_REG_TYPE_NR; i++)
  248. buf_info->reg_types[i] = REG_TYPE_NONE;
  249. list_add_tail(&node[nr].list, &g2d->free_cmdlist);
  250. }
  251. return 0;
  252. err:
  253. dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE,
  254. g2d->cmdlist_pool_virt,
  255. g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs);
  256. return ret;
  257. }
  258. static void g2d_fini_cmdlist(struct g2d_data *g2d)
  259. {
  260. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  261. kfree(g2d->cmdlist_node);
  262. if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) {
  263. dma_free_attrs(subdrv->drm_dev->dev, G2D_CMDLIST_POOL_SIZE,
  264. g2d->cmdlist_pool_virt,
  265. g2d->cmdlist_pool, &g2d->cmdlist_dma_attrs);
  266. }
  267. }
  268. static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d)
  269. {
  270. struct device *dev = g2d->dev;
  271. struct g2d_cmdlist_node *node;
  272. mutex_lock(&g2d->cmdlist_mutex);
  273. if (list_empty(&g2d->free_cmdlist)) {
  274. dev_err(dev, "there is no free cmdlist\n");
  275. mutex_unlock(&g2d->cmdlist_mutex);
  276. return NULL;
  277. }
  278. node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node,
  279. list);
  280. list_del_init(&node->list);
  281. mutex_unlock(&g2d->cmdlist_mutex);
  282. return node;
  283. }
  284. static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node)
  285. {
  286. mutex_lock(&g2d->cmdlist_mutex);
  287. list_move_tail(&node->list, &g2d->free_cmdlist);
  288. mutex_unlock(&g2d->cmdlist_mutex);
  289. }
  290. static void g2d_add_cmdlist_to_inuse(struct exynos_drm_g2d_private *g2d_priv,
  291. struct g2d_cmdlist_node *node)
  292. {
  293. struct g2d_cmdlist_node *lnode;
  294. if (list_empty(&g2d_priv->inuse_cmdlist))
  295. goto add_to_list;
  296. /* this links to base address of new cmdlist */
  297. lnode = list_entry(g2d_priv->inuse_cmdlist.prev,
  298. struct g2d_cmdlist_node, list);
  299. lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr;
  300. add_to_list:
  301. list_add_tail(&node->list, &g2d_priv->inuse_cmdlist);
  302. if (node->event)
  303. list_add_tail(&node->event->base.link, &g2d_priv->event_list);
  304. }
  305. static void g2d_userptr_put_dma_addr(struct drm_device *drm_dev,
  306. unsigned long obj,
  307. bool force)
  308. {
  309. struct g2d_cmdlist_userptr *g2d_userptr =
  310. (struct g2d_cmdlist_userptr *)obj;
  311. if (!obj)
  312. return;
  313. if (force)
  314. goto out;
  315. atomic_dec(&g2d_userptr->refcount);
  316. if (atomic_read(&g2d_userptr->refcount) > 0)
  317. return;
  318. if (g2d_userptr->in_pool)
  319. return;
  320. out:
  321. exynos_gem_unmap_sgt_from_dma(drm_dev, g2d_userptr->sgt,
  322. DMA_BIDIRECTIONAL);
  323. exynos_gem_put_pages_to_userptr(g2d_userptr->pages,
  324. g2d_userptr->npages,
  325. g2d_userptr->vma);
  326. exynos_gem_put_vma(g2d_userptr->vma);
  327. if (!g2d_userptr->out_of_list)
  328. list_del_init(&g2d_userptr->list);
  329. sg_free_table(g2d_userptr->sgt);
  330. kfree(g2d_userptr->sgt);
  331. drm_free_large(g2d_userptr->pages);
  332. kfree(g2d_userptr);
  333. }
  334. static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev,
  335. unsigned long userptr,
  336. unsigned long size,
  337. struct drm_file *filp,
  338. unsigned long *obj)
  339. {
  340. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  341. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  342. struct g2d_cmdlist_userptr *g2d_userptr;
  343. struct g2d_data *g2d;
  344. struct page **pages;
  345. struct sg_table *sgt;
  346. struct vm_area_struct *vma;
  347. unsigned long start, end;
  348. unsigned int npages, offset;
  349. int ret;
  350. if (!size) {
  351. DRM_ERROR("invalid userptr size.\n");
  352. return ERR_PTR(-EINVAL);
  353. }
  354. g2d = dev_get_drvdata(g2d_priv->dev);
  355. /* check if userptr already exists in userptr_list. */
  356. list_for_each_entry(g2d_userptr, &g2d_priv->userptr_list, list) {
  357. if (g2d_userptr->userptr == userptr) {
  358. /*
  359. * also check size because there could be same address
  360. * and different size.
  361. */
  362. if (g2d_userptr->size == size) {
  363. atomic_inc(&g2d_userptr->refcount);
  364. *obj = (unsigned long)g2d_userptr;
  365. return &g2d_userptr->dma_addr;
  366. }
  367. /*
  368. * at this moment, maybe g2d dma is accessing this
  369. * g2d_userptr memory region so just remove this
  370. * g2d_userptr object from userptr_list not to be
  371. * referred again and also except it the userptr
  372. * pool to be released after the dma access completion.
  373. */
  374. g2d_userptr->out_of_list = true;
  375. g2d_userptr->in_pool = false;
  376. list_del_init(&g2d_userptr->list);
  377. break;
  378. }
  379. }
  380. g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL);
  381. if (!g2d_userptr)
  382. return ERR_PTR(-ENOMEM);
  383. atomic_set(&g2d_userptr->refcount, 1);
  384. start = userptr & PAGE_MASK;
  385. offset = userptr & ~PAGE_MASK;
  386. end = PAGE_ALIGN(userptr + size);
  387. npages = (end - start) >> PAGE_SHIFT;
  388. g2d_userptr->npages = npages;
  389. pages = drm_calloc_large(npages, sizeof(struct page *));
  390. if (!pages) {
  391. DRM_ERROR("failed to allocate pages.\n");
  392. ret = -ENOMEM;
  393. goto err_free;
  394. }
  395. down_read(&current->mm->mmap_sem);
  396. vma = find_vma(current->mm, userptr);
  397. if (!vma) {
  398. up_read(&current->mm->mmap_sem);
  399. DRM_ERROR("failed to get vm region.\n");
  400. ret = -EFAULT;
  401. goto err_free_pages;
  402. }
  403. if (vma->vm_end < userptr + size) {
  404. up_read(&current->mm->mmap_sem);
  405. DRM_ERROR("vma is too small.\n");
  406. ret = -EFAULT;
  407. goto err_free_pages;
  408. }
  409. g2d_userptr->vma = exynos_gem_get_vma(vma);
  410. if (!g2d_userptr->vma) {
  411. up_read(&current->mm->mmap_sem);
  412. DRM_ERROR("failed to copy vma.\n");
  413. ret = -ENOMEM;
  414. goto err_free_pages;
  415. }
  416. g2d_userptr->size = size;
  417. ret = exynos_gem_get_pages_from_userptr(start & PAGE_MASK,
  418. npages, pages, vma);
  419. if (ret < 0) {
  420. up_read(&current->mm->mmap_sem);
  421. DRM_ERROR("failed to get user pages from userptr.\n");
  422. goto err_put_vma;
  423. }
  424. up_read(&current->mm->mmap_sem);
  425. g2d_userptr->pages = pages;
  426. sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
  427. if (!sgt) {
  428. ret = -ENOMEM;
  429. goto err_free_userptr;
  430. }
  431. ret = sg_alloc_table_from_pages(sgt, pages, npages, offset,
  432. size, GFP_KERNEL);
  433. if (ret < 0) {
  434. DRM_ERROR("failed to get sgt from pages.\n");
  435. goto err_free_sgt;
  436. }
  437. g2d_userptr->sgt = sgt;
  438. ret = exynos_gem_map_sgt_with_dma(drm_dev, g2d_userptr->sgt,
  439. DMA_BIDIRECTIONAL);
  440. if (ret < 0) {
  441. DRM_ERROR("failed to map sgt with dma region.\n");
  442. goto err_sg_free_table;
  443. }
  444. g2d_userptr->dma_addr = sgt->sgl[0].dma_address;
  445. g2d_userptr->userptr = userptr;
  446. list_add_tail(&g2d_userptr->list, &g2d_priv->userptr_list);
  447. if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) {
  448. g2d->current_pool += npages << PAGE_SHIFT;
  449. g2d_userptr->in_pool = true;
  450. }
  451. *obj = (unsigned long)g2d_userptr;
  452. return &g2d_userptr->dma_addr;
  453. err_sg_free_table:
  454. sg_free_table(sgt);
  455. err_free_sgt:
  456. kfree(sgt);
  457. err_free_userptr:
  458. exynos_gem_put_pages_to_userptr(g2d_userptr->pages,
  459. g2d_userptr->npages,
  460. g2d_userptr->vma);
  461. err_put_vma:
  462. exynos_gem_put_vma(g2d_userptr->vma);
  463. err_free_pages:
  464. drm_free_large(pages);
  465. err_free:
  466. kfree(g2d_userptr);
  467. return ERR_PTR(ret);
  468. }
  469. static void g2d_userptr_free_all(struct drm_device *drm_dev,
  470. struct g2d_data *g2d,
  471. struct drm_file *filp)
  472. {
  473. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  474. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  475. struct g2d_cmdlist_userptr *g2d_userptr, *n;
  476. list_for_each_entry_safe(g2d_userptr, n, &g2d_priv->userptr_list, list)
  477. if (g2d_userptr->in_pool)
  478. g2d_userptr_put_dma_addr(drm_dev,
  479. (unsigned long)g2d_userptr,
  480. true);
  481. g2d->current_pool = 0;
  482. }
  483. static enum g2d_reg_type g2d_get_reg_type(int reg_offset)
  484. {
  485. enum g2d_reg_type reg_type;
  486. switch (reg_offset) {
  487. case G2D_SRC_BASE_ADDR:
  488. case G2D_SRC_COLOR_MODE:
  489. case G2D_SRC_LEFT_TOP:
  490. case G2D_SRC_RIGHT_BOTTOM:
  491. reg_type = REG_TYPE_SRC;
  492. break;
  493. case G2D_SRC_PLANE2_BASE_ADDR:
  494. reg_type = REG_TYPE_SRC_PLANE2;
  495. break;
  496. case G2D_DST_BASE_ADDR:
  497. case G2D_DST_COLOR_MODE:
  498. case G2D_DST_LEFT_TOP:
  499. case G2D_DST_RIGHT_BOTTOM:
  500. reg_type = REG_TYPE_DST;
  501. break;
  502. case G2D_DST_PLANE2_BASE_ADDR:
  503. reg_type = REG_TYPE_DST_PLANE2;
  504. break;
  505. case G2D_PAT_BASE_ADDR:
  506. reg_type = REG_TYPE_PAT;
  507. break;
  508. case G2D_MSK_BASE_ADDR:
  509. reg_type = REG_TYPE_MSK;
  510. break;
  511. default:
  512. reg_type = REG_TYPE_NONE;
  513. DRM_ERROR("Unknown register offset![%d]\n", reg_offset);
  514. break;
  515. }
  516. return reg_type;
  517. }
  518. static unsigned long g2d_get_buf_bpp(unsigned int format)
  519. {
  520. unsigned long bpp;
  521. switch (format) {
  522. case G2D_FMT_XRGB8888:
  523. case G2D_FMT_ARGB8888:
  524. bpp = 4;
  525. break;
  526. case G2D_FMT_RGB565:
  527. case G2D_FMT_XRGB1555:
  528. case G2D_FMT_ARGB1555:
  529. case G2D_FMT_XRGB4444:
  530. case G2D_FMT_ARGB4444:
  531. bpp = 2;
  532. break;
  533. case G2D_FMT_PACKED_RGB888:
  534. bpp = 3;
  535. break;
  536. default:
  537. bpp = 1;
  538. break;
  539. }
  540. return bpp;
  541. }
  542. static bool g2d_check_buf_desc_is_valid(struct g2d_buf_desc *buf_desc,
  543. enum g2d_reg_type reg_type,
  544. unsigned long size)
  545. {
  546. unsigned int width, height;
  547. unsigned long area;
  548. /*
  549. * check source and destination buffers only.
  550. * so the others are always valid.
  551. */
  552. if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST)
  553. return true;
  554. width = buf_desc->right_x - buf_desc->left_x;
  555. if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) {
  556. DRM_ERROR("width[%u] is out of range!\n", width);
  557. return false;
  558. }
  559. height = buf_desc->bottom_y - buf_desc->top_y;
  560. if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) {
  561. DRM_ERROR("height[%u] is out of range!\n", height);
  562. return false;
  563. }
  564. area = (unsigned long)width * (unsigned long)height *
  565. g2d_get_buf_bpp(buf_desc->format);
  566. if (area > size) {
  567. DRM_ERROR("area[%lu] is out of range[%lu]!\n", area, size);
  568. return false;
  569. }
  570. return true;
  571. }
  572. static int g2d_map_cmdlist_gem(struct g2d_data *g2d,
  573. struct g2d_cmdlist_node *node,
  574. struct drm_device *drm_dev,
  575. struct drm_file *file)
  576. {
  577. struct g2d_cmdlist *cmdlist = node->cmdlist;
  578. struct g2d_buf_info *buf_info = &node->buf_info;
  579. int offset;
  580. int ret;
  581. int i;
  582. for (i = 0; i < buf_info->map_nr; i++) {
  583. struct g2d_buf_desc *buf_desc;
  584. enum g2d_reg_type reg_type;
  585. int reg_pos;
  586. unsigned long handle;
  587. dma_addr_t *addr;
  588. reg_pos = cmdlist->last - 2 * (i + 1);
  589. offset = cmdlist->data[reg_pos];
  590. handle = cmdlist->data[reg_pos + 1];
  591. reg_type = g2d_get_reg_type(offset);
  592. if (reg_type == REG_TYPE_NONE) {
  593. ret = -EFAULT;
  594. goto err;
  595. }
  596. buf_desc = &buf_info->descs[reg_type];
  597. if (buf_info->types[reg_type] == BUF_TYPE_GEM) {
  598. unsigned long size;
  599. size = exynos_drm_gem_get_size(drm_dev, handle, file);
  600. if (!size) {
  601. ret = -EFAULT;
  602. goto err;
  603. }
  604. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  605. size)) {
  606. ret = -EFAULT;
  607. goto err;
  608. }
  609. addr = exynos_drm_gem_get_dma_addr(drm_dev, handle,
  610. file);
  611. if (IS_ERR(addr)) {
  612. ret = -EFAULT;
  613. goto err;
  614. }
  615. } else {
  616. struct drm_exynos_g2d_userptr g2d_userptr;
  617. if (copy_from_user(&g2d_userptr, (void __user *)handle,
  618. sizeof(struct drm_exynos_g2d_userptr))) {
  619. ret = -EFAULT;
  620. goto err;
  621. }
  622. if (!g2d_check_buf_desc_is_valid(buf_desc, reg_type,
  623. g2d_userptr.size)) {
  624. ret = -EFAULT;
  625. goto err;
  626. }
  627. addr = g2d_userptr_get_dma_addr(drm_dev,
  628. g2d_userptr.userptr,
  629. g2d_userptr.size,
  630. file,
  631. &handle);
  632. if (IS_ERR(addr)) {
  633. ret = -EFAULT;
  634. goto err;
  635. }
  636. }
  637. cmdlist->data[reg_pos + 1] = *addr;
  638. buf_info->reg_types[i] = reg_type;
  639. buf_info->handles[reg_type] = handle;
  640. }
  641. return 0;
  642. err:
  643. buf_info->map_nr = i;
  644. return ret;
  645. }
  646. static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d,
  647. struct g2d_cmdlist_node *node,
  648. struct drm_file *filp)
  649. {
  650. struct exynos_drm_subdrv *subdrv = &g2d->subdrv;
  651. struct g2d_buf_info *buf_info = &node->buf_info;
  652. int i;
  653. for (i = 0; i < buf_info->map_nr; i++) {
  654. struct g2d_buf_desc *buf_desc;
  655. enum g2d_reg_type reg_type;
  656. unsigned long handle;
  657. reg_type = buf_info->reg_types[i];
  658. buf_desc = &buf_info->descs[reg_type];
  659. handle = buf_info->handles[reg_type];
  660. if (buf_info->types[reg_type] == BUF_TYPE_GEM)
  661. exynos_drm_gem_put_dma_addr(subdrv->drm_dev, handle,
  662. filp);
  663. else
  664. g2d_userptr_put_dma_addr(subdrv->drm_dev, handle,
  665. false);
  666. buf_info->reg_types[i] = REG_TYPE_NONE;
  667. buf_info->handles[reg_type] = 0;
  668. buf_info->types[reg_type] = 0;
  669. memset(buf_desc, 0x00, sizeof(*buf_desc));
  670. }
  671. buf_info->map_nr = 0;
  672. }
  673. static void g2d_dma_start(struct g2d_data *g2d,
  674. struct g2d_runqueue_node *runqueue_node)
  675. {
  676. struct g2d_cmdlist_node *node =
  677. list_first_entry(&runqueue_node->run_cmdlist,
  678. struct g2d_cmdlist_node, list);
  679. int ret;
  680. ret = pm_runtime_get_sync(g2d->dev);
  681. if (ret < 0)
  682. return;
  683. writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
  684. writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
  685. }
  686. static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d)
  687. {
  688. struct g2d_runqueue_node *runqueue_node;
  689. if (list_empty(&g2d->runqueue))
  690. return NULL;
  691. runqueue_node = list_first_entry(&g2d->runqueue,
  692. struct g2d_runqueue_node, list);
  693. list_del_init(&runqueue_node->list);
  694. return runqueue_node;
  695. }
  696. static void g2d_free_runqueue_node(struct g2d_data *g2d,
  697. struct g2d_runqueue_node *runqueue_node)
  698. {
  699. struct g2d_cmdlist_node *node;
  700. if (!runqueue_node)
  701. return;
  702. mutex_lock(&g2d->cmdlist_mutex);
  703. /*
  704. * commands in run_cmdlist have been completed so unmap all gem
  705. * objects in each command node so that they are unreferenced.
  706. */
  707. list_for_each_entry(node, &runqueue_node->run_cmdlist, list)
  708. g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp);
  709. list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist);
  710. mutex_unlock(&g2d->cmdlist_mutex);
  711. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  712. }
  713. static void g2d_exec_runqueue(struct g2d_data *g2d)
  714. {
  715. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  716. if (g2d->runqueue_node)
  717. g2d_dma_start(g2d, g2d->runqueue_node);
  718. }
  719. static void g2d_runqueue_worker(struct work_struct *work)
  720. {
  721. struct g2d_data *g2d = container_of(work, struct g2d_data,
  722. runqueue_work);
  723. mutex_lock(&g2d->runqueue_mutex);
  724. pm_runtime_put_sync(g2d->dev);
  725. complete(&g2d->runqueue_node->complete);
  726. if (g2d->runqueue_node->async)
  727. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  728. if (g2d->suspended)
  729. g2d->runqueue_node = NULL;
  730. else
  731. g2d_exec_runqueue(g2d);
  732. mutex_unlock(&g2d->runqueue_mutex);
  733. }
  734. static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
  735. {
  736. struct drm_device *drm_dev = g2d->subdrv.drm_dev;
  737. struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
  738. struct drm_exynos_pending_g2d_event *e;
  739. struct timeval now;
  740. unsigned long flags;
  741. if (list_empty(&runqueue_node->event_list))
  742. return;
  743. e = list_first_entry(&runqueue_node->event_list,
  744. struct drm_exynos_pending_g2d_event, base.link);
  745. do_gettimeofday(&now);
  746. e->event.tv_sec = now.tv_sec;
  747. e->event.tv_usec = now.tv_usec;
  748. e->event.cmdlist_no = cmdlist_no;
  749. spin_lock_irqsave(&drm_dev->event_lock, flags);
  750. list_move_tail(&e->base.link, &e->base.file_priv->event_list);
  751. wake_up_interruptible(&e->base.file_priv->event_wait);
  752. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  753. }
  754. static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
  755. {
  756. struct g2d_data *g2d = dev_id;
  757. u32 pending;
  758. pending = readl_relaxed(g2d->regs + G2D_INTC_PEND);
  759. if (pending)
  760. writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
  761. if (pending & G2D_INTP_GCMD_FIN) {
  762. u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS);
  763. cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >>
  764. G2D_DMA_LIST_DONE_COUNT_OFFSET;
  765. g2d_finish_event(g2d, cmdlist_no);
  766. writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
  767. if (!(pending & G2D_INTP_ACMD_FIN)) {
  768. writel_relaxed(G2D_DMA_CONTINUE,
  769. g2d->regs + G2D_DMA_COMMAND);
  770. }
  771. }
  772. if (pending & G2D_INTP_ACMD_FIN)
  773. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  774. return IRQ_HANDLED;
  775. }
  776. static int g2d_check_reg_offset(struct device *dev,
  777. struct g2d_cmdlist_node *node,
  778. int nr, bool for_addr)
  779. {
  780. struct g2d_cmdlist *cmdlist = node->cmdlist;
  781. int reg_offset;
  782. int index;
  783. int i;
  784. for (i = 0; i < nr; i++) {
  785. struct g2d_buf_info *buf_info = &node->buf_info;
  786. struct g2d_buf_desc *buf_desc;
  787. enum g2d_reg_type reg_type;
  788. unsigned long value;
  789. index = cmdlist->last - 2 * (i + 1);
  790. reg_offset = cmdlist->data[index] & ~0xfffff000;
  791. if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
  792. goto err;
  793. if (reg_offset % 4)
  794. goto err;
  795. switch (reg_offset) {
  796. case G2D_SRC_BASE_ADDR:
  797. case G2D_SRC_PLANE2_BASE_ADDR:
  798. case G2D_DST_BASE_ADDR:
  799. case G2D_DST_PLANE2_BASE_ADDR:
  800. case G2D_PAT_BASE_ADDR:
  801. case G2D_MSK_BASE_ADDR:
  802. if (!for_addr)
  803. goto err;
  804. reg_type = g2d_get_reg_type(reg_offset);
  805. if (reg_type == REG_TYPE_NONE)
  806. goto err;
  807. /* check userptr buffer type. */
  808. if ((cmdlist->data[index] & ~0x7fffffff) >> 31) {
  809. buf_info->types[reg_type] = BUF_TYPE_USERPTR;
  810. cmdlist->data[index] &= ~G2D_BUF_USERPTR;
  811. } else
  812. buf_info->types[reg_type] = BUF_TYPE_GEM;
  813. break;
  814. case G2D_SRC_COLOR_MODE:
  815. case G2D_DST_COLOR_MODE:
  816. if (for_addr)
  817. goto err;
  818. reg_type = g2d_get_reg_type(reg_offset);
  819. if (reg_type == REG_TYPE_NONE)
  820. goto err;
  821. buf_desc = &buf_info->descs[reg_type];
  822. value = cmdlist->data[index + 1];
  823. buf_desc->format = value & 0xf;
  824. break;
  825. case G2D_SRC_LEFT_TOP:
  826. case G2D_DST_LEFT_TOP:
  827. if (for_addr)
  828. goto err;
  829. reg_type = g2d_get_reg_type(reg_offset);
  830. if (reg_type == REG_TYPE_NONE)
  831. goto err;
  832. buf_desc = &buf_info->descs[reg_type];
  833. value = cmdlist->data[index + 1];
  834. buf_desc->left_x = value & 0x1fff;
  835. buf_desc->top_y = (value & 0x1fff0000) >> 16;
  836. break;
  837. case G2D_SRC_RIGHT_BOTTOM:
  838. case G2D_DST_RIGHT_BOTTOM:
  839. if (for_addr)
  840. goto err;
  841. reg_type = g2d_get_reg_type(reg_offset);
  842. if (reg_type == REG_TYPE_NONE)
  843. goto err;
  844. buf_desc = &buf_info->descs[reg_type];
  845. value = cmdlist->data[index + 1];
  846. buf_desc->right_x = value & 0x1fff;
  847. buf_desc->bottom_y = (value & 0x1fff0000) >> 16;
  848. break;
  849. default:
  850. if (for_addr)
  851. goto err;
  852. break;
  853. }
  854. }
  855. return 0;
  856. err:
  857. dev_err(dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]);
  858. return -EINVAL;
  859. }
  860. /* ioctl functions */
  861. int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data,
  862. struct drm_file *file)
  863. {
  864. struct drm_exynos_file_private *file_priv = file->driver_priv;
  865. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  866. struct device *dev;
  867. struct g2d_data *g2d;
  868. struct drm_exynos_g2d_get_ver *ver = data;
  869. if (!g2d_priv)
  870. return -ENODEV;
  871. dev = g2d_priv->dev;
  872. if (!dev)
  873. return -ENODEV;
  874. g2d = dev_get_drvdata(dev);
  875. if (!g2d)
  876. return -EFAULT;
  877. ver->major = G2D_HW_MAJOR_VER;
  878. ver->minor = G2D_HW_MINOR_VER;
  879. return 0;
  880. }
  881. EXPORT_SYMBOL_GPL(exynos_g2d_get_ver_ioctl);
  882. int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data,
  883. struct drm_file *file)
  884. {
  885. struct drm_exynos_file_private *file_priv = file->driver_priv;
  886. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  887. struct device *dev;
  888. struct g2d_data *g2d;
  889. struct drm_exynos_g2d_set_cmdlist *req = data;
  890. struct drm_exynos_g2d_cmd *cmd;
  891. struct drm_exynos_pending_g2d_event *e;
  892. struct g2d_cmdlist_node *node;
  893. struct g2d_cmdlist *cmdlist;
  894. unsigned long flags;
  895. int size;
  896. int ret;
  897. if (!g2d_priv)
  898. return -ENODEV;
  899. dev = g2d_priv->dev;
  900. if (!dev)
  901. return -ENODEV;
  902. g2d = dev_get_drvdata(dev);
  903. if (!g2d)
  904. return -EFAULT;
  905. node = g2d_get_cmdlist(g2d);
  906. if (!node)
  907. return -ENOMEM;
  908. node->event = NULL;
  909. if (req->event_type != G2D_EVENT_NOT) {
  910. spin_lock_irqsave(&drm_dev->event_lock, flags);
  911. if (file->event_space < sizeof(e->event)) {
  912. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  913. ret = -ENOMEM;
  914. goto err;
  915. }
  916. file->event_space -= sizeof(e->event);
  917. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  918. e = kzalloc(sizeof(*node->event), GFP_KERNEL);
  919. if (!e) {
  920. spin_lock_irqsave(&drm_dev->event_lock, flags);
  921. file->event_space += sizeof(e->event);
  922. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  923. ret = -ENOMEM;
  924. goto err;
  925. }
  926. e->event.base.type = DRM_EXYNOS_G2D_EVENT;
  927. e->event.base.length = sizeof(e->event);
  928. e->event.user_data = req->user_data;
  929. e->base.event = &e->event.base;
  930. e->base.file_priv = file;
  931. e->base.destroy = (void (*) (struct drm_pending_event *)) kfree;
  932. node->event = e;
  933. }
  934. cmdlist = node->cmdlist;
  935. cmdlist->last = 0;
  936. /*
  937. * If don't clear SFR registers, the cmdlist is affected by register
  938. * values of previous cmdlist. G2D hw executes SFR clear command and
  939. * a next command at the same time then the next command is ignored and
  940. * is executed rightly from next next command, so needs a dummy command
  941. * to next command of SFR clear command.
  942. */
  943. cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET;
  944. cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR;
  945. cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR;
  946. cmdlist->data[cmdlist->last++] = 0;
  947. /*
  948. * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG
  949. * and GCF bit should be set to INTEN register if user wants
  950. * G2D interrupt event once current command list execution is
  951. * finished.
  952. * Otherwise only ACF bit should be set to INTEN register so
  953. * that one interrupt is occurred after all command lists
  954. * have been completed.
  955. */
  956. if (node->event) {
  957. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  958. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF;
  959. cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD;
  960. cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD;
  961. } else {
  962. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  963. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF;
  964. }
  965. /* Check size of cmdlist: last 2 is about G2D_BITBLT_START */
  966. size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2;
  967. if (size > G2D_CMDLIST_DATA_NUM) {
  968. dev_err(dev, "cmdlist size is too big\n");
  969. ret = -EINVAL;
  970. goto err_free_event;
  971. }
  972. cmd = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd;
  973. if (copy_from_user(cmdlist->data + cmdlist->last,
  974. (void __user *)cmd,
  975. sizeof(*cmd) * req->cmd_nr)) {
  976. ret = -EFAULT;
  977. goto err_free_event;
  978. }
  979. cmdlist->last += req->cmd_nr * 2;
  980. ret = g2d_check_reg_offset(dev, node, req->cmd_nr, false);
  981. if (ret < 0)
  982. goto err_free_event;
  983. node->buf_info.map_nr = req->cmd_buf_nr;
  984. if (req->cmd_buf_nr) {
  985. struct drm_exynos_g2d_cmd *cmd_buf;
  986. cmd_buf = (struct drm_exynos_g2d_cmd *)(uint32_t)req->cmd_buf;
  987. if (copy_from_user(cmdlist->data + cmdlist->last,
  988. (void __user *)cmd_buf,
  989. sizeof(*cmd_buf) * req->cmd_buf_nr)) {
  990. ret = -EFAULT;
  991. goto err_free_event;
  992. }
  993. cmdlist->last += req->cmd_buf_nr * 2;
  994. ret = g2d_check_reg_offset(dev, node, req->cmd_buf_nr, true);
  995. if (ret < 0)
  996. goto err_free_event;
  997. ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file);
  998. if (ret < 0)
  999. goto err_unmap;
  1000. }
  1001. cmdlist->data[cmdlist->last++] = G2D_BITBLT_START;
  1002. cmdlist->data[cmdlist->last++] = G2D_START_BITBLT;
  1003. /* head */
  1004. cmdlist->head = cmdlist->last / 2;
  1005. /* tail */
  1006. cmdlist->data[cmdlist->last] = 0;
  1007. g2d_add_cmdlist_to_inuse(g2d_priv, node);
  1008. return 0;
  1009. err_unmap:
  1010. g2d_unmap_cmdlist_gem(g2d, node, file);
  1011. err_free_event:
  1012. if (node->event) {
  1013. spin_lock_irqsave(&drm_dev->event_lock, flags);
  1014. file->event_space += sizeof(e->event);
  1015. spin_unlock_irqrestore(&drm_dev->event_lock, flags);
  1016. kfree(node->event);
  1017. }
  1018. err:
  1019. g2d_put_cmdlist(g2d, node);
  1020. return ret;
  1021. }
  1022. EXPORT_SYMBOL_GPL(exynos_g2d_set_cmdlist_ioctl);
  1023. int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
  1024. struct drm_file *file)
  1025. {
  1026. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1027. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1028. struct device *dev;
  1029. struct g2d_data *g2d;
  1030. struct drm_exynos_g2d_exec *req = data;
  1031. struct g2d_runqueue_node *runqueue_node;
  1032. struct list_head *run_cmdlist;
  1033. struct list_head *event_list;
  1034. if (!g2d_priv)
  1035. return -ENODEV;
  1036. dev = g2d_priv->dev;
  1037. if (!dev)
  1038. return -ENODEV;
  1039. g2d = dev_get_drvdata(dev);
  1040. if (!g2d)
  1041. return -EFAULT;
  1042. runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
  1043. if (!runqueue_node) {
  1044. dev_err(dev, "failed to allocate memory\n");
  1045. return -ENOMEM;
  1046. }
  1047. run_cmdlist = &runqueue_node->run_cmdlist;
  1048. event_list = &runqueue_node->event_list;
  1049. INIT_LIST_HEAD(run_cmdlist);
  1050. INIT_LIST_HEAD(event_list);
  1051. init_completion(&runqueue_node->complete);
  1052. runqueue_node->async = req->async;
  1053. list_splice_init(&g2d_priv->inuse_cmdlist, run_cmdlist);
  1054. list_splice_init(&g2d_priv->event_list, event_list);
  1055. if (list_empty(run_cmdlist)) {
  1056. dev_err(dev, "there is no inuse cmdlist\n");
  1057. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  1058. return -EPERM;
  1059. }
  1060. mutex_lock(&g2d->runqueue_mutex);
  1061. runqueue_node->pid = current->pid;
  1062. runqueue_node->filp = file;
  1063. list_add_tail(&runqueue_node->list, &g2d->runqueue);
  1064. if (!g2d->runqueue_node)
  1065. g2d_exec_runqueue(g2d);
  1066. mutex_unlock(&g2d->runqueue_mutex);
  1067. if (runqueue_node->async)
  1068. goto out;
  1069. wait_for_completion(&runqueue_node->complete);
  1070. g2d_free_runqueue_node(g2d, runqueue_node);
  1071. out:
  1072. return 0;
  1073. }
  1074. EXPORT_SYMBOL_GPL(exynos_g2d_exec_ioctl);
  1075. static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
  1076. {
  1077. struct g2d_data *g2d;
  1078. int ret;
  1079. g2d = dev_get_drvdata(dev);
  1080. if (!g2d)
  1081. return -EFAULT;
  1082. /* allocate dma-aware cmdlist buffer. */
  1083. ret = g2d_init_cmdlist(g2d);
  1084. if (ret < 0) {
  1085. dev_err(dev, "cmdlist init failed\n");
  1086. return ret;
  1087. }
  1088. if (!is_drm_iommu_supported(drm_dev))
  1089. return 0;
  1090. ret = drm_iommu_attach_device(drm_dev, dev);
  1091. if (ret < 0) {
  1092. dev_err(dev, "failed to enable iommu.\n");
  1093. g2d_fini_cmdlist(g2d);
  1094. }
  1095. return ret;
  1096. }
  1097. static void g2d_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
  1098. {
  1099. if (!is_drm_iommu_supported(drm_dev))
  1100. return;
  1101. drm_iommu_detach_device(drm_dev, dev);
  1102. }
  1103. static int g2d_open(struct drm_device *drm_dev, struct device *dev,
  1104. struct drm_file *file)
  1105. {
  1106. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1107. struct exynos_drm_g2d_private *g2d_priv;
  1108. g2d_priv = kzalloc(sizeof(*g2d_priv), GFP_KERNEL);
  1109. if (!g2d_priv)
  1110. return -ENOMEM;
  1111. g2d_priv->dev = dev;
  1112. file_priv->g2d_priv = g2d_priv;
  1113. INIT_LIST_HEAD(&g2d_priv->inuse_cmdlist);
  1114. INIT_LIST_HEAD(&g2d_priv->event_list);
  1115. INIT_LIST_HEAD(&g2d_priv->userptr_list);
  1116. return 0;
  1117. }
  1118. static void g2d_close(struct drm_device *drm_dev, struct device *dev,
  1119. struct drm_file *file)
  1120. {
  1121. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1122. struct exynos_drm_g2d_private *g2d_priv = file_priv->g2d_priv;
  1123. struct g2d_data *g2d;
  1124. struct g2d_cmdlist_node *node, *n;
  1125. if (!dev)
  1126. return;
  1127. g2d = dev_get_drvdata(dev);
  1128. if (!g2d)
  1129. return;
  1130. mutex_lock(&g2d->cmdlist_mutex);
  1131. list_for_each_entry_safe(node, n, &g2d_priv->inuse_cmdlist, list) {
  1132. /*
  1133. * unmap all gem objects not completed.
  1134. *
  1135. * P.S. if current process was terminated forcely then
  1136. * there may be some commands in inuse_cmdlist so unmap
  1137. * them.
  1138. */
  1139. g2d_unmap_cmdlist_gem(g2d, node, file);
  1140. list_move_tail(&node->list, &g2d->free_cmdlist);
  1141. }
  1142. mutex_unlock(&g2d->cmdlist_mutex);
  1143. /* release all g2d_userptr in pool. */
  1144. g2d_userptr_free_all(drm_dev, g2d, file);
  1145. kfree(file_priv->g2d_priv);
  1146. }
  1147. static int g2d_probe(struct platform_device *pdev)
  1148. {
  1149. struct device *dev = &pdev->dev;
  1150. struct resource *res;
  1151. struct g2d_data *g2d;
  1152. struct exynos_drm_subdrv *subdrv;
  1153. int ret;
  1154. g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
  1155. if (!g2d)
  1156. return -ENOMEM;
  1157. g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
  1158. sizeof(struct g2d_runqueue_node), 0, 0, NULL);
  1159. if (!g2d->runqueue_slab)
  1160. return -ENOMEM;
  1161. g2d->dev = dev;
  1162. g2d->g2d_workq = create_singlethread_workqueue("g2d");
  1163. if (!g2d->g2d_workq) {
  1164. dev_err(dev, "failed to create workqueue\n");
  1165. ret = -EINVAL;
  1166. goto err_destroy_slab;
  1167. }
  1168. INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker);
  1169. INIT_LIST_HEAD(&g2d->free_cmdlist);
  1170. INIT_LIST_HEAD(&g2d->runqueue);
  1171. mutex_init(&g2d->cmdlist_mutex);
  1172. mutex_init(&g2d->runqueue_mutex);
  1173. g2d->gate_clk = devm_clk_get(dev, "fimg2d");
  1174. if (IS_ERR(g2d->gate_clk)) {
  1175. dev_err(dev, "failed to get gate clock\n");
  1176. ret = PTR_ERR(g2d->gate_clk);
  1177. goto err_destroy_workqueue;
  1178. }
  1179. pm_runtime_enable(dev);
  1180. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1181. g2d->regs = devm_ioremap_resource(dev, res);
  1182. if (IS_ERR(g2d->regs)) {
  1183. ret = PTR_ERR(g2d->regs);
  1184. goto err_put_clk;
  1185. }
  1186. g2d->irq = platform_get_irq(pdev, 0);
  1187. if (g2d->irq < 0) {
  1188. dev_err(dev, "failed to get irq\n");
  1189. ret = g2d->irq;
  1190. goto err_put_clk;
  1191. }
  1192. ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
  1193. "drm_g2d", g2d);
  1194. if (ret < 0) {
  1195. dev_err(dev, "irq request failed\n");
  1196. goto err_put_clk;
  1197. }
  1198. g2d->max_pool = MAX_POOL;
  1199. platform_set_drvdata(pdev, g2d);
  1200. subdrv = &g2d->subdrv;
  1201. subdrv->dev = dev;
  1202. subdrv->probe = g2d_subdrv_probe;
  1203. subdrv->remove = g2d_subdrv_remove;
  1204. subdrv->open = g2d_open;
  1205. subdrv->close = g2d_close;
  1206. ret = exynos_drm_subdrv_register(subdrv);
  1207. if (ret < 0) {
  1208. dev_err(dev, "failed to register drm g2d device\n");
  1209. goto err_put_clk;
  1210. }
  1211. dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n",
  1212. G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER);
  1213. return 0;
  1214. err_put_clk:
  1215. pm_runtime_disable(dev);
  1216. err_destroy_workqueue:
  1217. destroy_workqueue(g2d->g2d_workq);
  1218. err_destroy_slab:
  1219. kmem_cache_destroy(g2d->runqueue_slab);
  1220. return ret;
  1221. }
  1222. static int g2d_remove(struct platform_device *pdev)
  1223. {
  1224. struct g2d_data *g2d = platform_get_drvdata(pdev);
  1225. cancel_work_sync(&g2d->runqueue_work);
  1226. exynos_drm_subdrv_unregister(&g2d->subdrv);
  1227. while (g2d->runqueue_node) {
  1228. g2d_free_runqueue_node(g2d, g2d->runqueue_node);
  1229. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  1230. }
  1231. pm_runtime_disable(&pdev->dev);
  1232. g2d_fini_cmdlist(g2d);
  1233. destroy_workqueue(g2d->g2d_workq);
  1234. kmem_cache_destroy(g2d->runqueue_slab);
  1235. return 0;
  1236. }
  1237. #ifdef CONFIG_PM_SLEEP
  1238. static int g2d_suspend(struct device *dev)
  1239. {
  1240. struct g2d_data *g2d = dev_get_drvdata(dev);
  1241. mutex_lock(&g2d->runqueue_mutex);
  1242. g2d->suspended = true;
  1243. mutex_unlock(&g2d->runqueue_mutex);
  1244. while (g2d->runqueue_node)
  1245. /* FIXME: good range? */
  1246. usleep_range(500, 1000);
  1247. flush_work(&g2d->runqueue_work);
  1248. return 0;
  1249. }
  1250. static int g2d_resume(struct device *dev)
  1251. {
  1252. struct g2d_data *g2d = dev_get_drvdata(dev);
  1253. g2d->suspended = false;
  1254. g2d_exec_runqueue(g2d);
  1255. return 0;
  1256. }
  1257. #endif
  1258. #ifdef CONFIG_PM
  1259. static int g2d_runtime_suspend(struct device *dev)
  1260. {
  1261. struct g2d_data *g2d = dev_get_drvdata(dev);
  1262. clk_disable_unprepare(g2d->gate_clk);
  1263. return 0;
  1264. }
  1265. static int g2d_runtime_resume(struct device *dev)
  1266. {
  1267. struct g2d_data *g2d = dev_get_drvdata(dev);
  1268. int ret;
  1269. ret = clk_prepare_enable(g2d->gate_clk);
  1270. if (ret < 0)
  1271. dev_warn(dev, "failed to enable clock.\n");
  1272. return ret;
  1273. }
  1274. #endif
  1275. static const struct dev_pm_ops g2d_pm_ops = {
  1276. SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume)
  1277. SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL)
  1278. };
  1279. static const struct of_device_id exynos_g2d_match[] = {
  1280. { .compatible = "samsung,exynos5250-g2d" },
  1281. { .compatible = "samsung,exynos4212-g2d" },
  1282. {},
  1283. };
  1284. MODULE_DEVICE_TABLE(of, exynos_g2d_match);
  1285. struct platform_driver g2d_driver = {
  1286. .probe = g2d_probe,
  1287. .remove = g2d_remove,
  1288. .driver = {
  1289. .name = "s5p-g2d",
  1290. .owner = THIS_MODULE,
  1291. .pm = &g2d_pm_ops,
  1292. .of_match_table = exynos_g2d_match,
  1293. },
  1294. };