atmel_hlcdc_dc.c 15 KB

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  1. /*
  2. * Copyright (C) 2014 Traphandler
  3. * Copyright (C) 2014 Free Electrons
  4. * Copyright (C) 2014 Atmel
  5. *
  6. * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
  7. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published by
  11. * the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but WITHOUT
  14. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. * more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along with
  19. * this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include <linux/clk.h>
  22. #include <linux/irq.h>
  23. #include <linux/irqchip.h>
  24. #include <linux/module.h>
  25. #include <linux/pm_runtime.h>
  26. #include "atmel_hlcdc_dc.h"
  27. #define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
  28. static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
  29. {
  30. .name = "base",
  31. .formats = &atmel_hlcdc_plane_rgb_formats,
  32. .regs_offset = 0x40,
  33. .id = 0,
  34. .type = ATMEL_HLCDC_BASE_LAYER,
  35. .nconfigs = 7,
  36. .layout = {
  37. .xstride = { 2 },
  38. .default_color = 3,
  39. .general_config = 4,
  40. .disc_pos = 5,
  41. .disc_size = 6,
  42. },
  43. },
  44. {
  45. .name = "overlay1",
  46. .formats = &atmel_hlcdc_plane_rgb_formats,
  47. .regs_offset = 0x140,
  48. .id = 1,
  49. .type = ATMEL_HLCDC_OVERLAY_LAYER,
  50. .nconfigs = 10,
  51. .layout = {
  52. .pos = 2,
  53. .size = 3,
  54. .xstride = { 4 },
  55. .pstride = { 5 },
  56. .default_color = 6,
  57. .chroma_key = 7,
  58. .chroma_key_mask = 8,
  59. .general_config = 9,
  60. },
  61. },
  62. {
  63. .name = "overlay2",
  64. .formats = &atmel_hlcdc_plane_rgb_formats,
  65. .regs_offset = 0x240,
  66. .id = 2,
  67. .type = ATMEL_HLCDC_OVERLAY_LAYER,
  68. .nconfigs = 10,
  69. .layout = {
  70. .pos = 2,
  71. .size = 3,
  72. .xstride = { 4 },
  73. .pstride = { 5 },
  74. .default_color = 6,
  75. .chroma_key = 7,
  76. .chroma_key_mask = 8,
  77. .general_config = 9,
  78. },
  79. },
  80. {
  81. .name = "high-end-overlay",
  82. .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
  83. .regs_offset = 0x340,
  84. .id = 3,
  85. .type = ATMEL_HLCDC_OVERLAY_LAYER,
  86. .nconfigs = 42,
  87. .layout = {
  88. .pos = 2,
  89. .size = 3,
  90. .memsize = 4,
  91. .xstride = { 5, 7 },
  92. .pstride = { 6, 8 },
  93. .default_color = 9,
  94. .chroma_key = 10,
  95. .chroma_key_mask = 11,
  96. .general_config = 12,
  97. .csc = 14,
  98. },
  99. },
  100. {
  101. .name = "cursor",
  102. .formats = &atmel_hlcdc_plane_rgb_formats,
  103. .regs_offset = 0x440,
  104. .id = 4,
  105. .type = ATMEL_HLCDC_CURSOR_LAYER,
  106. .nconfigs = 10,
  107. .max_width = 128,
  108. .max_height = 128,
  109. .layout = {
  110. .pos = 2,
  111. .size = 3,
  112. .xstride = { 4 },
  113. .pstride = { 5 },
  114. .default_color = 6,
  115. .chroma_key = 7,
  116. .chroma_key_mask = 8,
  117. .general_config = 9,
  118. },
  119. },
  120. };
  121. static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
  122. .min_width = 0,
  123. .min_height = 0,
  124. .max_width = 2048,
  125. .max_height = 2048,
  126. .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
  127. .layers = atmel_hlcdc_sama5d3_layers,
  128. };
  129. static const struct of_device_id atmel_hlcdc_of_match[] = {
  130. {
  131. .compatible = "atmel,sama5d3-hlcdc",
  132. .data = &atmel_hlcdc_dc_sama5d3,
  133. },
  134. { /* sentinel */ },
  135. };
  136. int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
  137. struct drm_display_mode *mode)
  138. {
  139. int vfront_porch = mode->vsync_start - mode->vdisplay;
  140. int vback_porch = mode->vtotal - mode->vsync_end;
  141. int vsync_len = mode->vsync_end - mode->vsync_start;
  142. int hfront_porch = mode->hsync_start - mode->hdisplay;
  143. int hback_porch = mode->htotal - mode->hsync_end;
  144. int hsync_len = mode->hsync_end - mode->hsync_start;
  145. if (hsync_len > 0x40 || hsync_len < 1)
  146. return MODE_HSYNC;
  147. if (vsync_len > 0x40 || vsync_len < 1)
  148. return MODE_VSYNC;
  149. if (hfront_porch > 0x200 || hfront_porch < 1 ||
  150. hback_porch > 0x200 || hback_porch < 1 ||
  151. mode->hdisplay < 1)
  152. return MODE_H_ILLEGAL;
  153. if (vfront_porch > 0x40 || vfront_porch < 1 ||
  154. vback_porch > 0x40 || vback_porch < 0 ||
  155. mode->vdisplay < 1)
  156. return MODE_V_ILLEGAL;
  157. return MODE_OK;
  158. }
  159. static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
  160. {
  161. struct drm_device *dev = data;
  162. struct atmel_hlcdc_dc *dc = dev->dev_private;
  163. unsigned long status;
  164. unsigned int imr, isr;
  165. int i;
  166. regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
  167. regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
  168. status = imr & isr;
  169. if (!status)
  170. return IRQ_NONE;
  171. if (status & ATMEL_HLCDC_SOF)
  172. atmel_hlcdc_crtc_irq(dc->crtc);
  173. for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
  174. struct atmel_hlcdc_layer *layer = dc->layers[i];
  175. if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
  176. continue;
  177. atmel_hlcdc_layer_irq(layer);
  178. }
  179. return IRQ_HANDLED;
  180. }
  181. static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
  182. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  183. {
  184. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  185. }
  186. static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
  187. {
  188. struct atmel_hlcdc_dc *dc = dev->dev_private;
  189. if (dc->fbdev) {
  190. drm_fbdev_cma_hotplug_event(dc->fbdev);
  191. } else {
  192. dc->fbdev = drm_fbdev_cma_init(dev, 24,
  193. dev->mode_config.num_crtc,
  194. dev->mode_config.num_connector);
  195. if (IS_ERR(dc->fbdev))
  196. dc->fbdev = NULL;
  197. }
  198. }
  199. static const struct drm_mode_config_funcs mode_config_funcs = {
  200. .fb_create = atmel_hlcdc_fb_create,
  201. .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
  202. .atomic_check = drm_atomic_helper_check,
  203. .atomic_commit = drm_atomic_helper_commit,
  204. };
  205. static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
  206. {
  207. struct atmel_hlcdc_dc *dc = dev->dev_private;
  208. struct atmel_hlcdc_planes *planes;
  209. int ret;
  210. int i;
  211. drm_mode_config_init(dev);
  212. ret = atmel_hlcdc_create_outputs(dev);
  213. if (ret) {
  214. dev_err(dev->dev, "failed to create panel: %d\n", ret);
  215. return ret;
  216. }
  217. planes = atmel_hlcdc_create_planes(dev);
  218. if (IS_ERR(planes)) {
  219. dev_err(dev->dev, "failed to create planes\n");
  220. return PTR_ERR(planes);
  221. }
  222. dc->planes = planes;
  223. dc->layers[planes->primary->layer.desc->id] =
  224. &planes->primary->layer;
  225. if (planes->cursor)
  226. dc->layers[planes->cursor->layer.desc->id] =
  227. &planes->cursor->layer;
  228. for (i = 0; i < planes->noverlays; i++)
  229. dc->layers[planes->overlays[i]->layer.desc->id] =
  230. &planes->overlays[i]->layer;
  231. ret = atmel_hlcdc_crtc_create(dev);
  232. if (ret) {
  233. dev_err(dev->dev, "failed to create crtc\n");
  234. return ret;
  235. }
  236. dev->mode_config.min_width = dc->desc->min_width;
  237. dev->mode_config.min_height = dc->desc->min_height;
  238. dev->mode_config.max_width = dc->desc->max_width;
  239. dev->mode_config.max_height = dc->desc->max_height;
  240. dev->mode_config.funcs = &mode_config_funcs;
  241. return 0;
  242. }
  243. static int atmel_hlcdc_dc_load(struct drm_device *dev)
  244. {
  245. struct platform_device *pdev = to_platform_device(dev->dev);
  246. const struct of_device_id *match;
  247. struct atmel_hlcdc_dc *dc;
  248. int ret;
  249. match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
  250. if (!match) {
  251. dev_err(&pdev->dev, "invalid compatible string\n");
  252. return -ENODEV;
  253. }
  254. if (!match->data) {
  255. dev_err(&pdev->dev, "invalid hlcdc description\n");
  256. return -EINVAL;
  257. }
  258. dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
  259. if (!dc)
  260. return -ENOMEM;
  261. dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
  262. if (!dc->wq)
  263. return -ENOMEM;
  264. dc->desc = match->data;
  265. dc->hlcdc = dev_get_drvdata(dev->dev->parent);
  266. dev->dev_private = dc;
  267. ret = clk_prepare_enable(dc->hlcdc->periph_clk);
  268. if (ret) {
  269. dev_err(dev->dev, "failed to enable periph_clk\n");
  270. goto err_destroy_wq;
  271. }
  272. pm_runtime_enable(dev->dev);
  273. ret = atmel_hlcdc_dc_modeset_init(dev);
  274. if (ret < 0) {
  275. dev_err(dev->dev, "failed to initialize mode setting\n");
  276. goto err_periph_clk_disable;
  277. }
  278. drm_mode_config_reset(dev);
  279. ret = drm_vblank_init(dev, 1);
  280. if (ret < 0) {
  281. dev_err(dev->dev, "failed to initialize vblank\n");
  282. goto err_periph_clk_disable;
  283. }
  284. pm_runtime_get_sync(dev->dev);
  285. ret = drm_irq_install(dev, dc->hlcdc->irq);
  286. pm_runtime_put_sync(dev->dev);
  287. if (ret < 0) {
  288. dev_err(dev->dev, "failed to install IRQ handler\n");
  289. goto err_periph_clk_disable;
  290. }
  291. platform_set_drvdata(pdev, dev);
  292. drm_kms_helper_poll_init(dev);
  293. /* force connectors detection */
  294. drm_helper_hpd_irq_event(dev);
  295. return 0;
  296. err_periph_clk_disable:
  297. pm_runtime_disable(dev->dev);
  298. clk_disable_unprepare(dc->hlcdc->periph_clk);
  299. err_destroy_wq:
  300. destroy_workqueue(dc->wq);
  301. return ret;
  302. }
  303. static void atmel_hlcdc_dc_unload(struct drm_device *dev)
  304. {
  305. struct atmel_hlcdc_dc *dc = dev->dev_private;
  306. if (dc->fbdev)
  307. drm_fbdev_cma_fini(dc->fbdev);
  308. flush_workqueue(dc->wq);
  309. drm_kms_helper_poll_fini(dev);
  310. drm_mode_config_cleanup(dev);
  311. drm_vblank_cleanup(dev);
  312. pm_runtime_get_sync(dev->dev);
  313. drm_irq_uninstall(dev);
  314. pm_runtime_put_sync(dev->dev);
  315. dev->dev_private = NULL;
  316. pm_runtime_disable(dev->dev);
  317. clk_disable_unprepare(dc->hlcdc->periph_clk);
  318. destroy_workqueue(dc->wq);
  319. }
  320. static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
  321. {
  322. struct drm_connector *connector, *failed;
  323. int ret;
  324. mutex_lock(&dev->mode_config.mutex);
  325. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  326. ret = drm_connector_register(connector);
  327. if (ret) {
  328. failed = connector;
  329. goto err;
  330. }
  331. }
  332. mutex_unlock(&dev->mode_config.mutex);
  333. return 0;
  334. err:
  335. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  336. if (failed == connector)
  337. break;
  338. drm_connector_unregister(connector);
  339. }
  340. mutex_unlock(&dev->mode_config.mutex);
  341. return ret;
  342. }
  343. static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
  344. {
  345. mutex_lock(&dev->mode_config.mutex);
  346. drm_connector_unplug_all(dev);
  347. mutex_unlock(&dev->mode_config.mutex);
  348. }
  349. static void atmel_hlcdc_dc_preclose(struct drm_device *dev,
  350. struct drm_file *file)
  351. {
  352. struct drm_crtc *crtc;
  353. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
  354. atmel_hlcdc_crtc_cancel_page_flip(crtc, file);
  355. }
  356. static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
  357. {
  358. struct atmel_hlcdc_dc *dc = dev->dev_private;
  359. drm_fbdev_cma_restore_mode(dc->fbdev);
  360. }
  361. static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
  362. {
  363. struct atmel_hlcdc_dc *dc = dev->dev_private;
  364. unsigned int cfg = 0;
  365. int i;
  366. /* Enable interrupts on activated layers */
  367. for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
  368. if (dc->layers[i])
  369. cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
  370. }
  371. regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
  372. return 0;
  373. }
  374. static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
  375. {
  376. struct atmel_hlcdc_dc *dc = dev->dev_private;
  377. unsigned int isr;
  378. regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
  379. regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
  380. }
  381. static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev, int crtc)
  382. {
  383. struct atmel_hlcdc_dc *dc = dev->dev_private;
  384. /* Enable SOF (Start Of Frame) interrupt for vblank counting */
  385. regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
  386. return 0;
  387. }
  388. static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev, int crtc)
  389. {
  390. struct atmel_hlcdc_dc *dc = dev->dev_private;
  391. regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
  392. }
  393. static const struct file_operations fops = {
  394. .owner = THIS_MODULE,
  395. .open = drm_open,
  396. .release = drm_release,
  397. .unlocked_ioctl = drm_ioctl,
  398. #ifdef CONFIG_COMPAT
  399. .compat_ioctl = drm_compat_ioctl,
  400. #endif
  401. .poll = drm_poll,
  402. .read = drm_read,
  403. .llseek = no_llseek,
  404. .mmap = drm_gem_cma_mmap,
  405. };
  406. static struct drm_driver atmel_hlcdc_dc_driver = {
  407. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  408. .preclose = atmel_hlcdc_dc_preclose,
  409. .lastclose = atmel_hlcdc_dc_lastclose,
  410. .irq_handler = atmel_hlcdc_dc_irq_handler,
  411. .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
  412. .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
  413. .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
  414. .get_vblank_counter = drm_vblank_count,
  415. .enable_vblank = atmel_hlcdc_dc_enable_vblank,
  416. .disable_vblank = atmel_hlcdc_dc_disable_vblank,
  417. .gem_free_object = drm_gem_cma_free_object,
  418. .gem_vm_ops = &drm_gem_cma_vm_ops,
  419. .dumb_create = drm_gem_cma_dumb_create,
  420. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  421. .dumb_destroy = drm_gem_dumb_destroy,
  422. .fops = &fops,
  423. .name = "atmel-hlcdc",
  424. .desc = "Atmel HLCD Controller DRM",
  425. .date = "20141504",
  426. .major = 1,
  427. .minor = 0,
  428. };
  429. static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
  430. {
  431. struct drm_device *ddev;
  432. int ret;
  433. ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
  434. if (!ddev)
  435. return -ENOMEM;
  436. ret = drm_dev_set_unique(ddev, dev_name(ddev->dev));
  437. if (ret)
  438. goto err_unref;
  439. ret = atmel_hlcdc_dc_load(ddev);
  440. if (ret)
  441. goto err_unref;
  442. ret = drm_dev_register(ddev, 0);
  443. if (ret)
  444. goto err_unload;
  445. ret = atmel_hlcdc_dc_connector_plug_all(ddev);
  446. if (ret)
  447. goto err_unregister;
  448. return 0;
  449. err_unregister:
  450. drm_dev_unregister(ddev);
  451. err_unload:
  452. atmel_hlcdc_dc_unload(ddev);
  453. err_unref:
  454. drm_dev_unref(ddev);
  455. return ret;
  456. }
  457. static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
  458. {
  459. struct drm_device *ddev = platform_get_drvdata(pdev);
  460. atmel_hlcdc_dc_connector_unplug_all(ddev);
  461. drm_dev_unregister(ddev);
  462. atmel_hlcdc_dc_unload(ddev);
  463. drm_dev_unref(ddev);
  464. return 0;
  465. }
  466. #ifdef CONFIG_PM
  467. static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
  468. {
  469. struct drm_device *drm_dev = dev_get_drvdata(dev);
  470. struct drm_crtc *crtc;
  471. if (pm_runtime_suspended(dev))
  472. return 0;
  473. drm_modeset_lock_all(drm_dev);
  474. list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
  475. atmel_hlcdc_crtc_suspend(crtc);
  476. drm_modeset_unlock_all(drm_dev);
  477. return 0;
  478. }
  479. static int atmel_hlcdc_dc_drm_resume(struct device *dev)
  480. {
  481. struct drm_device *drm_dev = dev_get_drvdata(dev);
  482. struct drm_crtc *crtc;
  483. if (pm_runtime_suspended(dev))
  484. return 0;
  485. drm_modeset_lock_all(drm_dev);
  486. list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
  487. atmel_hlcdc_crtc_resume(crtc);
  488. drm_modeset_unlock_all(drm_dev);
  489. return 0;
  490. }
  491. #endif
  492. static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
  493. atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
  494. static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
  495. { .compatible = "atmel,hlcdc-display-controller" },
  496. { },
  497. };
  498. static struct platform_driver atmel_hlcdc_dc_platform_driver = {
  499. .probe = atmel_hlcdc_dc_drm_probe,
  500. .remove = atmel_hlcdc_dc_drm_remove,
  501. .driver = {
  502. .name = "atmel-hlcdc-display-controller",
  503. .pm = &atmel_hlcdc_dc_drm_pm_ops,
  504. .of_match_table = atmel_hlcdc_dc_of_match,
  505. },
  506. };
  507. module_platform_driver(atmel_hlcdc_dc_platform_driver);
  508. MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
  509. MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
  510. MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
  511. MODULE_LICENSE("GPL");
  512. MODULE_ALIAS("platform:atmel-hlcdc-dc");